JP2012227424A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2012227424A
JP2012227424A JP2011095098A JP2011095098A JP2012227424A JP 2012227424 A JP2012227424 A JP 2012227424A JP 2011095098 A JP2011095098 A JP 2011095098A JP 2011095098 A JP2011095098 A JP 2011095098A JP 2012227424 A JP2012227424 A JP 2012227424A
Authority
JP
Japan
Prior art keywords
semiconductor element
control
circuit board
semiconductor device
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011095098A
Other languages
Japanese (ja)
Other versions
JP5558405B2 (en
Inventor
Koji Kichise
幸司 吉瀬
Takeshi Ikeda
孟 池田
Hiroyuki Waku
宏之 和久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2011095098A priority Critical patent/JP5558405B2/en
Publication of JP2012227424A publication Critical patent/JP2012227424A/en
Application granted granted Critical
Publication of JP5558405B2 publication Critical patent/JP5558405B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Inverter Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device using a power semiconductor element, which has a high heat dissipation capacity and does not have an adverse thermal effect on a control semiconductor element and a control circuit board.SOLUTION: A semiconductor device comprises: a power semiconductor element 2; a control circuit board 5 on which a control semiconductor element 4 that controls the power semiconductor element 2 is mounted; a housing 9 that houses the power semiconductor element 2 and the control circuit board 5; and a control wiring 6 that electrically connects the power semiconductor element 2 with the control circuit board 5, whose tip part 6t on the control circuit board 5 side extends and protrudes to the outside through a through hole 13 provided in the housing 9. The semiconductor device suppresses heat conduction through the control wiring 6 from the power semiconductor element 2 to the control semiconductor element 4 and the control circuit board 5, so that the control semiconductor element 4 and the control circuit board 5 can be protected.

Description

本発明は、パワー半導体素子を搭載し、放熱対策を講じた半導体装置に関するものである。   The present invention relates to a semiconductor device on which a power semiconductor element is mounted and a heat dissipation measure is taken.

従来、パワー半導体素子により構成されるインバータ装置では、パワー半導体素子を安定して動作させるために、パワー半導体素子の温度上昇を抑制するため効率よく冷却する対策が講じられている。   Conventionally, in an inverter device composed of power semiconductor elements, in order to stably operate the power semiconductor elements, measures for efficiently cooling the power semiconductor elements have been taken in order to suppress a temperature rise of the power semiconductor elements.

例えば、特許文献１に示されるインバータ装置では、パワー半導体素子と冷媒間の熱抵抗を低減することを目的として、パワー半導体素子と、電極板が表裏に接合されパワー半導体素子が搭載された絶縁基板及び端子などからなるパワー回路部と、冷却媒体の流路が形成されたケースと、制御回路部分とを備えていて、電極板が接合された絶縁基板の裏面を冷却媒体によって冷却し、流路の両端部で絶縁基板とケースが接合されている。絶縁基板の裏面が冷媒によって直接冷却されることによりパワー半導体素子と冷媒間の熱抵抗が低減されるとともに、流路の両端部で絶縁基板とケースが接合されているため流路形成時のばらつきが小さく流路を再現性よく形成でき、冷媒の内圧による流路の変形が小さく低熱抵抗化が安定に達成される。また、インバータ装置を小型化できる。   For example, in the inverter device shown in Patent Document 1, for the purpose of reducing the thermal resistance between the power semiconductor element and the refrigerant, the power semiconductor element and the insulating substrate on which the power semiconductor element is mounted by bonding the electrode plates to the front and back And a power circuit unit composed of terminals and the like, a case in which a flow path of the cooling medium is formed, and a control circuit part, and the back surface of the insulating substrate to which the electrode plate is bonded is cooled by the cooling medium. The insulating substrate and the case are bonded to each other at both ends. The back surface of the insulating substrate is directly cooled by the refrigerant, so that the thermal resistance between the power semiconductor element and the refrigerant is reduced, and the insulating substrate and the case are joined at both ends of the flow path, so that variations in the flow path formation occur. The flow path can be formed with good reproducibility, the deformation of the flow path due to the internal pressure of the refrigerant is small, and low thermal resistance is stably achieved. Further, the inverter device can be reduced in size.

また、特許文献２に示される半導体装置では、パワー部と、パワー部の上方に位置する制御部との間に、パワー部封止樹脂と熱伝導率の異なる絶縁体を介在させている。制御回路基板が、一つのモジュールとして半導体装置内に組み込まれた場合、制御回路部の熱流入を抑制するため、制御回路部に仕切り蓋を設置し、熱伝導率の異なる絶縁体を介在させることで、パワー半導体素子で発生した熱が主回路部に流入することを抑制できる構造になっている。   Further, in the semiconductor device disclosed in Patent Document 2, an insulator having a thermal conductivity different from that of the power unit sealing resin is interposed between the power unit and the control unit located above the power unit. When the control circuit board is incorporated into a semiconductor device as a single module, a partition lid is installed in the control circuit unit to interpose insulators having different thermal conductivities in order to suppress heat inflow of the control circuit unit. Thus, the heat generated in the power semiconductor element can be prevented from flowing into the main circuit portion.

特開２００２−３１５３５７号公報JP 2002-315357 A 特開２０００−２２８４９２号公報JP 2000-228492 A

しかしながら、このような半導体装置にあっては、パワー半導体素子の動作を制御するために、制御回路基板とパワー半導体素子間で制御信号を送受信するための制御配線が存在している。この制御配線には、パワー半導体素子と周辺機器間に介在する電極に流れるような大電流は流れないが、パワー半導体素子と直接電気的に接続されているため、熱の伝わり方も良いので、制御回路基板と制御配線との接続部の温度が局所的に上昇して、信頼性を損ねるという問題点があった。   However, in such a semiconductor device, there is a control wiring for transmitting / receiving a control signal between the control circuit board and the power semiconductor element in order to control the operation of the power semiconductor element. In this control wiring, a large current that flows through the electrode interposed between the power semiconductor element and the peripheral device does not flow, but since it is directly electrically connected to the power semiconductor element, the heat transfer method is also good, There is a problem in that the temperature of the connection portion between the control circuit board and the control wiring rises locally, impairing reliability.

また、特に、パワー半導体素子として、ＳｉＣ等を用いて、パワー半導体素子を高温動作させた場合、パワー半導体素子温度が制御回路基板の耐熱温度、制御用半導体素子の耐熱温度より高い場合、制御配線と制御回路基板の接続部の温度が局所的に上昇する場合があるという問題点があった。   In particular, when the power semiconductor element is operated at a high temperature using SiC or the like as the power semiconductor element, when the power semiconductor element temperature is higher than the heat resistance temperature of the control circuit board and the heat resistance temperature of the control semiconductor element, the control wiring There is a problem that the temperature of the connection portion of the control circuit board may locally rise.

本発明は、上記のような問題を解決するためになされたものであり、発熱量の大きいパワー半導体素子を使用する半導体装置においても、高い放熱性を有し、制御用半導体素子
及び制御回路基板に熱的な悪影響を与えない半導体装置を提供することを目的としている。 The present invention has been made to solve the above-described problems, and has high heat dissipation even in a semiconductor device using a power semiconductor element having a large calorific value, and has a control semiconductor element and a control circuit board. An object of the present invention is to provide a semiconductor device that does not adversely affect heat.

上記課題を解決するために、本発明の半導体装置は、パワー半導体素子と、前記パワー半導体素子を制御する制御用半導体素子が搭載された制御回路基板と、前記パワー半導体素子及び前記制御回路基板が収容される筐体と、前記パワー半導体素子と前記制御回路基板とを電気的に接続する制御配線と、を備え、前記制御配線は、前記制御回路基板側の先端部が延伸され、当該先端部が前記筐体の内壁と接触、もしくは前記筐体に設けられた貫通孔に少なくとも達するように配置されていることを特徴とするものである。   In order to solve the above problems, a semiconductor device according to the present invention includes a power semiconductor element, a control circuit board on which a control semiconductor element for controlling the power semiconductor element is mounted, the power semiconductor element and the control circuit board. A housing to be accommodated, and a control wiring for electrically connecting the power semiconductor element and the control circuit board, and the control wiring is extended at a tip end on the control circuit board side, and the tip end Is arranged so as to be in contact with the inner wall of the housing or at least reach a through hole provided in the housing.

本発明の半導体装置によれば、パワー半導体素子と制御回路基板とを接続する制御配線の一端を筐体に近傍もしくは筐体外に露出させることにより、発熱量の大きいパワー半導体の熱により生じる制御回路基板や制御用半導体素子の温度上昇を抑制することができ、熱的な損傷から保護することができ半導体装置の信頼性を向上させることができる。   According to the semiconductor device of the present invention, the control circuit that is generated by the heat of the power semiconductor that generates a large amount of heat by exposing one end of the control wiring connecting the power semiconductor element and the control circuit board to the vicinity of the casing or outside the casing. The temperature rise of the substrate and the control semiconductor element can be suppressed, the thermal damage can be protected, and the reliability of the semiconductor device can be improved.

実施の形態１に係る半導体装置を示す模式断面図である。1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. 実施の形態１における制御配線部の要部を示す部分模式断面図である。FIG. 3 is a partial schematic cross-sectional view showing a main part of a control wiring portion in the first embodiment. 実施の形態１における制御配線の構成例を示す模式斜視図である。FIG. 3 is a schematic perspective view illustrating a configuration example of a control wiring in the first embodiment. 実施の形態１に係る半導体装置の他の実施態様を示す模式断面図である。6 is a schematic cross-sectional view showing another embodiment of the semiconductor device according to the first embodiment. FIG. 実施の形態１に係る半導体装置のさらに他の実施態様を示す模式断面図である。FIG. 6 is a schematic cross-sectional view showing still another embodiment of the semiconductor device according to the first embodiment. 実施の形態２における制御配線の要部を示す部分模式断面図である。FIG. 6 is a partial schematic cross-sectional view showing a main part of a control wiring in a second embodiment. 実施の形態３における制御配線の要部を示す部分模式断面図である。FIG. 10 is a partial schematic cross-sectional view showing a main part of a control wiring in a third embodiment. 実施の形態４に係る半導体装置であるインバータを示す模式断面図である。FIG. 6 is a schematic cross-sectional view showing an inverter that is a semiconductor device according to a fourth embodiment. 実施の形態４におけるインバータの他の実施態様を示す模式断面図である。FIG. 10 is a schematic cross-sectional view showing another embodiment of the inverter in the fourth embodiment.

以下、本発明の実施の形態に係る半導体装置について図１〜図９に基づいて説明する。   A semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS.

実施の形態１．
図１は、実施の形態１に係る半導体装置を示す模式断面図であり、図２は、この制御配線部の要部を示す部分模式断面図であり、また、図３は、制御配線の構造例を示す模式斜視図である。 Embodiment 1 FIG.
FIG. 1 is a schematic cross-sectional view showing the semiconductor device according to the first embodiment, FIG. 2 is a partial schematic cross-sectional view showing the main part of the control wiring portion, and FIG. 3 shows the structure of the control wiring. It is a model perspective view which shows an example.

図１に示すように、半導体装置１は、パワー半導体素子２と、このパワー半導体素子２が載置される銅パターンが両面に形成された絶縁体３と、このパワー半導体素子２を制御する制御用半導体素子４と、この制御用半導体素子４が搭載された制御回路基板５と、パワー半導体素子２と制御回路基板５とを電気的に接続する制御配線６（リード（薄い導電性の板）で構成された６ａ，６ｂとアルミワイヤで構成された６ｃ，６ｄ）と、パワー半導体素子２の大電流を取り出す電極７（７ａ，７ｂ）と、このパワー半導体素子２と電極７を接続するアルミワイヤ８（８ａ,８ｂ）と、これらを収容する筐体９（ここで、筐体９は、絶縁体３が載置され熱伝導体で形成される熱拡散板９ａと、絶縁体で形成される側部９ｂ及び天板９ｃとで構成されている）と、パワー半導体２の周囲を覆うゲル状の絶縁樹脂１０と、制御信号を制御回路基板５に送る制御信号入力端子１１と、この制御信号入力端子１１を補強する補強部材１２とで構成されている。また、図２の制御配線６ａ、６ｂの先端部６ｔの詳細図に示すようには、制御配線６ａ、６ｂの先端部６ｔは、天板９ｃに設けられた貫通孔１３を通り筐体９の外部に突出されており、さらに絶縁材である熱伝
導性樹脂１４で被覆され、熱伝導性樹脂１４の表面に導電体キャップ１５が設置されている。筐体９の天板９ｃには、導電体キャップ１５を取り付けるためのネジ１６用の溝１６ａが設けられている。また、図３に、リードで構成された制御配線６ａ，６ｂの構造例を示す。 As shown in FIG. 1, the semiconductor device 1 includes a power semiconductor element 2, an insulator 3 on which both sides of the copper pattern on which the power semiconductor element 2 is placed, and a control for controlling the power semiconductor element 2. Semiconductor element 4, control circuit board 5 on which this control semiconductor element 4 is mounted, and control wiring 6 (lead (thin conductive plate) for electrically connecting power semiconductor element 2 and control circuit board 5. 6a, 6b, 6c, 6d) made of aluminum wire, electrodes 7 (7a, 7b) for taking out a large current of the power semiconductor element 2, and aluminum for connecting the power semiconductor element 2 and the electrode 7 Wires 8 (8a, 8b) and a housing 9 for housing them (here, the housing 9 is formed of a heat diffusion plate 9a on which the insulator 3 is placed and formed of a heat conductor, and an insulator. Side part 9b and top plate 9c. A gel-like insulating resin 10 that covers the periphery of the power semiconductor 2, a control signal input terminal 11 that sends a control signal to the control circuit board 5, and a reinforcing member 12 that reinforces the control signal input terminal 11. It is configured. Further, as shown in the detailed view of the front end portion 6t of the control wirings 6a and 6b in FIG. 2, the front end portion 6t of the control wirings 6a and 6b passes through the through holes 13 provided in the top plate 9c. It protrudes to the outside, is further covered with a heat conductive resin 14 that is an insulating material, and a conductor cap 15 is installed on the surface of the heat conductive resin 14. A groove 16 a for a screw 16 for attaching the conductor cap 15 is provided on the top plate 9 c of the housing 9. FIG. 3 shows an example of the structure of the control wirings 6a and 6b composed of leads.

なお、絶縁体３の上にパワー半導体素子２が配設されており、接触面は半田で接合されている。熱拡散板９ａは通常、導電体である銅板で作製されるが、パワー半導体素子２が高温になる場合、ヒートサイクルによる半田部の破壊を抑制するため、ＡｌＳｉＣやＣｕＭｏ合金等を用いてもよい。また、筐体９の側部９ｂ、天板９には耐熱性を有し、絶縁体であるＰＰＳが用いられる。アルミワイヤ８（８ａ,８ｂ）の代わりに、アルミ、銅等で作製された電気抵抗の小さいリードを用いてもよい。また、制御配線６におけるアルミワイヤ６ｃ、６ｄを、リードで形成してもよい。あるいは、リード６ａとアルミワイヤ６ｃ、リード６ｂとアルミワイヤ６ｄとがそれぞれリードで一体に形成されたものであってもよい。   In addition, the power semiconductor element 2 is arrange | positioned on the insulator 3, and the contact surface is joined with solder. The heat diffusing plate 9a is usually made of a copper plate as a conductor. However, when the power semiconductor element 2 is at a high temperature, AlSiC, CuMo alloy or the like may be used in order to suppress destruction of the solder part due to heat cycle. . Further, the side portion 9b of the housing 9 and the top plate 9 are heat resistant and PPS which is an insulator is used. Instead of the aluminum wire 8 (8a, 8b), a lead having a small electrical resistance made of aluminum, copper or the like may be used. Further, the aluminum wires 6c and 6d in the control wiring 6 may be formed by leads. Alternatively, the lead 6a and the aluminum wire 6c, and the lead 6b and the aluminum wire 6d may be integrally formed with the leads.

ここで、パワー半導体素子２としては、例えば、ＩＧＢＴ（ＩｎｓｕＩａｔｅｄ Ｇａｔｅ ＢｉｐｏＩａｒ Ｔｒａｎｓｉｓｔｏｒ）、もしくはＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ ＦｉｅＩｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）がある。   Here, as the power semiconductor element 2, for example, there is an IGBT (Insulated Gate BipoIar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Id Effect Transistor).

次に、半導体装置１の動作を図１及び図２を用いて説明する。
まず、制御回路基板５上の制御用半導体素子４は、制御信号入力端子１１からの入力信号に従って、制御配線６（６ａ，６ｂ，６ｃ，６ｄ）を通してパワー半導体素子２に制御信号を送る。これによりパワー半導体素子２は、オン／オフ動作を行い、接続されたアルミワイヤ８ａ，８ｂを通して電極７ａ，７ｂ間での大電流の流れを制御する。これに伴ってパワー半導体素子２が発熱し、この熱は絶縁体３を介して、熱拡散板９ａから外部へ放散され、パワー半導体素子２が冷却される。しかし、この熱の一部が制御配線６（６ａ，６ｂ，６ｃ，６ｄ）を通して、制御回路基板５及び制御用半導体素子４の温度を上昇させる。この熱によって、これら制御回路基板５及び制御用半導体素子４の温度が耐熱温度を超える場合には不具合が発生する。制御回路基板５及び制御用半導体素子４をこの熱から守るため、制御配線６ａ，６ｂの先端部６ｔは、貫通孔１３を通して筐体９の天板９ｃから外部に突出されている。 Next, the operation of the semiconductor device 1 will be described with reference to FIGS.
First, the control semiconductor element 4 on the control circuit board 5 sends a control signal to the power semiconductor element 2 through the control wiring 6 (6a, 6b, 6c, 6d) in accordance with the input signal from the control signal input terminal 11. As a result, the power semiconductor element 2 performs an on / off operation, and controls the flow of a large current between the electrodes 7a and 7b through the connected aluminum wires 8a and 8b. Along with this, the power semiconductor element 2 generates heat, and this heat is dissipated from the heat diffusion plate 9a through the insulator 3 to cool the power semiconductor element 2. However, a part of this heat raises the temperature of the control circuit board 5 and the control semiconductor element 4 through the control wiring 6 (6a, 6b, 6c, 6d). If the temperature of the control circuit board 5 and the control semiconductor element 4 exceeds the heat resistance temperature due to this heat, a problem occurs. In order to protect the control circuit board 5 and the control semiconductor element 4 from this heat, the front end portions 6t of the control wirings 6a and 6b protrude from the top plate 9c of the housing 9 to the outside through the through holes 13.

露出されている制御配線６ａ，６ｂの先端部６ｔは、図２に示すように絶縁材の熱伝導樹脂１４で被覆され、さらにその表面には、導電体キャップ１５が天板９ｃにネジ１６により取り付けられている。この導電体キャップ１５の材料は金属材料であれば、熱が拡散しやすく、制御配線６の冷却能力アップにつながる。また、外部の電気的なノイズを遮断して、安定動作が可能になる。さらに、熱伝導樹脂１４が絶縁材料で構成されておれば、万一、内部で短絡が発生した場合でも、大電流が制御配線６を経由して外部に漏れることを防ぐことができる効果もある。これにより制御配線６ａ，６ｂを伝ってきた熱は放散、冷却され、制御回路基板５及び制御用半導体素子４の温度上昇を低く抑えることができ、制御回路基板５及び制御用半導体素子４は熱的に保護される。   As shown in FIG. 2, the exposed end portions 6t of the control wirings 6a and 6b are covered with a heat conductive resin 14 which is an insulating material. Further, a conductor cap 15 is attached to the top plate 9c with screws 16 on the surface. It is attached. If the material of the conductor cap 15 is a metal material, heat easily diffuses, leading to an increase in the cooling capacity of the control wiring 6. In addition, external electrical noise can be cut off to enable stable operation. Furthermore, if the heat conductive resin 14 is made of an insulating material, it is possible to prevent a large current from leaking outside via the control wiring 6 even if a short circuit occurs inside. . As a result, the heat transmitted through the control wirings 6a and 6b is dissipated and cooled, so that the temperature rise of the control circuit board 5 and the control semiconductor element 4 can be kept low, and the control circuit board 5 and the control semiconductor element 4 are heated. Protected.

なお、熱伝導樹脂１４として、高熱伝導性樹脂が使用され、導電体キャップ１５と制御配線６間に高熱伝導性樹脂が挿入されている場合に、制御配線６の冷却能力を強化することが可能である。ここで、高熱伝導性樹脂とは、樹脂に良熱伝導の粒子が混入された材料であり、通常の樹脂の熱伝導率の約０．２Ｗ／ｍＫより、１桁以上高い（２Ｗ／ｍＫ）材料をいう。このような構成を採ることにより、制御配線６の放熱性を向上させることができる。   In addition, when the high thermal conductive resin is used as the thermal conductive resin 14 and the high thermal conductive resin is inserted between the conductor cap 15 and the control wiring 6, it is possible to enhance the cooling capacity of the control wiring 6. It is. Here, the high thermal conductive resin is a material in which particles having good thermal conductivity are mixed in the resin, and is higher by one digit or more than the thermal conductivity of about 0.2 W / mK of a normal resin (2 W / mK). Say material. By adopting such a configuration, the heat dissipation of the control wiring 6 can be improved.

また、制御配線６が図３に示す様に複数本並列に並んでいる場合、この熱伝導樹脂１４が、１つの部品で構成されていると、部品点数減少に有効である。   In addition, when a plurality of control wirings 6 are arranged in parallel as shown in FIG. 3, if the heat conductive resin 14 is composed of one component, it is effective for reducing the number of components.

また、導電体キャップ１５は、天板９ｃに固定するのに接着や半田等ネジ以外の方法で接合されていてもよい。   In addition, the conductor cap 15 may be joined by a method other than screws such as adhesion or soldering for fixing to the top plate 9c.

図４は、実施の形態１に係る半導体装置の他の実施態様を示す模式断面図である。図１及び図２に示す半導体装置では、制御配線６の先端部６ｔが、筐体９の天板９ｃを貫通して外部に露出される場合について説明したが、図４に示すように、制御配線６の先端部６ｔが、筐体９の側部９ｂを貫通して外部に露出させる場合であっても、同様の効果を奏するものである。   FIG. 4 is a schematic cross-sectional view showing another embodiment of the semiconductor device according to the first embodiment. In the semiconductor device shown in FIGS. 1 and 2, the case where the tip 6t of the control wiring 6 passes through the top plate 9c of the housing 9 and is exposed to the outside has been described. However, as shown in FIG. Even when the tip portion 6t of the wiring 6 penetrates the side portion 9b of the housing 9 and is exposed to the outside, the same effect can be obtained.

また、図５は、実施の形態１に係る半導体装置のさらに他の実施態様を示す模式断面図である。図１及び図２に示す半導体装置では、制御配線６は、制御回路基板５を貫通していたが、この実施態様では、制御配線６と制御回路基板５とは、分離されて配置されており、制御配線６と制御回路基板５とは細い導線７ｅ，７ｆで接続されている。この導線７ｅ，７ｆは、通常、アルミワイヤで構成されるが、電気を通す材料であれば、他の素材でも使用可能である。また、リードであってもよい。このような構造にすることで、制御配線６の冷却を促進させるとともに、パワー半導体素子２から制御回路基板５までの信号経路に細い導線が挿入されることで熱が伝わりにくくなり、制御回路基板５の局所的温度上昇を抑制することが可能である。また、制御配線６は、一端筐体９外部で露出された後、再度筐体内部に戻る構造であってもよい。このように、実施の形態１では、制御配線６の一部が筐体９を貫通して外気に露出する構造に対するものであり、制御配線６が露出される筐体の位置には当然のことながら依存しない。   FIG. 5 is a schematic cross-sectional view showing still another embodiment of the semiconductor device according to the first embodiment. In the semiconductor device shown in FIGS. 1 and 2, the control wiring 6 penetrates the control circuit board 5, but in this embodiment, the control wiring 6 and the control circuit board 5 are arranged separately. The control wiring 6 and the control circuit board 5 are connected by thin conducting wires 7e and 7f. The conducting wires 7e and 7f are usually made of aluminum wires, but other materials can be used as long as they are materials that conduct electricity. It may also be a lead. By adopting such a structure, cooling of the control wiring 6 is promoted and heat is not easily transmitted by inserting a thin conductive wire in the signal path from the power semiconductor element 2 to the control circuit board 5. 5 local temperature rise can be suppressed. Further, the control wiring 6 may have a structure in which the control wiring 6 returns to the inside of the housing again after being exposed outside the housing 9. As described above, in the first embodiment, a part of the control wiring 6 penetrates the housing 9 and is exposed to the outside air, and the position of the housing where the control wiring 6 is exposed is a matter of course. But do not depend.

これにより、制御配線６が筐体９を貫通して、外部に露出されているため制御配線６ａ，６ｂの先端部６ｔが冷却されるので、制御配線６と制御回路基板５の接続部の局所的な温度上昇を抑制することができる。特に、パワー半導体素子２がＳｉＣ等のワイドバンドギャップ半導体で構成され、制御回路基板５及び制御用半導体素子（ＩＣ）４の耐熱温度より高温で動作する場合でもあっても、従来と同様の仕様の制御回路基板及び制御用半導体素子を使用することができ、半導体装置を特別な仕様で製作することが不要となる。   As a result, the control wiring 6 penetrates the housing 9 and is exposed to the outside, so that the tip end 6t of the control wiring 6a, 6b is cooled. Temperature rise can be suppressed. In particular, even if the power semiconductor element 2 is composed of a wide band gap semiconductor such as SiC and operates at a temperature higher than the heat resistance temperature of the control circuit board 5 and the control semiconductor element (IC) 4, the same specifications as in the past are used. The control circuit board and the control semiconductor element can be used, and it is not necessary to manufacture the semiconductor device with a special specification.

このように、実施の形態１における半導体装置によれば、パワー半導体素子と制御回路基板とを接続する制御配線の一端を筐体外に露出させることにより、発熱量の大きいパワー半導体の熱により生じる制御回路基板や制御用半導体素子の温度上昇を抑制することができ、これらを熱的な損傷から保護することができるので半導体装置の信頼性を向上させることができるという顕著な効果がある。   As described above, according to the semiconductor device in the first embodiment, the control wiring that connects the power semiconductor element and the control circuit board is exposed to the outside of the housing, so that the control generated by the heat of the power semiconductor that generates a large amount of heat. Since the temperature rise of the circuit board and the control semiconductor element can be suppressed and these can be protected from thermal damage, there is a remarkable effect that the reliability of the semiconductor device can be improved.

実施の形態２．
図６は、実施の形態２における制御配線の要部を示す部分模式断面図である。
図１の実施の形態１と異なる点は、実施の形態２では、熱伝導樹脂１４が貫通孔１３に充填されており、また、制御配線６ａ，６ｂの先端部６ｔを筐体９から突出させず貫通孔１３内に留まらせ、貫通孔内にある熱伝導樹脂１４と接触させている点であり、その他の構成要素については同様であり、説明を省略する。 Embodiment 2. FIG.
FIG. 6 is a partial schematic cross-sectional view showing the main part of the control wiring in the second embodiment.
The difference from the first embodiment of FIG. 1 is that in the second embodiment, the heat conductive resin 14 is filled in the through holes 13 and the tip ends 6t of the control wirings 6a and 6b are projected from the housing 9. The other components are the same because they remain in the through holes 13 and are in contact with the heat conductive resin 14 in the through holes.

筐体９の天板９ｃの貫通孔１３内に熱伝導樹脂１４が充填されており、制御配線６ａ，６ｂの先端部６ｔは、この熱伝導樹脂１４内で接触されている。熱伝導樹脂１４の上部は、導電体板１７で覆われ、この導電体板１７はネジ１６で天板９ｃに固定されている。制御配線６ａ，６ｂの熱は、熱伝導樹脂１４を通して導電体板１７に伝達され冷却される。これにより、パワー半導体素子２の熱が、制御配線６ａ，６ｂを伝わって制御回路基板５や制御用半導体素子４の温度を上昇させることを軽減、抑制することができる。   The through hole 13 of the top plate 9 c of the housing 9 is filled with the heat conductive resin 14, and the tip ends 6 t of the control wirings 6 a and 6 b are in contact with each other in the heat conductive resin 14. The upper part of the heat conductive resin 14 is covered with a conductor plate 17, and this conductor plate 17 is fixed to the top plate 9 c with screws 16. The heat of the control wires 6a and 6b is transmitted to the conductor plate 17 through the heat conductive resin 14 and cooled. Thereby, it is possible to reduce or suppress the heat of the power semiconductor element 2 from being transmitted through the control wirings 6 a and 6 b and raising the temperature of the control circuit board 5 and the control semiconductor element 4.

このような構成によれば、冷却効果は、実施の形態１の制御配線６ａ，６ｂの先端部６ｔを筐体９から貫通させた場合と比較して小さいが、制御配線６が筐体９の天板９ｃより外部に突出していないため、外観上シンプルになるとともに、使用方法ミスによる突出した制御配線６ａ，６ｂの先端部６ｔの座屈等を防ぐという利点がある。   According to such a configuration, the cooling effect is small as compared with the case where the front end portions 6t of the control wirings 6a and 6b of Embodiment 1 are penetrated from the housing 9, but the control wiring 6 Since it does not protrude outward from the top plate 9c, there are advantages in that it is simple in appearance and prevents buckling of the protruding end portions 6t of the control wirings 6a and 6b due to a usage error.

このように、実施の形態２に係る半導体装置によれば、パワー半導体素子と制御回路基板とを接続する制御配線の一端を筐体の貫通孔の熱伝導樹脂に接触させることにより、発熱量の大きいパワー半導体素子の熱により生じる制御回路基板や制御用半導体素子の温度上昇を抑制することができ、これらを熱的な損傷から保護することができるので半導体装置の信頼性を向上させることができるという顕著な効果がある。   As described above, according to the semiconductor device of the second embodiment, one end of the control wiring that connects the power semiconductor element and the control circuit board is brought into contact with the heat conductive resin in the through hole of the housing, thereby The temperature rise of the control circuit board and the control semiconductor element caused by the heat of the large power semiconductor element can be suppressed, and these can be protected from thermal damage, so that the reliability of the semiconductor device can be improved. There is a remarkable effect.

実施の形態３．
図７は、実施の形態３における制御配線の要部を示す部分模式断面図である。
図１の実施の形態１と異なる点は、実施の形態３では、制御配線６ａ，６ｂの先端部６ｔを筐体９から突出させず、屈曲させて筐体９の内壁に接触させている点であり、その他の構成要素については同様であり、説明を省略する。 Embodiment 3 FIG.
FIG. 7 is a partial schematic cross-sectional view showing the main part of the control wiring in the third embodiment.
The difference from the first embodiment of FIG. 1 is that in the third embodiment, the tip ends 6t of the control wirings 6a and 6b are not projected from the housing 9, but are bent and brought into contact with the inner wall of the housing 9. The other components are the same and will not be described.

図７に示すように、制御配線６ａ，６ｂの先端部６ｔは、Ｌ字形に屈曲されており、一定の力で筐体９の天板９ｃの内壁に接触されている。貫通孔１３内に熱伝導樹脂１４が充填されており、この熱伝導樹脂１４内で接触されている。これにより、パワー半導体素子の熱は、制御配線６ａ，６ｂを伝わり、先端部６ｔから接触している筐体９の天板９ｃに伝達され冷却される。これにより、パワー半導体素子２の熱が、制御配線６ａ，６ｂを伝わって制御回路基板５や制御用半導体素子４の温度を上昇させることを軽減、抑制することができる。   As shown in FIG. 7, the front end portions 6t of the control wirings 6a and 6b are bent in an L shape and are in contact with the inner wall of the top plate 9c of the housing 9 with a constant force. The through hole 13 is filled with a heat conductive resin 14 and is in contact with the heat conductive resin 14. Thereby, the heat of the power semiconductor element is transmitted through the control wirings 6a and 6b, and is transmitted from the tip 6t to the top plate 9c of the housing 9 and is cooled. Thereby, it is possible to reduce or suppress the heat of the power semiconductor element 2 from being transmitted through the control wirings 6 a and 6 b and raising the temperature of the control circuit board 5 and the control semiconductor element 4.

Ｌ字形に屈曲させて筐体９の天板９ｃに接触させることにより、組立時に筐体９の天板９ｃが閉じられたときに必ず確実に制御配線６ａ，６ｂの先端部６ｔを接触させることができる。なお、筐体９の天板９ｃの温度は、外気温度に近くなっており、制御配線６ａ，６ｂの先端部６ｔを接触させることにより充分冷却することができる。例え、接触していなくても制御配線６ａ，６ｂの先端部６ｔが、天板９ｃ近傍にあれば冷却効果はあり、一般に、１ｍｍ程度の近傍であれば充分、冷却効果は認められる。   By bending it into an L shape and bringing it into contact with the top plate 9c of the housing 9, the top ends 6t of the control wires 6a and 6b are surely brought into contact when the top plate 9c of the housing 9 is closed during assembly. Can do. Note that the temperature of the top plate 9c of the housing 9 is close to the outside air temperature, and can be sufficiently cooled by bringing the tip ends 6t of the control wirings 6a and 6b into contact with each other. For example, even if they are not in contact with each other, the cooling effect can be obtained if the tip portions 6t of the control wirings 6a and 6b are in the vicinity of the top plate 9c.

このような構成によれば、冷却効果は、実施の形態１や実施の形態２の場合と比較して小さいが、実施の形態２と同様、制御配線６が筐体９の天板９ｃより外部に突出していないため、外観上シンプルになるとともに、使用方法ミスによる突出した制御配線６ａ，６ｂの先端部６ｔの座屈等を防ぐという利点がある。   According to such a configuration, the cooling effect is small compared to the case of the first and second embodiments, but the control wiring 6 is external to the top plate 9c of the housing 9 as in the second embodiment. Therefore, there is an advantage that the appearance is simplified and buckling or the like of the protruding end portions 6t of the control wirings 6a and 6b due to a usage error is prevented.

このように、実施の形態３に係る半導体装置によれば、パワー半導体素子と制御回路基板とを接続する制御配線の一端を筐体の内壁に接触させることにより、発熱量の大きいパワー半導体素子の熱により生じる制御回路基板や制御用半導体素子の温度上昇を抑制することができ、これらを熱的な損傷から保護することができるので半導体装置の信頼性を向上させることができるという顕著な効果がある。   As described above, according to the semiconductor device according to the third embodiment, one end of the control wiring that connects the power semiconductor element and the control circuit board is brought into contact with the inner wall of the housing, thereby The temperature rise of the control circuit board and the control semiconductor element caused by heat can be suppressed, and since these can be protected from thermal damage, there is a remarkable effect that the reliability of the semiconductor device can be improved. is there.

実施の形態４．
図８は、実施の形態４に係る半導体装置がインバータである場合を示す模式断面図である。
図８に示すように、インバータ１８は、パワー半導体素子２と、このパワー半導体素子２が載置される銅パターンが両面に形成された絶縁体３と、熱拡散板９ａと、このパワー
半導体素子２を制御する制御用半導体素子４と、この制御用半導体素子４が搭載された制御回路基板５と、パワー半導体素子２と制御回路基板５とを電気的に接続する制御配線６（薄い導電性の板で構成された６ａとアルミワイヤで構成された６ｃ）と、パワー半導体素子２の大電流を取り出す電極７と、この電極７にブスバ２０を介して接続されたコンデンサ２１と、パワー半導体２の周囲を覆う封止樹脂材料２３と、制御信号を制御回路基板５に送る制御信号入力端子１１と、この制御信号入力端子１１を補強する補強部材１２と、これらを収容する筐体９（ここで、筐体９は、天板９ｃと、側部９ｂと、グリースを介して熱拡散板９ａを取り付ける取付板１９で構成されている）と、で構成されている。取付板１９には、冷却流路２２が設けられており、パワー半導体素子２で発生した熱は冷却流路２２に流す冷媒で放熱される。また取付板１９には、コンデンサ２１が取り付けられている（ただし、コンデンサを取り付ける際、グリースは必ずしも必要ではない）。制御配線６の先端部６ｔは、実施の形態１と同様、図２の詳細図に示すように、天板９ｃに設けられた貫通孔１３を通り筐体９の外部に突出されており、さらに絶縁材である熱伝導性樹脂１４で被覆され、熱伝導性樹脂１４の表面に導電体キャップ１５が設置されている。 Embodiment 4 FIG.
FIG. 8 is a schematic cross-sectional view showing a case where the semiconductor device according to the fourth embodiment is an inverter.
As shown in FIG. 8, the inverter 18 includes a power semiconductor element 2, an insulator 3 on which both sides of the copper pattern on which the power semiconductor element 2 is placed, a heat diffusion plate 9a, and the power semiconductor element. 2, a control circuit board 5 on which the control semiconductor element 4 is mounted, and a control wiring 6 (thin conductive) that electrically connects the power semiconductor element 2 and the control circuit board 5. 6a made of a metal plate and 6c made of an aluminum wire, an electrode 7 for taking out a large current of the power semiconductor element 2, a capacitor 21 connected to the electrode 7 through a bus bar 20, and a power semiconductor 2 A sealing resin material 23 that covers the periphery, a control signal input terminal 11 that sends a control signal to the control circuit board 5, a reinforcing member 12 that reinforces the control signal input terminal 11, and a housing 9 (this In a housing 9, a top plate 9c, and side 9b, and through the grease is composed of a mounting plate 19 for mounting the thermal diffusion plate 9a), in being configured. The mounting plate 19 is provided with a cooling flow path 22, and heat generated in the power semiconductor element 2 is dissipated by the refrigerant flowing through the cooling flow path 22. A capacitor 21 is mounted on the mounting plate 19 (however, grease is not always necessary when the capacitor is mounted). As shown in the detailed view of FIG. 2, the tip 6t of the control wiring 6 protrudes outside the housing 9 through the through hole 13 provided in the top plate 9c, as shown in the detailed view of FIG. It is covered with a heat conductive resin 14 that is an insulating material, and a conductor cap 15 is installed on the surface of the heat conductive resin 14.

なお、図１の実施の形態１では、金属の熱拡散板９ａが筐体９の一部になっているが、図８では、取付板１９が筐体９の一部となっている。また、筐体９は、例えば、Ａｌダイキャスト等で作製した金属であっても構わない。   In Embodiment 1 of FIG. 1, the metal heat diffusion plate 9 a is a part of the housing 9, but in FIG. 8, the mounting plate 19 is a part of the housing 9. Further, the housing 9 may be a metal produced by, for example, Al die casting.

また、図９は、インバータの他の実施態様を示す模式断面図である。図９に示すように、インバータ２４は、パワー半導体素子２と、パワー半導体素子２と半田で接合された熱拡散板９ａと、熱拡散板９ａの他方の面に取り付けられた絶縁性の樹脂３ｂ、銅箔２５と、このパワー半導体素子２を制御する制御用半導体素子４と、この制御用半導体素子４が搭載された制御回路基板５と、パワー半導体素子２と制御回路基板５とを電気的に接続する制御配線６（薄い導電性の板で構成された６ａ）と、パワー半導体素子２の大電流を取り出す電極７と、この電極７にブスバ２０を介して接続されたコンデンサ２１と、パワー半導体や熱拡散板９ａの周囲を覆う封止樹脂材料２３と、制御信号を制御回路基板５に送る制御信号入力端子１１と、この制御信号入力端子１１を補強する補強部材１２と、これらを収容する筐体９（天板９ｃと、側部９ｂと、取付板１９で構成されている）と、で構成されている。制御配線６の先端部６ｔは、実施の形態１と同様、図２の詳細図に示すように、天板９ｃに設けられた貫通孔１３を通り、筐体９の外部に突出されており、さらに絶縁材である熱伝導性樹脂１４で被覆され、熱伝導性樹脂１４の表面に導電体キャップ１５が設置されている。なお、樹脂３ｂは絶縁性を有していればよく、例えばセラミック等でもよい。この他の実施態様においても、上述した実施の形態４と同様の効果がある。   FIG. 9 is a schematic cross-sectional view showing another embodiment of the inverter. As shown in FIG. 9, the inverter 24 includes a power semiconductor element 2, a heat diffusion plate 9a bonded to the power semiconductor element 2 by solder, and an insulating resin 3b attached to the other surface of the heat diffusion plate 9a. The copper foil 25, the control semiconductor element 4 for controlling the power semiconductor element 2, the control circuit board 5 on which the control semiconductor element 4 is mounted, and the power semiconductor element 2 and the control circuit board 5 are electrically connected. A control wiring 6 (6a composed of a thin conductive plate) connected to the electrode 7, an electrode 7 for taking out a large current of the power semiconductor element 2, a capacitor 21 connected to the electrode 7 via a bus bar 20, and a power A sealing resin material 23 that covers the periphery of the semiconductor and the heat diffusion plate 9a, a control signal input terminal 11 that sends a control signal to the control circuit board 5, a reinforcing member 12 that reinforces the control signal input terminal 11, and these are accommodated You Housing 9 (and the top plate 9c, and side 9b, is composed of a mounting plate 19) and, in being configured. As shown in the detailed view of FIG. 2, the tip 6t of the control wiring 6 passes through the through hole 13 provided in the top plate 9c and protrudes to the outside of the housing 9, as in the first embodiment. Furthermore, it coat | covers with the heat conductive resin 14 which is an insulating material, and the conductor cap 15 is installed in the surface of the heat conductive resin 14. As shown in FIG. In addition, the resin 3b should just have insulation, for example, a ceramic etc. may be sufficient as it. This other embodiment also has the same effect as that of the fourth embodiment described above.

このようなインバータの場合であっても、パワー半導体素子２の動作を制御するため、制御配線６（アルミワイヤ６ｃ、リード６ａ）と制御回路基板５との接続部は温度が上昇するため、特に、パワー半導体素子がＳｉＣ等であり、高温動作する場合には問題となる。   Even in the case of such an inverter, in order to control the operation of the power semiconductor element 2, the temperature of the connection portion between the control wiring 6 (aluminum wire 6c, lead 6a) and the control circuit board 5 rises. When the power semiconductor element is SiC or the like and operates at a high temperature, it becomes a problem.

このような構成によれば、制御配線６の先端部６ｔが、筐体９の天板９ｃから突出されて、外部に露出されて冷却されることにより、制御配線６と制御回路基板５の接続部の局所的な温度上昇を抑制することができる。特に、パワー半導体素子２がＳｉＣ等であり、制御回路基板５、制御用半導体素子４の耐熱温度より高温で動作する場合であっても、従来と同様の制御用半導体素子、制御回路基板を使用することができ、特別な仕様が不要となる効果がある。   According to such a configuration, the front end portion 6t of the control wiring 6 protrudes from the top plate 9c of the housing 9 and is exposed to the outside to be cooled, whereby the connection between the control wiring 6 and the control circuit board 5 is achieved. The local temperature rise of the part can be suppressed. In particular, even when the power semiconductor element 2 is SiC or the like and operates at a temperature higher than the heat-resistant temperature of the control circuit board 5 and the control semiconductor element 4, the same control semiconductor element and control circuit board as in the past are used. This has the effect of eliminating the need for special specifications.

また、図４に示された実施の形態１の他の実施態様のように、制御配線６の先端部６ｔが、筐体９の側面部を貫通して外部に露出される場合であってもよい。また、実施の形態２あるいは実施の形態３と同様に、制御配線６の先端部６ｔが、筐体９から突出していな
い場合であってもよい。 Further, as in another embodiment of the first embodiment shown in FIG. 4, even when the tip portion 6 t of the control wiring 6 penetrates the side surface portion of the housing 9 and is exposed to the outside. Good. Further, similarly to the second embodiment or the third embodiment, the tip 6t of the control wiring 6 may not protrude from the housing 9.

このように、実施の形態４に係るインバータによれば、パワー半導体素子と制御回路基板とを接続する制御配線の一端を筐体の外部に突出させることにより、発熱量の大きいパワー半導体素子の熱により生じる制御回路基板や制御用半導体素子の温度上昇を抑制することができ、これらを熱的な損傷から保護することができるので半導体装置であるインバータの信頼性を向上させることができるという顕著な効果がある。   As described above, according to the inverter according to the fourth embodiment, one end of the control wiring connecting the power semiconductor element and the control circuit board is protruded to the outside of the housing, so that the heat of the power semiconductor element having a large heat generation amount can be obtained. As a result, it is possible to suppress the temperature rise of the control circuit board and the control semiconductor element caused by the above, and to protect them from thermal damage, so that the reliability of the inverter which is a semiconductor device can be improved. effective.

なお、パワー半導体素子２の半導体材料としては、シリコン半導体の他、ＳｉＣ（Ｓｉｌｉｃｏｎ Ｃａｒｂｉｄｅ）を始め、窒化ガリウム（ＧａＮ）、ダイアモンドといった珪素（Ｓｉ）に比べてバンドギャップが大きいワイドバンドギャップ半導体により形成されたパワー半導体素子であってもよい。   The semiconductor material of the power semiconductor element 2 is not only a silicon semiconductor but also a wide band gap semiconductor having a larger band gap than silicon (Si) such as SiC (Silicon Carbide), gallium nitride (GaN), and diamond. It may be a power semiconductor element.

また、ワイドバンドギャップ半導体によるパワー半導体素子では、耐電圧性が高く、許容電流密度も高いため、素子の小型化が可能であり、小型化されたパワー半導体素子を組み込んだ半導体装置の小型化が可能になる。   In addition, power semiconductor elements using wide bandgap semiconductors have high voltage resistance and high allowable current density, so the elements can be miniaturized, and semiconductor devices incorporating miniaturized power semiconductor elements can be miniaturized. It becomes possible.

なお、図において、同一符号は、同一または相当部分を示す。   In the drawings, the same reference numerals indicate the same or corresponding parts.

１ 半導体装置
２ パワー半導体素子
３，３ｂ 絶縁体
４ 制御用半導体素子
５ 制御回路基板
６ 制御配線
６ａ，６ｂ リード
６ｃ，６ｄ アルミワイヤ
９ 筐体（９ａ 熱拡散板、９ｂ 側部、９ｃ 天板、１９ 取付板）
１３ 貫通孔
１４ 熱伝導樹脂
１５ 導電体キャップ
１７ 導電体板
１８，２４ インバータ
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Power semiconductor element 3, 3b Insulator 4 Control semiconductor element 5 Control circuit board 6 Control wiring 6a, 6b Lead 6c, 6d Aluminum wire 9 Case (9a Heat diffusion plate, 9b side, 9c Top plate, 19 Mounting plate)
13 Through hole 14 Thermal conductive resin 15 Conductor cap 17 Conductor plate 18, 24 Inverter

Claims (12)

パワー半導体素子と、
前記パワー半導体素子を制御する制御用半導体素子が搭載された制御回路基板と、
前記パワー半導体素子及び前記制御回路基板が収容される筐体と、
前記パワー半導体素子と前記制御回路基板とを電気的に接続する制御配線と、を備え、
前記制御配線は、前記制御回路基板側の先端部が延伸され、当該先端部が前記筐体の内壁と接触、もしくは前記筐体に設けられた貫通孔に少なくとも達するように配置されていることを特徴とする半導体装置。 A power semiconductor element;
A control circuit board on which a control semiconductor element for controlling the power semiconductor element is mounted;
A housing that houses the power semiconductor element and the control circuit board;
Control wiring for electrically connecting the power semiconductor element and the control circuit board,
The control wiring is arranged such that a front end portion on the control circuit board side is extended and the front end portion is in contact with an inner wall of the housing or at least reaches a through hole provided in the housing. A featured semiconductor device. 前記先端部が、前記筐体の外部にまで延伸されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the tip portion extends to the outside of the housing. 前記先端部が、絶縁樹脂で被覆されていることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the tip portion is covered with an insulating resin. 前記絶縁樹脂の表面には、導電体キャップが設置されていることを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein a conductor cap is provided on a surface of the insulating resin. 前記貫通孔内に絶縁樹脂が充填されており、前記先端部が前記絶縁樹脂内にあることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the through-hole is filled with an insulating resin, and the tip portion is in the insulating resin. 前記筐体の外壁に前記貫通孔を覆う導電体板が設置されていることを特徴とする請求項５に記載の半導体装置。   The semiconductor device according to claim 5, wherein a conductor plate that covers the through hole is provided on an outer wall of the housing. 前記先端部が、Ｌ字状に屈曲され、前記筐体の内壁に接触されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the tip portion is bent in an L shape and is in contact with an inner wall of the housing. 前記絶縁樹脂が、熱伝導性樹脂であることを特徴とする請求項３または請求項５に記載の半導体装置。   The semiconductor device according to claim 3, wherein the insulating resin is a heat conductive resin. 前記制御回路基板もしくは前記制御用半導体素子の耐熱温度が前記パワー半導体素子の耐熱温度よりも低いことを特徴とする請求項１から請求項８のいずれか１項に記載の半導体装置。   9. The semiconductor device according to claim 1, wherein a heat-resistant temperature of the control circuit board or the control semiconductor element is lower than a heat-resistant temperature of the power semiconductor element. 前記パワー半導体素子は、ワイドバンドギャップ半導体素子によって形成されていることを特徴とする請求項１から請求項９のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the power semiconductor element is formed of a wide band gap semiconductor element. 前記ワイドバンドギャップ半導体素子は、炭化珪素、窒化ガリウム又はダイアモンドを材料とするものであることを特徴とする請求項１０に記載の半導体装置。   The semiconductor device according to claim 10, wherein the wide band gap semiconductor element is made of silicon carbide, gallium nitride, or diamond. 前記半導体装置は、インバータ装置であることを特徴とする請求項１から請求項１１のいずれか１項に記載の半導体装置。
The semiconductor device according to claim 1, wherein the semiconductor device is an inverter device.
JP2011095098A 2011-04-21 2011-04-21 Semiconductor device Active JP5558405B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011095098A JP5558405B2 (en) 2011-04-21 2011-04-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011095098A JP5558405B2 (en) 2011-04-21 2011-04-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2012227424A true JP2012227424A (en) 2012-11-15
JP5558405B2 JP5558405B2 (en) 2014-07-23

Family

ID=47277240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011095098A Active JP5558405B2 (en) 2011-04-21 2011-04-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JP5558405B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014203861A (en) * 2013-04-02 2014-10-27 三菱電機株式会社 Semiconductor device and semiconductor module
JP2015142018A (en) * 2014-01-29 2015-08-03 三菱電機株式会社 power semiconductor device
WO2017163583A1 (en) * 2016-03-22 2017-09-28 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243713A (en) * 2004-02-24 2005-09-08 Toshiba Corp Power module and mounting board
JP2008010617A (en) * 2006-06-29 2008-01-17 Matsushita Electric Ind Co Ltd Power semiconductor module

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005243713A (en) * 2004-02-24 2005-09-08 Toshiba Corp Power module and mounting board
JP2008010617A (en) * 2006-06-29 2008-01-17 Matsushita Electric Ind Co Ltd Power semiconductor module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014203861A (en) * 2013-04-02 2014-10-27 三菱電機株式会社 Semiconductor device and semiconductor module
JP2015142018A (en) * 2014-01-29 2015-08-03 三菱電機株式会社 power semiconductor device
WO2017163583A1 (en) * 2016-03-22 2017-09-28 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device
JPWO2017163583A1 (en) * 2016-03-22 2018-06-07 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
US10283440B2 (en) 2016-03-22 2019-05-07 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP5558405B2 (en) 2014-07-23

Similar Documents

Publication Publication Date Title
JP6237912B2 (en) Power semiconductor module
CN101847620B (en) Power module
US7679182B2 (en) Power module and motor integrated control unit
JP7023298B2 (en) Power converter and manufacturing method of power converter
KR100752239B1 (en) Power module package structure
US10163752B2 (en) Semiconductor device
JP2013123014A (en) Semiconductor device
JP5851599B2 (en) Power module
JP2018196180A (en) Power conversion device power module, power conversion device, rotary electric machine integrated with control device
CN110933900B (en) Electrical device and heat sink
JP2022160154A (en) Semiconductor device
CN111418049B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
JP7379886B2 (en) semiconductor equipment
US20240186221A1 (en) Semiconductor device
JP2019161967A (en) Power conversion device
JP5558405B2 (en) Semiconductor device
JP5101971B2 (en) Semiconductor device
JP2019013079A (en) Power semiconductor device and power conversion equipment using the same
JP2020184561A (en) Semiconductor device
CN111587528A (en) Power semiconductor device
JP2020087966A (en) Semiconductor module and semiconductor device using the same
CN212783425U (en) IGBT power semiconductor module structure capable of monitoring temperature
JP7392319B2 (en) semiconductor equipment
CN220963320U (en) Electronic equipment
JP7337214B1 (en) power converter

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130927

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140129

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140225

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140410

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140507

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140604

R151 Written notification of patent or utility model registration

Ref document number: 5558405

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250