JP2012227269A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having reduced rush current and power noise occurring when a power-supply control region is switched from a power-supply cutoff state to a power-supply feeding state.SOLUTION: A semiconductor device comprises a first switch cell SWa and a second switch cell SWb. The first switch cell SWa has a first switch transistor 11 that starts supplying a power-supply voltage from global power-supply wiring GVDD to local power-supply wiring LVDD based on a control signal CNT and a first signal transmission section that transmits the control signal CNT. The second switch cell SWb has a second switch transistor 21 that starts supplying the power-supply voltage from the global power-supply wiring GVDD to the local power-supply wiring LVDD based on the logic level of the control signal CNT and a second signal transmission section that cuts off the transmission of the control signal CNT to a post-stage circuit for a period of time until the voltage value of the local power-supply wiring LVDD reaches the threshold voltage.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a constant power supply region where power is constantly supplied and a power control region where supply and interruption of power are controlled.

  In recent years, semiconductor devices have been strongly demanded to reduce power consumption. Therefore, by reducing the power consumption of the semiconductor device by arranging the circuit that realizes the function of the semiconductor device in a plurality of regions and switching between power supply and cutoff for each region according to the operation of the semiconductor device. Has been done. In view of this, Patent Documents 1 to 4 propose techniques for performing power supply control for each region of a semiconductor chip in a semiconductor device.

  A circuit diagram of the switch cell SWC described in Patent Document 1 is shown in FIG. As shown in FIG. 15, the switch cell SWC includes a delay element (delay circuit DLY), a control signal input terminal SIN, a control signal output terminal SOUT, and a switch transistor SWTr. The delay circuit DLY delays the control signal input from the control signal input terminal SIN and outputs it to the control signal output terminal SOUT. The delay circuit DLY is connected between the global power supply wiring GVDD and the ground wiring, and operates without depending on the power supplied to the power supply control region. In Patent Document 1, it is assumed that the delay circuit DLY drives the switch transistor SWTr in the same cell. That is, the delay circuit DLY has both a function as a control signal delay circuit and a function as a drive buffer provided for the switch transistor SWTr. Note that the delay circuit DLY may drive the switch transistor SWTr in the switch cell arranged in the next stage. The switch transistor SWTr is configured by, for example, a PMOS transistor. The source of the switch transistor SWTr is connected to the global power supply line GVDD, and the drain is connected to the local power supply line LVDD. A control signal input from the control signal input terminal SIN is given to the gate of the switch transistor SWTr. Then, the switch transistor SWTr controls the conduction state between the global power supply wiring GVDD and the local power supply wiring LVDD according to the logic level of the control signal.

  In the semiconductor device according to Patent Document 1, a plurality of switch cells SWC shown in FIG. 15 are arranged in the power control region. Then, the connection of the delay circuit DLY of the switch cell SWC is changed according to the order of the switch cells to be turned on. FIG. 16 shows a schematic diagram of the switch cell SWC arranged in the power control region. As shown in FIG. 16, in Patent Document 1, switch cells SWC are arranged on a matrix in the power supply control region. Then, the switch cells SWC are classified into a chain portion and a tree portion according to the sequence in which the switch cells SWC are turned on. The tree part in Patent Document 1 is arranged at the subsequent stage of the chain part. Note that the arrows shown in FIG. 16 indicate the propagation direction of the control signal CONT. Further, in FIG. 16, a number for specifying a switch cell is added after the code indicating the switch cell SWC.

  By arranging and connecting the switch cells SWC as shown in FIG. 16, the control signal CONT is gradually propagated between the switch transistors SWTr by the delay circuit DLY, and the number of switch transistors SWTr to be turned on is gradually increased. In Patent Document 1, the peak value of the inrush current can be reduced by gradually increasing the number of switch transistors SWTr that are turned on.

  Patent Documents 2 and 3 also disclose a method for reducing the peak value of the inrush current by delaying the propagation of a control signal for controlling the conduction state of the switch transistor using a delay circuit or a delay element.

  Patent Document 4 discloses a technique for reducing a peak value of an inrush current by setting a switch transistor to a complete ON state after a half-ON state having a high resistance value. FIG. 17 is a block diagram of the power switch controller 132 provided in the semiconductor integrated circuit device described in Patent Document 4. As shown in FIG. 17, the power switch controller 132 includes a bias circuit (BIS) 321, a p-channel MOS transistor 323 (first driver), an n-channel MOS transistor 329, and a p-channel MOS transistor 324 (second driver). ), Control logic (LOG) 322, Schmitt circuit 325, voltage dividing resistor elements R11 and R12, and comparison circuit 326.

  P-channel MOS transistors 323 and 324 are coupled to high potential side power supply Vcc. The bias circuit 321 is activated when the request signal REQ is set to a low level, and supplies a predetermined bias voltage to the p-channel MOS transistor 323. As a result, a constant current I 0 flows through the p-channel MOS transistor 323. The n-channel MOS transistor 329 is turned off when the request signal REQ is set to high level and the output signal of the inverter 327 is set to low level. In this state, the gate signal GATE is set to the high level, and thereby the power switch 122 is turned on. The p-channel MOS transistor 324 is controlled by the control logic 322. When the p-channel MOS transistor 324 is turned on, the power supply switch 122 is turned on by setting the gate signal GATE to the high level. The load driving capability of the p-channel MOS transistor 324 is set larger than the load driving capability of the p-channel MOS transistor 323.

  The drive timing of the power switch 122 by the p-channel MOS transistor 323 is determined by the assertion timing of the request signal REQ, whereas the drive timing of the power switch 122 by the p-channel MOS transistor 324 is determined by the output signal of the control logic 322. Determined by. The control logic 322 obtains a logical sum of the request signal REQ, the output signal of the Schmitt circuit 325, and the control signal CNTL from the system controller, thereby forming a signal for controlling the p-channel MOS transistor 324. The gate signal GATE for driving the power switch 122 is transmitted to the Schmitt circuit 325 as the monitor signal MONI, and after being waveform-shaped there, is transmitted to the control logic 322. The output signal of the Schmitt circuit 325 is transmitted to the comparator 326, where it is compared with a reference voltage determined by a voltage dividing resistance element for dividing the potential of the high potential side power supply Vcc, thereby forming an acknowledge signal ACK. Is done. When the request signal REQ goes low, the n-channel MOS transistor 329 is turned on and the p-channel MOS transistors 323 and 324 are turned off, so that the gate signal GATE goes low and the power switch 122 is turned off. Is done. At this time, the circuit block 112 is turned off.

JP 2010-153535 A JP 2010-258267 A JP 2008-065732 A JP 2008-218722 A

  However, in Patent Documents 1 to 3, in order to perform control for shifting the conduction timing of the switch transistor (hereinafter, this control is referred to as slow switch control), a delay circuit must be provided together with the switch transistor. Therefore, in Patent Documents 1 to 3, there is a problem that the number of delay elements increases in proportion to the area of the power control region, and the circuit area increases.

  Further, in the technique described in Patent Document 4, since the power switch controller 132 that controls the switch transistor is configured by an analog circuit such as a comparator or a bias circuit, when the circuit formed in the power cutoff region is a digital circuit, It is necessary to arrange the power switch controller 132 in a region other than the power cutoff region. Further, since the power switch controller 132 includes a comparator, a Schmitt circuit, a reference voltage generation circuit that generates a reference potential, and the like, there is a problem that the number of circuit elements is large and the circuit area increases.

  One aspect of the semiconductor device according to the present invention includes: a global power supply wiring that supplies a power supply voltage to a plurality of regions; a local power supply wiring that supplies the power supply voltage to one of the plurality of regions; First and second switch cells that switch supply and cutoff of the power supply voltage from the power supply wiring to the local power supply wiring based on a logic level of a control signal, the first switch cell including the control A first switch transistor that switches between the global power supply wiring and the local power supply wiring in a conductive state or a cut-off state in accordance with a logic level of the signal; and a first signal transmission unit that transmits the control signal; And the second switch cell brings the global power supply wiring and the local power supply wiring into a conductive state in accordance with the logic level of the control signal. A second switch transistor that switches between a switching state and a cutoff state; a second signal transmission unit that blocks transmission of the control signal to a subsequent circuit during a period until a voltage value of the local power supply wiring reaches a threshold voltage; And the second switch cell is arranged at a subsequent stage of the first switch cell.

  According to the semiconductor device of the present invention, the second switch cell does not supply the power supply voltage from the global power supply wiring to the local power supply wiring until the voltage value of the local power supply wiring exceeds the threshold voltage. According to the semiconductor device of the present invention, the voltage of the local power supply wiring is gradually increased by the first switch cell, and when the voltage value of the local power supply wiring exceeds the threshold voltage, the first switch cell and the second switch cell The voltage of the local power supply wiring is rapidly increased by the switch cell. In other words, according to the semiconductor device of the present invention, the peak value of the inrush current can be reduced by having the first and second switch cells to gradually increase the voltage value of the local power supply wiring. it can. At this time, in the semiconductor device according to the present invention, since it is not necessary to delay the propagation of the signal by a delay circuit or the like, it is possible to prevent the circuit area from being increased by adding the delay circuit.

  According to the semiconductor device of the present invention, it is possible to reduce inrush current and power supply noise that occur when the power supply control region is switched from the power supply cutoff state to the power supply state.

1 is a schematic diagram of a planar layout of a semiconductor device according to a first embodiment; 1 is a schematic diagram of a wiring layout of a semiconductor device according to a first embodiment; 2 is a block diagram showing an arrangement of switch cells of the semiconductor device according to the first exemplary embodiment; FIG. 1 is a block diagram of a switch cell of a semiconductor device according to a first embodiment; FIG. 3 is a circuit diagram of a second signal transmission unit according to the first embodiment. 3 is a timing chart showing operations of first and second switch cells of the semiconductor device according to the first exemplary embodiment; FIG. 3 is a schematic plan view illustrating an arrangement of switch cells in the semiconductor device according to the first embodiment. 4 is a timing chart of a start operation and a stop operation of a power control region in the semiconductor device according to the first embodiment. FIG. 6 is a schematic plan view illustrating the layout of switch cells in the semiconductor device according to the second embodiment. 7 is a schematic diagram of a planar layout for explaining the arrangement of switch cells in a semiconductor device according to a third embodiment; FIG. FIG. 6 is a schematic plan view illustrating the layout of switch cells in a semiconductor device according to a fourth embodiment. FIG. 9 is a block diagram of a switch cell of a semiconductor device according to a fifth embodiment. FIG. 10 is a circuit diagram of a Schmitt trigger circuit according to a fifth embodiment; 10 is a graph showing input / output characteristics of a Schmitt trigger circuit according to a fifth embodiment; 2 is a circuit diagram of a switch cell described in Patent Document 1. FIG. 10 is a schematic diagram of a planar layout for explaining the arrangement of switch cells in a semiconductor device described in Patent Document 1. FIG. 10 is a block diagram of a power switch controller of a semiconductor integrated circuit device according to Patent Document 4. FIG.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device according to the first embodiment includes an I / O region, a first region (for example, a power control region), and a second region (for example, a constant power supply region).

  The I / O region is a region where an external interface circuit in the semiconductor device is arranged. The external interface circuit includes, for example, an input / output circuit and a pad. In both the power control area and the constant power supply area, functional circuits that implement various functions mounted on the semiconductor device are arranged. In the first embodiment, the functional circuit is configured by combining cells (hereinafter referred to as standard cells) that realize the minimum function of the circuit.

  The power supply control region has a switch circuit (hereinafter referred to as a switch cell). The standard cells arranged in the power control region are supplied with power via the switch cells. That is, the standard cell arranged in the power control region is supplied with power when the switch cell is in an on state and is in an operable state, and when the switch cell is in an off state, the supply of power is cut off and is in a stopped state.

  On the other hand, the standard cells arranged in the constant power supply area are supplied with the power supplied from the outside without going through the switch cells. In other words, the standard cells arranged in the constant power supply region are always supplied with power while the power is supplied from the outside to the semiconductor device.

  Here, FIG. 2 shows a schematic diagram of a cross-sectional view of the semiconductor device along the line II-II shown in FIG. As shown in FIG. 2, the semiconductor device has a semiconductor substrate 1 and a plurality of wiring layers provided in an upper layer of the semiconductor substrate 1. In the example shown in FIG. 2, the number of wiring layers is three. However, in implementing the present invention, the number of wiring layers can be arbitrarily set.

  In a region corresponding to the constant power supply region in the semiconductor substrate 1, a transistor (simply referred to as a cell in FIG. 2) constituting a standard cell provided in the semiconductor device is formed, and in a region corresponding to the power control region Standard cells and switch cells SWC are formed.

  In the example shown in FIG. 2, the global power supply wiring GVDD is provided in the uppermost layer of the wiring layers. The global power supply wiring GVDD supplies power to a circuit formed in a circuit formation region (a region including a power control region and a constant power supply region) of the semiconductor device. The global power supply wiring GVDD is formed over the entire circuit formation region. The global power supply wiring GVDD is connected to a power supply pad provided in the I / O region, and is supplied with power from the outside.

  In the example shown in FIG. 2, the local power supply wiring LVDD is provided below the global power supply wiring GVDD. The local power supply wiring LVDD is formed separately in the power supply control region and the constant power supply region. Of the local power supply wiring LVDD, the local power supply wiring LVDD provided corresponding to the power supply control region is connected to the global power supply wiring GVDD via the switch cell SW. Further, the local power supply wiring LVDD provided corresponding to the power supply control region in the local power supply wiring LVDD supplies power to a circuit provided in the power supply control region. Of the local power supply wiring LVDD, the local power supply wiring LVDD provided corresponding to the constant power supply region is directly connected to the global power supply wiring GVDD. In addition, the local power supply wiring LVDD provided corresponding to the constant power supply region in the local power supply wiring LVDD supplies power to a circuit provided in the constant power supply region.

  In the example shown in FIG. 2, a cell wiring is provided below the local power supply wiring LVDD. The cell wiring is a wiring for connecting between standard cells formed on the semiconductor substrate 1 or between elements constituting the circuit. A part of the cell wiring can be used as the local power supply wiring LVDD. In this case, the cell wiring used as the local power supply wiring LVDD is directly connected to the switch cell SW.

  In the semiconductor device according to the first embodiment, the global power supply wiring GVDD and the local power supply wiring LVDD in the constant power supply region are connected by via wiring. The local power supply wiring LVDD and the cell wiring are connected by via wiring. The cell wiring and the standard cell are connected by contact wiring.

  Here, details of the switch cell SW according to the first embodiment will be described. In the semiconductor device according to the first embodiment, the switch cell SW includes a first switch cell SWa and a second switch cell SWb. FIG. 3 is a block diagram showing the arrangement of the switch cells of the semiconductor device according to the first embodiment. Note that FIG. 3 also shows the constant power supply region and the circuits provided in the constant power supply region in order to explain the power supply control circuit 1 that generates the control signal CNT to the switch cell.

  A power supply control circuit 1 and other circuits are provided in the constant power supply circuit area. The other circuit includes a circuit for realizing the function of the semiconductor device. The power supply control circuit 1 controls a control signal CNT that controls switching of the first switch cell SWa and the second switch cell SWb between a conduction state and a cutoff state. Since the power supply control circuit 1 is always arranged in the power supply area, it operates even during a period when the power supply to the power supply control area is stopped. The control signal CNT may be input from the outside without using the power supply control circuit 1.

  In the power control region, the first switch cell SWa, the second switch cell SWb, and a power control target circuit are arranged. The power control target circuit is a circuit that switches between supply and cutoff of the power supply voltage, and is a circuit that realizes the function of the semiconductor device. The first switch cell SWa switches between supply and cutoff of the power supply voltage from the global power supply wiring GVDD to the power supply control target circuit based on the logic level of the control signal CNT. Further, the first switch cell SWa transmits the input control signal CNT to the subsequent circuit. The second switch cell SWb switches between supply and cutoff of the power supply voltage from the global power supply wiring GVDD to the power supply control target circuit based on the logic level of the control signal CNT. The second switch cell SWb is arranged at the subsequent stage of the first switch cell SWa. The second switch cell SWb receives the control signal CNT that is transmitted to the subsequent circuit in response to the voltage value MON of the local power supply wiring that supplies the power supply voltage to the power control target circuit reaching the threshold voltage. CNT is transmitted to the subsequent circuit. In the semiconductor device according to the first embodiment, the second switch cell SWb is configured to start supplying power from the global power supply wiring to the local power supply wiring at the timing of outputting the control signal CNT.

  Next, a more detailed configuration of the first switch cell SWa and the second switch cell SWb will be described. FIG. 4 shows a block diagram of the switch cell of the semiconductor device according to the first embodiment. In the example shown in FIG. 4, the local power supply wiring LVDD, the ground wiring GND, and the cells are shown in the power control target circuit. The cell is connected between the local power supply line LVDD and the ground line GND. That is, the cell operates based on the power supply voltage applied to the local power supply wiring LVDD and the ground voltage supplied via the ground wiring GND.

  As shown in FIG. 4, the first switch cell SWa includes a first signal transmission unit and a first switch transistor 11. The first switch cell SWa has a control signal input terminal SWIN, a control signal output terminal SWOUT, a power input terminal PIN, and a power output terminal POUT. A global power supply line GVDD is connected to the power supply input terminal PIN, and a local power supply line LVDD is connected to the power supply output terminal POUT. A path from the control signal input terminal SWIN to the control signal output terminal SWOUT is the first signal transmission unit. The first signal transmission unit is a path for transmitting the control signal CNT. In the example shown in FIG. 4, a buffer circuit 10 is provided in the first signal transmission unit. The buffer circuit 10 operates based on the power supply voltage supplied from the global power supply wiring GVDD and the ground voltage supplied from the ground wiring GND. That is, the first switch cell SWa transmits the control signal CNT via the buffer circuit 10. The buffer circuit 10 is provided for the purpose of reducing the transmission delay of the control signal CNT.

  The first switch transistor 11 is formed by a PMOS transistor. The first switch transistor 11 has a source connected to the power input terminal PIN and a drain connected to the power output terminal POUT. A control signal CNT is input to the gate of the first switch transistor 11 via the buffer circuit 10. That is, the first switch transistor 11 switches whether the global power supply wiring and the local power supply wiring are brought into a conductive state or a cut-off state according to the logic level of the control signal CNT.

  The second switch cell SWb includes a second signal transmission unit and a second switch transistor 21. The second switch cell SWb has a control signal input terminal SWINa, a control signal output terminal SWOUT, a power supply input terminal PIN, and a power supply output terminal POUT. A global power supply line GVDD is connected to the power supply input terminal PIN, and a local power supply line LVDD is connected to the power supply output terminal POUT. A path from the control signal input terminal SWINa to the control signal output terminal SWOUT is a second signal transmission unit. The second signal transmission unit is a path for transmitting the control signal CNT. In the example shown in FIG. 4, a gating circuit 20 is provided in the second signal transmission unit. The gating circuit 20 cuts off the transmission of the control signal CNT to the subsequent circuit until the voltage value MON of the local power supply wiring LVDD exceeds the threshold voltage Vth. The gating circuit 20 operates based on the power supply voltage supplied from the global power supply wiring GVDD and the ground voltage supplied from the ground wiring GND. Details of the gating circuit 20 will be described later. Note that the voltage value MON of the local power supply wiring LVDD input to the inverting input terminal of the gating circuit 20 is connected to the first-layer power supply wiring wired in the vicinity of the second switch cell SWb. This is because the progress of the charge on the transistor layer is monitored by monitoring the voltage value MON of the power supply wiring of the first layer as well as the wiring layer.

  The second switch transistor 21 is formed by a PMOS transistor. The second switch transistor 21 has a source connected to the power input terminal PIN and a drain connected to the power output terminal POUT. A control signal CNT is input to the gate of the second switch transistor 21 via the gating circuit 20. That is, the second switch transistor 21 switches whether the global power supply line and the local power supply line are in a conductive state or a cut-off state according to the logic level of the control signal CNT output from the gating circuit 20.

  Here, details of the gating circuit 20 will be described. A circuit diagram of the gating circuit 20 is shown in FIG. The gating circuit 20 includes an inverter 30 and an OR circuit 31. The inverter 30 generates a determination signal MONb that becomes a low level when the voltage value MON of the local power supply wiring LVDD exceeds the threshold voltage Vth. The determination signal MONb is at a high level when the voltage value MON of the local power supply wiring LVDD is lower than the threshold voltage Vth. That is, the threshold voltage Vth of the gating circuit 20 is the threshold voltage Vt of the inverter 30. The OR circuit 31 outputs a logical sum operation result of the determination signal MONb and the control signal CNT as the control signal CNT.

  The inverter 30 includes an NMOS transistor N1 and a PMOS transistor P1. The NMOS transistor N1 has a source connected to the ground wiring GND and a drain connected to the drain of the PMOS transistor P1. The source of the PMOS transistor P1 is connected to the global power supply line GVDD. The gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are connected in common, and the voltage value MON of the local power supply wiring LVDD is input. Then, the determination signal MONb is output from the connection point between the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1. The threshold voltage Vth of the inverter 30 is generally a voltage value that is ½ of the voltage difference between the power supply voltage and the ground voltage. The threshold voltage Vth can be set high, for example, by inserting a resistor between the ground wiring GND and the source of the NMOS transistor N1.

  The OR circuit 31 includes NMOS transistors N2 to N4 and PMOS transistors P2 to P4. The source of the NMOS transistor N2 is connected to the ground wiring GND, and the determination signal MONb is input to the gate. The source of the NMOS transistor N3 is connected to the ground wiring GND, and the control signal CNT is input to the gate. The drains of the NMOS transistors N2 and N3 are connected to each other and to the drain of the PMOS transistor P3. A node to which the drains of the NMOS transistors N2 and N3 and the drain of the PMOS transistor P3 are connected is hereinafter referred to as a node ND. The source of the PMOS transistor P3 is connected to the drain of the PMOS transistor P2, and the control signal CNT is input to the gate. The source of the PMOS transistor P2 is connected to the global power supply wiring GVDD, and the determination signal MONb is input to the gate.

  The NMOS transistor N4 has a source connected to the ground wiring GND and a drain connected to the drain of the PMOS transistor P4. The source of the PMOS transistor P4 is connected to the global power supply line GVDD. The gate of the PMOS transistor P4 and the gate of the NMOS transistor N4 are connected in common and connected to the node ND. Then, a control signal CNT is output from the connection point between the drain of the PMOS transistor P4 and the drain of the NMOS transistor N4 to the subsequent circuit and the gate of the second switch transistor 21.

  When both the control signal CNT and the determination signal MONb are at the low level, the PMOS transistors P2 and P3 are turned on, and the NMOS transistors N2 and N3 are both turned off, so that the OR circuit 31 has a high level ( For example, a signal of power supply voltage) is generated. The OR circuit 31 outputs a control signal CNT of a low level (for example, ground voltage) by an inverter formed by the NMOS transistor N4 and the PMOS transistor P4. When at least one of the control signal CNT and the determination signal MONb is at a high level, at least one of the PMOS transistors P2 and P3 is turned off and at least one of the NMOS transistors N2 and N3 is turned on. 31 generates a low level signal at the node ND. The OR circuit 31 outputs a control signal CNT of a high level (for example, ground voltage) by an inverter formed by the NMOS transistor N4 and the PMOS transistor P4.

  Next, the operation of the semiconductor device when the first switch cell SWa and the second switch cell SWb are configured as shown in FIG. 4 will be described. A timing chart showing the operation of the semiconductor device having the first switch cell SWa and the second switch cell SWb is shown in FIG. The example shown in FIG. 6 mainly describes the operations of the first switch cell SWa and the second switch cell SWb. In the example shown in FIG. 6, the semiconductor device has four states according to the conduction state of the first switch cell SWa and the second switch cell SWb. In the following description, the operation of the semiconductor device will be described for each state of the semiconductor device.

  First, in the first state (state number 1 in FIG. 6), the control signal CNT input to the control signal input terminal SWIN of the first switch cell SWa is at a high level. For this reason, the control signal CNT output from the control signal output terminal SWOUT of the first switch cell also becomes a high level. In the first state, the power supply voltage is not supplied to the local power supply wiring LVDD. Therefore, the voltage of the local power supply wiring LVDD is almost the ground voltage. Therefore, in the first state, the determination signal MONb in the second switch cell SWb is at a high level. The second switch cell SWb is connected to the control signal output terminal SWOUT in response to the control signal CNT output from the first switch cell SWa provided in the previous stage being low level and the determination signal MONb being high level. Output high level. That is, in the first state, the first switch cell SWa and the second switch cell SWb are in a cut-off state, and the supply of the power supply voltage from the global power supply line GVDD to the local power supply line LVDD is cut off.

  Next, the operation in the second state (state number 2 in FIG. 6) will be described. In the second state, the control signal CNT output from the power supply control circuit 1 changes from the high level to the low level. In response to the transition of the logic level of the control signal CNT, the control signal CNT output from the first switch cell SWa also transitions to the low level. Then, in the first switch cell SWa, the first switch transistor 11 is turned on, and supply of the power supply voltage from the global power supply wiring GVDD to the local power supply wiring LVDD is started. Therefore, in the second state, the voltage of the local power supply line LVDD increases. In addition, when the first switch transistor 11 is switched from the off state to the on state, a current flows into the blocking capacity of the transistor constituting the cell arranged in the power control target circuit and the wiring capacity of the power control target circuit. Electric current is generated. In addition, the voltage of the global power supply wiring GVDD temporarily decreases in accordance with the occurrence of the inrush current. The drop of the inrush current and the voltage generated at this time is limited by the capability of the first switch transistor 11 to turn on.

  In the second state, the voltage value MON of the local power supply wiring LVDD is equal to or lower than the threshold voltage Vth of the inverter 30 of the second switch cell SWb. Therefore, the determination signal MONb output from the inverter 30 maintains a high level. Therefore, even when the control signal CNT output from the first switch cell SWa becomes low level, the control signal CNT output from the second switch cell SWb maintains high level. In the second switch cell SWb, since the output control signal CNT is maintained at the high level, the second switch transistor 21 is maintained in the cutoff state.

  Next, the operation in the third state (state number 3 in FIG. 6) will be described. In the third state, the control signal CNT output from the power supply control circuit 1 maintains the low level. As a result, the control signal CNT output from the first switch cell SWa also maintains the low level. Therefore, in the first switch cell SWa, the first switch transistor 11 is kept on, and the supply of the power supply voltage from the global power supply wiring GVDD to the local power supply wiring LVDD is continued.

  In the third state, the voltage value MON of the local power supply wiring LVDD exceeds the threshold voltage Vth of the inverter 30 of the second switch cell SWb. Therefore, the determination signal MONb output from the inverter 30 transitions from the high level to the low level. Thereby, the OR circuit 31 switches the logic level of the output control signal CNT from the high level to the low level. That is, the control signal CNT output from the second switch cell SWb transitions from a high level to a low level. In the second switch cell SWb, the second switch transistor 21 is switched from the off state to the on state in accordance with the switching of the logic level of the output control signal CNT. As a result, supply of power supply voltage from the global power supply wiring GVDD to the local power supply wiring LVDD is started via the second switch transistor 21. That is, in the third state, the power supply voltage is supplied to the local power supply wiring LVDD using the first switch transistor 11 and the second switch transistor 21.

  At the start of the third state, an inrush current is generated according to an increase in the number of switch transistors that are turned on. Since the voltage of the local power supply wiring LVDD is higher than the start time of the second state, the inrush current is smaller than the inrush current generated at the start time of the second state. Further, as the inrush current decreases, the voltage drop amount of the global power supply wiring GVDD also decreases. In the third state, as the number of switch transistors that supply the power supply voltage to the local power supply line LVDD increases, the voltage increase rate of the local power supply line LVDD increases. Note that in the third state, the voltage of the local power supply wiring LVDD rises to a voltage equal to the voltage of the global power supply wiring GVDD.

  Next, the operation in the fourth state (state number 4 in FIG. 6) will be described. In the fourth state, the control signal CNT output from the power supply control circuit 1 changes from the low level to the high level. In response to the transition of the logic level of the control signal CNT, the control signal CNT output from the first switch cell SWa also transitions to a high level. In the first switch cell SWa, the first switch transistor 11 is turned off, and supply of the power supply voltage from the global power supply wiring GVDD to the local power supply wiring LVDD is stopped. Further, the gating circuit 20 of the second switch cell SWb (that is, the OR circuit 31 in the gating circuit 20) outputs in response to the transition of the logic level of the control signal CNT output from the first switch cell SWa. The control signal CNT also changes to a high level. In the second switch cell SWb, the second switch transistor 21 is switched off, and supply of the power supply voltage from the global power supply wiring GVDD to the local power supply wiring LVDD is stopped.

  That is, in the fourth state, both the first switch transistor 11 and the second switch transistor 21 are cut off. In response to this, the voltage value MON of the local power supply wiring LVDD decreases. When the voltage value MON of the local power supply line LVDD falls below the threshold voltage Vth of the inverter 30 of the gating circuit 20, the determination signal MONb changes from the low level to the high level and returns from the fourth state to the first state.

  As described above, in the semiconductor device according to the first embodiment, the slow switch control is realized by switching the conduction state of the second switch cell SWb according to the voltage value MON of the local power supply wiring LVDD. However, when actually designing a semiconductor device, the area of the power control region is larger than the area that can be controlled by only two switch cells. Therefore, an arrangement example of the first switch cell SWa and the second switch cell SWb will be described. FIG. 7 is a schematic diagram of a planar layout for explaining the arrangement of switch cells in the semiconductor device according to the first embodiment. In FIG. 7, numbers indicating the order in which the control signal CNT propagates are shown on the switch cell.

  As shown in FIG. 7, in a layout that is closer to reality, switch cells are arranged in a matrix in the power supply control region. Then, the second switch cell SWb is arranged at the subsequent stage of the first switch cell. In addition, when there are a plurality of second switch cells SWb, the first switch cells SWa are arranged so as to be inserted between the two second switch cells SWb. With this arrangement, it is possible to set the number of switch transistors that are simultaneously turned on by the first switch cell SWb inserted between the second switch cells SWb.

  In the example shown in FIG. 7, the switch cells in the order of propagation of the control signal CNT are arranged so that the control signal CNT propagates in series, and the switch cells after the 52nd are controlled by the control signal CNT. Is arranged to propagate in a tree shape. In the example shown in FIG. 7, the switch cell through which the control signal CNT propagates at the 30th, 35th, 40th, and 45th is configured by the second switch cell SWb, and the other switch cells are the first switch cell. It consists of SWa.

  Next, the operation of the semiconductor device according to the first embodiment corresponding to the arrangement example of the switch cell shown in FIG. 7 will be described. FIG. 8 shows a timing chart of the start operation and the stop operation in the power control region (arrangement example in FIG. 7) in the semiconductor device according to the first embodiment.

  In the example shown in FIG. 8, at timing t1, the control signal CNT output from the power supply control circuit 1 transits from a high level to a low level. Then, the first to 29th switch cells are turned on in response to the transition of the control signal CNT. At the timing t1, the voltage value MON of the local power supply wiring LVDD increases in accordance with the switch that is turned on. The rate of increase of this voltage varies depending on the position of the power supply control region. Specifically, the local power supply wiring LVDD near the area where the first to 29th switches are arranged rapidly reaches the voltage of the global power supply wiring GVDD. On the other hand, the voltage increase rate of the local power supply wiring LVDD in the region where the switch cells (30th and subsequent switch cells) that are still in the off state are arranged is the local power supply wiring in the vicinity of the region where the first to 29th switches are arranged. It becomes smaller than the voltage increase rate of LVDD. This is because the local power supply line LVDD far from the switch cell in the on state has a parasitic resistance component that increases according to the distance from the switch cell in the on state, and thus a voltage drop occurs due to the parasitic resistance component.

  Subsequently, an operation after the timing t2 will be described. After the timing t2, the second switch cells SWb arranged at the 30th, 35th, 40th, and 45th positions are sequentially switched to the ON state at each timing from the timing t2 to the time t5. This is because the threshold voltage Vth of the second switch cell SWb arranged at the 30th, 35th, 40th, and 45th times is set to the voltage of the local power supply wiring LVDD near the switch cell at each time point from timing t2 to t5. This is because the value MON exceeds. Then, the local power supply wiring LVDD rises rapidly when the threshold voltage Vth of the second switch cell SWb is exceeded.

  In the example illustrated in FIG. 8, the number of switch cells that are turned on at each time point in the timings t1 to t5 increases. Therefore, an inrush current is generated at each time point of timings t1 to t5. This inrush current decreases with time from timing t1 to t5. This is due to the fact that the uncharged parasitic capacitance decreases with time and that the voltage value MON of the local power supply wiring LVDD increases with time. Further, as the inrush current decreases, the voltage drop of the global power supply wiring GVDD also decreases.

  From the above description, the semiconductor device according to the first embodiment has the first switch cell SWa and the second switch cell SWb in the power control region. The second switch cell SWb maintains the OFF state and transmits it to the subsequent circuit until the voltage value MON of the local power supply line LVDD to which the switch cell supplies the power supply voltage reaches a preset threshold voltage Vth. The control signal CNT is maintained at a value (for example, high level) indicating the OFF state of the switch cell. On the other hand, the first switch cell SWa immediately transmits the input control signal CNT to the subsequent circuit and immediately turns on according to the input control signal CNT. In the semiconductor device according to the first embodiment, the control signal CNT is transmitted to the first switch cell SWa and then transmitted to the second switch cell SWb. Thereby, in the semiconductor device according to the first embodiment, the first switch cell SWa and the second switch cell SWb are prevented from being simultaneously turned on. By arranging the switch cells in this way, in the semiconductor device according to the first embodiment, the inrush current flowing from the global power supply wiring GVDD to the power supply control region is dispersed and the peak value of the inrush current flowing at a time is reduced. be able to.

  In addition, the second switch cell SWb has a later timing for switching to the ON state than the first switch cell SWa. Conventionally, the amount of delay time for switching the switch cell to the ON state is set by a delay circuit such as a capacitor. Therefore, conventionally, in order to set the delay amount, it has been necessary to set the capacitance value of the capacitor while estimating the inrush current by simulation or the like. However, in the second switch cell SWb according to the first embodiment, the propagation of the control signal CNT can be delayed without using a capacitor. Thereby, in the semiconductor device according to the first embodiment, it is possible to reduce the design time by omitting the adjustment process of the parameters (for example, the capacitance value of the capacitor) by simulation.

  In general, a capacitor tends to have a large circuit area, but the second switch cell SWb does not include an element that requires a large circuit area, such as a capacitor. Therefore, the semiconductor device according to the first embodiment can reduce the circuit area as compared with the conventional one.

  The first switch cell SWa and the second switch cell SWb can be configured without using an analog circuit. A circuit used for an analog circuit is generally required to have different characteristics from a circuit used for a digital circuit. For example, a comparator malfunctions due to power supply noise, and a circuit that operates based on the reference voltage malfunctions when the reference voltage formed by the reference voltage generation unit or the like is affected by the power supply noise or the like. In order to prevent such a malfunction, the analog circuit is formed in a region of a power supply system different from the digital circuit. However, since the first switch cell SWa and the second switch cell SWb used in the semiconductor device according to the first embodiment do not include an analog circuit, the power supply control region includes only a digital circuit. It can be formed in the control region. Since such an arrangement is possible, the semiconductor device according to the first embodiment can increase the degree of design freedom.

  In the semiconductor device according to the first embodiment, as shown in FIG. 7, the control signal CNT is propagated to the outer periphery of the power supply control region and then propagated toward the inside of the power supply control region. By propagating the control signal CNT in this way, the voltage of the local power supply wiring LVDD in the outer peripheral portion of the power supply control region is first increased, and then the voltage of the local power supply wiring LVDD in the inner peripheral portion of the power supply control region is increased. In general, an interface circuit for exchanging signals between the power control region and other regions is provided in the outer periphery of the power control region, and a processing circuit is provided in the inner periphery of the power control region. Therefore, by raising the voltage from the outer periphery of the power supply control region, the processing circuit provided therein can be expected to suppress the through current of the CMOS gate when the power supply is generated due to an undefined input signal, and , Leading to shortened power-up time.

Embodiment 2
In the second embodiment, another example of the switch cell arrangement method will be described. FIG. 9 shows a schematic diagram of a planar layout showing the arrangement of switch cells in the semiconductor device according to the second embodiment. In the second embodiment, the second switch cell SWb includes the low threshold switch cell SWb1 and the high threshold switch cell SWb2.

  The low threshold switch cell SWb1 is the same as the second switch cell SWb of the first embodiment, and the first voltage (a voltage value that is half the power supply voltage (eg, 0.6 V)) is set as the threshold voltage Vth. Is done. The high threshold switch cell SWb2 has a threshold voltage Vth of a second voltage (for example, 0.9 V) higher than that of the low threshold switch cell SWb1.

  As shown in FIG. 9, in the semiconductor device according to the second embodiment, the low threshold switch cell SWb1 is arranged at the position where the control signal CNT is transmitted to the 30th, 35th, 40th, and 45th. In the semiconductor device according to the second embodiment, the high threshold switch cell SWb2 is arranged at the position where the control signal CNT is transmitted to the 49th and 52nd.

  By arranging the high threshold switch cell SWb2 in such a manner, the timing at which the switch cell to which the control signal CNT is transmitted after the 49th is turned on is determined from the semiconductor device according to the first embodiment (for example, FIG. 7). Can also be slow.

  When the propagation of the control signal CNT is in the second half, the voltage of the local power supply wiring LVDD is increased by the switch cell that is turned on before the control signal CNT arrives, and the voltage is higher than the threshold voltage Vth of the switch cell arranged in the second half It may become. In such a case, there is a problem that the slow switch control cannot be substantially performed in the latter switch cell. However, in the first embodiment, by arranging the high threshold switch cell SWb2 at the subsequent stage of the low threshold switch cell SWb1, the slow switch control is effectively performed even in the latter switch cell that takes time until the control signal CNT propagates. It can be carried out. That is, in the semiconductor device according to the second embodiment, the voltage value of the local power supply wiring LVDD can be increased more gently than in the semiconductor device according to the first embodiment.

Embodiment 3
In the third embodiment, another example of the switch cell arrangement method will be described. Also in the third embodiment, the low threshold switch cell SWb1 and the high threshold switch cell SWb2 are used. FIG. 10 shows a schematic diagram of a planar layout showing the arrangement of switch cells in the semiconductor device according to the third embodiment.

  As shown in FIG. 10, in the semiconductor device according to the third embodiment, the first switch cell SWa is arranged as a switch cell in which the control signal CNT is propagated from the first to the 28th (first half). In the semiconductor device according to the third embodiment, the low threshold switch cell SWb1 is disposed as a switch cell through which the control signal CNT is propagated from the 29th to the 48th (middle). Further, in the semiconductor device according to the third embodiment, the high threshold switch cell SWb2 is disposed as a switch cell in which the control signal CNT is propagated after the 49th (second half).

  The third embodiment shows an example in which the second switch cells SWb can be continuously arranged. In such a case, as shown in FIG. 10, by arranging the high threshold switch cell SWb2 after the low threshold switch cell SWb1, the slow switch control can function effectively in the entire power control region.

Embodiment 4
In the fourth embodiment, another example of the switch cell arrangement method will be described. Also in the fourth embodiment, the low threshold switch cell SWb1 and the high threshold switch cell SWb2 are used. FIG. 11 is a schematic plan view showing the layout of switch cells in the semiconductor device according to the fourth embodiment.

  As shown in FIG. 11, in the semiconductor device according to the fourth embodiment, the control signal CNT is propagated from the first to the 51st as in the semiconductor device according to the first embodiment (FIG. 8). The switch cell to which the control signal CNT propagates for the 51st time propagates the control signal CNT in parallel to the four switch cells. A high threshold switch cell SWb2 is provided as four switch cells to which the control signal CNT is applied in parallel.

  That is, the fourth embodiment shows another form of the propagation method of the control signal CNT. At this time, by using the high-threshold switch cell SWb2 as the switch cell that is switched on in parallel, the slow switch control can be validated for the switch cell that is switched on in the second half.

Embodiment 5
In the fifth embodiment, a second switch cell SWc, which is another form of the second switch cell SWb, will be described. FIG. 12 is a block diagram of a semiconductor device including the second switch cell SWc. In the description of the fifth embodiment, description of the components described in the first embodiment is omitted.

  As shown in FIG. 12, the second switch cell SWc has a logic corresponding to the voltage value MON of the local power supply wiring LVDD at the inverting input terminal (input terminal of the inverter 30) of the gating circuit 20 via the Schmitt trigger circuit 22. Input level signal. The details of the Schmitt trigger circuit 22 will be described.

  A circuit diagram of the Schmitt trigger circuit 22 is shown in FIG. As shown in FIG. 13, the Schmitt trigger circuit 22 includes NMOS transistors N11 to N14 and PMOS transistors P11 to P14.

  The NMOS transistor N11 has a source connected to the ground wiring GND and a drain connected to the source of the NMOS transistor N12. The drain of the NMOS transistor N12 is connected to the drain of the PMOS transistor P12. The source of the PMOS transistor P11 is connected to the global power supply wiring GVDD. The voltage value MON of the local power supply wiring LVDD is input as the input voltage Vin to the gates of the NMOS transistors N11 and N2 and the PMOS transistors P11 and P12.

  The NMOS transistor N13 has a source connected to the ground wiring GND and a drain connected to a connection point between the drain of the NMOS transistor N11 and the source of the NMOS transistor N12. The output voltage Vout of the Schmitt trigger circuit 22 is input to the gate of the NMOS transistor N13. The source of the PMOS transistor P13 is connected to the global power supply wiring GVDD, and the drain is connected to the connection point between the drain of the PMOS transistor P11 and the source of the PMOS transistor P12. The output voltage Vout of the Schmitt trigger circuit 22 is input to the gate of the PMOS transistor P13.

  The NMOS transistor N14 has a source connected to the ground wiring GND and a drain connected to the drain of the PMOS transistor P14. The source of the PMOS transistor P14 is connected to the global power supply line GVDD. The gate of the PMOS transistor P14 and the gate of the NMOS transistor N14 are connected in common, and are connected to the connection point between the drain of the NMSO transistor N12 and the drain of the PMOS transistor P12. The output voltage Vout is output to the gating circuit 20 from the connection point between the drain of the PMOS transistor P14 and the drain of the NMOS transistor N14.

  The input / output characteristics of the Schmitt trigger circuit 22 are shown in FIG. As shown in FIG. 14, the Schmitt trigger circuit 22 has a threshold voltage Vth_H with respect to the rising edge of the input voltage Vin. The threshold voltage Vth_L for the falling edge of the input voltage Vin is different. More specifically, the threshold voltage Vht_H is higher than the threshold voltage Vth_L.

  The Schmitt trigger circuit 22 having such input / output characteristics determines the voltage level of the voltage value MON of the local power supply wiring LVDD, so that the voltage value MON of the local power supply wiring LVDD temporarily decreases after exceeding the threshold voltage once. Even in such a case, it is possible to prevent the second switch transistor 21 from repeating the on state and the off state. The voltage of the local power supply wiring LVDD may increase or decrease depending on the operating state of the cell connected to the local power supply wiring LVDD. Therefore, the operation of the circuit arranged in the power supply control region can be stabilized by determining the voltage level of the voltage value MON of the local power supply wiring LVDD by the Schmitt trigger circuit 22.

  From the above description, the semiconductor device according to the fifth embodiment can realize more stable circuit operation than the semiconductor devices according to the other embodiments by using the Schmitt trigger circuit 22. The Schmitt trigger circuit 22 is a digital circuit, and can obtain the effect of reducing the circuit area and the effect of simplifying the circuit design as in the semiconductor device according to the first embodiment. Also in the semiconductor devices according to the first to fourth embodiments, the second switch cell SWc having the Schmitt trigger circuit 22 can be used.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Power supply control circuit 10 Buffer circuit 11, 21 Switch transistor 20 Gating circuit 22 Schmitt trigger circuit 30 Inverter 31 OR circuit CNT Control signal DLY Delay circuit GND Ground wiring GVDD Global power supply wiring LVDD Local power supply wiring MON Voltage value MONb Determination signal N1 N4, N11-N14 NMOS transistors P1-P4, P11-P14 PMOS transistor PIN Power input terminal POUT Power output terminals SWa, SWb, SWc Switch cell SWb1 Low threshold switch cell SWb2 High threshold switch cell SWIN, SWINa Control signal input terminal SWOUT control Signal output terminal

Claims (9)

Global power supply wiring that supplies power supply voltage to multiple areas,
Local power supply wiring for supplying the power supply voltage to one of the plurality of regions;
First and second switch cells that switch supply and cutoff of the power supply voltage from the global power supply wiring to the local power supply wiring based on a logic level of a control signal;
The first switch cell includes a first switch transistor that switches between the global power supply wiring and the local power supply wiring being turned on or off according to a logic level of the control signal, and the control signal. A first signal transmission unit for transmitting
The second switch cell includes a second switch transistor that switches between the global power supply line and the local power supply line being turned on or off according to the logic level of the control signal, and the local power supply. A second signal transmission unit that interrupts transmission of the control signal to a subsequent circuit during a period until the voltage value of the wiring reaches a threshold voltage;
The second switch cell is a semiconductor device arranged at a subsequent stage of the first switch cell.   2. The second switch transistor switches whether the global power supply wiring and the local power supply wiring are in a conductive state or a cut-off state in accordance with the control signal output from the second signal transmission unit. A semiconductor device according to 1. The second signal transmission unit includes:
An inverter that generates a determination signal that goes low when the voltage value of the local power supply wiring exceeds the threshold voltage;
The semiconductor device according to claim 1, further comprising: a logical sum circuit that outputs a logical sum operation result of the determination signal and the control signal as the control signal.   4. The semiconductor device according to claim 3, wherein the second signal transmission unit includes a Schmitt trigger circuit that receives the voltage value of the local power supply wiring as an input signal and outputs an output signal to the inverter.   5. The semiconductor device according to claim 1, wherein the first signal transmission unit transmits the control signal via a buffer circuit that reduces a propagation delay of the control signal. 6.   A plurality of the second switch cells are arranged in the one region, and a plurality of the first switch cells connected in series are arranged between the second switch cells. 6. The semiconductor device according to any one of 5 above.   The second switch cell includes a low threshold switch cell in which a first voltage is set as the threshold voltage, and a high threshold switch cell in which a second voltage higher than the first voltage is set as the threshold voltage. The semiconductor device according to claim 1, wherein the high-threshold switch cell is arranged at a later stage than the low-threshold switch cell. The local power supply wiring supplies a high potential side power supply to a circuit arranged in the one region,
The semiconductor device according to claim 1, wherein the first and second switch transistors are PMOS transistors.   9. The semiconductor device according to claim 1, wherein the control signal is generated by a control circuit disposed in a constant power supply region where the power supply voltage is always supplied from the global power supply wiring.

Images