JP2012226604A - Semiconductor device and data abnormality determination method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an increase in physical size of a second chip while improving data reliability of a semiconductor device including a first chip having storage means and the second chip including instruction means of instructing the storage means to read memory data out and determination means of determining reliability of read-out control data at least by majority decision.SOLUTION: Each piece of control data is stored in three different addresses as memory data to which check data corresponding to a part of an address of a storage destination is added. Parts of respective addresses associated with one piece of control data except parts corresponding to check data are mutually different, and the same among a plurality of pieces of control data. Further, control data, check data, and parts of addresses corresponding to the check data are the same or in relation of mirror inversion with respect to three pieces of memory data.

Description

  The present invention provides a first chip having storage means, instruction means for instructing reading of memory data from the storage means, and determination for determining the reliability of the read control data by at least a majority vote The present invention relates to a semiconductor device including a second chip having means and a data abnormality determination method thereof.

  Conventionally, as a technique for preventing control using erroneous control data, for example, as shown in Patent Document 1, a plurality of data corresponding to the control data is stored in memory for one control data There is known a majority voting method in which a plurality of data is sequentially read out and a majority is determined by reading the plurality of data sequentially when the control data is read out.

  In Patent Document 1, as a plurality of data corresponding to one control data, control data, mirror data of the control data, and mirror data are respectively written at different addresses, and these three data (control data and 2 Majority decision is performed on two mirror data). As described above, when a large number of pieces of data are used for one control data, the data reliability can be improved.

JP-A-8-95868

  By the way, when not performing high-functional control to adopt a microcomputer, the first chip having a memory (storage means), the instruction means for instructing the memory means to read out memory data, and at least the majority vote, A method is used in which the read control data is divided into a second chip having determination means for determining the reliability of the control data read out. In this case, the second chip is configured as, for example, a so-called custom IC chip that includes only a function according to the user's needs, and the cost of the semiconductor device including two chips can be reduced as compared with the microcomputer.

  However, in the majority decision described above, the memory data relating to one control data is stored at three addresses, and therefore the number of memory data stored in the storage means is large. Therefore, in the case where the majority method is adopted in the semiconductor device constituted by the two chips described above, the scale of the instruction means that designates the address and instructs the reading of the control data on the second chip side, that is, the second The size of the chip (circuit scale) also increases.

  Further, as shown in Patent Document 1, when the control data itself or the mirror inverted data of the control data itself is used as memory data stored in the storage means, the second chip (custom IC chip) reads out the data. It is not possible to determine whether the control data is correct. For this reason, even if a part of the memory data is destroyed, it cannot be determined whether or not the memory data is destroyed, and the reliability of the data is low.

  In view of the above problems, the present invention increases the reliability of control data read out by a first chip having storage means, instruction means for instructing the storage means to read out memory data, and at least a majority vote. An object of the present invention is to suppress an increase in the physique of a second chip while improving data reliability in a semiconductor device including a second chip having a determination means for determining.

In order to achieve the above object, a semiconductor device according to claim 1,
A first chip having storage means;
A second chip having instruction means for instructing the storage means to read out the control data, and determination means for determining the reliability of the read control data by at least a majority vote.

The control data is stored in the storage means as memory data to which check data corresponding to a plurality of bits that are part of the storage destination address is added,
The memory means stores three memory data at different addresses for one control data,
In each address where three memory data related to one control data is stored, portions other than a part corresponding to the check data are different from each other and the same for a plurality of control data,
In the three memory data related to one control data, the control data, the check data, and some of the addresses corresponding to the check data are in the same or mirror inversion relationship, respectively.
The instructing means sequentially reads out a plurality of control data, and instructs the storage means to sequentially read out three related memory data for each control data,
The determination means is characterized by comparing each check data with a part of the corresponding address for the three read memory data, and performing majority determination of the control data for a plurality of matching memory data. To do.

  In the present invention, the control data or its mirror inversion data is not directly stored in the storage means as memory data (for example, 16 bits), but is stored in the control data (for example, 11 bits) as part of the storage destination address. It is stored as memory data to which check data (for example, 5 bits) corresponding to (for example, 5 bits of 8 bits) is added. Of the three addresses corresponding to one control data, a part (for example, 5 bits) corresponding to the check data has the same or mirror inversion relationship. The remaining portions (for example, 3 bits) are different from each other and are the same for a plurality of control data, and have regularity. For this reason, it is possible to simplify the configuration of the instruction means for instructing the storage means to sequentially read out a plurality of control data and to sequentially read out three related memory data for each control data. That is, it is possible to suppress an increase in the size of the instruction means, and hence an increase in the size of the second chip.

  Further, according to the present invention, since a majority decision is made for a plurality of memory data with respect to one control data, the reliability of the data can be improved. Further, as described above, the memory data includes check data corresponding to a part of the address of the storage destination, and the determination means corresponds to each check data for the three memory data before the majority decision. Check with a part of the address you want. For example, if the memory data is destroyed, the address corresponding to the check data does not match. Therefore, the reliability of the data is improved compared to the configuration in which the majority of the memory data consisting only of the control data or its mirror inversion data is determined. Can be improved.

  As described above, according to the present invention, it is possible to suppress an increase in the size of the second chip, and thus the semiconductor device, while improving data reliability.

Moreover, the semiconductor device according to claim 2 is also provided.
A first chip having storage means;
A second chip having instruction means for instructing the storage means to read out the control data, and determination means for determining the reliability of the read control data by at least a majority vote.

The control data is stored in the storage means as memory data to which check data corresponding to a plurality of bits that are part of the storage destination address is added,
The memory means stores three memory data at different addresses for one control data,
In each address where three memory data related to one control data is stored, portions other than a part corresponding to the check data are different from each other and the same for a plurality of control data,
In the three memory data related to one control data, the control data, the check data, and some of the addresses corresponding to the check data are in the same or mirror inversion relationship, respectively.
The instructing means sequentially reads out a plurality of control data, and instructs the storage means to sequentially read out three related memory data for each control data,
The determination unit performs majority determination of the control data for the three read memory data, and when the plurality of control data match, the address corresponding to each check data for the plurality of matching memory data It is characterized by collating with a part of.

  The difference between the present invention and the invention described in claim 1 is only the order of the majority decision executed by the determination means and the collation of the check data and a part of the corresponding address. Since this is equivalent to the operational effect of the invention described in 1, the description is omitted.

  Preferably, the second chip is read-only with respect to the storage unit.

  According to this, since the memory data is not written to the storage means from the second chip side, erroneous writing itself does not occur, and thereby the reliability of the control data can be improved.

  As described in claim 4, it is preferable that the addresses of the three memory data are distributed and stored in the storage means.

  When memory data is corrupted in the storage means, memory data in a predetermined range where addresses are continuous often breaks together. On the other hand, according to the present invention, it is possible to reduce the risk of destroying all three memory data related to one control data. That is, the reliability of data can be improved.

  In particular, it is preferable that the check data corresponds to a plurality of lower-order bits in the storage destination address of the corresponding memory data.

  According to this, compared with the configuration in which the check data corresponds to a plurality of upper bits, the degree of distribution of the three memory data can be increased, thereby further improving the reliability of the data.

As recited in claim 6, the three memory data includes first memory data, second memory data, and third memory data,
The second memory data check data and the control data are mirror-inverted with the first memory data check data and the control data, respectively. The third memory data check data and the first memory data check It is preferable that one of the control data, the control data for the third memory data, and the control data for the first memory data is the same, and the other is in a mirror inversion relationship.

  According to this, when the same memory data is read a plurality of times (for example, when the first memory data is read twice), the malfunction can be detected.

  Preferably, the check data is set excluding all bits 0 and all bits 1.

  When a memory data error occurs, all bits are often set to '0' or '1'. According to the present invention, since the check data is set excluding all bits 0 and all bits 1, a data error can be detected.

Next, the invention according to claim 8 is:
A data abnormality determination method for a semiconductor device for determining the presence or absence of abnormality in control data read from a storage unit of a first chip to a second chip,
When writing the control data to the storage means, the control data is stored in the address as memory data to which check data corresponding to a plurality of bits that are a part of the address of the storage destination is added. For control data, store three memory data at different addresses,
In each address where three memory data related to one control data is stored, the portions other than a part corresponding to the check data are different from each other and are the same in a plurality of control data,
In the three memory data related to one control data, the control data, the check data, and a part of the addresses corresponding to the check data are in the same or mirror inversion relationship, respectively.
When reading control data from the storage means into the second chip, a plurality of control data are read sequentially, and three related memory data are sequentially read for each control data,
For each of the three read memory data, each check data is compared with a part of the corresponding address, and when all the memory data does not match, it is determined that the memory data is abnormal,
In a plurality of memory data, when each check data and a part of the corresponding address match, the majority decision of the control data is performed for the plurality of matching memory data, and when the control data is different from each other, the memory data It is determined to be abnormal.

  Since the operational effects of the present invention are the same as the operational effects of the invention described in claim 1, the description thereof is omitted.

The invention according to claim 9 is
A data abnormality determination method for a semiconductor device for determining the presence or absence of abnormality in control data read from a storage unit of a first chip to a second chip,
When writing the control data to the storage means, the control data is stored in the address as memory data to which check data corresponding to a plurality of bits that are a part of the address of the storage destination is added. For control data, store three memory data at different addresses,
In each address where three memory data related to one control data is stored, the portions other than a part corresponding to the check data are different from each other and are the same in a plurality of control data,
In the three memory data related to one control data, the control data, the check data, and a part of the addresses corresponding to the check data are in the same or mirror inversion relationship, respectively.
When reading control data from the storage means into the second chip, a plurality of control data are read sequentially, and three related memory data are sequentially read for each control data,
The majority decision of the control data is performed for the three read memory data, and when the control data for the three memory data are different from each other, it is determined that the memory data is abnormal,
When multiple control data matches, the memory data containing the matching control data is checked against each check data and a part of the corresponding address. It is characterized by determining that it is abnormal.

  Since the operational effects of the present invention are the same as the operational effects of the invention described in claim 2, the description thereof is omitted.

1 is a diagram illustrating a schematic configuration of a semiconductor device according to a first embodiment. It is a figure which shows the content of the memory data regarding arbitrary control data N, and the relationship between memory data and a write-destination address. It is a figure which shows the specific example by which memory data was written in memory. It is a flowchart which shows the data abnormality determination method. It is a flowchart which shows a modification of a data abnormality determination method.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
As shown in FIG. 1, a semiconductor device 10 includes a first chip 11 having a memory circuit, and a circuit that reads memory data from the first chip 11 and determines normality / abnormality of control data included in the memory data. The second chip 12 is configured.

  The first chip 11 is a so-called memory IC chip, and a memory 20 as a storage unit is configured. The memory 20 stores memory data corresponding to a plurality of control data.

  The memory 20 is not particularly limited. It is possible to employ an EEPROM, EPROM, flash memory capable of rewriting data, a mask ROM capable of writing data only at the time of factory shipment, an OTP (One Time Programmable) memory which can be written only once. In the present embodiment, an EEPROM is configured as the memory 20.

  On the other hand, unlike the microcomputer, the second chip 12 is a so-called custom IC chip in which memory data is read from the first chip 11 and necessary circuits for determination processing are configured. The second chip 12 includes a counter 30, a memory control unit 31, and a determination unit 32. In the present embodiment, the second chip 12 does not have a writing function with respect to the memory 20 of the first chip 11 and reads a memory data stored in the memory 20 of the first chip 11. It has become. The counter 30 and the memory control unit 31 correspond to the instruction unit described in the claims, and the determination unit 32 corresponds to the determination unit.

  Based on the count value of the counter 30, the memory control unit 31 instructs the memory 20 to sequentially read three memory data related to certain control data. When the count value of the counter 30 increases by one, the memory 20 is instructed to sequentially read three memory data related to the control data to be read next.

  Further, the memory control unit 31 processes the memory data read from the memory 20 and the data at the address where the memory data is stored as necessary, and outputs the processed data to the determination unit 32. In the present embodiment, a process of inverting the mirror inversion data is performed on the data in the check data portion and the control data portion of the memory data. The memory control unit 31 is connected to the memory 20 of the first chip 11 via an address line and a data line.

  Based on the output from the memory control unit 31, the determination unit 32 determines the data in the corresponding address check unit (hereinafter referred to as address data) and the data in the memory data check data unit (hereinafter referred to as check data). Matching). If there is a plurality of matches between the address data and the check data, the majority decision of the data in the control data section, that is, the control data described above is performed for the matched memory data. And the output based on these determination results is performed.

  Next, a rule for writing control data, which is a main feature of the present embodiment, specifically, the contents of memory data stored in the memory corresponding to the control data, and the memory data and writing The relationship with the previous address will be described with reference to FIGS.

  First, arbitrary control data N will be described with reference to FIG.

  As shown in FIG. 2, arbitrary control data N is a check corresponding to the control data N or its mirror inversion data corresponding to address data of a plurality of bits (the check unit) which is a part of the storage destination address. It is stored in the memory 20 as memory data to which additional data (same as address data or mirror inversion data thereof) is added.

  In the present embodiment, of the memory data, the data stored in the upper multi-bit check data part is the check data, and the data stored in the control data part that is the remaining lower multi-bits is the control data (or The mirror inversion data). As described above, the check data corresponds to a plurality of lower bits among the addresses of the storage destination of the corresponding memory data.

  The memory 20 stores three pieces of memory data (first memory data, second memory data, and third memory data) at different addresses for one control data N. In each of the addresses (three addresses) where the three pieces of memory data related to the control data N are stored, the fixed part, which is a part excluding a part corresponding to the check data, is different from each other, and a plurality of control data It is the same. As a result, the three memory data are stored in the memory 20 in a distributed manner, with addresses not being continuous. In the present embodiment, as shown in FIG. 2, in the three memory data related to the control data N, the fixed portion is a numerical value different from α, β, and γ. As described above, the three memory data are stored in the memory 20 in a distributed manner, with addresses not being continuous. In the above description, the values of a plurality of bits are simply shown as α, β, and γ.

  Further, in the three memory data related to the control data N, the control data stored in the control data portion, the check data stored in the check data portion, and the address data in the address check portion are: As shown in FIG. 2, they have the same or mirror inversion relationship. The control data stored in the control data section refers to the control data N or mirror inversion data of the control data N as described above.

  Here, address data that is not mirror-inverted is A, and check data is A. In the above description, the value of a plurality of bits is simplified as A.

  As shown in FIG. 2, the first memory data is formed by storing data A in the check data portion and data N in the control data portion in an address composed of data α and data A. The second memory data is formed by storing the mirror inverted data of data A in the check data portion and the mirror inverted data of data N in the control data portion at the address composed of data β and data A. The third memory data has an address composed of the data γ and the mirror inverted data of the data A, the mirror inverted data of the data A stored in the check data portion, and the data N stored in the control data portion. As described above, for the three memory data, the combination of the address data at the storage destination address and the check data is the same for the data A, the data A and the mirror inverted data of the data A, and the mirror inverted data of the data A are the same. It is the same. Further, among the three control data, two are data N and one is mirror inverted data of data N.

  Next, FIG. 3 shows an example of a memory in which a plurality of control data is written in accordance with the rules described above. In FIG. 3, two of data 1 and data 2 among the plurality of control data are specifically illustrated, and illustration of other control data is omitted. The first data is data that is read first when data is read, and the second data is data that is read second after the first data. In order to simplify the description, the numerical value of each bit is represented by a binary number.

  As shown in FIG. 3, each data conforms to the rules for data N described above. In the 8-bit address, the upper 3 bits are a fixed part and the lower 5 bits are a check part. Looking at the first data, the data of the fixed part is (000), (010), and (100) in the three memory data, which are different from each other. The address data of the check unit is (00001), (00001), and (11110), and the third memory data is compared to the address data of the address where the first memory data and the second memory data are stored. The address data of the stored address is a value obtained by mirror inversion.

  On the other hand, of the 16-bit memory data, 5 bits are the check data. The data 1 is (00001), (11110), and (11110), and the values obtained by mirror-inversion of the second memory data and the third memory data check data with respect to the first memory data check data. It has become. For the first memory data, the address data and the check data are the same at (00001), and for the second memory data, the address data and the check data are at the mirror inversion at (00001) and (11110), the third memory Regarding the data, the address data and the check data are the same at (11110). As described above, the check data and the address data are set so that all 5 bits are not 0 and all 5 bits are not 1.

  The 11-bit control data is data 1, mirror inversion data of data 1, and data 1. For the control data of the first memory data and the third memory data, the control data for the second memory data is used. The data is a mirror inverted value.

  Next, regarding the second data, the data of the fixed part is (000), (010), and (100) in the three memory data. Thus, the data of the fixed part has the same (common) value as the control data.

  On the other hand, the address data of the check unit is (00010), (00010), and (11101), and the third memory data is compared to the address data of the address where the first memory data and the second memory data are stored. The address data of the stored address is a value obtained by mirror inversion.

  On the other hand, the check data is (00010), (11101), and (11101), and the check data of the second memory data and the third memory data are mirror-inverted with respect to the check data of the first memory data. It is the value. For the second memory data, the address data and the check data are the same at (00001). For the second memory data, the address data and the check data are at the mirror inversion at (00001) and (11110), the third memory. Regarding the data, the address data and the check data are the same at (11110). As described above, the check data and the address data are set so that all 5 bits are not 0 and all 5 bits are not 1.

  The 11-bit control data is data 2, mirror-inverted data of data 2, and data 2. For the control data of the first memory data and the third memory data, the control data for the second memory data is used. The data is a mirror inverted value.

  Next, a data abnormality determination method for determining the presence or absence of data abnormality in the control data (memory data) read from the memory 20 of the first chip 11 to the second chip 12 will be described with reference to FIGS.

  The rules for writing memory data to the memory 20 are as described above. When the power is turned on, the 5-bit count value in the counter 30 of the second chip 12 becomes (00001). The counter 30 outputs this count value to the memory control unit 31 (step 10).

  When the count value is input, the memory control unit 31 sequentially adds (000), (010), and (100) to the input count value or its mirror inversion data, to the address line as 8-bit data. And outputs an instruction to the memory 20 to read the memory data at the address.

  Specifically, when the count value (00001) is input, first, the count value is set to the lower 5 bits, and the upper 3 bits are set to (000) to output an 8-bit address (00000001) to the address line. (Step 11). At this address, the first memory data related to the first data is stored.

  Upon receiving the output request, the memory 20 outputs the first memory data (see FIG. 3) related to the first data stored at the address (00000001) to the memory control unit 31 of the second chip 12. The memory control unit 31 temporarily stores the first memory data related to the output first data and the address data among the addresses requested to be output (step 12).

  Next, when the output of the address for reading the first memory data is completed, the memory control unit 31 sets the count value to the lower 5 bits and the upper 3 bits to (010), so that an 8-bit address ( 000010001) is output (step 13). The second memory data relating to the first data is stored at this address.

  Upon receiving the output request, the memory 20 outputs the second memory data (see FIG. 3) related to the first data stored at the address (01000001) to the memory control unit 31 of the second chip 12. The memory control unit 31 temporarily stores the second memory data related to the output first data and the address data among the addresses requested to be output. In this storage, the second memory data is not stored as it is, but the check data and the control data are both mirror-inverted and stored (step 14).

  Next, when the output of the address for reading the second memory data is completed, the memory control unit 31 sets the mirror inversion value of the count value to the lower 5 bits and sets the upper 3 bits to (100), so that the address line has 8 bits. The bit address (10011110) is output (step 15). This address stores third memory data related to the first data.

  Then, the memory 20 that has received the output request outputs the third memory data (see FIG. 3) relating to the first data stored in the address (10011110) to the memory control unit 31 of the second chip 12. The memory control unit 31 temporarily stores the third memory data related to the output first data and the address data among the addresses requested to be output. In this storage, the third memory data is not stored as it is, but the check data is mirror-inverted and stored (step 16).

  As described above, when the reading of the three memory data related to data 1 is completed, the determination unit 32 reads each data temporarily stored in the memory control unit 31 and sequentially executes the following determination processing.

  First, in the present embodiment, each check data temporarily stored in the three memory data (corresponding data) and the address data of the control data (in other words, the count value) are collated. Specifically, it is determined whether or not the check data of the data read as the first memory data matches the address data (count value). Further, it is determined whether or not the mirror inversion value of the check data in the data read as the second memory data matches the address data (count value). Furthermore, it is determined whether the mirror inversion value of the check data of the data read as the third memory data matches the address data (count value). Based on these determinations, it is determined whether or not a plurality of the three pieces of memory data match (step 17).

  If a plurality of memory data match as a result of the determination in step 17, whether or not a plurality of temporarily stored control data (corresponding data) matches in the matching memory data (for example, all memory data). Determine (step 18). In the present embodiment, the control data (data 1) of the data read as the first memory data, the mirror inversion value of the control data (data 1) of the data read as the second memory data, It is determined whether or not the control data (data 1) of the data read as the three memory data match each other.

  In step 18, when a plurality of control data (corresponding data) match, the determination unit 32 uses, for example, control data 1 for controlling the driving of an actuator (not shown) for control on the three read memory data. Update to data 1 (step 19).

  On the other hand, if the plurality does not match in either step 17 or step 18, the determination unit 32 reads out the control data 1 for controlling the driving of the actuator (not shown), assuming that the read data has low reliability. The control data 1 for the three memory data is not updated (step 20). In this case, for example, the value currently set as the control data 1 for controlling the driving of the actuator is held.

  Then, in step 21, it is determined whether or not the reading / determination process has been completed for all the control data. If completed, the control data (memory data) reading / determination process is terminated. On the other hand, if not completed, the count value of the counter 30 is incremented by one in step 22. Then, step 10 and subsequent steps are sequentially executed. For example, when the reading / determination process of the first data is completed, the count value of the counter 30 is incremented by 1 in step 22 and becomes (00010). In step 10, the counter 30 outputs the value to the memory control unit 31 as the second output. Step 11 and subsequent steps are the same if the count value at the time of reading the data 1 is replaced with the count value at the time of reading the second data, and the description thereof is omitted.

  In the present embodiment, the control data or its mirror inversion data is not directly stored in the memory 20 as memory data, but check data corresponding to the address data of the storage destination address is added to the control data. Is remembered. In addition, in the address where the three memory data related to one control data is stored, each address data has the same or mirror inversion relationship. In addition, among the addresses, the data in the fixed portion is different from each other at each address where three memory data related to one control data is stored, and is the same in a plurality of control data. That is, it has regularity.

  For this reason, a plurality of control data are sequentially read out, and the instruction means (counter 30 and memory control unit 31) for instructing the memory 20 to sequentially read out the three related memory data for each control data is simplified. be able to. That is, it is possible to suppress an increase in the size of the instruction means, and hence an increase in the size of the second chip 12. In particular, in this embodiment, (000), (010), and (100) are sequentially added to the count value of the counter 30 or its mirror inversion value to obtain an address for reading out three memory data. Can be simplified.

  In the present embodiment, since the majority decision is performed for three pieces of memory data with respect to one piece of control data, data reliability can be improved. Further, as described above, the memory data includes the check data corresponding to the address data of a part of the storage destination address (check unit), and the determination unit 32 determines the three memory data before the majority decision. , Each check data and corresponding address data (count value of the counter 30) are collated. For example, if the memory data is destroyed, the check data (or its mirror inversion data) and the address data do not match, so the memory data consisting only of the control data or its mirror inversion data is simply compared with the configuration in which majority decision is made. Data reliability can be improved.

  As described above, according to the present embodiment, it is possible to suppress an increase in the size of the second chip 12 and thus the semiconductor device 10 while improving data reliability.

  Furthermore, in the present embodiment, the second chip 12 is read-only with respect to the memory 20 (first chip 11). For this reason, memory data is not written into the memory 20 from the second chip 12 side, and erroneous writing itself does not occur. Thereby, the reliability of the control data can be further improved.

  Also, three memory data related to the same control data are stored in the memory 20 with addresses dispersed. When memory data is corrupted in the memory 20, memory data in a predetermined range where addresses are continuous often breaks together. On the other hand, if the addresses are distributed as in the present embodiment, the risk of destroying all three memory data related to one control data can be reduced. That is, the reliability of data can be improved.

  In particular, in this embodiment, a plurality of lower bits of the storage destination address are used as a check unit, and the address data value of the check unit or its mirror inversion value is used as memory data check data. Therefore, the degree of distribution of the three memory data is increased as compared with the case where the upper multiple bits of the address are used as a check unit and the value of the address data of the check unit or its mirror inversion value is used as the check data of the memory data. be able to. As a result, the reliability of the data can be further improved.

  In this embodiment, for the same control data, the mirror inversion value of the check data for the first memory data is used as the check data for the second memory data, and the mirror inversion value of the control data for the first memory data is used. Is used as control data for the second memory data. The mirror inversion value of the check data for the first memory data is set as the check data for the third memory data, and the control data for the third memory data is the same as the control data for the first memory data. . For this reason, when reading the control data, if the same memory data is read multiple times (for example, when the first memory data is read twice) due to a failure of the memory 20 or a read error, the malfunction is detected. can do. The mirror inversion value of the control data for the first memory data may be the control data for the third memory data, and the check data for the third memory data may be the same as the check data for the first memory data. An equivalent effect can be achieved.

  In this embodiment, the check data is set except for all bits 0 and all bits 1. In other words, memory data is stored except for addresses where the address data of the check unit is all 0 bits and all 1 bits. When a memory data error occurs, all bits are often set to '0' or '1'. For this reason, according to this embodiment, a data error can be detected.

(Modification)
In the determination method shown in FIG. 4, with respect to the same control data, for each of the three memory data sequentially read, first, the check data and corresponding address data (in other words, the count value of the counter 30) match. Determine whether there are multiple things. In the case where there are a plurality of matches, an example is shown in which it is determined whether or not there is a plurality of matches in the control data for the matched memory data. However, as shown in FIG. 5, after step 16, with respect to the same control data, it is first determined whether or not there is a plurality of matching of the control data for the three memory data read sequentially (step 27). . If there is a plurality of matches in step 27, it is determined whether or not there is a plurality of matching memory data in which each check data and corresponding address data (in other words, the count value of the counter 30) match ( Step 28). Then, if a plurality of matches are found in step 28, the control data is updated (step 19), and if they do not match in either step (steps 27, 28), the control data is not updated (step 20). May be. The flowchart shown in FIG. 5 is the same as FIG. 4 except that steps 17 and 18 shown in FIG. 4 are replaced by steps 27 and 28.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In the present embodiment, an example in which the second chip 12 is a read-only chip has been described. However, the second chip 12 that can be read and written to the first chip 11 may be employed.

  In the present embodiment, an example has been shown in which the lower-order multiple bits of the storage destination address are used as the address data of the check unit, and this address data or its mirror inversion data is used as data for checking memory data. However, the higher-order multiple bits of the storage destination address may be used as the address data of the check unit, and this address data or its mirror inversion data may be used as memory data check data.

  In the present embodiment, as shown in FIG. 2, for the same control data, the first memory data with the data A as the check data, the data N as the control data, and the mirror inversion data of the data A as the check data In the example, the second memory data having the mirror inverted data of the data N as control data, the mirror inverted data of the data A as the check data, and the third memory data having the data N as the control data are shown. However, the three memory data related to one control data is not limited to the above example. Regarding the three memory data, the control data and the check data may have the same or mirror inversion relationship, and the storage address data may have the same or mirror inversion relationship.

  In the present embodiment, an example is shown in which the check data of the memory data is set except for all bits 0 and all bits 1, but may be all bits 0 or all bits 1.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device 11 ... 1st chip 12 ... 2nd chip 20 ... Memory 30 ... Counter 31 ... Memory control part 32 ... Determination part

Claims (9)

A first chip having storage means;
A semiconductor device comprising: an instruction unit that instructs the storage unit to read control data; and a second chip that includes a determination unit that determines the reliability of the read control data by at least a majority vote. Because
The control data is stored in the storage means as memory data to which check data corresponding to a plurality of bits that are a part of a storage destination address is added,
The memory means stores three memory data at different addresses for one control data,
In each address where three pieces of memory data related to one piece of control data are stored, portions other than a part corresponding to the check data are different from each other, and are the same for a plurality of pieces of control data.
In the three memory data related to one control data, the control data, the check data, and some of the addresses corresponding to the check data are in the same or mirror inversion relationship, respectively.
The instruction means sequentially reads the plurality of control data, and instructs the storage means to sequentially read three memory data related to each control data,
The determination unit compares each check data with a part of the corresponding address for the read three memory data, and a plurality of the check data match with a part of the corresponding address. A majority decision of the control data is performed for a plurality of matching memory data. A first chip having storage means;
A semiconductor device comprising: an instruction unit that instructs the storage unit to read control data; and a second chip that includes a determination unit that determines the reliability of the read control data by at least a majority vote. Because
The control data is stored in the storage means as memory data to which check data corresponding to a plurality of bits that are a part of a storage destination address is added,
The memory means stores three memory data at different addresses for one control data,
In each address where three pieces of memory data related to one piece of control data are stored, portions other than a part corresponding to the check data are different from each other, and are the same for a plurality of pieces of control data.
In the three memory data related to one control data, the control data, the check data, and some of the addresses corresponding to the check data are in the same or mirror inversion relationship, respectively.
The instruction means sequentially reads the plurality of control data, and instructs the storage means to sequentially read three memory data related to each control data,
The determination means performs majority determination of the control data for the read three memory data, and when a plurality of the control data match, for each of the plurality of matching memory data, for each check A semiconductor device characterized by collating data with a part of a corresponding address.   The semiconductor device according to claim 1, wherein the second chip is read-only for the storage unit.   The semiconductor device according to claim 1, wherein addresses of the three memory data are distributed and stored in the storage unit.   5. The semiconductor device according to claim 4, wherein the check data corresponds to a plurality of lower bits among the addresses of the storage destination of the corresponding memory data. The three memory data includes first memory data, second memory data, and third memory data,
The check data and control data of the second memory data are in a mirror inversion relationship with the check data and control data of the first memory data, respectively, and the check data of the third memory data and the first data Any one of the memory data check data, the third memory data control data, and the first memory data control data is the same, and the other is in a mirror inversion relationship. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the check data is set excluding all bits 0 and all bits 1. A data abnormality determination method for a semiconductor device for determining the presence or absence of abnormality in control data read from a storage unit of a first chip to a second chip,
When writing the control data to the storage means, the control data is stored at the address as memory data to which check data corresponding to a plurality of bits that are part of the storage destination address is added. For one control data, store the three memory data at different addresses,
In each address where three pieces of memory data related to one control data are stored, portions other than a part corresponding to the check data are different from each other and are the same in a plurality of control data,
In the three memory data related to one control data, the control data, the check data, and a part of addresses corresponding to the check data are in the same or mirror inversion relationship. West,
When reading the control data from the storage means to the second chip, a plurality of the control data are sequentially read, and three related memory data are sequentially read for each control data,
For each of the three memory data read out, each check data is compared with a part of the corresponding address, and when all the memory data does not match, it is determined that the memory data is abnormal,
In the plurality of memory data, when the check data and a part of the corresponding address match, the majority decision of the control data is performed for the plurality of matching memory data, and when the control data are different from each other, the memory A data abnormality determination method for a semiconductor device, characterized by determining that the data is abnormal. A data abnormality determination method for a semiconductor device for determining the presence or absence of abnormality in control data read from a storage unit of a first chip to a second chip,
When writing the control data to the storage means, the control data is stored at the address as memory data to which check data corresponding to a plurality of bits that are part of the storage destination address is added. For one control data, store the three memory data at different addresses,
In each address where three pieces of memory data related to one control data are stored, portions other than a part corresponding to the check data are different from each other and are the same in a plurality of control data,
In the three memory data related to one control data, the control data, the check data, and a part of addresses corresponding to the check data are in the same or mirror inversion relationship. West,
When reading the control data from the storage means to the second chip, a plurality of the control data are sequentially read, and three related memory data are sequentially read for each control data,
The majority decision of the control data is performed on the read three memory data, and when the control data is different from each other, it is determined that the memory data is abnormal,
When a plurality of the control data match, for the memory data including the matching control data, each check data is compared with a part of the corresponding address, and all the plurality of the memory data do not match A data abnormality determination method for a semiconductor device, characterized by determining an abnormality in memory data.

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