JP2012222632A - Solid-state image pickup device, driving method of the same and electronic information apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of increasing exposure time while suppressing decline in spatial resolution and sensitivity.SOLUTION: A CMOS image sensor 100 having a sensor array 110 formed by arraying a plurality of pixels in a matrix shape includes: a row selection part 130 for selecting a pixel row constituting the sensor array 110; a column selection part 140 for selecting a pixel column constituting the sensor array; and a timing control part 150 for controlling the row selection part and the column selection part. The timing control part 150 controls the row selection part and the column selection part so that pixel signals are read from first and second pixel groups obtained by grouping the plurality of pixels constituting the sensor array at timing different for each pixel group.

Description

  The present invention relates to a solid-state imaging device, a driving method thereof, and an electronic information device, and in particular, a solid-state imaging device capable of avoiding a maximum exposure time being limited by a frame rate during continuous shooting of moving images and the like, a driving method thereof, and an electronic information device It is about.

  2. Description of the Related Art Conventionally, a digital camera that photographs a subject uses a solid-state imaging device that converts light into an electrical signal and outputs an image signal. In recent years, in the field of solid-state imaging devices, with the increase in the number of pixels and the increase in frame rate, a technology for realizing high-speed reading and a technology for reducing power consumption have become indispensable technologies.

  As one of such solid-state imaging devices, there is a CMOS (including MOS) type image sensor (hereinafter referred to as “CMOS image sensor”) utilizing characteristics that can be manufactured by a process similar to that of a CMOS integrated circuit. The CMOS image sensor has a configuration in which signal charges obtained by photoelectric conversion are converted into electric signals for each pixel, and electric signals (pixel signals) corresponding to the respective pixels are processed in parallel for a plurality of pixel columns. ing. Such parallel processing of pixel signals can improve the reading speed of the pixel signals.

  FIG. 24 is a diagram for explaining a conventional CMOS image sensor that performs parallel processing of such pixel signals.

  The CMOS image sensor 20 is configured as one semiconductor chip, and pixels are arranged in a matrix on a semiconductor substrate (not shown) constituting the semiconductor chip, and a signal is converted by photoelectric conversion at each pixel. A sensor array 21 that generates electric charges, and a peripheral circuit unit that is integrated on the same semiconductor chip as the sensor array 21 and that reads out signal charges generated in the respective pixels of the sensor array 21 as pixel signals. Yes.

  Here, the peripheral circuit unit includes, for example, a row selection unit 23 that selects a predetermined pixel row from a plurality of pixel rows (horizontal pixel columns) in the sensor array 21, and each pixel from each pixel of the selected pixel row. An AD converter 22 that AD converts an analog pixel signal output to a read signal line (not shown) corresponding to a column and outputs a digital pixel signal as a pixel output OUT, and a read signal line corresponding to each pixel column Are selected based on the column selection signal Col, and an analog pixel signal is output from the readout signal line to the AD conversion unit 22, a column selection unit 23, an AD conversion unit 22, and a column selection unit And a timing control unit 25 for controlling the operation timing of 24 by the control signals TC1 and TC2.

  FIG. 25 is a block diagram showing the configuration of the sensor array 21 of the CMOS image sensor 20, and FIG. 26 is a diagram showing the configuration of the pixels.

  As shown in FIG. 26, the pixel P includes a photodiode (PD) PD, which is a photoelectric conversion element, and four pixel transistors, specifically, a transfer transistor Tt, an amplification transistor AMP, a selection transistor Ts, and a reset transistor Tr. Have.

  Here, the photodiode PD generates and accumulates signal charges by photoelectric conversion, and the transfer transistor Tr floats the signal charges accumulated in the photodiode PD based on the transfer signal Trans from the row selection unit 23. The data is transferred to a diffusion (charge storage unit) FD. The amplification transistor AMP has a gate connected to the charge storage unit FD, and converts the potential of the charge storage unit FD, which varies according to the amount of signal charge transferred, into an electric signal (pixel signal). . The selection transistor Ts selects a pixel from which a pixel signal is to be read out in units of rows based on the row selection signal Row from the row selection unit 23. The reset transistor Tr resets the potential of the charge storage unit FD to VDD (power supply voltage) based on the reset signal Reset from the row selection unit 23.

  In the sensor array 21, such pixels P are arranged in a matrix of m rows and n columns (5 rows × 4 columns in FIG. 25). For example, red pixels (R) and green pixels (G) are alternately arranged in the first pixel row, and green pixels (G) are arranged in the second pixel row. Blue pixels (B) are alternately arranged. Here, the pixel array of the odd-numbered pixel rows is the same as the pixel array of the first pixel row, and the pixel array of the even-numbered pixel rows is the same as the pixel array of the second pixel row. is there. In FIG. 25, pixels Pmn (m: 1 to 5, n: 1 to 4) indicate pixels in the m-th row and the n-th column.

  Also, read signal lines L1 to L4 are provided for each pixel column, and the pixel signal output from the selection transistor Ts of each pixel column is read to the corresponding read signal lines L1 to L4.

  Further, the same reset signal Reset, transfer signal Trans, and selection signal Row are supplied to the pixels in each pixel row. For example, the pixels P11 to P14 in the first row include a row selection unit. The reset signal Reset1, the transfer signal Trans1, and the selection signal Row1 are supplied from 23, and the signals Reset2 to 5 and Trans2 to 5 are similarly supplied to the pixels in the second to fifth pixel rows. The

  The read signal lines L1 to L4 are connected to one ends of the column selection transistors CTr1 to CTr4, and the other ends out1 to out4 of the column selection transistors CTr1 to CTr4 correspond to the read signal lines of the AD conversion unit 22, respectively. Connected to AD converter. The gates of the column selection transistors CTr1 to CTr4 are connected to the column selection signals col1 to col4.

  Next, the operation will be described.

  In such a conventional CMOS image sensor 20, the row selection unit 23, the column selection unit 24, and the AD conversion unit 22 are operated by the control signals TC 1 and TC 2 from the timing control unit 25, and each pixel of the sensor array 21 is changed from pixel to pixel. The signal is read out.

  In FIG. 27, the timings for resetting the charges of the pixels in each pixel row and the timing for reading the charges of the pixels are indicated by ● and ○, respectively. In FIG. 27, a plurality of pixel rows (horizontal pixel columns) are shown as the first to nth pixel columns.

  For example, when the reset transistor Tr of the pixel column in the first row is turned on by the reset signal Reset1 from the row selection unit 130 (timing S1), the charge storage unit FD is reset, and then, the selection signal Row When the selection transistor Ts is turned on (timing E1), a signal voltage (pixel signal) corresponding to the signal charge stored in the charge storage unit is amplified by the amplification transistor AMP and read to the read signal line L1 through the selection transistor Ts. . Here, for convenience of explanation, it is assumed that the transfer transistor of the pixel is turned on at a timing synchronized with the selection transistor.

  At this time, the period from the timing S1 to the timing E1 is the exposure time Te, and after the reset transistor Tr of the pixel in the pixel column of the first row is turned on by the reset signal Reset1, it is between the next turning on. Is one frame period (frame time difference) T.

  That is, the pixel signal of each pixel in the pixel row is read out to the corresponding readout signal lines L1 to L4 from the first pixel row shown in FIG. 25, and the pixel signal read out to each readout signal line is The column selection signals col1 to col4 are output to the AD converter 22 via the column selection transistors CTr1 to CTr4. The AD converter 22 converts the analog pixel signal input from the readout signal line into a digital pixel signal and outputs it as a pixel signal OUT.

  The operation of reading out the pixel signal corresponding to each pixel in the first pixel column is performed in the same manner from the second row onward, and when the pixel signal corresponding to each pixel in the nth pixel column is read out. , Pixel signals on the entire surface of the sensor array consisting of pixels of m rows × n columns are read out.

  The CMOS image sensor as described above is disclosed in Patent Document 1, for example.

JP 2010-263526 A

  By the way, in such a conventional CMOS image sensor, in order to increase a reading speed when capturing a moving image or the like, a thinning process for thinning out pixels to read out pixel signals or reading out pixel signals of a plurality of pixels simultaneously to obtain pixel values. Processing such as pixel addition is performed.

  FIGS. 28A and 28B are diagrams for explaining measures for increasing the reading speed. FIG. 28A shows pixel thinning processing, and FIG. 28B shows pixel addition processing.

  For example, FIG. 28A shows an array of pixels in 8 rows and 8 columns, that is, green pixels PGa and red pixels PR are alternately arranged from the left in odd rows, and blue pixels PB and green pixels from the left in even rows. An arrangement in which PGb is alternately arranged is shown.

  In such a pixel array, the pixels in the first and second columns in the first and second pixel rows, that is, the four pixels PGa, PR, PB, and PGb are grouped into 8 groups. By selecting the four groups G1 to G4 from the pixels in the pixel array of 8 rows and columns, the number of readout pixels is reduced and the readout speed of the entire sensor array is increased. In this case, the sensitivity is the same as normal all-pixel readout.

  FIG. 28B shows an array of pixels of 4 rows and 4 columns in the array of pixels of 8 rows and 8 columns shown in FIG.

  Here, the pixel values of the pixel P21 in the second row and first column, the pixel P23 in the second row and third column, the pixel P41 in the fourth row and first column, and the pixel P43 in the fourth row and third column are added, The blue pixel output data of the pixel region of 4 rows and 4 columns shown in FIG. Here, the pixels P21, P23, P41, and P43 are all blue pixels.

  Thus, four pixels are simultaneously selected and read out once, thereby reducing the number of times of reading and increasing the reading speed of the entire sensor array.

  In this case, the sensitivity of four pixels can be obtained because the charges of four pixels are integrated.

  By performing the thinning process and the pixel addition process during moving image shooting in this way, the reading speed can be increased, but there is a problem that the upper limit of the exposure time is limited by the frame rate.

  Further, in the thinning-out process, the upper limit of the exposure time is restricted, so that there is a problem that the image quality deteriorates due to insufficient exposure time at low illuminance.

  On the other hand, in the pixel addition process, the sensitivity is quadrupled, so that the exposure time is less problematic than the thinning process. However, since the pixel values of a plurality of pixels are added, there arises a problem that the spatial resolution deteriorates.

  The present invention has been made to solve the above-described problems. A solid-state imaging device capable of increasing an exposure time while suppressing a decrease in spatial resolution and sensitivity, a driving method thereof, and electronic information. The purpose is to obtain equipment.

  A solid-state imaging device according to the present invention is a solid-state imaging device having a pixel array in which a plurality of pixels are arranged in a matrix, a row selection unit that selects a pixel row constituting the pixel array, and the pixel array. A column selection unit that selects a pixel column to be configured; and a control unit that controls the row selection unit and the column selection unit. The control unit obtains a plurality of pixels that form the pixel array by grouping. The row selection unit and the column selection unit are controlled so that pixel signals are read out from a plurality of pixel groups at different timings for each pixel group, thereby achieving the above object.

  According to the present invention, in the solid-state imaging device, the plurality of pixel groups are first and second pixel groups obtained by dividing a plurality of pixels constituting the pixel array into two groups, and the control unit The row selection unit and the column selection unit are configured so that pixel signals of the pixels of the first pixel group are read out in odd frames and pixel signals of the pixels in the second pixel group are read out in even frames. It is preferable to control.

  According to the present invention, in the solid-state imaging device, the first pixel group includes four pixels of adjacent two rows and two columns as a unit pixel group, and the pixels in the pixel array are one unit pixel in a row direction and a column direction. It is a pixel group obtained by selecting every other group, and the second pixel group is a pixel group composed of unit pixel groups other than the unit pixel group included in the first pixel group in the pixel array. Is preferred.

  According to the present invention, in the solid-state imaging device, the plurality of pixel groups are first to fourth pixel groups obtained by dividing a plurality of pixels constituting the pixel array into four groups, and the control unit The pixel signal of the pixel of the first pixel group is read in the (4n-3) th (n is an integer) frame, and the pixel of the pixel of the second pixel group is read in the (4n-2) th frame. When the signal is read, the pixel signal of the pixel in the third pixel group is read out in the (4n-1) th frame, and the pixel signal of the pixel in the fourth pixel group is read out in the (4n) frame. It is preferable to control the row selection unit and the column selection unit.

  According to the present invention, in the solid-state imaging device, the first pixel group includes four pixels in two rows and two columns adjacent to each other in the pixel array as unit pixel groups, and unit pixels in odd rows and odd columns in the pixel array. A pixel group obtained by selecting a group, and the second pixel group is a pixel group obtained by selecting an odd row and even column unit pixel group in the pixel array, and the third pixel group Is a pixel group obtained by selecting unit pixel groups of even rows and even columns in the pixel array, and the fourth pixel group selects unit pixel groups of even rows and odd columns in the pixel array. It is preferable that the pixel group is obtained in this way.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that the control unit controls the row selection unit and the column selection unit so that exposure times are different in different pixel groups among the plurality of pixel groups.

  According to the present invention, in the solid-state imaging device, the pixel photoelectrically converts incident light to generate a signal charge, stores the signal charge generated by the photoelectric conversion unit, and stores the signal charge. A charge storage unit that generates a signal voltage corresponding to the amount of storage, a reset transistor that resets the signal charge stored in the charge storage unit, and amplifies the signal voltage generated in the charge storage unit and reads it as the pixel signal The control unit has a different reset timing for resetting the signal charges accumulated in the charge accumulation unit of the pixels constituting the pixel group in different pixel groups of the plurality of pixel groups, In addition, it is preferable to control the row selection unit so that read timings for reading out pixel signals from the pixels constituting the pixel group are the same.

  In the solid-state imaging device, the present invention is an AD conversion unit that converts an analog pixel signal read as the pixel signal into a digital pixel value, and a unit pixel group that constitutes a different pixel group among the plurality of pixel groups. It is preferable to include a pixel comparison processing unit that compares digital pixel signals from unit pixel groups close to each other between different pixel groups.

  In the solid-state imaging device according to the aspect of the invention, it is preferable that the pixel comparison processing unit compares digital pixel values of the same color pixel among the plurality of unit pixel groups close to each other.

  According to the present invention, in the solid-state imaging device, the pixel comparison processing unit determines an optimal digital pixel value suitable for an incident light amount based on a comparison result of the digital pixel value, and a pixel having the optimal digital pixel value belongs It is preferable that the digital pixel value of the pixel group is output as the representative digital pixel value of the unit pixel group close to each other.

  According to the present invention, in the solid-state imaging device, the pixel comparison processing unit is a unit pixel group that configures a different pixel group among the plurality of pixel groups based on the comparison result of the digital pixel value and the incident light amount. It is preferable to perform arithmetic processing on digital pixel values from a certain unit pixel group close to each other and output the digital pixel values obtained by this arithmetic processing as representative digital pixel values of the unit pixel groups close to each other.

  A driving method of a solid-state imaging device according to the present invention is a method for driving a solid-state imaging device having a pixel array in which a plurality of pixels are arranged in a matrix, and groups the plurality of pixels constituting the pixel array. The pixels of the plurality of pixel groups obtained in this manner are driven at independent timing for each pixel group, and pixel signals are read out at different timings for each pixel group, thereby achieving the above object.

  In the driving method of the solid-state imaging device according to the aspect of the invention, it is preferable that the plurality of pixel groups are driven so that exposure times are different in different pixel groups among the plurality of pixel groups.

  In the driving method of the solid-state imaging device according to the present invention, the pixel includes a photoelectric conversion unit that photoelectrically converts incident light to generate a signal charge, a signal charge generated by the photoelectric conversion unit, A charge accumulator that generates a signal voltage corresponding to the amount of signal charge accumulated; a reset transistor that resets the signal charge accumulated in the charge accumulator; and the pixel that amplifies the signal voltage generated in the charge accumulator And a reset timing for resetting the signal charge accumulated in the charge accumulation portion of the pixel constituting the pixel group is different in different pixel groups of the plurality of pixel groups, and The plurality of pixel groups are preferably driven so that the readout timings for reading out pixel signals from the pixels constituting the pixel group are the same.

  In the driving method of the solid-state imaging device, the present invention is a unit pixel group that converts an analog pixel signal read as the pixel signal into a digital pixel value and configures a different pixel group among the plurality of pixel groups. Digital pixel signals from unit pixel groups close to each other are compared between different pixel groups, and an optimal digital pixel value suitable for the amount of incident light is determined based on the comparison result of the digital pixel values, and the optimal digital pixel value It is preferable that a digital pixel value of a pixel group to which a pixel having a pixel belongs is output as a representative digital pixel value of the unit pixel group close to each other.

  In the driving method of the solid-state imaging device, the present invention is a unit pixel group that converts an analog pixel signal read as the pixel signal into a digital pixel value and configures a different pixel group among the plurality of pixel groups. Digital pixel signals from unit pixel groups close to each other are compared between different pixel groups, and different pixel groups of the plurality of pixel groups are configured based on the comparison result of the digital pixel values and the amount of incident light. To calculate digital pixel values from unit pixel groups close to each other, and output the digital pixel values obtained by this calculation processing as representative digital pixel values of the unit pixel groups close to each other. It is preferable.

  An electronic information device according to the present invention is an electronic information device including an imaging unit that captures an image of a subject, and the imaging unit is the above-described solid-state imaging device according to the present invention. Is done.

  Next, the operation will be described.

  In the present invention, in a solid-state imaging device having a sensor array in which a plurality of pixels are arranged in a matrix, a row selection unit that selects a pixel row that constitutes the pixel array and a pixel column that constitutes the pixel array are selected. A plurality of pixels obtained by grouping a plurality of pixels constituting the pixel array, and a timing control unit that controls the row selection unit and the column selection unit. Since the row selection unit and the column selection unit are controlled so that pixel signals are read out from the group at different timings for each pixel group, the exposure time can be increased while suppressing the reduction in spatial resolution and sensitivity.

  Further, in the present invention, since photographing is performed with different exposure times for each divided region, that is, for each pixel group, since the exposure times overlap, the simultaneity of the obtained pixel information can be increased.

  In the present invention, in the solid-state imaging device, only reset is performed by dividing each pixel group, and image reading is performed simultaneously by each pixel group. Therefore, the reset timing differs depending on the region (pixel group) of the pixel array. Thus, even when reading is performed simultaneously, the exposure time can be changed for each region, and the simultaneity of pixel information obtained from each pixel group can be increased.

  In the present invention, since the pixel information acquired from each pixel group is calculated and output based on a predetermined calculation formula in the solid-state imaging device, the dynamic range is expanded by combining pixel values having different exposure times. You can also.

  As described above, according to the present invention, it is possible to obtain a solid-state imaging device capable of increasing the exposure time while suppressing a decrease in spatial resolution and sensitivity, a driving method thereof, and an electronic information device.

FIG. 1 is a diagram showing a schematic configuration of a CMOS image sensor according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing the configuration of the sensor array of the CMOS image sensor according to Embodiment 1 of the present invention. FIG. 3 is a diagram for explaining the operation of the CMOS image sensor according to the first embodiment of the present invention. The timing for resetting the charge of the pixels in each pixel row and the timing for reading the charge of the pixels are indicated by ● and ○, respectively. ing. 4A and 4B are diagrams for explaining the operation of the CMOS image sensor according to the first embodiment of the present invention. FIGS. 4A and 4B show pixel groups (group A and group B) in the sensor array. Yes. FIG. 5 is a diagram for explaining the operation of the CMOS image sensor according to the first modification of the first embodiment of the present invention. The timing for resetting the charge of the pixels in each pixel row and the timing for reading the charge of the pixels are indicated by ● and Shown with a circle. FIG. 6 is a diagram for explaining the operation of the CMOS image sensor according to the first modification of the first embodiment of the present invention. The timing for resetting the charges of the pixels in each pixel row and the timing for reading the charges of the pixels (FIG. )), And the waveform of the control signal (FIG. 6B). FIG. 7 is a diagram for explaining the operation of the CMOS image sensor according to the first modification of the first embodiment of the present invention, in which pixel groups (groups A to D) in the sensor array (FIGS. 7A to 7D). ). FIG. 8 is a diagram for explaining the operation of the CMOS image sensor according to the second modification of the first embodiment of the present invention, and groups of pixels (group A to group D) in the sensor array (FIGS. 8A to 8D). ). FIG. 9 is a diagram for explaining a CMOS image sensor according to Embodiment 2 of the present invention. The timing for resetting the charge of the pixels in each pixel row and the timing for reading out the charges of the pixels (FIG. 9B) are shown as comparative examples. Are indicated by ● and ○, respectively. FIG. 10 is a diagram for explaining a CMOS image sensor according to the first modification of the second embodiment of the present invention. The timing for resetting the charge of the pixels in each pixel row and the timing for reading out the charges of the pixels are marked with ● and ○, respectively. Is shown. FIG. 11 is a diagram for explaining a CMOS image sensor according to the first modification of the second embodiment of the present invention. Timing for resetting the charges of the pixels in each pixel row and timing for reading out the charges of the pixels (FIG. 11A) , And the waveform of the control signal (FIG. 11B). FIG. 12 is a diagram for explaining a CMOS image sensor according to Embodiment 3 of the present invention, and the timing for resetting the charge of the pixels in each pixel row and the timing for reading out the charges of the pixels are indicated by ● and ○, respectively. . FIG. 13 is a diagram for explaining a CMOS image sensor according to the first modification of the third embodiment of the present invention. The timing for resetting the charge of the pixels in each pixel row and the timing for reading out the charges of the pixels are indicated by ● and ○, respectively. Is shown. FIG. 14 is a diagram for explaining a CMOS image sensor according to Modification 1 of Embodiment 3 of the present invention, in which the charge reset of the pixels in each pixel row and the timing of reading out the charge of the pixels (FIG. 14A), And the waveform (FIG. 14B) of the control signal is shown. FIG. 15 is a diagram for explaining a CMOS image sensor according to the first modification of the third embodiment of the present invention, and shows the pixel value level of each group. FIG. 16 is a diagram showing a schematic configuration of a CMOS image sensor according to Embodiment 4 of the present invention. FIG. 17 is a diagram for explaining a CMOS image sensor according to Embodiment 4 of the present invention, and shows pixel value levels of each group. FIG. 18 is a diagram for explaining a CMOS image sensor according to Embodiment 4 of the present invention. The relationship between the input light amount and the pixel output value (FIG. 18A), and the pixel output value selection process (FIG. 18B). FIG. 18 (c)). FIG. 19 is a diagram for explaining a CMOS image sensor according to the first modification of the fourth embodiment of the present invention, and shows calculation processing for pixel output values. FIG. 20 is a view for explaining a CMOS image sensor according to the fifth embodiment of the present invention. FIG. 21 is a diagram for explaining the operation of the CMOS image sensor according to the fifth embodiment of the present invention. FIG. 22 is a diagram for explaining a CMOS image sensor according to the first modification of the fifth embodiment of the present invention, and shows the charge reset and readout timing of the pixel in the operation. FIG. 23 is a block diagram illustrating a schematic configuration example of an electronic information device using the solid-state imaging device according to any of Embodiments 1 to 5 as an imaging unit as Embodiment 6 of the present invention. FIG. 24 is a diagram illustrating a schematic configuration of a conventional CMOS image sensor. FIG. 25 is a block diagram showing a configuration of a sensor array of the CMOS image sensor. FIG. 26 is a diagram illustrating a configuration of a pixel constituting the CMOS image sensor. FIG. 27 is a diagram for explaining the operation of the conventional CMOS image sensor, and the timings for resetting the charges of the pixels in each pixel row and the timing for reading the charges of the pixels are indicated by ● and ○, respectively. 28A and 28B are diagrams for explaining measures for increasing the reading speed in a conventional CMOS image sensor. FIG. 28A shows pixel thinning processing, and FIG. 28B shows pixel addition processing. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a schematic configuration of a CMOS image sensor according to Embodiment 1 of the present invention.

  The CMOS image sensor (solid-state imaging device) 100 according to the first embodiment includes a sensor array (pixel array) 110 in which a plurality of pixels are arranged in a matrix, and a row selection for selecting a pixel row constituting the sensor array 110. Unit 130, a column selection unit 140 that selects a pixel column constituting the pixel array, and an AD conversion unit 120 that converts an analog pixel signal read from the sensor array 110 into a digital pixel value (pixel output) OUT and outputs the digital pixel value (pixel output) OUT. And a timing control unit 150 for controlling the row selection unit 130 and the column selection unit 140 by control signals TC1 and TC2, respectively.

  Here, the timing control unit 150 selects the row so that pixel signals are read out at different timings for each pixel group from a plurality of pixel groups obtained by grouping a plurality of pixels constituting the sensor array 110. The unit 130 and the column selection unit 140 are configured to be controlled.

  4A and 4B are diagrams for explaining the operation of the CMOS image sensor according to the first embodiment of the present invention. FIGS. 4A and 4B show pixel groups (group A and group B) in the sensor array. Yes.

  Specifically, in the first embodiment, the timing control unit 150 reads out the pixel signals of the pixels of the first pixel group (group A shown in FIG. 4A) in the odd-numbered frame and outputs the pixel signal in the even-numbered frame. The row selection unit 130 and the column selection unit 140 are controlled so that the pixel signals of the pixels of the second pixel group (group B shown in FIG. 4B) are read out. The plurality of pixel groups are first and second pixel groups (group A and group B) obtained by dividing a plurality of pixels constituting the pixel array into two groups (FIG. 4A and FIG. 4). (See (b)).

  Here, the first pixel group (Group A) selects four pixels in adjacent two rows and two columns as a unit pixel group, and selects pixels in the pixel array for every one unit pixel group in the row direction and the column direction. The second pixel group (B group) is a pixel group made up of unit pixel groups other than the unit pixel group included in the first pixel group in the pixel array.

  FIG. 4A shows a first pixel group (group A) in a pixel array of 8 rows and 8 columns, and the first pixel group (group A) includes pixels P11, P12, P15, P16, P21, and P22. , P25, P26, P33, P34, P37, P38, P43, P44, P47, P48, P51, P52, P55, P56, P61, P62, P65, P66, P73, P74, P77, P78, P83, P84, P87 , P88. In the figure, the pixels with the right-up hatching are red pixels, the pixels with the left-up hatching are blue pixels, and the pixels with the dots are green pixels.

  FIG. 4B shows a second pixel group (group B) in the pixel array of 8 rows and 8 columns, and the second pixel group (group B) is the pixels P13, P14, P17, P18, P23, P24. , P27, P28, P31, P32, P35, P36, P41, P42, P45, P46, P53, P54, P57, P58, P63, P64, P67, P68, P71, P72, P75, P76, P81, P82, P85 , P86. In the figure, the pixels with right-up hatching are red pixels, the pixels with left-up hatching are blue pixels, and the pixels with dots are green pixels.

  FIG. 2 is a block diagram showing a configuration of the sensor array 110 of the CMOS image sensor 100.

  Also in the sensor array 110 of the first embodiment, the pixel P (Pmn (m: 1 to 5, n: 1 to 4) in FIG. 2) has the same configuration as that in the conventional CMOS image sensor shown in FIG. ing.

  In the sensor array 110 of Embodiment 1, such pixels P are arranged in a matrix of m rows and n columns (5 rows × 4 columns in FIG. 2). For example, red pixels (R) and green pixels (G) are alternately arranged in the first pixel row, and green pixels (G) are arranged in the second pixel row. Blue pixels (B) are alternately arranged. Here, the pixel arrangement of the odd-numbered pixel rows is the same as the pixel arrangement of the first pixel row (the uppermost pixel row in the drawing), and the pixel arrangement of the even-numbered pixel rows is the second row. This is the same as the pixel array of the pixel row. In FIG. 22, pixels Pmn (m: 1 to 5, n: 1 to 4) indicate pixels in the m-th row and the n-th column.

  Also, read signal lines L1 to L4 are provided for each pixel column, and the pixel signal output from the selection transistor Ts of each pixel column is read to the corresponding read signal lines L1 to L4.

  One of the reset signals ResetA and ResetB, the transfer signal Trans, and the selection signal Row are supplied to the pixels in each pixel row.

  That is, in the first embodiment, for example, among the pixels P11 to P14 in the first row, the first reset signal ResetA1 is supplied to the pixels P11 and P12 in the first column and the second column, and the first row Among the pixels P11 to P14 of the eye, the second reset signal ResetB1 is supplied to the pixels P13 and P14 in the third column and the fourth column.

  That is, in the entire sensor array 110, the first reset signal ResetAm is supplied to the pixels in the (4k-3) th and (4k-2) th columns, and the (4k-1) th and (4k) th columns are supplied. ) Column pixels are supplied with a second reset signal ResetBm, where k is a natural number.

  The read signal lines L1 to L4 are connected to one ends of the column selection transistors CTr1 to CTr4, and the other ends out1 to out4 of the column selection transistors CTr1 to CTr4 correspond to the read signal lines of the AD conversion unit 22, respectively. Connected to the AD converter. The gates of the column selection transistors CTr1 to CTr4 are connected to column selection signals col1 to col4 (column selection signal col in FIG. 1) output from the column selection unit 140. The AD converter corresponding to each read signal line is provided in the AD converter 120.

  Next, the operation will be described.

  In the conventional CMOS image sensor 100 having such a configuration, the row selection unit 130, the column selection unit 140, and the AD conversion unit 120 are operated by the control signals TC1 and TC2 from the timing control unit 150, and each pixel of the sensor array 110 is operated. A pixel signal is read out from.

  FIG. 3 is a diagram for explaining the operation of the CMOS image sensor according to the first embodiment of the present invention. Timings Sa1,..., San, Sb1,. .., Ean, Eb1,..., Ebn for reading out the charges of the pixels are indicated by ● and ○, respectively.

  For example, for the pixel column in the first row of the sensor array shown in FIG. 2, the reset transistor Tr of the pixels P11 and P12 is turned on by the reset signal ResetA1 (timing Sa1), the charge accumulation unit FD is reset, Thereafter, the selection transistor Ts is turned on by the row selection signal Row1 (timing Ea1), and the signal charge stored in the charge storage unit is amplified by the amplification transistor AMP and read to the read signal lines L1 and L2 via the selection transistor Ts. . Here, for simplification of explanation, the operation of the transfer transistor in the pixel is omitted. However, before the selection transistor is turned on, the operation is performed so that the signal charge is transferred to the charge storage portion FD. (See FIG. 26).

  At this time, the column selection transistors CTr1 and CTr2 are turned on by the control of the column selection unit 140, and the pixel signals of the pixels P11 and P12 are output to the AD conversion unit. On the other hand, the column selection transistor CTr3, CTr4 is turned off, and the pixel signals of the pixels P13 and P14 are not output to the AD converter.

  Also in the pixel column of the second row, when the reset transistors Tr of the pixels P21 and P22 are turned on by the reset signal ResetA2, the charge storage unit FD is reset, and then the selection transistor Ts is turned on by the row selection signal Row2. The signal charge stored in the charge storage section is amplified by the amplification transistor AMP and read out to the read signal lines L1 and L2 via the selection transistor Ts.

  At this time, the pixel signals of the pixels P21 and P22 are output to the AD conversion unit, but the pixel signals of the pixels P23 and P24 are output to the AD conversion unit, as in the case of reading out the pixel signals from the pixel column of the first row. Not.

  In the pixel column of the third row, the reset transistor Tr of the pixels P33 and P34 is turned on by the reset signal ResetB3, the charge accumulation unit FD is reset, and then the selection transistor Ts is turned on by the row selection signal Row3. The signal charge stored in the charge storage section is amplified by the amplification transistor AMP and read out to the read signal lines L3 and L4 via the selection transistor Ts.

  At this time, the column selection transistors CTr3 and CTr4 are turned on by the control of the column selection unit 140, and the pixel signals of the pixels P33 and P34 are output to the AD conversion unit, while the column selection transistors CTr1, CTr2 is turned off, and the pixel signals of the pixels P31 and P32 are not output to the AD converter.

  In the pixel column of the fourth row, the reset transistor Tr of the pixels P43 and P44 is turned on by the reset signal ResetB4, the charge accumulation unit FD is reset, and then the selection transistor Ts is turned on by the row selection signal Row4. The signal charge stored in the charge storage section is amplified by the amplification transistor AMP and read out to the read signal lines L3 and L4 via the selection transistor Ts.

  At this time, the pixel signals of the pixels P43 and P44 are output to the AD conversion unit, but the pixel signals of the pixels P41 and P42 are output to the AD conversion unit, as in the case of reading the pixel signals from the pixel column of the third row. Not.

  By repeating the pixel signal reading operation from the first row to the n-th pixel column, pixel signals are read from the pixels in the A group in the sensor array.

  In addition, in such a sensor array, a pixel signal read operation from the group B pixels is performed in parallel with a pixel signal read operation from the group A pixels. In the readout operation from the B group, the readout operation by the reset signal ResetA and the reset signal ResetB is opposite to the readout operation of the pixel signal from the pixels in the A group.

  That is, for the pixel column in the first row of the sensor array shown in FIG. 2, the reset transistor Tr of the pixels P13 and P14 is turned on by the reset signal ResetB1 (timing Sb1), the charge accumulation unit FD is reset, Thereafter, the selection transistor Ts is turned on by the row selection signal Row1 (timing Eb1), and the signal charge accumulated in the charge accumulation unit is amplified by the amplification transistor AMP and read to the read signal lines L3 and L4 via the selection transistor Ts. .

  At this time, the column selection transistors CTr3 and CTr4 are turned on under the control of the column selection unit 140, and the pixel signals of the pixels P13 and P14 are output to the AD conversion unit, while the column selection transistors CTr1, CTr2 is turned off, and the pixel signals of the pixels P11 and P12 are not output to the AD converter.

  Also in the pixel column of the second row, when the reset transistors Tr of the pixels P23 and P24 are turned on by the reset signal ResetB2, the charge storage unit FD is reset, and then the selection transistor Ts is turned on by the row selection signal Row2. The signal charge stored in the charge storage section is amplified by the amplification transistor AMP and read out to the read signal lines L3 and L4 via the selection transistor Ts.

  At this time, the pixel signals of the pixels P23 and P24 are output to the AD conversion unit, but the pixel signals of the pixels P21 and P22 are output to the AD conversion unit, as in the case of reading out the pixel signals from the pixel column of the first row. Not.

  In the pixel column of the third row, the reset transistor Tr of the pixels P31 and P32 is turned on by the reset signal ResetA3, the charge storage unit FD is reset, and then the selection transistor Ts is turned on by the row selection signal Row3. The signal charge stored in the charge storage section is amplified by the amplification transistor AMP and read out to the read signal lines L1 and L2 via the selection transistor Ts.

  At this time, the column selection transistors CTr1 and CTr2 are turned on by the control of the column selection unit 140, and the pixel signals of the pixels P31 and P32 are output to the AD conversion unit. On the other hand, the column selection transistor CTr3, CTr4 is turned off, and the pixel signals of the pixels P33 and P34 are not output to the AD converter.

  In the pixel column in the fourth row, the reset transistor Tr of the pixels P41 and P42 is turned on by the reset signal ResetA4, the charge storage unit FD is reset, and then the selection transistor Ts is turned on by the row selection signal Row4. The signal charge stored in the charge storage section is amplified by the amplification transistor AMP and read out to the read signal lines L1 and L2 via the selection transistor Ts.

  At this time, the pixel signals of the pixels P41 and P42 are output to the AD conversion unit, but the pixel signals of the pixels P43 and P44 are output to the AD conversion unit, as in the case of reading the pixel signals from the pixel column of the third row. Not.

  Such pixel signal readout operation is repeatedly performed from the first row to the n-th pixel column, whereby pixel signals are read from the group B pixels in the sensor array.

As described above, in the first embodiment, the pixels in the sensor array are read out in two groups of the A group and the B group, and the reading of these two groups can be performed in an overlapping manner, and the frame rate It is possible to secure a sufficient exposure time even for higher speed.
(Modification 1 of Embodiment 1)
FIG. 5 is a diagram for explaining the operation of the CMOS image sensor according to the first modification of the first embodiment of the present invention. Timings Sa1,..., San-2, Sb1, ..., Sbn-2, Sc1, ..., Scn, Sd1, ..., Sdn and timings for reading out the charges of the pixels Ea1, ..., Ean-2, Eb1, ..., Ebn-2, Ec1,..., Ecn, Ed1,..., Edn are indicated by ● and ○, respectively.

  FIG. 6 is a diagram for explaining the operation of the CMOS image sensor according to the first modification of the first embodiment of the present invention. The timing for resetting the charges of the pixels in each pixel row and the timing for reading the charges of the pixels (FIG. )), And the waveform of the control signal (FIG. 6B). FIG. 6 shows timings Sa1, Sb1, Sc1, Sd1 for resetting the charges of the pixels in the first pixel rows of the groups A to D shown in FIG. 5, and timings Ea1, Eb1 for reading the charges of the pixels. .

  FIG. 7 is a diagram for explaining the operation of the CMOS image sensor according to the first modification of the first embodiment of the present invention, and shows pixel groups (Group A to Group D) in the sensor array.

  In the first modification of the first embodiment, the pixels in the sensor array are read out in four groups of groups A to D, and the reading of these four groups can be performed in an overlapping manner. It is possible to secure a sufficient exposure time for increasing the frame rate.

  That is, in the 8 × 8 pixel array shown in FIG. 7, the first column, the second row, the fifth row, and the sixth row are arranged in the first row, the second row, the fifth row, and the sixth row, respectively. The pixels in the second column, the fifth column, and the sixth column are selected. The reset signal ResetA1, row selection signal Row1, and column selection signals ColA and ColB at this time are as shown in FIG. Here, the column selection signal ColA is a column selection signal for selecting the A group and the D group, and the column selection signal ColB is a column selection signal for selecting the B group and the C group.

  Hereinafter, readout of pixel signals from the A group of pixels in the 8-by-8 pixel array shown in FIG. 7A will be specifically described.

  The potentials of the charge storage portions FD of the pixels P11, P12, P15, and P16 in the first (first) pixel column of the 8-by-8 pixel array are reset by the reset signal ResetA1 (timing Sa1), and then In response to the row selection signal Row1, the signal charges accumulated in the charge accumulation portions of these pixels are read out to the corresponding readout signal lines (timing Ea1). At this time, the column selection signal ColA turns on the column selection transistors of the first, second, fifth, and sixth pixel columns, and the pixel signals of the pixels P11, P12, P15, and P16 are AD converted. On the other hand, the column selection signal ColB turns off the column selection transistors of the third, fourth, seventh, and eighth pixel columns, and the pixel signals of the pixels P13, P14, P17, and P18 are It is not output to the AD converter.

  In the same manner as the charge reset and charge read in the pixel column of the first row, the charge reset and charge read in the pixel columns of the second row, the fifth row, and the sixth row are performed, and the pixel P11 in the A group, Pixel signals P12, P15, P16, P21, P22, P25, P26, P51, P52, P55, P56, P61, P62, P65, and P66 are output to the AD conversion unit.

  Further, as the pixels of the B group, the pixels in the third column, the fourth column, the seventh column, and the eighth column in the pixel columns of the first row, the second row, the fifth row, and the sixth row, respectively. Select. The reset signal ResetB1, the row selection signal Row1, and the column selection signals ColA and ColB at this time are as shown in FIG.

  The potentials of the charge storage portions FD of the pixels P13, P14, P17, and P18 in the first (first) pixel column of the 8-by-8 pixel array are reset by the reset signal ResetB1 (timing Sb1), and then In response to the row selection signal Row1, the signal charges accumulated in the charge accumulation portions of these pixels are read out to the corresponding readout signal lines (timing Eb1). At this time, the column selection transistor Col of the third, fourth, seventh, and eighth pixel columns is turned on by the column selection signal ColB, and the pixel signals of the pixels P13, P14, P17, and P18 are AD converted. On the other hand, the column selection signal ColA turns off the column selection transistors of the first, second, fifth, and sixth pixel columns, and the pixel signals of the pixels P11, P12, P15, and P16 are It is not output to the AD converter.

  In the same manner as the charge reset and charge readout in the pixel column of the first row, the charge reset and charge readout in the pixel columns of the second row, the fifth row, and the sixth row are performed, and the pixel P13 in the B group, Pixel signals P14, P17, P18, P23, P24, P27, P28, P53, P54, P57, P58, P63, P64, P67, and P68 are output to the AD converter.

  In addition, as the pixels in the C group, the pixels in the third, fourth, seventh, and eighth columns in the third, fourth, seventh, and eighth pixel columns, respectively. Select. The reset signal ResetB1, the row selection signal Row3, and the column selection signals ColA and ColB at this time are as shown in FIG.

  The potentials of the charge storage portions FD of the pixels P33, P34, P37, and P38 in the third pixel column of the pixel array of 8 rows and 8 columns are reset by the reset signal ResetB3 (timing Sc1), and then the row selection signal Row3. As a result, the signal charges accumulated in the charge accumulation portions of these pixels are read out to the corresponding readout signal lines. At this time, the column selection signal ColB turns on the column selection transistors of the third, fourth, seventh, and eighth pixel columns, and the pixel signals of the pixels P33, P34, P37, and P38 are sent to the AD conversion unit. On the other hand, the column selection signal ColA turns off the column selection transistors of the first, second, fifth, and sixth pixel columns, and the pixel signals of the pixels P31, P32, P35, and P36 are AD converted. It is not output to the part.

  In the same manner as the charge reset and charge readout in the pixel column of the third row, the charge reset and charge readout in the pixel columns of the fourth row, the seventh row, and the eighth row are performed, and the pixel P33 in the B group, Pixel signals P34, P37, P38, P43, P44, P47, P48, P73, P74, P77, P78, P83, P84, P87, and P88 are output to the AD converter.

  In addition, as pixels in the D group, pixels in the first column, the second column, the fifth column, and the sixth column in the pixel columns of the third row, the fourth row, the seventh row, and the eighth row, respectively. Select. The reset signal ResetA1, the row selection signal Row3, and the column selection signals ColA and ColB at this time are as shown in FIG.

  The potentials of the charge storage portions FD of the pixels P31, P32, P35, and P36 in the third pixel column of the pixel array of 8 rows and 8 columns are reset by the reset signal ResetA3 (timing Sd1), and then the row selection signal Row3. Thus, the signal charges accumulated in the charge accumulation portions of these pixels are read out to the corresponding readout signal lines. At this time, the column selection signal ColA turns on the column selection transistors of the first, second, fifth, and sixth pixel columns, and the pixel signals of the pixels P31, P32, P35, and P36 are AD converted. On the other hand, the column selection signal ColB turns off the column selection transistors of the third, fourth, seventh, and eighth pixel columns, and the pixel signals of the pixels P33, P34, P37, and P38 are It is not output to the AD converter.

  In the same manner as the charge reset and charge readout in the pixel column of the third row, the charge reset and charge readout in the pixel columns of the fourth row, the seventh row, and the eighth row are performed, and the pixel P31 in the D group, Pixel signals P32, P35, P36, P41, P42, P45, P46, P71, P72, P75, P76, P81, P82, P85, and P86 are output to the AD conversion unit.

As described above, in the first modification of the first embodiment, the pixels in the sensor array are read out in four groups of the A group to the D group, and these four groups can be read out in an overlapping manner. In addition, it is possible to secure a sufficient exposure time even when the frame rate is increased.
(Modification 2 of Embodiment 1)
FIG. 8 is a diagram for explaining the operation of the CMOS image sensor according to the second modification of the first embodiment of the present invention, and shows pixel groups (Group A to Group D) in the sensor array.

  The second modification of the first embodiment is different from the first modification of the first embodiment only in the position of each pixel in the pixel group (Group A to Group D) in the sensor array.

When the plurality of pixels constituting the sensor array are divided into four groups, the timing control unit outputs the pixel signals of the pixels of the first pixel group in the (4n-3) th (n is an integer) frame. Is read, the pixel signal of the pixel of the second pixel group is read in the (4n-2) th frame, and the pixel signal of the pixel of the third pixel group is read in the (4n-1) th frame. However, the row selection unit and the column selection unit are controlled so that the pixel signals of the pixels of the fourth pixel group are read in the (4n) th frame.
(Embodiment 2)
FIG. 9 is a diagram for explaining a CMOS image sensor according to Embodiment 2 of the present invention. The timing for resetting the charge of the pixels in each pixel row and the timing for reading out the charges of the pixels (FIG. 9B) are shown as comparative examples. Are indicated by ● and ○, respectively.

  The CMOS image sensor according to the second embodiment is different from the CMOS image sensor according to the first embodiment in that the control unit is configured so that the exposure time is different between different pixel groups of the first and second pixel groups A and B. The selection unit and the column selection unit are controlled.

  Hereinafter, the operation of the CMOS image sensor of the second embodiment will be described with reference to FIG. 9B in contrast to the operation of the conventional CMOS image sensor (FIG. 9A).

  When photographing the same subject with two types of exposure times ELt and ESt, the conventional CMOS image sensor continuously shoots by changing the exposure time for each frame.

  For example, the pixel column in the first row is reset at timing S1, read out at timing E1, and further reset at this timing E1, so that reading is performed at the subsequent timing Ea1 to obtain the result shown in FIG. As shown, a long exposure time ELt and a short exposure time ESt occur. Similarly, by reading out pixels in each row, it is possible to shoot with different exposure times for each frame. However, even if charge readout is used as a substitute for charge reset, a time difference corresponding to a short exposure time ESt occurs between the two images.

  On the other hand, in the second embodiment of the present invention, the exposure time of the B group is overlapped by shooting with different exposure times such as the long exposure time ELt in the A group and the short exposure time ESt in the B group. Therefore, the time difference between the two images can be reduced to the pixel reading time of the A group.

As described above, even in the conventional technique, it is possible to capture with different exposure times in units of frames. However, in the second embodiment, the exposure time overlaps by capturing with different exposure times for each divided region. The simultaneity increases.
(Modification 1 of Embodiment 2)
FIG. 10 is a diagram for explaining a CMOS image sensor according to the first modification of the second embodiment of the present invention, and timings Sa1,..., San-2, Sb1,. .., Sbn-2, Sc1,..., Scn, Sd1,..., Sdn and timings for reading out the charges of the pixels Ea1,..., Ean-2, Eb1,. .., Ecn, Ed1,..., Edn are indicated by ● and ○, respectively.

  FIG. 11 is a diagram for explaining a CMOS image sensor according to the first modification of the second embodiment of the present invention. Timing for resetting the charges of the pixels in each pixel row and timing for reading out the charges of the pixels (FIG. 11A) , And the waveform of the control signal (FIG. 11B). Note that FIG. 11 shows timings Sa1, Sb1, Sc1, Sd1 for resetting the charges of the pixels in the first pixel rows of the groups A to D shown in FIG. 10, and timings Ea1, Eb1 for reading the charges of the pixels. .

  In the first modification of the second embodiment, in the CMOS image sensor of the second embodiment, the pixels in the sensor array are read by being divided into four groups of A group to D group.

  Here, the exposure time ELt is increased in the A group and the C group, and the exposure time ESt is decreased in the B group and the D group.

Other configurations of the CMOS image sensor according to the first modification of the second embodiment are the same as those of the CMOS image sensor of the second embodiment.
(Embodiment 3)
FIG. 12 is a diagram for explaining a CMOS image sensor according to Embodiment 3 of the present invention. Timings Sa1,..., San, Sb1,. The timings Ea1,..., Ean for reading out charges are indicated by ● and ◯, respectively.

  In the CMOS image sensor of the third embodiment, in the CMOS image sensor 100 of the first embodiment, the timing control unit 150 is the first and second pixel groups A and B, and only the reset is performed separately, that is, the timing Sa1, .., San, Sb1,..., Sbn, and the row selection unit and the column selection unit are controlled so that charge reading is performed simultaneously, that is, at timings Ea1,. It is a thing.

  That is, in the third embodiment of the present invention, as shown in FIG. 12, only the reset is performed at different timings in the first and second pixel groups A and B (for example, timings Sa1 and Sb1 in the first pixel column). The charge readout is performed simultaneously (for example, timing Ea1 in the first pixel column).

  As described above, in the third embodiment, only reset is performed by dividing the pixel groups A and B, and the image reading is performed simultaneously on the pixel columns in each row as in the conventional case.

For this reason, since the reset timing differs depending on the area of the sensor array, the exposure time can be changed for each area even when reading is performed simultaneously, and the simultaneity of pixel signals can be further increased.
(Modification 1 of Embodiment 3)
FIG. 13 is a diagram for explaining a CMOS image sensor according to the first modification of the third embodiment of the present invention. The timing for resetting the charge of the pixels in each pixel row and the timing for reading out the charges of the pixels are indicated by ● and ○, respectively. Is shown.

  FIG. 14 is a diagram for explaining a CMOS image sensor according to Modification 1 of Embodiment 3 of the present invention. Timing for resetting the charge of the pixels in each pixel row and timing for reading out the charges of the pixels (FIG. 14A) , And the waveform of the control signal (FIG. 14B).

  In the first modification of the third embodiment, in the CMOS image sensor of the third embodiment, the pixels in the sensor array are read out in four groups A group to D group. Here, Group A to Group D are the same as Group A to Group D shown in FIGS.

  Here, the timing shown in FIG. 14 (a) is obtained by taking out the timing of the first row of the groups A, B, C, and D shown in FIG. 13, and FIG. 14 (b) is the same as FIG. 14 (a). Are replaced with the timings of the row selection signal and the column selection signal.

  Here, since all pixels are read out, the column selection signals ColA and ColB become High at the same time.

  Further, since the charge reading of the pixels is performed without skipping from the first row to the 4nth row, the charges of the pixels of the pixel groups A to D are read at the same timing in the same pixel row of the sensor array, and exposure is performed. The time is set so that the pixels in the A group are the longest and the pixels in the D group are the shortest. That is, assuming that the exposure times EA to ED of the pixels in the A group to the D group are EA> EB> EC> ED. However, the order of shortening the exposure time is not limited to this.

  Other configurations of the CMOS image sensor according to the first modification of the third embodiment are the same as those of the CMOS image sensor of the third embodiment.

  FIG. 15 is a diagram for explaining a CMOS image sensor according to the first modification of the third embodiment of the present invention, and shows the pixel value level of each group.

  In the CMOS image sensor of Modification 1 of Embodiment 3, as shown in FIG. 15, pixel information corresponding to one screen is output in a state where pixel information of four types of exposure times are mixed.

  Note that the pixel group Ga shown in FIG. 15 is a unit pixel group that constitutes the A group shown in FIG. 7 (FIG. 7A), and has four adjacent pixels (the upper left green pixel, the upper right red pixel, and the lower left pixel). Blue pixel, lower right green pixel).

  Similarly, the pixel groups Gb to Gd shown in FIG. 15 are unit pixel groups constituting the B group to D group (FIGS. 7B to 7D) shown in FIG. Consists of four adjacent pixels (upper left green pixel, upper right red pixel, lower left blue pixel, lower right green pixel).

  That is, the pixels of the unit pixel group Ga that constitutes the A group have the longest exposure time, and the pixels of the unit pixel group Cb that constitute the B group have the second longest exposure time, and the unit pixel group Gc that constitutes the C group. The exposure time is the second shortest, and the pixels of the unit pixel group Cd constituting the D group have the shortest exposure time.

It is also possible to expand the dynamic range by processing information on pixel value levels of a plurality of groups having different exposure times.
(Embodiment 4)
FIG. 16 is a diagram showing a schematic configuration of a CMOS image sensor according to Embodiment 4 of the present invention. FIG. 17 is a diagram for explaining a CMOS image sensor according to Embodiment 4 of the present invention, and shows pixel value levels of each group.

  The CMOS image sensor 400 according to the fourth embodiment configures different pixel groups (that is, a group A to a group D shown in FIG. 7) among the plurality of pixel groups in the CMOS image sensor 100 according to the first modification of the third embodiment. A pixel comparison processing unit 467 that compares digital pixel signals from unit pixel groups Ga to Gd that are adjacent to each other, which are unit pixel groups, between different pixel groups is added, and adjacent to the left and right and up and down of the pixels in the sensor array. As a pixel signal of the adjacent pixel region RG composed of four unit pixel groups, a pixel signal of one unit pixel group of four groups of A group to D group is selected and read out to the AD conversion unit. is there.

  Here, the pixel comparison processing unit 467 includes a pixel comparison unit 460 and a line memory 470, stores the pixel information from the A group and the B group in the line memory 470, and the pixel information from the C group and the D group is stored. When obtained from the sensor array, the pixel comparison unit 460 compares the pixel information of the four groups A to D between the same color pixels.

  The line memory is not necessary when the pixel group is not divided in the row direction. In other words, when pixel division is not performed in the row direction, pixels to be compared appear in close proximity in the same row, so comparison is performed if each color has R, Gr, B, and Gb as many storage areas as the number of divisions. be able to.

  Specifically, using FIG. 7, when the pixel group is not divided in the row direction, the A group (FIG. 7A) and the D group (FIG. 7D) are not divided and one group is not divided. Group (first group) is formed, group B (Fig. 7 (b)) and group C (Fig. 7 (c)) are not divided, forming one group (second group) In this case, a pixel in a different pixel row (for example, pixel P31 for pixel P11) is not a comparison target with pixel P11, and a pixel to be compared (pixel P13 for pixel P11) is , Appear in a close location in the same row (first row) as the pixel P11. Therefore, for example, in order to hold the pixel signal of the pixel P11 until the pixel signal of the second group of pixels P13 to be compared with the first group of pixels P11 is output, it is necessary to have a storage area corresponding to the number of divisions. The pixel signals can be compared. In this case, no line memory is required. On the other hand, as shown in FIGS. 7A to 7D, when the pixel group is divided in the row direction, pixels in different pixel rows (for example, pixels P31 and P33 with respect to the pixel P11) are also different from the pixel P11. Pixels to be compared and to be compared (pixels P31 and P33 with respect to the pixel P11) appear in a different row (third row) from the pixel P11. Therefore, a line memory is required to hold the pixel signals of the pixels P11 and P13 until the pixel signal of the group C pixel P33 to be compared with the group A pixel P11 is output.

  18 shows the relationship between the input light quantity and the pixel output value (FIG. 18A), the pixel output value selection process (FIG. 18B), and the pixel output value selection method according to the input light quantity (FIG. It is a figure explaining c)).

  In such a CMOS image sensor, based on the relationship between the pixel output value of each group obtained by the pixel comparison unit 460 and the input light amount in the shooting state, as shown in FIG. An appropriate group of pixel output values can be selected based on the selection formula shown in FIG.

  For example, considering the case where the input light amount is the input light amount InA as shown in FIG. 18C, the pixel output value reaches the saturation level because the exposure time is long in the pixels of the A group and the B group, The signal amount of the input light amount InA cannot be measured correctly.

  In general, in order to accurately measure the signal amount of the input light amount InA, it is better that the signal level (pixel output value) is as large as possible within the measurement range.

  However, since the linearity may be lost if the pixel output value is too close to the saturation level, 90% of the actual saturation level is regarded as a criterion for determining the saturation level in the selection formula shown in FIG.

  As shown in FIG. 18C, the signal amount of the input light amount InA can be correctly measured in both the C group and D group pixels. For the above reason, the pixel signal of the C group pixel is selected, A value obtained by multiplying the pixel signal by a gain (gain C) corresponding to the group C is output as a pixel output value.

  The value obtained by multiplying the pixel information by the gain is used as the pixel output value so that the output pixel output value becomes the same level regardless of which group is selected.

  Specifically, paying attention to the input light amount InB, when the digital pixel signals outA to outD from the AD conversion units of the pixels of the A group to the D group are directly used as the pixel output values, the same due to the difference in the exposure time of each group. The pixel output value Out differs with respect to the input light amount In.

  Therefore, correction is performed by multiplying each signal by gainA to D so that the same pixel output InB can be obtained regardless of which signal is selected.

  For example, the ratio of the signal level of the pixel signal from each group of pixels is 8 (group A): 4 (group B): 2 (group C): 1 (D according to the difference in exposure time of each group. Group A to D, for example, values corresponding to the ratio of the signal levels, that is, gain A = 1.5, gain B = 3, gain C = 6, and gain D = 12, are set.

  In this case, if the pixel output values of the pixels of the A group, the B group, the C group, and the D group with respect to the input light amount InB are 8, 4, 2, 1, respectively, the gain corresponding to the pixel output value of each group. , The pixel output value of each group with respect to the input light amount InB becomes a constant value as follows.

Pixel output value of group A = outA × gain A = 8 × 1.5 = 12.
Group B pixel output value = outB × gainB = 4 × 3 = 12.
C group pixel output value = outC × gainC = 2 × 6 = 12.
D group pixel output value = outD × gainD = 1 × 12 = 12.
(Modification 1 of Embodiment 4)
FIG. 19 is a diagram for explaining a CMOS image sensor according to the first modification of the fourth embodiment of the present invention, and shows calculation processing for pixel output values.

  In the first modification of the fourth embodiment, instead of selecting a group from which appropriate pixel information can be obtained from the four groups of pixel output values as in the fourth embodiment, a predetermined calculation is performed on the four groups of pixel output values. The pixel value obtained by performing the process is output, and other configurations are the same as those in the fourth embodiment.

In each of the above embodiments, the exposure time in each group may be feedback controlled according to the imaging situation.
(Embodiment 5)
FIG. 20 is a diagram showing a schematic configuration of a CMOS image sensor according to Embodiment 5 of the present invention. FIG. 21 is a diagram for explaining the operation of the CMOS image sensor according to the fifth embodiment of the present invention.

  In the CMOS image sensor 500 of the fifth embodiment, the exposure time is controlled based on the pixel output value output from the AD converter 520 in the CMOS image sensor 100 of the first embodiment.

  That is, the CMOS image sensor 500 according to the fifth embodiment determines the luminance level of the subject based on the imaging unit 500a that images the subject and the digital pixel signal (pixel output value) output from the imaging unit 500, And a digital signal processing unit (DSP) 500b that controls the exposure time of the pixels in the A group and the B group based on the determination result.

  Similar to the CMOS image sensor 100 of the first embodiment, the imaging unit 500a selects a sensor array (pixel array) 510 in which a plurality of pixels are arranged in a matrix, and a row that selects a pixel row that constitutes the sensor array 510. A selection unit 530, a column selection unit 540 for selecting a pixel column constituting the pixel array, and an AD conversion unit for converting an analog pixel signal read from the sensor array 510 into a digital pixel value (pixel output) OUT and outputting the digital pixel value (pixel output) OUT 520, and a timing control unit 550 that controls the row selection unit 530 and the column selection unit 540 with control signals TC1 and TC2, respectively.

  Here, the sensor array (pixel array) 510, the row selection unit 530, the column selection unit 540, and the AD conversion unit 520 are the same as those in the CMOS image sensor of the first embodiment, and the timing control unit is Based on the exposure time data Tex for controlling the exposure time from the digital signal processing unit 500b, the row selection unit 530 is controlled to change the reset timing of the pixels in the A group and the B group. Yes.

  Also, the digital signal processing unit 500b performs timing control so that the luminance information is calculated based on the digital pixel signal and the exposure time is changed based on the luminance information obtained by the luminance integration unit. An exposure control unit 502 that outputs exposure time data Tex to the unit 550.

  The exposure time is generally controlled by the digital signal processing unit (DSP) 500b as described above, but the DSP 500b may be mounted on the same chip as the sensor (imaging unit) 500a. Further, a CPU of a general-purpose computer such as a personal computer may be used for controlling the exposure time.

  The luminance integrating unit 501 is configured to calculate the luminance information of the A group from all the pixel information of the A group during the image processing, and obtain a luminance value distribution (luminance histogram). The unit 502 evaluates whether or not the luminance value distribution is a target distribution. When the luminance distribution is closer to the high luminance side, the exposure time is shortened. The exposure time is set to the timing control unit 550 so as to be longer.

  Next, the operation will be described.

  FIG. 21 is a diagram for explaining the operation of the CMOS image sensor according to the fifth embodiment of the present invention. Timings Sa1,..., San, Sb1,. .., Ean, Eb1,..., Ebn for reading out the charges of the pixels are indicated by ● and ○, respectively.

  In the CMOS image sensor according to the fifth embodiment, the pixel signals are read into two groups of A group and B group and read out in the same manner as the CMOS image sensor according to the first embodiment.

  In the fifth embodiment, the digital signal processing unit 500b performs feedback control of the exposure time in the sensor array based on the group A pixel output values.

  That is, at timing Ta, the DSP unit 500b reads all image information of the A group (that is, pixel signals of all pixels of the A group). The DSP unit 500b integrates the luminance from the read image information, and evaluates the exposure time of the image FA1 of the group A that has read the image information. As described above, the luminance information obtained by the luminance integration is the target luminance. Depending on whether it is higher or lower.

  Then, at the timing Tb when such luminance determination processing is completed, the exposure time is set in the timing control unit 550 according to the exposure time data Tex as necessary. Note that the time difference between the timings Ta and Tb corresponds to the processing time in the DSP unit.

  However, at the timing Tb, the pixels in the first row of the group A image FA2 (that is, the image of the next frame of the group A image FA1) have already started exposure (timing Tc). That is, the timing Tc is the reset timing Sa1 for the pixel column in the first row of the A group.

  Therefore, for the A group, the evaluation result of the exposure time of the group A image FA1 is reflected in the exposure time at the time of imaging from the next frame of the A group image FA2.

  Also, for the B group, the timing Tb is the timing immediately before the output of the B group image FB1 starts, that is, immediately before reading (timing Td), and therefore the evaluation result of the exposure time of the A group image FA1 is used as the B group image FB1. And cannot be reflected on the image FB2 of the next frame of the group B image FA1.

  Further, if the processing of the DSP unit is slow and the completion of the exposure time evaluation of the A group image FA1 is delayed from the timing Tb to the timing Tb ′, the A group starts from the next frame of the A group image FA2 as described above. The evaluation result of the exposure time of the A group image FA1 is reflected in the exposure time at the time of imaging. For the B group, the evaluation result of the exposure time of the A group image FA1 is the next of the B group image FB2. It is reflected from an image (not shown) of the frame.

  This is because the timing Tb 'is before the exposure start timing Te of the B group image FB2, but the timing Te may be advanced to the timing Td depending on the setting of the exposure time.

In the fifth embodiment, the feedback control of the exposure time when the same exposure time is set in the A group and the B group has been described. However, the A group, the B group (or the A group, the B group, the C group, and the D group). When different exposure times are set for each group, the DSP unit 500b evaluates the images of the A group and the B group (or the A group, the B group, the C group, and the D group), respectively, and the A group and the B group ( Or you may make it reflect in each exposure time of A group, B group, C group, and D group).
(Modification 1 of Embodiment 5)
FIG. 22 is a diagram for explaining a CMOS image sensor according to the first modification of the fifth embodiment of the present invention, and shows the pixel value level of each group.

  The CMOS image sensor 500 of the fifth embodiment is such that the exposure time is controlled based on the pixel output value output from the AD converter in the CMOS image sensor of the first modification of the third embodiment shown in FIG. It is.

  The CMOS image sensor according to the first modification of the fifth embodiment includes a digital signal processing unit (DSP) similar to the CMOS image sensor according to the fifth embodiment, and a digital pixel signal (pixel) output from the imaging unit 500. The luminance level of the subject is determined based on the output value), and the exposure time at the pixels in the A group to D group is controlled based on the determination result.

  Next, the operation will be described.

  In the CMOS image sensor according to the first modification of the fifth embodiment, the operation of reading the pixel signals divided into four groups of A group to D group is performed similarly to the CMOS image sensor according to the first modification of the third embodiment.

  And in the modification 1 of this Embodiment 5, the digital signal processing part (DSP part) performs feedback control of the exposure time in a sensor array based on the pixel output value of A group.

  Hereinafter, the operation when the DSP unit feeds back the evaluation result of the group A image F1 will be specifically described.

  The DSP reads the data of the image F1 (timing Ta), and evaluates the exposure time from the read image data.

  Based on the evaluation result at timing Tb, exposure time data is set in the timing control unit of the CMOS image sensor. Here, the time difference between the timings Ta and Tb corresponds to the processing time of the exposure time evaluation in the DSP unit.

  At this timing Tb, since the part constituted by the pixels of the A group in the image F2 starts exposure (timing Tc), the timing control unit of the CMOS image sensor is set by the exposure time data from the DSP unit. The exposure time is reflected from the image of the next frame of the image F2.

  The timing Tc for starting the exposure of the A group is advanced to the position of the timing Tc ′ when the exposure time is the longest. Therefore, basically, the exposure time is set to 2 of the frame for which the exposure time evaluation is performed. It will be reflected in the next frame.

  However, when the processing of the DSP unit is slow and the timings Ta to Tb take one frame time or more, the frame that can reflect the evaluation result of the exposure time is further away from the frame for which the exposure time evaluation is performed.

  In the first modification of the fifth embodiment, the exposure time data may be set for each of the A to D groups. However, the exposure time for the A group: the exposure time for the B group: the exposure time for the C group: As the exposure time of group D = 4: 3: 2: 1, the ratio of the exposure time in each group is determined to set one exposure time, thereby simultaneously setting the exposure time of the four groups. It is also possible to change.

Furthermore, although not specifically described in the first to fifth embodiments, for example, a digital video camera using at least one of the first to fifth embodiments or a solid-state imaging device according to a modification of these embodiments as an imaging unit. An electronic information device having an image input device, such as a digital camera such as a digital still camera, an image input camera, a scanner, a facsimile, and a camera-equipped mobile phone device will be briefly described below.
(Embodiment 6)
FIG. 23 is a block diagram illustrating a schematic configuration example of an electronic information device using, as an embodiment 6 of the present invention, a CMOS image sensor (solid-state imaging device) according to any of the above-described embodiments 1 to 5 or a modification thereof as an imaging unit. .

  An electronic information device 90 according to Embodiment 6 of the present invention shown in FIG. 23 includes at least one of the solid-state imaging devices according to Embodiments 1 to 5 of the present invention or modifications thereof as an imaging unit 91 that captures a subject. And a memory unit 92 such as a recording medium for recording data after high-quality image data obtained by photographing by such an imaging unit is subjected to predetermined signal processing for recording, and this image data for display A display unit 93 such as a liquid crystal display device that displays on a display screen such as a liquid crystal display screen after performing predetermined signal processing, and a communication unit such as a transmission / reception device that performs communication processing after processing this image data for predetermined signal processing 94 and at least one of an image output unit 95 for printing (printing) and outputting (printing out) the image data.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention can provide a solid-state imaging device capable of increasing an exposure time while suppressing a decrease in spatial resolution and sensitivity in the fields of a solid-state imaging device, a driving method thereof, and an electronic information device.

DESCRIPTION OF SYMBOLS 90 Electronic information apparatus 91 Imaging part 92 Memory part 93 Display means 94 Communication means 95 Image output means 100, 400, 500 CMOS image sensor (solid-state imaging device)
110, 410, 510 Sensor array 120, 420, 520 AD conversion unit 130, 430, 530 Row selection unit 140, 440, 540 Column selection unit 150, 450, 550 Timing control unit 467 Pixel comparison processing unit 460 Pixel comparison unit 470 lines Memory 501 Imaging unit 502 Digital signal processing unit (DSP unit)

Claims (17)

A solid-state imaging device having a pixel array in which a plurality of pixels are arranged in a matrix,
A row selection unit for selecting pixel rows constituting the pixel array;
A column selection unit for selecting pixel columns constituting the pixel array;
A control unit for controlling the row selection unit and the column selection unit,
The control unit includes the row selection unit and the column selection unit so that pixel signals are read out at different timings for each pixel group from a plurality of pixel groups obtained by grouping a plurality of pixels constituting the pixel array. A solid-state imaging device to be controlled. The solid-state imaging device according to claim 1,
The plurality of pixel groups are first and second pixel groups obtained by dividing a plurality of pixels constituting the pixel array into two groups,
The control unit reads the pixel signals of the pixels of the first pixel group in odd frames and reads the pixel signals of the pixels of the second pixel group in even frames. A solid-state imaging device that controls a selection unit. The solid-state imaging device according to claim 2,
The first pixel group is a pixel group obtained by selecting four pixels in two adjacent rows and two columns as a unit pixel group, and selecting pixels in the pixel array every other unit pixel group in the row and column directions. And
The solid-state imaging device, wherein the second pixel group is a pixel group including unit pixel groups other than the unit pixel group included in the first pixel group in the pixel array. The solid-state imaging device according to claim 1,
The plurality of pixel groups are first to fourth pixel groups obtained by dividing a plurality of pixels constituting the pixel array into four groups,
The control unit reads the pixel signal of the pixel of the first pixel group in the (4n-3) th frame (n is an integer), and the second pixel group in the (4n-2) th frame. The pixel signal of the pixel is read, the pixel signal of the pixel of the third pixel group is read in the (4n-1) th frame, and the pixel of the pixel of the fourth pixel group is read in the (4n) frame. A solid-state imaging device that controls the row selection unit and the column selection unit so that signals are read out. The solid-state imaging device according to claim 4,
The first pixel group is a pixel group obtained by selecting unit pixels of odd rows and odd columns in the pixel array using four pixels of adjacent 2 rows and 2 columns in the pixel array as unit pixel groups. Yes,
The second pixel group is a pixel group obtained by selecting unit pixel groups of odd rows and even columns in the pixel array,
The third pixel group is a pixel group obtained by selecting unit pixel groups of even rows and even columns in the pixel array,
The solid-state imaging device, wherein the fourth pixel group is a pixel group obtained by selecting unit pixel groups in even rows and odd columns in the pixel array. The solid-state imaging device according to claim 1,
The control unit is a solid-state imaging device that controls the row selection unit and the column selection unit so that exposure times are different in different pixel groups of the plurality of pixel groups. The solid-state imaging device according to claim 6,
The pixel is
A photoelectric conversion unit that photoelectrically converts incident light to generate a signal charge;
A charge accumulator that accumulates signal charges generated by the photoelectric converter and generates a signal voltage corresponding to the amount of accumulated signal charges;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that amplifies a signal voltage generated in the charge storage section and reads out the pixel signal;
The controller is
The different pixel groups of the plurality of pixel groups have different reset timings for resetting signal charges accumulated in the charge accumulation units of the pixels constituting the pixel group, and pixel signals from the pixels constituting the pixel group. A solid-state imaging device that controls the row selection unit so that read-out timings are the same. The solid-state imaging device according to claim 7,
An AD converter that converts an analog pixel signal read out as the pixel signal into a digital pixel value;
A pixel comparison processing unit that compares digital pixel signals from unit pixel groups close to each other, which are unit pixel groups constituting different pixel groups of the plurality of pixel groups, between different pixel groups; Solid-state imaging device. The solid-state imaging device according to claim 8,
The pixel comparison processing unit is a solid-state imaging device that compares digital pixel values of pixels of the same color between the plurality of unit pixel groups close to each other. The solid-state imaging device according to claim 9,
The pixel comparison processing unit determines an optimum digital pixel value suitable for an incident light amount based on a comparison result of the digital pixel values, and sets a digital pixel value of a pixel group to which pixels having the optimum digital pixel value belong to each other. A solid-state imaging device that outputs as representative digital pixel values of adjacent unit pixel groups. The solid-state imaging device according to claim 9,
The pixel comparison processing unit is a unit pixel group that constitutes a different pixel group of the plurality of pixel groups based on the comparison result of the digital pixel value and the incident light amount, and from unit pixel groups close to each other. A solid-state imaging device that performs arithmetic processing on a digital pixel value and outputs a digital pixel value obtained by the arithmetic processing as a representative digital pixel value of the unit pixel group close to each other. A method of driving a solid-state imaging device having a pixel array in which a plurality of pixels are arranged in a matrix,
Driving pixels of a plurality of pixel groups obtained by grouping a plurality of pixels constituting the pixel array at independent timing for each pixel group;
A method for driving a solid-state imaging device, wherein pixel signals are read at different timings for each pixel group. The driving method of the solid-state imaging device according to claim 12,
A driving method of a solid-state imaging device, wherein the plurality of pixel groups are driven so that different pixel groups of the plurality of pixel groups have different exposure times. The solid-state imaging device driving method according to claim 13,
The pixel,
A photoelectric conversion unit that photoelectrically converts incident light to generate a signal charge;
A charge accumulator that accumulates signal charges generated by the photoelectric converter and generates a signal voltage corresponding to the amount of accumulated signal charges;
A reset transistor for resetting signal charges accumulated in the charge accumulation unit;
An amplification transistor that amplifies a signal voltage generated in the charge storage section and reads out the pixel signal;
The different pixel groups of the plurality of pixel groups have different reset timings for resetting signal charges accumulated in the charge accumulation units of the pixels constituting the pixel group, and pixel signals from the pixels constituting the pixel group. A method for driving a solid-state imaging device, wherein the plurality of pixel groups are driven so that read-out timings are the same. The driving method of the solid-state imaging device according to claim 14,
Converting an analog pixel signal read out as the pixel signal into a digital pixel value;
Digital pixel signals from unit pixel groups close to each other, which are unit pixel groups constituting different pixel groups of the plurality of pixel groups, are compared between different pixel groups,
Determine the optimal digital pixel value suitable for the incident light amount based on the comparison result of the digital pixel value,
A solid-state imaging device driving method, wherein a digital pixel value of a pixel group to which a pixel having the optimum digital pixel value belongs is output as a representative digital pixel value of the unit pixel group close to each other. The driving method of the solid-state imaging device according to claim 14,
Converting an analog pixel signal read out as the pixel signal into a digital pixel value;
Digital pixel signals from unit pixel groups close to each other, which are unit pixel groups constituting different pixel groups of the plurality of pixel groups, are compared between different pixel groups,
Based on the comparison result of the digital pixel values and the amount of incident light, arithmetic processing is performed on digital pixel values from unit pixel groups that are adjacent to each other, which are unit pixel groups that constitute different pixel groups of the plurality of pixel groups. Done
A method for driving a solid-state imaging device, wherein a digital pixel value obtained by this arithmetic processing is output as a representative digital pixel value of the unit pixel group close to each other. An electronic information device having an imaging unit for imaging a subject,
The electronic imaging device is the solid-state imaging device according to claim 1.

Images