JP2012222576A - Communication device, communication method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove interference more surely with a smaller scale circuit (processing) and to reduce processing volume and processing time.SOLUTION: A de-spreader 12 de-spreads an equalization result Z[i] with non-orthogonal sequences of a Primary-SCH and a Secondary-SCH, and calculates interference amplitude A. A flip-flop 13 buffers the interference amplitude A and supplies interference amplitude A' relative to an equalization result Z of a slot which is one slot ahead to a spreader 14. The spreader 14 spreads the interference amplitude A' with the Primary-SCH and the Secondary-SCH, and calculates an interference removal signal for each chip. A subtractor 15 subtracts the interference removal signal from the spreader 14 from the equalization result Z[i] from a chip equalizer 11. A Fast Hadamard Transform (FHT) unit 16 de-spreads a signal Z'[i] after interference removal with a code of an HS-PDSCH which has up to 15 codes.

Description

  The present invention relates to a communication device, a communication method, and a program.

  In HSPA + (High Speed Packet Access Plus) defined by 3GPP (3rd Generation Partnership Project), a CDMA (Code Division Multiple Access) system is used. In the CDMA system, a control channel (CH (Channel)) and a data channel are spread by a predetermined orthogonal sequence and communicated between a base station and a mobile terminal. However, among these channels (hereinafter also referred to as CHs), the Primary-SCH (Synchronization Channel) and Secondary-SCH for synchronizing the base station and the mobile terminal are particularly HS-PDSCH (High Speed-Phisical A non-orthogonal sequence that is not orthogonal to (Downlink Shared Channel) is used, and when HS-PDSCH is received, there is a problem that it appears as an interference component and lowers the throughput.

  FIG. 6 is a diagram illustrating a timing relationship between the SCH and the HS-PDSCH. Within 1 slot, the SCH is transmitted in the first 256 chips of P-CCPCH (Primary Common Control Physical Channel) and interferes with the HS-PDSCH, and the throughput in this section decreases.

  One method for solving this problem is disclosed in Patent Document 1.

  Patent Document 1 discloses that interference cancellation is realized by generating a signal spread by a non-orthogonal sequence on the mobile terminal side and subtracting it from the interfered signal.

  However, the invention described in Patent Document 1 does not consider the amplitude of a signal that is actually received and spread by a non-orthogonal sequence, and has a problem that the characteristics are poor.

  One method for solving this is disclosed in Patent Document 2.

  Patent Document 2 discloses that an amplitude of an interference signal is calculated by despreading a received signal using a non-orthogonal sequence, that is, a Primary-SCH and a Secondary-SCH, and interference is removed using this amplitude. .

  Incidentally, in recent years, especially in communication devices that realize high-speed communication such as HSPA +, a chip equalizer is used for receiving HS-PDSCH, apart from the RAKE combining method in the conventional CDMA method.

  RAKE combining is a method in which the results of despreading for each finger are integrated, that is, RAKE combining is performed, and then equalized by channel estimation values. Finger is one despreading timing of a signal to be received, and usually there are a plurality of fingers. This is the method described in Patent Document 2.

  On the other hand, in a chip equalizer, if it demonstrates simply, it will equalize with an equalization coefficient before de-spreading. At this time, the calculation method of the equalization coefficient is important, and generally MMSE (Most Mean Square Error) is used. When applying the interference cancellation described in Patent Document 2 to this chip equalizer, a circuit shown in FIG. 7 can be considered.

  The chip equalizer 201 equalizes the received signal on a chip basis with an equalization coefficient. The non-orthogonal sequence despreading unit 202 despreads the equalization result Z [i] (equalized signal Z [i]) with the non-orthogonal sequence to calculate the interference amplitude A. An FHT (Fast Hadamard Transform) unit 203 despreads the equalization result Z [i] with HS-PDSCH codes having a maximum of 15 codes. The subtractor 204 subtracts the interference amplitude A from the result R of HS-PDSCH despreading.

・・・（１） That is, first, chip equalization is performed in the chip equalizer 201 as shown in Expression (1) for the received signal.

... (1)

  The received signal Y [i] is a complex signal, and is a signal in which various CHs are multiplexed by the CDMA system in addition to the SCH and HS-PDSCH. The value range of Chip unit i is 0 to 255, and Chip unit i represents one Symbol section of SCH. Further, a Chip unit i which is 0 represents the first Chip of the Slot.

  The equalization coefficient W [t] is calculated by MMSE. The tap number F indicates the number of taps. The range of the variable t is −floor (F / 2) to floor (F / 2). Here, the floor function floor () is a function that assigns an integer to an arbitrary real number. The equalization signal Z [i] indicates the equalization result.

・・・（２） Subsequently, in the non-orthogonal sequence despreading unit 202, the equalization signal Z [i] is despread by the non-orthogonal sequence, and an interference signal is detected. Here, the despreading of the Primary-SCH is shown in Expression (2), and the despreading of the Secondary-SCH is shown in Expression (3).

... (2)

・・・（３）

... (3)

The Primary-SCH is spread in the non-orthogonal sequence psc [i]. Secondary-SCH is spread in the non-orthogonal sequence ssc [i]. The despread result R _psc is a despread result by the non-orthogonal sequence psc [i]. The despread result R _ssc is the despread result by the non-orthogonal sequence ssc [i].

・・・（４） Each non-orthogonal sequence is different for each slot. The despread results obtained in this way are integrated to obtain an interference amplitude A. Formula (4) shows the calculation formula of interference amplitude A.

... (4)

  The subtractor 204 subtracts the interference amplitude A from the despreading result R of HS-PDSCH obtained in the FHT unit 203. The FHT unit 203 is a circuit that performs despreading of HS-PDSCH for 15 codes, and as a result, a maximum of 15 types of R are output.

Japanese Patent Laid-Open No. 2001-156749 JP 2005-354255 A

  However, in the case of the configuration shown in FIG. 7, interference removal with the calculated amplitude is uniformly performed on the despreading result R of HS-PDSCH having a maximum of 15 codes, and the characteristics deteriorate.

  This is because each despread result R is spread with different orthogonal sequences, and the result of despreading the Primary-SCH and Secondary-SCH with the same orthogonal sequence produces a difference for each orthogonal sequence. This is because is not considered.

  For this reason, it is necessary to remove interference before the HS-PDSCH despreading result, that is, the chip equalization result.

  The circuit configuration in that case is shown in FIG.

  The chip equalizer 221 equalizes the received signal on a chip basis with an equalization coefficient. The buffer 222 buffers the equalization result Z [i] (equalization signal Z [i]). The non-orthogonal sequence despreading unit 223 calculates the interference amplitude A by despreading the equalization result Z [i] (equalized signal Z [i]) with the non-orthogonal sequence. The non-orthogonal sequence spreading unit 224 spreads the interference amplitude A in a non-orthogonal sequence to obtain an interference cancellation component in units of chips. The subtracter 225 subtracts the interference removal component in units of chips from the buffered equalization result Z [i] (equalization signal Z [i]).

  The FHT unit 226 despreads the equalization result Z [i] (equalization signal Z [i]) from which the interference removal component in units of chips is removed with the code of HS-PDSCH having a maximum of 15 codes, and performs the inverse of HS-PDSCH. Output the diffusion result R.

In the case shown in FIG. 8 as well, the calculation for calculating the despread result R _psc and the despread result R _ssc is the same as that shown in the equations (2) and (3).

・・・（５） However, the interference amplitude A is calculated as shown in Equation (5), unlike the calculation shown in Equation (4).

... (5)

  Here, the function Re () is a function that extracts a real number from complex numbers. The function Im () is a function that extracts an imaginary number from complex numbers. The function || is a function that takes an absolute value.

・・・（６） The accuracy is improved by averaging the real and imaginary numbers. The interference amplitude A calculated in this way is spread by the non-orthogonal sequence psc [i] and non-orthogonal sequence ssc [i] in the non-orthogonal sequence spreading unit 224 as shown in the equation (6). The interference is canceled by subtracting from the equalized signal Z [i].

... (6)

  Here, the interference amplitude A divided by 256 is a process of dividing the interference amplitude A into chip rates. The equalization signal Z ′ [i] is an equalization signal after SCH cancellation.

  In the configuration of FIG. 8, the buffer 222 for storing the equalized signal Z [i] when the interference amplitude A is calculated is required.

FIG. 9 is a timing chart for explaining a conventional 1-slot process. Numbers # 0 to # 9 arranged in the squares in FIG. 9 are CPICH (Common PIlot Channel) symbol numbers that are being processed. When not buffering, it is necessary to perform equalization again after calculating the despreading result R _psc and the despreading result R _ssc , which increases the processing amount. A timing chart in this case is shown in FIG.

  In the circuit shown in FIG. 8, while the amplitude is calculated by despreading using a non-orthogonal sequence, it is necessary to buffer the chip equalization result, which increases the circuit scale. Alternatively, when the buffering is not performed, it is necessary to perform the calculation of the amplitude as a preprocessing, and the processing time overhead increases. In order to remove interference in units of chips, it is necessary to make interference components in units of chips by spreading them in a non-orthogonal sequence with respect to the approximate amplitude.

  As described above, in the communication system using the CDMA system, the interference caused by the signal spread in the non-orthogonal sequence, particularly in the case of using a chip equalizer, in order to remove the interference, the chip in the non-orthogonal sequence It is necessary to subtract from the chip equalization result after deriving the equalization result to derive the amplitude of the interference component.

  For this reason, while despreading by a non-orthogonal sequence is performed, it is necessary to buffer the chip equalization result, which increases the circuit scale.

  Alternatively, when this buffering is not performed, it is necessary to perform the chip equalization process twice in order to remove interference, which increases the processing amount and the processing time overhead.

  Therefore, the present invention solves the above problems, that is, a communication device and a communication method capable of more reliably removing interference with a smaller circuit (processing), and reducing the processing amount and processing time, The purpose is to provide a program.

  In order to solve the above-described problem, one aspect of the communication apparatus of the present invention is a CDMA communication apparatus, which performs first spreading of chip equalization results using a non-orthogonal sequence for non-orthogonal sequence interference. It has diffusion means and removal means for removing interference from the chip equalization result using the amplitude of interference obtained as a result of past despreading.

  According to another aspect of the communication apparatus of the present invention, in addition to the above-described configuration, the chip equalization result is obtained by multiplying a predetermined equalization coefficient and the received signal and integrating a predetermined number of multiplication results. Equalizing means, buffering means for buffering the amplitude of interference obtained by the first despreading means, and spreading means for spreading the buffered interference amplitude in a non-orthogonal sequence are further removed. The means subtracts the interference cancellation component obtained by spreading the interference amplitude in a non-orthogonal sequence from the chip equalization result, thereby removing the interference from the chip equalization result and the chip from which the interference cancellation component has been subtracted. The second despreading means for despreading the conversion result is further provided.

  Further, one aspect of the communication method of the present invention is a CDMA communication method, in which a despreading step of despreading a chip equalization result with a non-orthogonal sequence for interference due to a non-orthogonal sequence; And a removal step of removing the interference from the chip equalization result using the interference amplitude obtained as a result.

  Further, according to one aspect of the program of the present invention, there is provided a despreading step for despreading a chip equalization result with a non-orthogonal sequence for interference caused by a non-orthogonal sequence to a computer of a CDMA communication apparatus; A process including a removal step of removing the interference from the chip equalization result using the amplitude of the obtained interference is performed.

  According to one aspect of the present invention, it is possible to provide a communication device, a communication method, and a program capable of more reliably removing interference with a smaller circuit (processing) and reducing the processing amount and processing time. Can do.

It is a block diagram which shows the example of a structure of the communication apparatus of one embodiment of this invention. It is a figure explaining interference amplitude A '. 6 is a flowchart for describing processing for obtaining a result R of despreading of HS-PDSCH. It is a block diagram which shows the other example of a structure of the communication apparatus of one embodiment of this invention. It is a block diagram which shows the structural example of the hardware of a computer. It is a figure which shows the interference period of a non-orthogonal sequence. It is a block diagram which shows the structure of the circuit of the conventional reception. It is a block diagram which shows the structure of the circuit of the conventional reception. 10 is a timing chart illustrating conventional 1 slot processing. 10 is a timing chart illustrating conventional 1 slot processing.

  Hereinafter, a communication apparatus according to an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing an example of the configuration of a communication apparatus according to an embodiment of the present invention. The communication apparatus includes a chip equalizer 11, a despreader 12, a flip-flop (Flip Flop) 13, a spreader 14, a subtractor 15, and an FHT unit 16.

  The chip equalizer 11 equalizes the received signal Y [i] on a chip basis with the equalization coefficient. The chip equalizer 11 supplies the equalization result Z [i] obtained as a result of the equalization to the despreader 12 and the subtractor 15.

  The despreader 12 despreads the equalization result Z [i] with a non-orthogonal sequence and calculates the interference amplitude A. For example, the despreader 12 despreads the equalization result Z [i] with a non-orthogonal sequence of Primary-SCH and Secondary-SCH, and calculates an interference amplitude A. The despreader 12 supplies the interference amplitude A to the flip-flop 13.

  The flip-flop 13 buffers the interference amplitude A. The flip-flop 13 supplies the buffered interference amplitude A ′ to the spreader 14. That is, the flip-flop 13 supplies the interference amplitude A ′ calculated in the past to the diffuser 14. For example, the flip-flop 13 supplies the spreader 14 with the interference amplitude A ′ for the equalization result Z of the previous slot.

  The spreader 14 spreads the buffered interference amplitude A ′ in a non-orthogonal sequence. For example, the spreader 14 spreads the interference amplitude A ′ between the Primary-SCH and the Secondary-SCH, and calculates an interference removal signal for each chip. The spreader 14 supplies an interference cancellation signal for each chip obtained as a result of spreading to the subtractor 15.

  The subtracter 15 subtracts the interference cancellation signal from the spreader 14 from the equalization result Z [i] from the chip equalizer 11. The subtractor 15 supplies the signal Z ′ [i] after interference removal obtained as a result of the subtraction to the FHT unit 16.

  The FHT unit 16 despreads the interference-removed signal Z ′ [i] with HS-PDSCH codes having a maximum of 15 codes, and outputs the result R of HS-PDSCH despreading.

  In short, the equalization result Z [i] is buffered in the communication apparatus having the configuration shown in FIG. 8, and the interference amplitude A is buffered in the communication apparatus having the configuration shown in FIG. The

・・・（７） Specifically, as shown in the equation (7), the interference amplitude A is buffered in the flip-flop 13 to be the interference amplitude A ′.

... (7)

・・・（８） As shown in FIG. 2, in the interference cancellation, the interference amplitude A ′ before the buffering shown in Expression (7), that is, the interference amplitude A ′ of the previous slot is used as shown in Expression (8).

... (8)

  Next, processing for obtaining the result R of HS-PDSCH despreading will be described with reference to the flowchart of FIG.

  In step S11, the chip equalizer 11 multiplies the equalization coefficient and the received signal Y [i], adds the multiplication results by a predetermined amount, and calculates the equalization result Z [i]. The equalization result Z [i] is input to the despreader 12 and the subtractor 15.

  In step S12, the despreader 12 despreads the equalization result Z [i] with the non-orthogonal sequence of the Primary-SCH and Secondary-SCH, and calculates the interference amplitude A. In step S13, the flip-flop 13 buffers the calculated interference amplitude A.

  Subsequently, in step S14, the spreader 14 inputs the past interference amplitude A ′ buffered in the flip-flop 13, spreads the interference amplitude A ′ in a non-orthogonal sequence, and calculates an interference removal component in units of chips. To do. This interference cancellation component is shown in the second term on the right side of Equation (8). The interference cancellation component in units of chips is input to the subtracter 15.

  In step S15, the subtracter 15 subtracts the interference cancellation component in units of chips obtained by spreading the interference amplitude A ′ with a non-orthogonal sequence from the equalization result Z [i].

  In step S16, the FHT unit 16 despreads the signal Z ′ [i] after the interference removal with a code of HS-PDSCH having a maximum of 15 codes, and outputs the result R of HS-PDSCH despreading, and the HS-PDSCH The process of obtaining the result R of the despreading is finished.

  In this way, buffering of the equalization result Z [i] becomes unnecessary.

  FIG. 4 is a block diagram illustrating another example of the configuration of the communication device according to the embodiment of this invention. 4 includes a chip equalizer 31, a despreader 32, flip-flops 33-1 to 33-4, a spreader 34, a subtractor 35, and an FHT unit 36.

  The chip equalizer 31 equalizes the received signal [i] on a chip basis with the equalization coefficient. The chip equalizer 31 supplies the equalization result Z [i] obtained as a result of the equalization to the despreader 32 and the subtractor 35.

  The despreader 32 despreads the equalization result Z [i] with a non-orthogonal sequence and calculates the interference amplitude A. For example, the despreader 32 despreads the equalization result Z [i] with a non-orthogonal sequence of Primary-SCH and Secondary-SCH, and calculates an interference amplitude A. The despreader 32 supplies the interference amplitude A to the flip-flop 33-1.

  The flip-flops 33-1 to 33-4 buffer the interference amplitude A as in the case of FIFO (First-In First-Out). The flip-flops 33-1 to 33-4 supply the buffered interference amplitude A ′ to the spreader 34. That is, the flip-flops 33-1 to 33-4 supply the spreader 34 with the interference amplitude A ′ calculated in the past.

  The spreader 34 spreads the buffered interference amplitude A ′ in a non-orthogonal sequence. For example, the spreader 34 spreads the interference amplitude A ′ between the Primary-SCH and the Secondary-SCH, and calculates an interference removal signal for each chip. The spreader 34 supplies an interference cancellation signal for each chip obtained as a result of spreading to the subtractor 35.

  The subtracter 35 subtracts the interference cancellation signal from the spreader 34 from the equalization result Z [i] from the chip equalizer 31. The subtractor 35 supplies the signal Z ′ [i] after interference removal obtained as a result of the subtraction to the FHT unit 36.

  The FHT unit 36 despreads the signal Z ′ [i] after interference removal with HS-PDSCH codes having a maximum of 15 codes, and outputs the result R of HS-PDSCH despreading.

  In short, in the communication apparatus having the configuration shown in FIG. 4, averaging is performed for the past several slots in the interference amplitude A ′ shown in FIG. 1, thereby improving accuracy.

・・・（９） In the equation (7), interference is removed using the interference amplitude A obtained in the previous slot, that is, the interference amplitude A ′, and the interference amplitude A obtained in the slot is stored as the interference amplitude A ′. In the communication apparatus indicated by (2), the interference amplitude A ′ is updated like a FIFO as shown in the equation (9).

... (9)

  The interference amplitude FIFO number n is a number corresponding to the number of past slots. The interference amplitude FIFO stage number N represents the number of FIFO stages.

・・・（１０） Using this interference amplitude A ′ [n], interference removal is performed as shown in Equation (10).

... (10)

  Here, the interference amplitude number m indicates the number of the interference amplitude to be averaged. The interference amplitude number M indicates the number of interference amplitudes to be averaged. For example, when the calculation of the interference amplitude A in the past slot is less than the interference amplitude FIFO stage number N, such as immediately after the channel is opened, the interference amplitude number M is set to the number of past slots that can be used for averaging.

  In the range in which interference removal is performed using the values calculated in the past slot, the calculated interference amplitude can be multiplied by an arbitrary adjustment coefficient. By appropriately selecting this coefficient, it can be used for MIMO (Multi Input Multi Output) separation.

  In addition, in the range where interference cancellation is performed using the values calculated in the past slot, there is no inconvenience even if part or all of the processing is programmed and executed by a DSP (Digital Signal Processor) or the like.

  As described above, the amplitude used for interference removal is derived in the past. This eliminates the need for buffering the chip equalization results while producing the current interference component amplitude. In other words, since the amplitude is obtained in the past, the interference can be removed immediately when the chip equalization result is obtained. Note that the amplitude of the current interference component is used for future interference removal.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  FIG. 5 is a block diagram illustrating an example of a hardware configuration of a computer that executes the above-described series of processes using a program.

  In a computer, a CPU (Central Processing Unit) 101, a ROM (Read Only Memory) 102, and a RAM (Random Access Memory) 103 are connected to each other via a bus 104.

  An input / output interface 105 is further connected to the bus 104. The input / output interface 105 includes an input unit 106 including a keyboard, a mouse, and a microphone, an output unit 107 including a display and a speaker, a storage unit 108 including a hard disk and nonvolatile memory, and a communication unit 109 including a network interface. A drive 110 for driving a removable medium 111 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is connected.

  In the computer configured as described above, the CPU 101 loads, for example, the program stored in the storage unit 108 to the RAM 103 via the input / output interface 105 and the bus 104 and executes the program. Is performed.

  The program executed by the computer (CPU 101) is, for example, a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc), etc.), a magneto-optical disk, or a semiconductor. The program is recorded on a removable medium 111 that is a package medium including a memory or the like, or is provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

  The program can be installed in the computer by loading the removable medium 111 in the drive 110 and storing it in the storage unit 108 via the input / output interface 105. Further, the program can be installed in a computer by being received by the communication unit 109 via a wired or wireless transmission medium and stored in the storage unit 108. In addition, the program can be installed in the computer in advance by storing the program in the ROM 102 or the storage unit 108 in advance.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 11 ... Chip equalizer, 12 ... Despreader, 13 ... Flip-flop, 14 ... Spreader, 15 ... Subtractor, 16 ... FHT part, 31 ... Chip equalizer, 32 ... Despreader, 33-1- 33-4 ... flip-flop, 34 ... diffuser, 35 ... subtractor, 36 ... FHT unit, 101 ... CPU, 102 ... ROM, 103 ... RAM, 108 ... storage unit, 109 ... communication unit, 111 ... removable media

Claims (4)

In a CDMA (Code Division Multiple Access) communication device,
A first despreading means for despreading the chip equalization result with the non-orthogonal sequence for interference due to the non-orthogonal sequence;
And a removing unit that removes interference from the chip equalization result using the amplitude of interference obtained as a result of past despreading. The communication device according to claim 1,
An equalizing means for multiplying a predetermined equalization coefficient and the received signal and obtaining the chip equalization result by integrating a predetermined number of multiplication results;
Buffering means for buffering the amplitude of the interference obtained by the first despreading means;
Spreading means for spreading the buffered interference amplitude in the non-orthogonal sequence;
The removing means removes interference from the chip equalization result by subtracting an interference removal component obtained by diffusing the amplitude of the interference with the non-orthogonal sequence from the chip equalization result,
The communication apparatus further comprising second despreading means for despreading the chip equalization result from which the interference cancellation component has been subtracted. In the CDMA communication method,
For interference due to non-orthogonal sequences, a despreading step for despreading the chip equalization results with the non-orthogonal sequences;
A removal step of removing interference from the chip equalization result using the amplitude of interference obtained as a result of past despreading. To the computer of the CDMA communication device,
For interference due to non-orthogonal sequences, a despreading step for despreading the chip equalization results with the non-orthogonal sequences;
A program for performing a process including a removal step of removing interference from the chip equalization result using the amplitude of interference obtained as a result of past despreading.

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