JP2012222331A - Semiconductor package - Google Patents

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JP2012222331A
JP2012222331A JP2011090258A JP2011090258A JP2012222331A JP 2012222331 A JP2012222331 A JP 2012222331A JP 2011090258 A JP2011090258 A JP 2011090258A JP 2011090258 A JP2011090258 A JP 2011090258A JP 2012222331 A JP2012222331 A JP 2012222331A
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ceramic substrate
heat spreader
multilayer ceramic
semiconductor package
semiconductor element
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JP5858637B2 (en
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Isao Kurata
功 倉田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package, which is an air-tight semiconductor package with a BGA mounting structure using a ceramic substrate, having improved heat dissipation characteristics of a semiconductor element.SOLUTION: A semiconductor package 100 comprises: a heat spreader 4 on which a semiconductor element 5 is directly mounted; a multi-layer ceramic substrate 1 that contacts the peripheral side surface of the heat spreader 4 and maintains airtightness of the semiconductor element 5; a metal block 15 that supports the heat spreader 4 from underneath, contacts the peripheral side surface of the multi-layer ceramic substrate 1, and has substantially the same linear expansion coefficient as the multi-layer ceramic substrate 1; and a plurality of solder balls 9 that are bonded to the under surfaces of the multi-layer ceramic substrate 1 and the metal block 15.

Description

本発明は、高出力半導体素子用パッケージ、特にＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）実装するセラミックパッケージに関する。   The present invention relates to a package for a high-power semiconductor device, and more particularly to a ceramic package for mounting on a BGA (Ball Grid Array).

近年の半導体素子の高集積化、高機能化に伴い半導体パッケージは接続端子数が増加する傾向にある。一方で、電子機器の小型化により１つの半導体パッケージの占有できる面積は減少の一途である。これら相反する２つの要求を満たす実装方法の一つとして、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）を用いた表面実装が用いられる。ＢＧＡは半導体パッケージと回路基板との接点にはんだボールを用いたものであり、接点の狭ピッチ化、多ピン化が容易であり、パッケージの小型化、接続距離の短縮による電気的特性の向上、接続距離のばらつき低減による電気的特性の向上という利点を持っている。   With the recent increase in integration and functionality of semiconductor devices, the number of connection terminals of semiconductor packages tends to increase. On the other hand, the area that can be occupied by one semiconductor package is steadily decreasing due to downsizing of electronic devices. As one of mounting methods that satisfy these two conflicting requirements, surface mounting using BGA (Ball Grid Array) is used. BGA uses solder balls for the contact between the semiconductor package and the circuit board, and it is easy to narrow the contact pitch and increase the number of pins. The package is downsized and the electrical characteristics are improved by shortening the connection distance. It has the advantage of improving electrical characteristics by reducing variation in connection distance.

通信信号の増幅に用いられるＦＥＴ（電界効果トランジスタ）、さらにはＦＥＴを含むＭＭＩＣ（モノリシックマイクロ波集積回路）には、ＧａＡｓ（ガリウムヒ素）やＧａＮ（ガリウムナイトライド）の化合物半導体が使用され、これら化合物半導体を実装する半導体パッケージには気密性が要求され、半導体素子搭載面には低い線膨張率が要求される。そのため通信分野の半導体パッケージは、ベース材料にＫＶ(コバール)、ＣｕＷ（銅タングステン）やＣｕＭｏ（銅モリブデン）のような低線膨張材料を用いて、金属リングをロウ付けしたメタルパッケージ、さらにはベース材料にＨＴＣＣやＬＴＣＣのような多層セラミック基板を用いて金属リングをロウ付けしたセラミックパッケージが使用されることが多い。   FETs (Field Effect Transistors) used to amplify communication signals, and MMICs (Monolithic Microwave Integrated Circuits) including FETs, use compound semiconductors such as GaAs (gallium arsenide) and GaN (gallium nitride). A semiconductor package on which a compound semiconductor is mounted requires airtightness, and a semiconductor element mounting surface requires a low coefficient of linear expansion. Therefore, the semiconductor package in the communication field is a metal package in which a metal ring is brazed using a low linear expansion material such as KV (Kovar), CuW (copper tungsten) or CuMo (copper molybdenum) as a base material, and further a base. A ceramic package in which a metal ring is brazed using a multilayer ceramic substrate such as HTCC or LTCC as a material is often used.

Ｎ2雰囲気化において、金属リング上に金属またはセラミックの蓋（リッド）をＡｕＳｎはんだ付けにより密着させる、或いは、金属の蓋（リッド）をシーム溶接により金属リングと溶接するなどの手法により気密性を確保し、パッケージ内部を水分や反応性ガスから保護することができる。ＢＧＡを用いる実装方式では、パッケージ下面にパッケージの端子が存在する必要があるため、多層セラミック基板をベース材に使用する。 In an N 2 atmosphere, the metal or ceramic lid (lid) is adhered to the metal ring by AuSn soldering, or the metal lid (lid) is welded to the metal ring by seam welding. It can be secured and the inside of the package can be protected from moisture and reactive gas. In the mounting method using BGA, since the package terminals need to be present on the lower surface of the package, a multilayer ceramic substrate is used as the base material.

また、半導体素子の高集積化、高出力化に伴い増幅素子等の高発熱素子は発熱量の増大、発熱密度の増大が顕著であり、温度上昇による半導体素子の破壊、素子出力の低下、寿命の低下を招く可能性があり、半導体パッケージの放熱特性の改善が要求されている。   In addition, with high integration and high output of semiconductor elements, high heat generation elements such as amplifier elements have a remarkable increase in heat generation and increase in heat generation density. There is a need to improve the heat dissipation characteristics of the semiconductor package.

従来、セラミックパッケージの熱抵抗を低減する方法として、多層セラミック基板を枠状にくり貫き、貫通部分に金属ブロックを配置してその上に半導体素子を搭載する構造が考えられている（例えば、特許文献１参照）。   Conventionally, as a method for reducing the thermal resistance of a ceramic package, a structure in which a multilayer ceramic substrate is cut into a frame shape, a metal block is disposed in a penetrating portion, and a semiconductor element is mounted thereon (for example, a patent) Reference 1).

特開２００４−２７３９２７号公報JP 2004-273927 A

しかしながら、上記従来の技術によれば、伝熱経路にセラミックが介在することは避けられないため、放熱特性には限界があり、増幅器等出力の大きい素子への適用は難しかった。また、セラミック基板と金属ブロックの間に隙間がありセラミックパッケージを気密に保持することも困難であった。   However, according to the above-described conventional technique, it is inevitable that ceramic is interposed in the heat transfer path, so that there is a limit to the heat dissipation characteristics, and it has been difficult to apply to an element having a large output such as an amplifier. Further, there is a gap between the ceramic substrate and the metal block, and it is difficult to keep the ceramic package airtight.

本発明は、上記に鑑みてなされたものであって、気密構造の半導体パッケージにおいて素子から電子機器の冷却装置取付け面までの熱抵抗を低減させることが可能となり、結果として半導体素子のジャンクション温度を下げ、半導体素子出力低下、半導体素子の寿命低下を防ぐことができる半導体パッケージを得ることを目的とする。   The present invention has been made in view of the above, and in a semiconductor package having an airtight structure, it is possible to reduce the thermal resistance from the element to the cooling device mounting surface of the electronic device. As a result, the junction temperature of the semiconductor element can be reduced. An object of the present invention is to obtain a semiconductor package that can reduce the output of the semiconductor element and the life of the semiconductor element.

上述した課題を解決し、目的を達成するために、本発明は、半導体素子を直接上に搭載するヒートスプレッダと、前記ヒートスプレッダの周囲側面と接触して前記半導体素子の気密性を保持する多層セラミック基板と、前記ヒートスプレッダを下から支え、前記多層セラミック基板の周囲側面と接触し前記多層セラミック基板とほぼ同等の線膨張係数を持つ金属ブロックと、前記多層セラミック基板および前記金属ブロックの下面に接合された複数のはんだボールとを備えたことを特徴とする。   In order to solve the above-mentioned problems and achieve the object, the present invention provides a heat spreader on which a semiconductor element is directly mounted, and a multilayer ceramic substrate that keeps the airtightness of the semiconductor element in contact with the peripheral side surface of the heat spreader. And a metal block that supports the heat spreader from below, contacts a peripheral side surface of the multilayer ceramic substrate and has a linear expansion coefficient substantially equal to the multilayer ceramic substrate, and is bonded to the lower surface of the multilayer ceramic substrate and the metal block. And a plurality of solder balls.

本発明によれば、セラミック基板を用いたＢＧＡ実装構造を有する気密半導体パッケージであって、半導体素子の放熱特性を向上させた半導体パッケージを得るという効果を奏する。   According to the present invention, there is an effect of obtaining an airtight semiconductor package having a BGA mounting structure using a ceramic substrate and having improved heat dissipation characteristics of a semiconductor element.

図１は、この発明の実施の形態１にかかる半導体パッケージを示す断面図である。1 is a cross-sectional view showing a semiconductor package according to Embodiment 1 of the present invention. 図２は、この発明の実施の形態２にかかる半導体パッケージを示す断面図である。FIG. 2 is a sectional view showing a semiconductor package according to the second embodiment of the present invention. 図３は、ヒートスプレッダを用いてＢＧＡ実装方式の半導体パッケージの熱抵抗を低減する従来の実装方法を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional mounting method for reducing the thermal resistance of a BGA mounting type semiconductor package using a heat spreader.

以下に、本発明にかかる半導体パッケージの実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。   Embodiments of a semiconductor package according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

実施の形態１．
図１は、実施の形態１にかかる半導体パッケージ１００を示す断面図である。本実施の形態にかかる半導体パッケージ１００は、多層セラミック基板１、ブロック１５、ヒートスプレッダ４、枠状のリング２、リッド（金属蓋／セラミック蓋）３、はんだボール９を備える。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a semiconductor package 100 according to the first embodiment. A semiconductor package 100 according to this embodiment includes a multilayer ceramic substrate 1, a block 15, a heat spreader 4, a frame-shaped ring 2, a lid (metal lid / ceramic lid) 3, and solder balls 9.

半導体パッケージ１００の気密性はヒートスプレッダ４の下部で保持されている。半導体素子５はヒートスプレッダ４の上に実装され、ヒートスプレッダ４とブロック１５、ブロック１５とはんだボール９（サーマルボール９ａ）はそれぞれ接続され、はんだボール９（サーマルボール９ａ）を介してプリント基板１０へ接続される。半導体素子５はボンディングワイヤ６により多層セラミック基板１に接続されている。   The airtightness of the semiconductor package 100 is maintained at the lower part of the heat spreader 4. The semiconductor element 5 is mounted on the heat spreader 4, the heat spreader 4 and the block 15, the block 15 and the solder ball 9 (thermal ball 9 a) are connected, and connected to the printed circuit board 10 via the solder ball 9 (thermal ball 9 a). Is done. The semiconductor element 5 is connected to the multilayer ceramic substrate 1 by a bonding wire 6.

ここで半導体パッケージ１００に使用される多層セラミック基板１は、アルミナセラミックスを主成分とするＨＴＣＣ(Ｈｉｇｈ Ｔｅｍｐｅｒａｔｕｒｅ Ｃｏ−ｆｉｒｅｄ Ｃｅｒａｍｉｃ)やガラスセラミックスを主成分とするＬＴＣＣ(Ｌｏｗ Ｔｅｍｐｅｒａｔｕｒｅ Ｃｏ−ｆｉｒｅｄ Ｃｅｒａｍｉｃ)のような立体配線ができる積層セラミック基板であり、半導体素子５の配置位置は枠状に繰りぬかれて貫通している。また、枠状に貫通している周囲にキャビティと呼ばれる凹状形状部を備えており、その凹状形状部底面には全面に基板導体７が配置されているものとする。   Here, the multilayer ceramic substrate 1 used for the semiconductor package 100 is an HTCC (High Temperature Co-fired Ceramic) mainly composed of alumina ceramics or an LTCC (Low Temperature Co-fired Ceramic) mainly composed of glass ceramics. This is a multilayer ceramic substrate capable of simple three-dimensional wiring, and the arrangement position of the semiconductor element 5 is passed through in a frame shape. Further, it is assumed that a concave shape portion called a cavity is provided around the periphery of the frame shape, and the substrate conductor 7 is disposed on the entire bottom surface of the concave shape portion.

ブロック１５は多層セラミック基板１と線膨張係数がほぼ同等で熱伝導率が高い銅タングステン合金やアルミダイヤモンドコンポジット材を使用する。ＢＧＡの接続部寿命は多層セラミック基板１とプリント基板１０との線膨張差が大きく関与することになるが、ブロック１５と多層セラミック基板１の線膨張率を合わせることで、ＢＧＡ接続部へ不均等に応力が発生することを抑えることができる。ブロック１５の大きさについては、多層セラミック基板１の枠状に貫通している部分に収まる寸法とする。   The block 15 uses a copper tungsten alloy or an aluminum diamond composite material having a linear expansion coefficient substantially equal to that of the multilayer ceramic substrate 1 and high thermal conductivity. The life of the connection part of the BGA is greatly related to the difference in linear expansion between the multilayer ceramic substrate 1 and the printed circuit board 10, but by combining the linear expansion coefficients of the block 15 and the multilayer ceramic substrate 1, the BGA connection part is uneven. It is possible to suppress the occurrence of stress on the surface. The size of the block 15 is set to a size that fits in a portion of the multilayer ceramic substrate 1 that penetrates in a frame shape.

ヒートスプレッダ４は半導体素子５の搭載に適するように、半導体素子５を構成する半導体材料と線膨張係数が近接しておりかつ熱伝導率の高い金属とする。多層セラミック基板１とヒートスプレッダ４の接合面にて、気密を確保するため、ヒートスプレッダ４の大きさについては多層セラミック基板１の凹状形状部と同等の寸法とする。   The heat spreader 4 is a metal having a high thermal conductivity and a linear expansion coefficient close to that of the semiconductor material constituting the semiconductor element 5 so as to be suitable for mounting the semiconductor element 5. The size of the heat spreader 4 is the same as the concave shape portion of the multilayer ceramic substrate 1 in order to ensure airtightness at the joint surface between the multilayer ceramic substrate 1 and the heat spreader 4.

多層セラミック基板１とヒートスプレッダ４の間やブロック１５とヒートスプレッダ４の間、リング２と多層セラミック基板１の間は接合材１６（高温はんだやろう材）にて接合される。接合材１６にて接合する際に半導体パッケージ１００のはんだボール９の搭載面を基準面として昇温して組立てることで、ブロック１５とヒートスプレッダ４の間はヒートスプレッダ／ブロック間接合部１６ａにより厚み方向の製造公差を吸収することができる。   The multilayer ceramic substrate 1 and the heat spreader 4, the block 15 and the heat spreader 4, and the ring 2 and the multilayer ceramic substrate 1 are joined by a joining material 16 (high-temperature solder or brazing material). When bonding is performed using the bonding material 16, the temperature is increased by assembling the mounting surface of the solder ball 9 of the semiconductor package 100 as a reference surface, so that the heat spreader / inter-block bonding portion 16 a is used in the thickness direction between the block 15 and the heat spreader 4. Manufacturing tolerances can be absorbed.

また、多層セラミック基板１とヒートスプレッダ４の間に、接合材１６からなるセラミック／ヒートスプレッダ間接合部１６ｂの層を設けることで半導体パッケージの気密を確保することが可能となる。接合材１６の供給は、印刷、塗布、ヒートスプレッダ４へのプリコートなど種類は問わない。しかし、段差があるため印刷は難しく、量産性を考えるとプリコートが望ましい。   Further, by providing a layer of the ceramic / heat spreader joint 16b made of the joining material 16 between the multilayer ceramic substrate 1 and the heat spreader 4, it becomes possible to ensure the airtightness of the semiconductor package. The bonding material 16 may be supplied by any type such as printing, coating, and pre-coating to the heat spreader 4. However, printing is difficult because of the difference in level, and pre-coating is desirable from the viewpoint of mass productivity.

はんだボール９の取り付けに関しては、上記で平面が保たれた（はんだボール９の）搭載面に対してフラックスを印刷後、はんだボール９を搭載し、再び昇温する。この２度目の昇温温度は１度目の昇温温度より低いため、接合材１６は溶けずにはんだボール９が溶ける。これにより、はんだボール９の搭載面のブロック１５および多層セラミック基板１の基板導体７にはんだボール９が接合される。特にブロック１５に接合されるはんだボール９は信号の接続には用いられず、専ら熱伝導に使用されるためサーマルボール９ａと呼ぶ。   Regarding the mounting of the solder balls 9, after printing the flux on the mounting surface (of the solder balls 9) on which the flat surface is maintained, the solder balls 9 are mounted and the temperature is raised again. Since the second temperature increase temperature is lower than the first temperature increase temperature, the bonding material 16 does not melt and the solder ball 9 melts. As a result, the solder ball 9 is joined to the block 15 on the mounting surface of the solder ball 9 and the substrate conductor 7 of the multilayer ceramic substrate 1. In particular, the solder ball 9 joined to the block 15 is not used for signal connection, but is used exclusively for heat conduction, and hence is called a thermal ball 9a.

その後、ヒートスプレッダ４の上に半導体素子５を接着／接合する。さらに、枠状のリング２に薄い金属でできたリッド（蓋）３をＡｕＳｎ封止やシーム溶接といった手段を用いて、真空下で封止もしくは窒素雰囲気で封止し気密パッケージとする。   Thereafter, the semiconductor element 5 is bonded / bonded onto the heat spreader 4. Further, a lid (cover) 3 made of a thin metal is sealed on the frame-like ring 2 under a vacuum or in a nitrogen atmosphere using means such as AuSn sealing or seam welding to form an airtight package.

プリント基板１０には、サーマルボール９ａが接続するパッドに基板表面上で放熱面積を拡大させるサーマルパッド１１を配置し、サーマルパッド１１にはプリント基板１０の厚み方向の熱伝導をよくするため、可能な限りのサーマルビア１２が配置される。そのプリント基板１０上にはんだを印刷により供給し上述した封止済の半導体パッケージ１００を搭載し再び温度を上げることで、半導体パッケージ１００がプリント基板１０の上に実装される。   The printed circuit board 10 is provided with a thermal pad 11 that expands the heat radiation area on the surface of the substrate on the pad connected to the thermal ball 9a, and the thermal pad 11 is capable of improving heat conduction in the thickness direction of the printed circuit board 10. All the thermal vias 12 are arranged. The semiconductor package 100 is mounted on the printed circuit board 10 by supplying solder on the printed circuit board 10 by mounting the above-described sealed semiconductor package 100 and raising the temperature again.

特許文献１に記載の発明の実施の形態１をＢＧＡ実装構造に適用すれば、図３に示したようになり、セラミック上に半導体素子５を搭載する場合に比べて、半導体素子５から冷却装置１３までの熱抵抗を削減することができる。しかし、伝熱経路にセラミックが介在することは避けられないため、放熱特性には限界があり、増幅器等出力の大きい素子への適用は難しい。   When the first embodiment of the invention described in Patent Document 1 is applied to a BGA mounting structure, it becomes as shown in FIG. 3, and the cooling device from the semiconductor element 5 is compared with the case where the semiconductor element 5 is mounted on the ceramic. Thermal resistance up to 13 can be reduced. However, since it is inevitable that ceramics are present in the heat transfer path, there is a limit to the heat dissipation characteristics, and it is difficult to apply to elements with high output such as amplifiers.

また、特許文献１に記載の発明の実施の形態２または実施の形態３によれば、セラミック基板と金属ブロックがともに金属製のキャリア上に配置されるため、ＢＧＡ実装をするセラミックパッケージに適用することができない。また、この方法ではセラミック基板と金属ブロックの間に隙間がありセラミックパッケージを気密に保持することも困難である。   Further, according to the second or third embodiment of the invention described in Patent Document 1, since both the ceramic substrate and the metal block are arranged on the metal carrier, the invention is applied to a ceramic package for BGA mounting. I can't. In this method, there is a gap between the ceramic substrate and the metal block, and it is difficult to keep the ceramic package airtight.

本実施の形態にかかる半導体パッケージ１００においては、半導体素子５が動作する際に発生した熱は半導体素子５の下のヒートスプレッダ４に伝熱し、そこで伝熱面積が拡大する。ヒートスプレッダ４の熱は一部多層セラミック基板１に伝わるが、大半はブロック１５を伝熱してはんだボール９（サーマルボール９ａ）からプリント基板１０へと伝熱される。即ち、熱伝導の悪い多層セラミック基板１を除いてプリント基板１０へ伝熱することが可能となる。プリント基板１０では、サーマルパッド１１やサーマルビア１２を介して冷却装置１３へ伝熱することにより、半導体パッケージ１００の半導体素子５から冷却装置１３までの熱抵抗を低減して放熱性を確保することが可能となる。   In the semiconductor package 100 according to the present embodiment, the heat generated when the semiconductor element 5 is operated is transferred to the heat spreader 4 under the semiconductor element 5, where the heat transfer area is expanded. Although the heat of the heat spreader 4 is partially transmitted to the multilayer ceramic substrate 1, most of the heat is transferred to the block 15 and transferred from the solder ball 9 (thermal ball 9 a) to the printed circuit board 10. That is, heat can be transferred to the printed circuit board 10 except for the multilayer ceramic substrate 1 having poor heat conduction. In the printed circuit board 10, heat transfer from the semiconductor element 5 of the semiconductor package 100 to the cooling device 13 is reduced by transferring heat to the cooling device 13 through the thermal pad 11 and the thermal via 12, thereby ensuring heat dissipation. Is possible.

実施の形態２．
図２は、実施の形態２にかかる高放熱な半導体パッケージ２００を示す断面図である。本実施の形態にかかる半導体パッケージ２００は、多層セラミック基板１、ブロック１５、ヒートスプレッダ４、枠状のリング２、リッド（金属蓋／セラミック蓋）３、はんだボール９を備える。 Embodiment 2. FIG.
FIG. 2 is a sectional view showing a semiconductor package 200 with high heat dissipation according to the second embodiment. A semiconductor package 200 according to the present embodiment includes a multilayer ceramic substrate 1, a block 15, a heat spreader 4, a frame-shaped ring 2, a lid (metal lid / ceramic lid) 3, and solder balls 9.

半導体パッケージ２００の気密性は半導体パッケージ２００下部のヒートスプレッダ４の上面で保持されている。半導体素子５は、ヒートスプレッダ４の上に実装されているブロック１５の上に実装される。ヒートスプレッダ４の下部には直接はんだボール９（サーマルボール９ａ）が接続され、はんだボール９（サーマルボール９ａ）を介してプリント基板１０へ接続される。半導体素子５はボンディングワイヤ６により多層セラミック基板１に接続されている。   The airtightness of the semiconductor package 200 is maintained on the upper surface of the heat spreader 4 below the semiconductor package 200. The semiconductor element 5 is mounted on the block 15 mounted on the heat spreader 4. A solder ball 9 (thermal ball 9a) is directly connected to the lower part of the heat spreader 4, and is connected to the printed circuit board 10 via the solder ball 9 (thermal ball 9a). The semiconductor element 5 is connected to the multilayer ceramic substrate 1 by a bonding wire 6.

先に説明した実施の形態１においては半導体素子５より大きい面積のヒートスプレッダ４と多層セラミック基板１の貫通部分より小さい面積のブロック１５の組み合わせにより熱抵抗をさげている。この場合、大きい面積のヒートスプレッダ４を採用するため、半導体素子５と多層セラミック基板１の接続距離が長くなり、場合によってはアルミナセラミックの中継基板を用いることが必要となる。そのため、電気的には好ましくない場合がある。また、小さい面積のブロック１５では、サーマルボール９ａの数が十分ではなく、熱抵抗の低減が限定的となってしまう。   In the first embodiment described above, the thermal resistance is reduced by the combination of the heat spreader 4 having an area larger than that of the semiconductor element 5 and the block 15 having an area smaller than the penetrating portion of the multilayer ceramic substrate 1. In this case, since the heat spreader 4 having a large area is employed, the connection distance between the semiconductor element 5 and the multilayer ceramic substrate 1 is increased, and in some cases, it is necessary to use an alumina ceramic relay substrate. Therefore, it may not be electrically preferable. Further, in the block 15 having a small area, the number of the thermal balls 9a is not sufficient, and the reduction of the thermal resistance is limited.

そこで、実施の形態２においては、半導体素子５をブロック１５に接合し、多層セラミック基板１の裏面にヒートスプレッダ４を配置した半導体パッケージ２００のようにすることで、上記した問題を克服することができる。ただし、サーマルボール９ａが増加する分相対的に半導体パッケージ２００の裏面のセラミック部分面積が減少するため、接続できる配線数は減少してしまう。   Therefore, in the second embodiment, the semiconductor element 5 is bonded to the block 15 and the heat spreader 4 is arranged on the back surface of the multilayer ceramic substrate 1 so that the above-described problem can be overcome. . However, since the ceramic portion area on the back surface of the semiconductor package 200 is relatively reduced as the thermal ball 9a is increased, the number of wires that can be connected is reduced.

ここで半導体パッケージ２００に使用される多層セラミック基板１は、実施の形態１で示したものと同様な材料を使用しているが、枠状に貫通している周囲にキャビティと呼ばれる凹状形状部を基板裏側に備えており、その凹状形状部底面には全面に基板導体７が配置されているものとする。   Here, the multilayer ceramic substrate 1 used for the semiconductor package 200 uses the same material as that shown in the first embodiment. However, a concave shape portion called a cavity is formed around the frame. It is provided on the back side of the substrate, and the substrate conductor 7 is disposed on the entire bottom surface of the concave shape portion.

ブロック１５およびヒートスプレッダ４については、実施の形態１で説明した材料および適合をとる対象の組合せが逆となり、ブロック１５は半導体素子５の搭載に適するように、半導体素子５を構成すると線膨張係数が近接しており、かつ熱伝導率の高い金属とする。大きさについては、多層セラミック基板１の枠状に貫通している部分と同等の寸法とする。   For the block 15 and the heat spreader 4, the combination of the material and the target to be matched described in the first embodiment is reversed, and the block 15 has a linear expansion coefficient when the semiconductor element 5 is configured to be suitable for mounting the semiconductor element 5. The metal should be close and have high thermal conductivity. About a magnitude | size, it is set as the dimension equivalent to the part penetrated in the frame shape of the multilayer ceramic substrate 1. FIG.

ヒートスプレッダ４は多層セラミック基板１と線膨張係数がほぼ同等で熱伝導率が高い銅タングステン合金やアルミダイヤモンドコンポジット材を使用し、ＢＧＡの接続部寿命を考慮するとともに、ヒートスプレッダ４と多層セラミック基板１の線膨張率を合わせることでパッケージの気密保持部分についての信頼性も確保するものとする。大きさは上記したブロック１５より一回り大きく、多層セラミック基板１の凹状形状部と同等の寸法とし、気密保持部分を設けるとともに、接続配線数を確保できる大きさに留める必要がある。   The heat spreader 4 uses a copper-tungsten alloy or an aluminum diamond composite material having a linear expansion coefficient substantially equal to that of the multilayer ceramic substrate 1 and high thermal conductivity, and considers the connection part life of the BGA, and the heat spreader 4 and the multilayer ceramic substrate 1. By matching the linear expansion coefficient, the reliability of the hermetic holding portion of the package is also ensured. The size is slightly larger than the above-described block 15 and should be the same size as the concave shape portion of the multilayer ceramic substrate 1, provided with an airtight holding portion, and kept at a size that can secure the number of connection wires.

多層セラミック基板１とヒートスプレッダ４の間やブロック１５とヒートスプレッダ４の間、リング２と多層セラミック基板１の間は接合材１６（高温はんだやろう材）にて接合される。ヒートスプレッダ４にはあらかじめ接合材１６をプリコートしておき、セラミック基板１とブロック１５を乗せる。半導体パッケージ２００のはんだボール９の搭載面を基準面として昇温して組立てることで、ブロック１５とヒートスプレッダ４の間はヒートスプレッダ／ブロック間接合部１６ａにより厚み方向の製造公差を吸収することができる。   The multilayer ceramic substrate 1 and the heat spreader 4, the block 15 and the heat spreader 4, and the ring 2 and the multilayer ceramic substrate 1 are joined by a joining material 16 (high-temperature solder or brazing material). The heat spreader 4 is pre-coated with a bonding material 16 in advance, and the ceramic substrate 1 and the block 15 are placed thereon. By assembling with the mounting surface of the solder ball 9 of the semiconductor package 200 as the reference surface and assembling, the manufacturing tolerance in the thickness direction can be absorbed between the block 15 and the heat spreader 4 by the heat spreader / inter-block joint 16a.

また、多層セラミック基板１とヒートスプレッダ４の間に、接合材１６からなるセラミック／ヒートスプレッダ間接合部１６ｂの層を設けることで半導体パッケージ２００の気密を確保することが可能となる。接合材１６の供給は、印刷、塗布、ヒートスプレッダ４へのプリコートなど種類は問わない。しかし、段差があるため印刷は難しく、量産性を考えるとプリコートが望ましい。   Further, by providing a layer of the ceramic / heat spreader joint portion 16b made of the joining material 16 between the multilayer ceramic substrate 1 and the heat spreader 4, it is possible to ensure the airtightness of the semiconductor package 200. The bonding material 16 may be supplied by any type such as printing, coating, and pre-coating to the heat spreader 4. However, printing is difficult because of the difference in level, and pre-coating is desirable from the viewpoint of mass productivity.

はんだボール９の取り付けに関しては、上記で平面が保たれた（はんだボール９の）搭載面に対してフラックスを印刷後、はんだボール９を搭載し、再び昇温する。この２度目の昇温温度は１度目の昇温温度より低いため、接合材１６は溶けずにはんだボール９が溶ける。これにより、はんだボール９の搭載面のヒートスプレッダ４および多層セラミック基板１の基板導体７にはんだボール９が接合される。特にヒートスプレッダ４に接合されるはんだボール９は信号の接続には用いられず、専ら熱伝導に使用されるためサーマルボール９ａと呼ぶ。その後のプリント基板１０への実装工程などは実施の形態１で説明したのと同様である。   Regarding the mounting of the solder balls 9, after printing the flux on the mounting surface (of the solder balls 9) on which the flat surface is maintained, the solder balls 9 are mounted and the temperature is raised again. Since the second temperature increase temperature is lower than the first temperature increase temperature, the bonding material 16 does not melt and the solder ball 9 melts. As a result, the solder balls 9 are joined to the heat spreader 4 on the mounting surface of the solder balls 9 and the substrate conductor 7 of the multilayer ceramic substrate 1. In particular, the solder ball 9 joined to the heat spreader 4 is not used for signal connection, but is used exclusively for heat conduction, and hence is called a thermal ball 9a. The subsequent mounting process on the printed circuit board 10 is the same as that described in the first embodiment.

本実施の形態にかかる半導体パッケージ２００においては、半導体素子５が動作する際に発生した熱は半導体素子５の下のブロック１５を介して、ヒートスプレッダ４に伝熱する。ヒートスプレッダ４で伝熱面積が拡大され、実施の形態１より数の多いはんだボール９（サーマルボール９ａ）からプリント基板１０へと伝熱される。即ち、熱伝導の悪い多層セラミック基板１を除いてより放熱性を高めてプリント基板１０へ伝熱することが可能となる。プリント基板１０では、サーマルパッド１１やサーマルビア１２により冷却装置１３へ伝熱することにより、半導体パッケージ２００の半導体素子５から冷却装置１３までの熱抵抗を低減して放熱性を確保することが可能となる。   In the semiconductor package 200 according to the present embodiment, heat generated when the semiconductor element 5 operates is transferred to the heat spreader 4 through the block 15 below the semiconductor element 5. The heat spreader 4 expands the heat transfer area, and heat is transferred from the solder balls 9 (thermal balls 9a), which are more numerous than in the first embodiment, to the printed circuit board 10. That is, it is possible to transfer heat to the printed circuit board 10 with higher heat dissipation except for the multilayer ceramic substrate 1 having poor heat conduction. In the printed circuit board 10, heat transfer from the semiconductor element 5 to the cooling device 13 of the semiconductor package 200 can be reduced by transferring heat to the cooling device 13 through the thermal pad 11 and the thermal via 12, thereby ensuring heat dissipation. It becomes.

更に、本願発明は上記実施の形態に限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で種々に変形することが可能である。また、上記実施の形態には種々の段階の発明が含まれており、開示される複数の構成要件における適宜な組み合わせにより種々の発明が抽出されうる。   Furthermore, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent requirements.

例えば、上記実施の形態１または２それぞれに示される全構成要件からいくつかの構成要件が削除されても、発明が解決しようとする課題の欄で述べた課題が解決でき、発明の効果の欄で述べられている効果が得られる場合には、この構成要件が削除された構成が発明として抽出されうる。更に、上記実施の形態１または２にわたる構成要件を適宜組み合わせてもよい。   For example, even if some constituent elements are deleted from all the constituent elements shown in the first or second embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the column of the effect of the invention. When the effects described in (1) are obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention. Furthermore, the structural requirements over the first or second embodiment may be combined as appropriate.

以上のように、本発明にかかる半導体パッケージは、気密構造を有する半導体パッケージのＢＧＡ実装に有用であり、特に、半導体素子からの放熱性を確保できる半導体パッケージに適している。   As described above, the semiconductor package according to the present invention is useful for BGA mounting of a semiconductor package having an airtight structure, and is particularly suitable for a semiconductor package that can ensure heat dissipation from a semiconductor element.

１ 多層セラミック基板
２ リング
３ リッド（金属蓋／セラミック蓋）
４ ヒートスプレッダ
５ 半導体素子
６ ボンディングワイヤ
７ 基板導体
８ サーマルビア
９ はんだボール
９a サーマルボール
１０ プリント基板
１１ サーマルパッド
１２ サーマルビア
１３ 冷却装置
１５ ブロック
１６ 接合材
１６ａ ヒートスプレッダ／ブロック間接合部
１６ｂ セラミック／ヒートスプレッダ間接合部
１００、２００ 半導体パッケージ 1 multilayer ceramic substrate 2 ring 3 lid (metal lid / ceramic lid)
DESCRIPTION OF SYMBOLS 4 Heat spreader 5 Semiconductor element 6 Bonding wire 7 Board | substrate conductor 8 Thermal via 9 Solder ball 9a Thermal ball 10 Printed board 11 Thermal pad 12 Thermal via 13 Cooling device 15 Block 16 Joining material 16a Heat spreader / block junction 16b Ceramic / heat spreader junction Part 100, 200 Semiconductor package

Claims (6)

半導体素子を直接上に搭載するヒートスプレッダと、
前記ヒートスプレッダの周囲側面と接触して前記半導体素子の気密性を保持する多層セラミック基板と、
前記ヒートスプレッダを下から支え、前記多層セラミック基板の周囲側面と接触し前記多層セラミック基板とほぼ同等の線膨張係数を持つ金属ブロックと、
前記多層セラミック基板および前記金属ブロックの下面に接合された複数のはんだボールと、
を備えたことを特徴とする半導体パッケージ。 A heat spreader that directly mounts a semiconductor element;
A multilayer ceramic substrate that is in contact with a peripheral side surface of the heat spreader and maintains the airtightness of the semiconductor element;
A metal block that supports the heat spreader from below, contacts a peripheral side surface of the multilayer ceramic substrate, and has a linear expansion coefficient substantially equal to the multilayer ceramic substrate;
A plurality of solder balls joined to the lower surface of the multilayer ceramic substrate and the metal block;
A semiconductor package comprising: 前記ヒートスプレッダの線膨張係数は、前記半導体素子を構成する半導体材料の線膨張係数とほぼ同等である
ことを特徴とする請求項１に記載の半導体パッケージ。 The semiconductor package according to claim 1, wherein a linear expansion coefficient of the heat spreader is substantially equal to a linear expansion coefficient of a semiconductor material constituting the semiconductor element. 前記金属ブロックは、銅タングステン合金またはアルミダイヤモンドコンポジット材である
ことを特徴とする請求項１または２に記載の半導体パッケージ。 The semiconductor package according to claim 1, wherein the metal block is a copper tungsten alloy or an aluminum diamond composite material. 半導体素子を直接上に搭載する金属ブロックと、
前記金属ブロックの周囲側面を囲む多層セラミック基板と、
前記金属ブロックを下から支え、前記多層セラミック基板の周囲側面と接触して前記半導体素子の気密性を保持し、前記多層セラミック基板とほぼ同等の線膨張係数を持つヒートスプレッダと、
前記多層セラミック基板および前記ヒートスプレッダの下面に接合された複数のはんだボールと、
を備えたことを特徴とする半導体パッケージ。 A metal block on which a semiconductor element is directly mounted;
A multilayer ceramic substrate surrounding a peripheral side surface of the metal block;
A heat spreader that supports the metal block from below, maintains the airtightness of the semiconductor element in contact with the peripheral side surface of the multilayer ceramic substrate, and has a linear expansion coefficient substantially equal to the multilayer ceramic substrate;
A plurality of solder balls bonded to the lower surface of the multilayer ceramic substrate and the heat spreader;
A semiconductor package comprising: 前記金属ブロックの線膨張係数は、前記半導体素子を構成する半導体材料の線膨張係数とほぼ同等である
ことを特徴とする請求項４に記載の半導体パッケージ。 The semiconductor package according to claim 4, wherein a linear expansion coefficient of the metal block is substantially equal to a linear expansion coefficient of a semiconductor material constituting the semiconductor element. 前記ヒートスプレッダは、銅タングステン合金またはアルミダイヤモンドコンポジット材である
ことを特徴とする請求項４または５に記載の半導体パッケージ。 The semiconductor package according to claim 4, wherein the heat spreader is a copper tungsten alloy or an aluminum diamond composite material.
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