JP2012222124A - Capacitor with insulating coating and manufacturing method therefor - Google Patents

Capacitor with insulating coating and manufacturing method therefor Download PDF

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JP2012222124A
JP2012222124A JP2011085911A JP2011085911A JP2012222124A JP 2012222124 A JP2012222124 A JP 2012222124A JP 2011085911 A JP2011085911 A JP 2011085911A JP 2011085911 A JP2011085911 A JP 2011085911A JP 2012222124 A JP2012222124 A JP 2012222124A
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capacitor
insulating coating
manufacturing
chip
insulating film
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Yasushi Kojima
靖 小島
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Maruwa Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a capacitor with an insulating coating in which short circuit between terminal electrodes is prevented even if a chip type multilayer ceramic capacitor is mounted on a metal pedestal, and connection by wire bonding is possible.SOLUTION: The capacitor with an insulating coating is manufactured by a step for manufacturing a chip type laminate, a step for applying an underlying electrode to the chip type laminate, a step for plating on a terminal electrode, and a step for applying an insulating coating on one surface simultaneously having a plurality of terminal electrodes not connected electrically. The part where the insulating coating is applied is a part, on one surface simultaneously having the plurality of terminal electrodes not connected electrically, including at least the terminal electrode on one surface.

Description

本発明は、部分的に絶縁被膜コーティングを施したチップ型積層セラミックコンデンサ及びその製造方法に関する。 The present invention relates to a chip-type multilayer ceramic capacitor partially coated with an insulating coating and a method for manufacturing the same.

焦電型赤外線センサーのパッケージ内などの導電性の台座の上に実装されるコンデンサは、そのまま導電性の台座に実装すると、その両端の端子電極が電気的に短絡してしまうので、例えば特開2004−279118号公報に示されているような複雑に配線された内部配線基板上に実装して、端子電極が短絡することを防止していると同時に、電気結線されているが、複雑な内部配線基板を設置する必要があるため、コスト的な問題があった。 When a capacitor mounted on a conductive base such as in a pyroelectric infrared sensor package is mounted on the conductive base as it is, the terminal electrodes at both ends thereof are electrically short-circuited. It is mounted on a complicatedly wired internal wiring board as shown in Japanese Patent Application Publication No. 2004-279118, and the terminal electrode is prevented from being short-circuited, and at the same time, it is electrically connected. There is a problem of cost because it is necessary to install a wiring board.

また、前記問題を解決するために、特開2010−169520号公報においては、内部配線基板を廃止し、ヘッダー上に直接コンデンサをエポキシ樹脂等の接着剤で固定し、各部品間の電気的結線をワイヤーボンディングで行っている。 Further, in order to solve the above problem, in Japanese Patent Application Laid-Open No. 2010-169520, the internal wiring board is abolished, and a capacitor is directly fixed on the header with an adhesive such as an epoxy resin, so that electrical connection between each component is achieved. Is done by wire bonding.

特開2004−279118号公報JP 2004-279118 A 特開2010−169520号公報JP 2010-169520 A

しかし、前記特許文献2では、金属台座の上に接着剤を用いて直接コンデンサを実装しているので、接着工程においてコンデンサを金属台座に押しつけたときに端子電極間で短絡してしまう場合があるという問題があった。 However, in Patent Document 2, since the capacitor is directly mounted on the metal pedestal using an adhesive, a short circuit may occur between the terminal electrodes when the capacitor is pressed against the metal pedestal in the bonding process. There was a problem.

この問題を解決するために、コンデンサを実装する部分の金属台座上に絶縁被膜を形成する手法も考えられるが、金属端子等の突起物の隙間というごく狭いスペースに限定して絶縁被膜を形成するのは非常に困難である。 In order to solve this problem, a method of forming an insulating film on the metal pedestal where the capacitor is mounted may be considered, but the insulating film is formed only in a very narrow space such as a gap between protrusions such as metal terminals. It is very difficult.

したがって、本発明は上記事情を鑑みて、金属台座上に直接チップ型積層セラミックコンデンサを実装しても、端子電極間で短絡してしまうことがなく、かつワイヤーボンディングによる結線が可能な絶縁被膜付きコンデンサ及びその製造方法を提供することを目的とする。 Therefore, in view of the above circumstances, the present invention has an insulating coating that does not short-circuit between terminal electrodes even when a chip-type multilayer ceramic capacitor is mounted directly on a metal pedestal and can be connected by wire bonding It is an object of the present invention to provide a capacitor and a manufacturing method thereof.

そして、本発明は、上記した課題を解決するために、2以上の端子電極を有するチップ型積層セラミックコンデンサにおいて、電気的に接続していない複数の端子電極を同時に有する一の面上の、少なくとも前記端子電極を含む部位に絶縁被膜を施した絶縁被膜付きコンデンサを採用する。 In order to solve the above-described problem, the present invention provides a chip-type multilayer ceramic capacitor having two or more terminal electrodes, at least on one surface having a plurality of terminal electrodes that are not electrically connected at the same time. A capacitor with an insulating coating in which an insulating coating is applied to a portion including the terminal electrode is employed.

このような絶縁被膜付きコンデンサの製造方法にして、従来から周知の方法でチップ型積層体を製造する第一の工程と、前記チップ型積層体に下地電極を施す第二の工程と、前記下地電極上にめっきを施す第三の工程と、電気的に接続していない複数の前記下地電極を同時に有する一の面上に絶縁被膜を施す第四の工程とからなる前記絶縁被膜付きコンデンサの製造方法。 In such a method of manufacturing a capacitor with an insulating film, a first step of manufacturing a chip-type laminate by a conventionally known method, a second step of applying a base electrode to the chip-type laminate, and the base Manufacture of a capacitor with an insulating coating comprising a third step of plating on an electrode and a fourth step of applying an insulating coating on one surface having a plurality of base electrodes that are not electrically connected simultaneously Method.

従来から周知の方法でチップ型積層体を製造する第一の工程と、前記チップ型積層体に下地電極を施す第二の工程と、電気的に接続していない複数の前記下地電極を同時に有する一の面上に絶縁被膜を施す第三の工程と、前記下地電極上にめっきを施す第四の工程とからなる前記絶縁被膜付きコンデンサの製造方法。 A first step of manufacturing a chip-type laminate by a conventionally known method, a second step of applying a base electrode to the chip-type laminate, and a plurality of base electrodes that are not electrically connected are simultaneously provided. The manufacturing method of the said capacitor | condenser with an insulating film which consists of a 3rd process of applying an insulating film on one surface, and a 4th process of plating on the said base electrode.

このような本発明による絶縁被膜付きコンデンサを用いれば、端子電極同士が導通することなく金属面上に実装することができる。 If the capacitor | condenser with an insulating film by this invention is used, it can mount on a metal surface, without terminal electrodes electrically connecting.

一般的なチップ型積層セラミックコンデンサの斜視図Perspective view of a general chip type multilayer ceramic capacitor 本発明による絶縁被膜付きコンデンサの斜視図The perspective view of the capacitor | condenser with an insulation film by this invention 図2の絶縁被膜付きコンデンサのA−A断面図AA cross-sectional view of the capacitor with an insulating film in FIG. 金属台座に絶縁被膜付きコンデンサを実装した外観斜視図External perspective view of a capacitor with an insulating film mounted on a metal base 金属台座に絶縁被膜付きコンデンサを実装したときの断面図Sectional view when a capacitor with an insulation coating is mounted on a metal base 絶縁被膜付きコンデンサの第二の形態の断面図Sectional view of the second form of capacitor with insulation coating

本発明を具体的に明らかにするために、本発明の実施の形態について図面を参照しつつ詳細に説明する。 In order to clarify the present invention, embodiments of the present invention will be described in detail with reference to the drawings.

まず、図1は、従来から周知である、対向する2面に端子電極1を有するチップ型積層セラミックコンデンサ2である。図2は、本発明による絶縁被膜付きコンデンサ3の外観を示したもので、また、図3はそのA−A断面図を示している。このように、チップ型積層セラミックコンデンサ2の6面のうち、2つの端子電極1を同時に有する面上において、少なくともこの面上の端子電極を含む部位に絶縁被膜4が施してある。すなわち、平面上にチップ型積層セラミックコンデンサ2を載置したときに、少なくともこの平面と接している端子電極部位に絶縁被膜4を施すのである。なお、絶縁被膜4は、図2及び図3に示すように、前記端子電極部位だけでなく、2つの端子電極1を同時に有する面上、さらには外周面にまで回り込んで被覆することによって、端子電極間の絶縁はより確実なものとなる。 First, FIG. 1 shows a chip-type multilayer ceramic capacitor 2 having terminal electrodes 1 on two opposing surfaces, which is well known. FIG. 2 shows the external appearance of the capacitor 3 with an insulating coating according to the present invention, and FIG. As described above, the insulating coating 4 is applied to at least a portion including the terminal electrode on the surface of the chip-type multilayer ceramic capacitor 2 on the surface having the two terminal electrodes 1 at the same time. That is, when the chip-type multilayer ceramic capacitor 2 is placed on a plane, the insulating coating 4 is applied to at least the terminal electrode portion in contact with the plane. In addition, as shown in FIG.2 and FIG.3, the insulating coating 4 covers not only the said terminal electrode part but the surface which has the two terminal electrodes 1 simultaneously, Furthermore, it wraps around and coat | covers to an outer peripheral surface, The insulation between the terminal electrodes is more reliable.

図3に示すように、このチップ型積層セラミックコンデンサ2の端子電極1は、第一の層であるCu、Ag、Niなどからなる下地電極5と、第二の層であるNiめっき6と、第三の層であるAuめっき7とから構成されている。また、絶縁被膜4はエポキシ系、フェノール系、アクリル系などの絶縁素材からなる。 As shown in FIG. 3, the terminal electrode 1 of the chip type multilayer ceramic capacitor 2 includes a base electrode 5 made of Cu, Ag, Ni or the like as a first layer, a Ni plating 6 as a second layer, It is comprised from Au plating 7 which is the third layer. The insulating coating 4 is made of an insulating material such as epoxy, phenol, or acrylic.

本発明による絶縁被膜付きコンデンサ3は、図4及び図5に示されるように、一般的な焦電型赤外線センサーのパッケージの金属台座8上に、例えばエポキシ系ような絶縁性の接着剤9によって固定される。そして、回路を形成するために、ワイヤー10を用いて金属端子電極11の上端部にワイヤーボンディング接続される。なお、金属端子電極11は絶縁支持部12によって金属台座8とは絶縁されている。 As shown in FIGS. 4 and 5, the capacitor 3 with an insulating film according to the present invention is formed on a metal base 8 of a general pyroelectric infrared sensor package by an insulating adhesive 9 such as an epoxy system. Fixed. And in order to form a circuit, it connects to the upper end part of the metal terminal electrode 11 using the wire 10 by wire bonding. The metal terminal electrode 11 is insulated from the metal pedestal 8 by the insulating support portion 12.

(実施例1)本発明による絶縁被膜付きコンデンサ3の製造方法として、従来から周知のチップ型積層体を製造する第一の工程と、前記チップ型積層体の内部電極が露出されている2面に下地電極5を施す第二の工程と、前記下地電極5にNiめっき6及びAuめっき7を施してチップ型積層セラミックコンデンサ2を完成させる第三の工程と、チップ型積層セラミックコンデンサ2の対向する2面の端子電極1を同時に有する一の面上に絶縁被膜を施す第四の工程とからなる絶縁被膜付きコンデンサ3の製造方法がある。 (Example 1) As a method of manufacturing a capacitor 3 with an insulating film according to the present invention, a first step of manufacturing a conventionally known chip type laminate, and two surfaces on which internal electrodes of the chip type laminate are exposed A second step of applying the base electrode 5 to the substrate, a third step of applying the Ni plating 6 and the Au plating 7 to the base electrode 5 to complete the chip type multilayer ceramic capacitor 2, and the opposing of the chip type multilayer ceramic capacitor 2 There is a method of manufacturing a capacitor 3 with an insulating coating comprising a fourth step of applying an insulating coating on one surface having the two terminal electrodes 1 simultaneously.

前記第一の工程から第三の工程までは、従来から周知の製造方法である。第四の工程であるチップ型積層セラミックコンデンサ2の、前記一の面上、すなわち金属台座への実装面13に絶縁被膜4を施す手法としては、インクジェット、スクリーン印刷、転写などがある。 The first process to the third process are conventionally known manufacturing methods. As a method of applying the insulating coating 4 to the one surface of the chip-type multilayer ceramic capacitor 2 as the fourth step, that is, the mounting surface 13 on the metal pedestal, there are inkjet, screen printing, transfer and the like.

この絶縁被膜付きコンデンサ3は、接着剤9を用いて金属台座8に固定するので、この接着工程において、絶縁被膜付きコンデンサ3を金属台座8に押しつける必要があるため、絶縁被膜付きコンデンサ3と金属台座8が接触してしまう場合がある。このとき、絶縁被膜4が施されていないコンデンサを使用している場合、端子電極がショートする不良を発生してしまう。しかし、図5に示すように、実装面13には絶縁被膜4が施されているので絶縁被膜付きコンデンサ3は、実装面と接触しても対向する2面の端子電極がショートしてしまうことはない。 Since the capacitor 3 with the insulating film is fixed to the metal base 8 using the adhesive 9, it is necessary to press the capacitor 3 with the insulating film against the metal base 8 in this bonding process. The base 8 may come into contact. At this time, when a capacitor not provided with the insulating coating 4 is used, a defect that the terminal electrode is short-circuited occurs. However, as shown in FIG. 5, since the mounting surface 13 is provided with the insulating film 4, the capacitor electrode 3 with the insulating film is short-circuited between the two terminal electrodes facing each other even when contacting the mounting surface. There is no.

そして、絶縁被膜付きコンデンサ3の実装面13と反対側の面には、絶縁被膜4が施されていないので、ワイヤーボンディングによって金属端子電極11と容易に接続することができる。したがって、複雑な内部配線基板を設置することなく電気回路を形成することができるのである。 And since the insulating film 4 is not given to the surface on the opposite side to the mounting surface 13 of the capacitor | condenser 3 with an insulating film, it can connect with the metal terminal electrode 11 easily by wire bonding. Therefore, an electric circuit can be formed without installing a complicated internal wiring board.

(実施例2)本発明による絶縁被膜付きコンデンサ3の別の製造方法として、従来から周知のチップ型積層体を製造する第一の工程と、前記チップ型積層体の対向する2面に下地電極5を施す第二の工程と、前記対向する2面の下地電極5を同時に有する一の面上に絶縁被膜4を施す第三の工程と、前記下地電極5にNiめっき6及びAuめっき7を施す第四の工程とからなる絶縁被膜付きコンデンサ3の製造方法がある。 (Embodiment 2) As another method of manufacturing the capacitor 3 with an insulating coating according to the present invention, a first step of manufacturing a conventionally known chip type laminate, and a base electrode on two opposing surfaces of the chip type laminate 5, a third step of applying the insulating coating 4 on one surface having the two opposing base electrodes 5 simultaneously, and Ni plating 6 and Au plating 7 on the base electrode 5. There is a method of manufacturing a capacitor 3 with an insulating film comprising a fourth step to be applied.

このように、下地電極5を施した後に絶縁被膜4を被覆し、その後Niめっき6およびAuめっき7を施したとしても、図6のように、めっきは絶縁被膜4の上には施されずに、導電性の下地電極5の上にしか施されない。したがって、実装面13上にめっきされることはなく、実施例1で示した絶縁被膜付きコンデンサ3と同様の効果を得ることができる。 Thus, even if the insulating film 4 is applied after the base electrode 5 is applied and then the Ni plating 6 and the Au plating 7 are applied, the plating is not applied on the insulating film 4 as shown in FIG. Further, it is applied only on the conductive base electrode 5. Therefore, the mounting surface 13 is not plated, and the same effect as the capacitor 3 with an insulating film shown in the first embodiment can be obtained.

さらに、実施例2の製造方法による絶縁被膜付きコンデンサ3は、Niめっき及びAuめっきを施す面積が、実施例1の製造方法による絶縁被膜付きコンデンサ3よりも小さくなるので、製造コストの面からみると有利になるのである。 Further, the capacitor 3 with the insulating coating film according to the manufacturing method of Example 2 has a smaller area for Ni plating and Au plating than the capacitor 3 with the insulating coating film according to the manufacturing method of Example 1, so that the manufacturing cost is viewed. It will be advantageous.

なお、Niめっき6を施した後に絶縁被膜4を被覆し、その後Auめっき7を施す手順は、生産効率を考慮すると現実的な手法ではないが、実施例1及び実施例2と同様の効果を得ることができる。 The procedure of coating the insulating coating 4 after applying the Ni plating 6 and then applying the Au plating 7 is not a practical method in consideration of production efficiency, but has the same effect as in the first and second embodiments. Obtainable.

以上、本発明の詳細について、具体的な実施例を示しながら説明してきたが、ここで示したのは本発明の一つの実施形態であり、その技術思想を踏まえた上で、発明の効果を著しく損なわない限度において、前記実施形態の一部を変更して実施することが可能であることが理解されるべきである。 As described above, the details of the present invention have been described with reference to specific examples. However, the present invention is shown as an embodiment of the present invention, and the effects of the invention are considered based on the technical idea. It should be understood that a part of the embodiment can be modified and implemented as long as it is not significantly impaired.

本発明による絶縁被膜付きコンデンサは、導電性の基板上に実装しても端子電極が導通してしまうことがなく、しかもワイヤーボンディングで容易に結線することができる。 The capacitor with an insulating film according to the present invention does not conduct the terminal electrode even when mounted on a conductive substrate, and can be easily connected by wire bonding.

1;,端子電極
2;,チップ型積層セラミックコンデンサ
3;,絶縁被膜付きコンデンサ
4;,絶縁被膜
5;,下地電極
6;,Niめっき
7;,Auめっき
8;,金属台座
9;,接着剤
10;,ワイヤー
11;,金属端子電極
12;,絶縁支持部
13;,実装面
1; Terminal electrode 2; Chip-type multilayer ceramic capacitor 3; Capacitor with insulating coating 4; Insulating coating 5; Base electrode 6; Ni plating 7; Au plating 8; Metal base 9; 10; Wire 11; Metal terminal electrode 12; Insulation support 13; Mounting surface

Claims (3)

2以上の端子電極を有するチップ型積層セラミックコンデンサにおいて、電気的に接続していない複数の端子電極を同時に有する一の面上の、少なくとも前記端子電極を含む部位に絶縁被膜を施した絶縁被膜付きコンデンサ。 In a chip-type multilayer ceramic capacitor having two or more terminal electrodes, an insulating coating is provided with an insulating coating applied to at least a portion including the terminal electrodes on one surface having a plurality of terminal electrodes that are not electrically connected simultaneously. Capacitor. チップ型積層体を製造する第一の工程と、
前記チップ型積層体に下地電極を施す第二の工程と、
前記下地電極上にめっきを施す第三の工程と、
電気的に接続していない複数の前記下地電極を同時に有する一の面上に絶縁被膜を施す第四の工程と、
からなる絶縁被膜付きコンデンサの製造方法。
A first step for producing a chip-type laminate,
A second step of applying a base electrode to the chip-type laminate;
A third step of plating on the base electrode;
A fourth step of applying an insulating film on one surface having the plurality of base electrodes that are not electrically connected simultaneously;
The manufacturing method of the capacitor | condenser with an insulating film which consists of.
チップ型積層体を製造する第一の工程と、
前記チップ型積層体に下地電極を施す第二の工程と、
電気的に接続していない複数の前記下地電極を同時に有する一の面上に絶縁被膜を施す第三の工程と、
前記下地電極上にめっきを施す第四の工程と、
からなる絶縁被膜付きコンデンサの製造方法。
A first step for producing a chip-type laminate,
A second step of applying a base electrode to the chip-type laminate;
A third step of applying an insulating film on one surface having the plurality of base electrodes that are not electrically connected simultaneously;
A fourth step of plating on the base electrode;
The manufacturing method of the capacitor | condenser with an insulating film which consists of.
JP2011085911A 2011-04-08 2011-04-08 Capacitor with insulating coating and manufacturing method therefor Withdrawn JP2012222124A (en)

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US20170207025A1 (en) * 2016-01-14 2017-07-20 Samsung Electro-Mechanics Co., Ltd. Multilayer electronic component and method of manufacturing the same
US10297387B2 (en) * 2016-11-21 2019-05-21 Samsung Electro-Mechanics Co., Ltd. Stress and moisture resistant capacitor and method of manufacturing the same
JP2020188144A (en) * 2019-05-15 2020-11-19 株式会社村田製作所 Electronic component packaging structure and manufacturing method therefor
US11538634B2 (en) 2020-02-27 2022-12-27 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including an insulating layer
US11610737B2 (en) 2020-02-27 2023-03-21 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170207025A1 (en) * 2016-01-14 2017-07-20 Samsung Electro-Mechanics Co., Ltd. Multilayer electronic component and method of manufacturing the same
US10431386B2 (en) * 2016-01-14 2019-10-01 Samsung Electro-Mechanics Co., Ltd. Multilayer electronic component including a composite body and method of manufacturing the same
US10297387B2 (en) * 2016-11-21 2019-05-21 Samsung Electro-Mechanics Co., Ltd. Stress and moisture resistant capacitor and method of manufacturing the same
JP2020188144A (en) * 2019-05-15 2020-11-19 株式会社村田製作所 Electronic component packaging structure and manufacturing method therefor
US11342122B2 (en) 2019-05-15 2022-05-24 Murata Manufacturing Co., Ltd. Electronic component assembly and method for manufacturing the same
JP7247740B2 (en) 2019-05-15 2023-03-29 株式会社村田製作所 Mounting structure for electronic components and manufacturing method thereof
US11538634B2 (en) 2020-02-27 2022-12-27 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including an insulating layer
US11610737B2 (en) 2020-02-27 2023-03-21 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component

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