JP2012221389A - Circuit simulation method and circuit simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the simulation time without lowering accuracy, in a circuit simulation of a semiconductor integrated circuit in consideration of a parasitic element.SOLUTION: A circuit simulation device includes: a parasitic element extraction part 120 for preparing a net list 130 including a parasitic element from layout data 110 of a semiconductor integrated circuit; a database part 150 for storing circuit block information without the need of taking influence of parasitism into consideration; and a circuit determination part 160 for determining whether or not a circuit block registered inside the database part 150 is present in an object semiconductor integrated circuit. When determined that the same circuit block is present, by replacing a net list of a part determined as the same circuit block in the net list 130 extracted from the layout data 110 with a net list 130Z of the circuit block not including the parasitic element by a net list replacement part 180, an unneeded parasitic element is deleted, the net list is simplified, and the circuit simulation is executed in a circuit simulator 190.

Description

  The present invention relates to a circuit simulation technique, for example, a technique effective when applied to a circuit simulation such as SPICE (Simulation Program with Integrated Circuit Emphasis) of a semiconductor integrated circuit considering a parasitic element.

  In the development process of a semiconductor integrated circuit, design of a semiconductor integrated circuit using CAD (Computer Aided Design) and circuit operation confirmation using a circuit simulator represented by SPICE (Simulation Program with Integrated Circuit) are performed.

  As the manufacturing process technology of a semiconductor integrated circuit advances, the distance between adjacent wirings and the width of the wirings are narrowed, and the wiring capacity and wiring resistance tend to increase. In order to consider this effect, as shown in FIG. 1, after performing layout, wiring resistance and wiring capacitance (hereinafter abbreviated as parasitic elements) are extracted from the layout and reflected in the circuit diagram to perform circuit simulation. . This is called back annotation.

  In recent years, as the size of semiconductor integrated circuits has increased, the number of parasitic elements has increased. When back-annotation is performed on all devices of a semiconductor integrated circuit, the execution time spent for simulation becomes large and difficult to converge. Etc., execution in a realistic time has become difficult.

  In order to solve the above technical problem, various methods for reducing the simulation time and reducing the simulation time by selecting a parasitic element to be considered based on a certain determination result have been proposed.

  For example, in Patent Document 1, a simulation is performed, and a pre-layout simulation for extracting a node (active node) whose potential has changed is performed, and a layout pattern verification is performed on the layout pattern data according to a conventional method. And parasitic elements are extracted from the layout pattern data based on the active node information extracted during the pre-layout simulation, and the parasitic element-added net including all the elements of the layout pattern data and the extracted parasitic element information. There is disclosed a back annotation method for executing a process of generating a list and a process of executing a post-layout simulation (back annotation) based on the generated netlist.

In the case of this patent document 1, by extracting only the parasitic elements related to the node whose potential has changed, it is intended to reduce the circuit scale and shorten the simulation time.
In Patent Document 2, an element extraction unit that creates a netlist including parasitic elements from layout data of a semiconductor integrated circuit, a node to which an interwiring capacitor is connected are extracted from a circuit defined by the netlist, and an input impedance of the node Whether to calculate an index value that defines the effect of inter-wire capacitance on circuit characteristics using the input impedance value, and to delete the inter-wire capacitance from the netlist based on the index value The inter-wiring capacity necessity determining section for determining whether or not, and the inter-wiring capacity deleting section for deleting the inter-wiring capacity from the net list based on the determination result and creating a net list to be analyzed. A layout detection apparatus is disclosed.

  In the case of this patent document 2, the circuit scale is reduced and the simulation time is reduced by selecting the inter-wiring capacitance to be considered according to the input impedance value.

JP 2002-41595 A JP 2004-78428 A

  The techniques of Patent Document 1 and Patent Document 2 described above attempt to reduce the simulation time by selecting a parasitic element to be considered based on a certain determination result, thereby reducing the simulation time.

  That is, in Patent Document 1, the parasitic elements to be considered are limited based on node (active node) information whose potential has changed, and in Patent Document 2, the wiring capacitance considered from the input impedance value of the node to which the wiring capacitance is connected. Is limited.

  However, in recent years, along with the further increase in the scale of semiconductor integrated circuits, the number of parasitic elements to be extracted tends to increase even if the above countermeasures are taken, so there is still a large amount of time spent for simulation. .

  An object of the present invention is to provide a technique for shortening the simulation time without reducing the accuracy of the simulation in the simulation of the semiconductor integrated circuit in consideration of the parasitic element.

According to a first aspect of the present invention, there is provided a step of preparing characteristic information including at least a first netlist relating to a first circuit block that does not need to consider the influence of parasitic elements;
A parasitic element extraction step of creating a second netlist including the parasitic elements from the layout data of the semiconductor integrated circuit;
A circuit determination step for determining whether or not a netlist of a second circuit block having the same topology as the first circuit block of the first netlist exists in the second netlist;
When it is determined that the net list of the second circuit block exists in the second net list, the portion of the net list of the second circuit block in the second net list is changed to the first of the first circuit block. A netlist replacing step of replacing with one netlist to obtain a third netlist;
A simulation execution step of performing a circuit simulation on the third netlist;
A circuit simulation method is provided.

According to a second aspect of the present invention, there is provided a database unit storing characteristic information including at least a first netlist relating to a first circuit block that does not need to consider the influence of parasitic elements;
A parasitic element extraction unit that creates a second netlist including the parasitic elements from layout data of the semiconductor integrated circuit;
A circuit determination unit that determines whether a net list of a second circuit block having the same topology as the first circuit block of the first net list exists in the second net list;
When it is determined that the net list of the second circuit block exists in the second net list, the portion of the net list of the second circuit block in the second net list extracted from the layout data is A net list replacement unit for replacing the first net list of the first circuit block to obtain a third net list;
A simulation execution unit for performing circuit simulation on the third netlist;
A circuit simulation apparatus is provided.

  According to the present invention, it is possible to provide a technique for shortening the simulation time without reducing the simulation accuracy in the simulation of the semiconductor integrated circuit in consideration of the parasitic element.

It is a conceptual diagram explaining a general back annotation. It is a block diagram which shows an example of a structure and effect | action of a circuit simulation apparatus which implements the circuit simulation method which is one embodiment in this invention. It is a conceptual diagram which shows the structural example of the information processing apparatus for implementing the circuit simulation method and circuit simulation apparatus which are one embodiment of this invention. 1 is a circuit diagram illustrating, in a simplified manner, a part of a semiconductor integrated circuit to be subjected to circuit simulation in an embodiment of the present invention. It is the conceptual diagram which simplified and partially illustrated the net list | wrist of the semiconductor integrated circuit used as the object of the circuit simulation in one embodiment of this invention. It is a top view which shows an example of the layout of the semiconductor integrated circuit used as the object of the circuit simulation in one embodiment of this invention. It is a conceptual diagram which shows an example of the net list | wrist including the parasitic element extracted from the layout data of a semiconductor integrated circuit. FIG. 7 is a circuit diagram corresponding to a netlist including a parasitic element illustrated in FIG. 6. It is a conceptual diagram of element information data showing the correspondence of symbol names between a net list of a semiconductor integrated circuit to be subjected to circuit simulation and a net list including parasitic elements. It is a conceptual diagram which shows the structural example of the database part used with the circuit simulation method and circuit simulation apparatus which are one embodiment of this invention. It is a conceptual diagram which shows the example of the circuit block corresponding to the net list registered into the database part. It is a conceptual diagram which shows the structural example of the net list registered into the database part. It is a conceptual diagram which shows the structural example of the parameter table registered into the database part. It is a conceptual diagram which shows the structural example of the connection element information table registered into the database part. It is the circuit diagram which simplified and illustrated other examples of the semiconductor integrated circuit used as the object of the circuit simulation in one embodiment of this invention. FIG. 12B is a conceptual diagram showing a net list corresponding to another example of the semiconductor integrated circuit of FIG. 12A. It is the circuit diagram which simplified and illustrated other examples of the semiconductor integrated circuit used as the object of the circuit simulation in one embodiment of this invention. 13B is a conceptual diagram showing a net list corresponding to another example of the semiconductor integrated circuit of FIG. 13A. FIG. It is a conceptual diagram which shows the structural example of the replacement circuit block element data produced | generated with the circuit simulation apparatus which is one embodiment of this invention. It is a conceptual diagram of the net list after replacement subjected to circuit simulation by the circuit simulation device according to one embodiment of the present invention. It is a conceptual diagram which shows the structural example of the database part used with the circuit simulation method and circuit simulation apparatus which are other embodiment of this invention. It is the conceptual diagram which illustrated the behavior model of the replacement | exchange object used with the circuit simulation method and circuit simulation apparatus which are other embodiment of this invention. FIG. 17B is a conceptual diagram illustrating a net list corresponding to the behavior model to be replaced in FIG. 17A. It is the circuit diagram which simplified a part of semiconductor integrated circuit circuit-simulated with the circuit simulation apparatus which is other embodiment of this invention. It is a conceptual diagram which shows an example of the net list corresponding to the circuit diagram of FIG. 18A. FIG. 18B is a conceptual diagram illustrating an example of a netlist including parasitic elements generated from layout data of the semiconductor integrated circuit in FIG. 18A. FIG. 20 is a circuit diagram of a circuit block corresponding to the net list of FIG. 19. It is a conceptual diagram which shows an example of the behavior model corresponding to the netlist which excluded the redundant parasitic element.

  The first aspect of the present embodiment is a parasitic element extraction technique capable of reducing the simulation time without reducing accuracy in the simulation of a semiconductor integrated circuit in consideration of parasitic elements. A parasitic element extraction unit that creates a netlist including parasitic elements, a database unit that stores circuit block information that does not need to consider the influence of parasitics, and a circuit block that has the same topology as the circuit block defined in the database unit The circuit determination unit that determines whether the netlist of the semiconductor integrated circuit exists in the netlist of the circuit data of the semiconductor integrated circuit, and the net including the parasitic element extracted from the layout data when it is determined that the netlist of the same circuit block exists. Netlist of circuit blocks with the same topology in the list The determination portion, illustrating the parasitic extraction technique and a net list replacing unit for replacing a netlist of a circuit block including no parasitic element.

  In the second mode of the present embodiment, when the net list replacement unit determines that a net list of the same circuit block exists in the net determination unit, the net list replacement unit includes a net list including parasitic elements extracted from layout data. Then, a parasitic element extraction technique for replacing a part determined as a net list of the same circuit block with a behavioral model of a circuit block that does not include a parasitic element will be exemplified.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 2 is a block diagram showing an example of the configuration and operation of a circuit simulation apparatus that implements a circuit simulation method according to an embodiment of the present invention.

FIG. 3 is a conceptual diagram showing a configuration example of an information processing apparatus for implementing a circuit simulation method and a circuit simulation apparatus according to an embodiment of the present invention.
As illustrated in FIG. 3, the information processing apparatus 10 according to the present embodiment includes a data storage device 11, a CPU 12, a memory 13, an input device 14, and an output device 15, which are connected to each other via a bus 16. Yes.

A circuit simulation apparatus 100 described later in the present embodiment is realized by executing a control program 17 described by a computer program in the information processing apparatus 10.
In other words, the control program 17 is stored in the data storage device 11 such as a hard disk device, and the stored control program 17 is executed by the CPU 12, thereby causing a parasitic element extraction unit 120, a circuit determination unit 160, and a parasitic parameter described later. The functions of the element extraction unit 120, the net list replacement unit 180, and the circuit simulator 190 are realized.

  The memory 13 temporarily stores the control program 17, parameters at the time of program execution, calculation results, and the like. The input device 14 communicates the operation of the designer, such as a keyboard and a mouse, to the CPU 12.

The output device 15 is a display for displaying an analysis result 200, which will be described later, which is data after execution of the control program 17 in the CPU 12, a printer for printing, or the like.
FIG. 4A is a circuit diagram illustrating, in a simplified manner, a portion of a semiconductor integrated circuit that is a target of circuit simulation according to an embodiment of the present invention.

FIG. 4B is a conceptual diagram illustrating a partially simplified net list of a semiconductor integrated circuit to be subjected to circuit simulation in one embodiment of the present invention.
FIG. 5 is a plan view showing an example of a layout of a semiconductor integrated circuit to be subjected to circuit simulation in one embodiment of the present invention.

FIG. 6 is a conceptual diagram illustrating an example of a netlist including parasitic elements extracted from layout data of a semiconductor integrated circuit.
As a specific embodiment, a case where the circuit simulation apparatus 100 of the present embodiment is applied to a layout corresponding to the semiconductor integrated circuit H10 shown in FIG. 4A and the semiconductor integrated circuit H10 shown in FIG. .

As illustrated in FIG. 4A, the semiconductor integrated circuit H10 includes, for example, a plurality of circuit blocks H11 to H15 connected to each other.
It should be noted that each element name in the circuit diagram, such as a symbol name such as M1, and each terminal name such as source (S), gate (G), drain (D) are added.

  Further, the wiring connecting the terminals is called a net, and information called a net name (for example, net1a) is added to each net. Furthermore, for each element, devices such as simulation model names such as pmos and nmos, gate width w, gate length l, and parallel connection number m (w = 4 um (micrometer), l = 2 um, m = 1), etc. Parameter information is added.

  The layout data 110 in FIG. 2 is layout data corresponding to the circuit diagram data 141 out of the circuit diagram data 141 and the netlist 142 constituting the analysis target circuit information 140 of the semiconductor integrated circuit.

A circuit element and a parasitic element are extracted from the layout data 110 by the parasitic element extraction unit 120, and a net list 130 (second net list) including the parasitic element is generated.
Further, element information data 130a is generated in which element information on the net list 130 including parasitic elements corresponding to each element on the net list 142 of the circuit diagram data 141 on a one-to-one basis is collected.

  Specifically, from the layout data 110 shown in FIG. 5, in addition to the circuit elements shown in FIG. 4A, the parasitic resistance of the wiring part and the parasitic capacitance between the wirings are extracted, and a circuit connection called a netlist 130 shown in FIG. Generate information.

  In the net list 130, a symbol name 131, a net name 132, a simulation model name 133, and parameter information 134 in the circuit diagram are described. Data contents and elements differ depending on the type of element.

  For example, in the case of a P-type MOSFET, pmos is stored in the model name 133, and net3a, net2a, and net1a, which are net names connected to the terminal D, terminal G, and terminal S, are sequentially stored in the net name 132. In the parameter information 134, values of gate width w, gate length l, and parallel connection number m are stored.

FIG. 7 is a circuit diagram corresponding to a net list including the parasitic elements illustrated in FIG.
FIG. 8 is a conceptual diagram of element information data showing the correspondence between symbol names of a net list of a semiconductor integrated circuit to be subjected to circuit simulation and a net list including parasitic elements.

When the net list 130 shown in FIG. 6 is expressed by a circuit diagram, FIG. 7 is obtained.
In FIG. 7, devices R2z and R3z added from FIG. 4A are parasitic resistances, and C1z is a parasitic capacitance.

  Further, the parasitic element extraction unit 120 includes a parasitic element that has a one-to-one correspondence with elements (symbol names:..., M1a, M2a, M3a, R1a,...) On the net list of the circuit diagram data illustrated in FIG. 4B. Element information data 130a in which information on elements (symbol names:..., M1z, M2z, M3z, R1z,...) On the list 130 is collected is generated as shown in FIG.

FIG. 9 is a conceptual diagram showing a configuration example of a database unit used in the circuit simulation method and the circuit simulation apparatus according to the embodiment of the present invention.
FIG. 10 is a conceptual diagram illustrating an example of a circuit block corresponding to a netlist registered in the database unit.

FIG. 11A is a conceptual diagram illustrating a configuration example of a netlist registered in the database unit.
FIG. 11B is a conceptual diagram illustrating a configuration example of a parameter table registered in the database unit.

FIG. 11C is a conceptual diagram illustrating a configuration example of a connection element information table registered in the database unit.
As shown in FIG. 9, the database unit 150 considers the influence of parasitic elements on the circuit characteristics under the use conditions (power supply voltage, use frequency, connection load, etc.) of the semiconductor integrated circuit defined by the analysis target circuit information 140. The circuit block netlist 151 (first netlist), the parameter table 152 that summarizes the parameter information of the circuit components created from the netlist information, and the terminals of the circuit components for the circuit blocks that can be determined to be unnecessary The connection element information table 153 in which element information connected to is stored for each target circuit block.

More specifically, it is assumed that there is a circuit block A (first circuit block) shown in FIG. 10 as a circuit block that does not need to consider the influence of parasitic elements.
Connected to the database unit 150 are the netlist 151 of the circuit block A shown in FIG. 11A, the parameter table 152 that summarizes the parameter information of the circuit constituent elements shown in FIG. 11B, and the terminals of the circuit constituent elements shown in FIG. 11C. The connection element information table 153 in which the element information is collected is stored.

The data structure of the net list 151 illustrated in FIG. 11A is the same as that of the net list 130 described above.
As illustrated in FIG. 11B, the parameter table 152 stores parameter information 152c (parameter information 134) in association with a combination of a symbol name 152a (symbol name 131) and a simulation model name 152b (model name 133). is doing.

As illustrated in FIG. 11C, the connection element information table 153 stores a symbol name 153a (symbol name 131) and connection element information 153b in association with each other.
Next, the circuit determination unit 160 checks whether a circuit block having the same topology as the circuit block defined in the database unit 150 exists in the circuit block of the circuit diagram data 141, and the result is used as the replacement circuit block element data 170. Save to.

  Specifically, the circuit determination unit 160 selects one circuit element of the circuit block A defined in the database unit 150, and acquires parameter information and connection terminal information of the element.

  For example, if M1 is selected as the symbol name 153a of the circuit block A, the simulation model name 152b of M1, parameter information 152c (pmos, w = 4um, l = 2um, m = 1), and connecting element information 153b ([[ D]: nmos [D], Resistance [R1]).

  Note that the connection element information 153b ([D]: nmos [D], Resistance [R1]) regarding M1 described above means that the D terminal of M1 is connected to the D terminal of nmos and the R1 terminal of Resistance. is doing.

  Next, it is checked whether or not an element having the same simulation model name, parameter information, and connecting element information as M1 exists in the net list of the circuit diagram data of the semiconductor integrated circuit. Save to element data.

  More specifically, in the case of the circuit block H11 (second circuit block) of the semiconductor integrated circuit shown in FIG. 4A, an element whose simulation model name 142c is pmos is first selected in the netlist 142 illustrated in FIG. 4B. , M1a is extracted. If there are other elements in the netlist 142 of FIG. 4B whose simulation model name 142c is pmos, they are also extracted.

  Next, the elements whose parameter information 142d is w = 4 μm, l = 2 μm, and m = 1 are extracted from the extracted elements. Furthermore, the net name 142b of the D terminal (the first element of the net name 132: net3a in the case of M1a) is acquired, and there is nmos whose net name 142b is the net name 132 of the D terminal, and the R1 terminal The element in which the resistance having the net name 132 exists is extracted.

In the net list 142 illustrated in FIG. 4B, M1a of the symbol name 142a corresponds to the above, and M1a is stored in the replacement circuit block element data 170.
FIG. 12A is a circuit diagram illustrating, in a simplified manner, another example of a semiconductor integrated circuit that is a target of circuit simulation according to an embodiment of the present invention.

12B is a conceptual diagram showing a netlist corresponding to another example of the semiconductor integrated circuit of FIG. 12A.
FIG. 13A is a circuit diagram illustrating, in a simplified manner, still another example of a semiconductor integrated circuit to be subjected to circuit simulation in one embodiment of the present invention.

FIG. 13B is a conceptual diagram showing a netlist corresponding to another example of the semiconductor integrated circuit of FIG. 13A.
FIG. 14 is a conceptual diagram showing a configuration example of replacement circuit block element data generated by the circuit simulation apparatus according to the embodiment of the present invention.

FIG. 15 is a conceptual diagram of a netlist after replacement subjected to circuit simulation by the circuit simulation apparatus according to the embodiment of the present invention.
For example, in the case of the circuit block H21 of the semiconductor integrated circuit H20 including the circuit blocks H21 to H25 as shown in FIG. 12A, M1b whose simulation model name 142c is pmos is extracted from the netlist 142 illustrated in FIG. 12B. The parameter information 142d is w = 6 um, l = 2 um, m = 1 and is different from M1 of the netlist 151 of the circuit block A, so that M1b is not stored in the replacement circuit block element data 170.

  In the case of the circuit block H31 of the semiconductor integrated circuit H30 including the circuit blocks H31 to H35 as shown in FIG. 13A, in the netlist 142 illustrated in FIG. 13B, M1c of the symbol name 142a is the simulation model name 142c. The parameter information 142d is the same as M1 of the netlist 151 of the circuit block A, but there is no Resistance in which the net3c of the net name 142b of the D terminal of M1c is the net name of the R1 terminal, and therefore M1c is a replacement circuit block. It is not stored in the element data 170.

  Subsequently, for the element connected to M1 of the circuit block A, the simulation model name 151c, the parameter information 151d, and the connection element information 153b are obtained in the same manner as described above, and whether or not they have the same information is checked. Adds the element information and saves it.

  More specifically, the simulation model name 151c and the parameter information 151d are connected in order with respect to M2 which is nmos connected to M1 of the circuit block A defined in the database unit 150 and R1 which is resistance. The element information 153b is acquired, and the same simulation model name 142c and parameter information 142d are obtained for M2a which is nmos connected to M1a of the semiconductor integrated circuit shown in FIG. 4A as the circuit diagram data 141, and R1a which is resistance. It is checked whether the connection element information 153b is possessed.

  As a result, if it exists, M2a and R1a are stored in the replacement circuit block element data 170 in addition to the previously stored M1a. If it does not exist, M1a is deleted from the database, and the determination for the circuit block A ends.

  Next, the same as above is repeated, and the simulation model name 151c, parameter information 151d, and connection element information 153b are acquired for the elements connected to M2 and R1 checked earlier, and the circuit diagram data 141 (net list 142) is the same. Check if you have the information.

At this time, the elements (M1a, M2a, R1a) already checked and stored in the replacement circuit block element data 170 are not checked.
By repeating this process, if a circuit block having the same topology as the circuit block registered in the database unit 150 exists in the net list 142 of the analysis target circuit information 140, it is saved as replacement circuit block element data 170. Will be.

In this case, as shown in FIG. 14, M1a, M2a, M3a, and R1a are stored as replacement circuit block element data 170.
In the replacement circuit block element data 170, a circuit block name 171 and a replacement circuit block element name 172 are stored in association with each other.

When a plurality of circuit blocks are registered in the database unit 150, the above check is executed for each circuit block.
In the net list replacement unit 180, when the data is stored in the replacement circuit block element data 170, the part determined to be the same circuit block in the net list 130 including the parasitic elements is stored in the database unit 150 including no parasitics. Replace with the specified netlist 151.

  More specifically, the replacement circuit block element data 170 includes element information (M1a) of the circuit block having the same topology as the circuit block defined in the database unit 150 in the net list 142 shown in FIG. , M2a, M3a, R1a).

  The parasitic element extraction unit 120 uses the correspondence table of the element information data 130a shown in FIG. 8 generated from the net list 130. In the net list 130 including the parasitic elements shown in FIG. 6, (M1a, M2a, M3a, R1a ) Are extracted (M1z, M2z, M3z, R1z).

  Further, the net names 132 of these elements are extracted from the net list 130 of FIG. (Net7z, net8z) is acquired.

  The above net names are searched one by one in the net list 130 including parasitic elements shown in FIG. 6, and the model name 133 of the parasitic element model name p_res or p_cap is obtained with the symbol name 131 having the net name. To extract.

  More specifically, first, the net list 130 of M1z is searched in the net list 130, R2z having net3z is searched, and the model name 133 is acquired. As a result, the model name 133 of the parasitic element is p_res. , R2z is extracted.

Subsequently, the same is performed for the other net names 132 of M1z and the net names 132 of other elements such as M2z.
As a result, in the case of the netlist 130 shown in FIG. 6, parasitic elements (R2z, R3z, C1z) are extracted.

  Next, the elements (M1z, M2z, M3z, R1z, R2z, R3z, C1z) extracted above are deleted from the netlist 130 including parasitics and are exemplified in FIG. 11A of the circuit block A stored in the database unit 150. The netlist 151 is added.

At this time, for the net connected to the circuit block A from the circuit block A, the net name 151b is replaced and the circuit connection information is corrected so that there is no contradiction.
More specifically, for the net names (net1, net2, net4, net5, net7, net8) connected to the external circuit block in FIG. 11A, first, net names 151b are obtained one by one (example: net1). The symbol name 151a having the net name 151b and the connection terminal name are obtained from the net list 151 and the connection element information table 153 (eg, symbol name M1, connection element name S).

  Next, the symbol (M1z) corresponding to the symbol is extracted from the net list 130 including the parasitic in FIG. 6, and the net name (net1z) of the connection terminal name (S) extracted above is acquired. For other nets, the corresponding net names are obtained in the same manner.

  As a result, the net names (net1, net2, net4, net5, net7, net8) connected to the other circuit blocks in the net list 151 of FIG. 11A are shown in FIG. 7, and the net names (net1z, net2z, net5z, net6z) corresponding to them. , Net10z, net11z) and convert them respectively.

  As a result of the above, the contents of the net list 130 including parasitic elements are changed as in the net list 130Z (third net list) shown in FIG. Compared with the net list 130 created by the parasitic element extraction unit 120 shown in FIG. 8, it can be seen that the net list 130Z has the parasitic elements deleted.

  That is, the netlist replacement unit 180 removes the parasitic elements from the netlist 130 including the parasitic elements from the circuit blocks that are considered unnecessary based on the circuit block information defined by the database unit 150. The list 130Z is edited, and the scale of the net list 130Z is smaller than that of the net list 130.

The circuit simulator 190 inputs the netlist 130Z, executes circuit simulation, and outputs an analysis result 200.
At this time, since the scale of the net list 130Z is much smaller than that of the net list 130, the simulation time is greatly shortened and the accuracy of the analysis result 200 is not lowered.

  That is, in the circuit simulator 190, by performing a simulation using a small netlist 130Z that does not include unnecessary (redundant) parasitic elements, an analysis result simulated using the netlist 130 including parasitic elements is obtained. The simulation time can be shortened without reducing the accuracy of the analysis result 200.

(Embodiment 2)
FIG. 16 is a conceptual diagram showing a configuration example of a database unit used in a circuit simulation method and a circuit simulation apparatus according to another embodiment of the present invention.

FIG. 17A is a conceptual diagram illustrating a behavior model to be replaced used in a circuit simulation method and a circuit simulation apparatus according to another embodiment of the present invention.
FIG. 17B is a conceptual diagram illustrating a netlist corresponding to the behavior model to be replaced in FIG. 17A.

FIG. 18A is a circuit diagram in which a part of a semiconductor integrated circuit subjected to circuit simulation by a circuit simulation apparatus according to another embodiment of the present invention is simplified.
FIG. 18B is a conceptual diagram illustrating an example of a netlist corresponding to the circuit diagram of FIG. 18A.

FIG. 19 is a conceptual diagram showing an example of a net list including parasitic elements generated from the layout data of the semiconductor integrated circuit of FIG. 18A.
FIG. 20 is a circuit diagram of a circuit block corresponding to the net list of FIG.

FIG. 21 is a conceptual diagram illustrating an example of a behavior model corresponding to a netlist excluding redundant parasitic elements.
In the second embodiment, an example is shown in which the circuit simulator 190 is applied to execute a circuit simulation by describing a net list by a behavior model in a language describing the operation of an analog circuit such as Verilog-AMS.

  That is, in the second embodiment, the database unit 150A illustrated in FIG. 16 is used in place of the database unit 150 illustrated in FIG. 2 in the simulation of the semiconductor integrated circuit considering the parasitic elements.

  The database unit 150A illustrated in FIG. 16 includes a circuit block B (first circuit block) that can be determined from the design experience so far that it is not necessary to consider the influence of parasitic elements on the circuit characteristics. In addition to the net list 151, the parameter table 152 that summarizes the parameter information of the circuit constituent elements, and the connection element information table 153 that summarizes the element information to which the terminals of the circuit constituent elements are connected, the net list of the circuit block B Information in which 151 is replaced with a behavior model 154 conforming to a language specification such as Verilog-AMS is stored.

  Verilog-AMS is a language that describes the operation of an analog circuit as shown in FIG. 17A. By expressing the netlist 151 created at the transistor level with a behavioral model 154 of a language description using Verilog-AMS, simulation can be performed at higher speed.

  From the extraction of the net list 130 including parasitic elements from the layout data 110, the circuit block B defined in the database unit 150 among the circuit blocks of the circuit diagram data 141 (net list 142) of the analysis target circuit information 140. The circuit determination unit 160 that checks whether there is a circuit block having the same topology and the operation until the replacement circuit block element data 170 that is the output result is stored are the same as those in the first embodiment.

  In the case of the second embodiment, when data exists as the replacement circuit block element data 170, the net list replacement unit 180 determines that the circuit block B is the same as the circuit block B in the net list 130 including the parasitic elements. The portion thus replaced is replaced with a behavior model of the circuit block B that does not include parasitics.

  A netlist 130 (second netlist) of FIG. 19 in which parasitic elements are extracted in one circuit block H41 (second circuit block) of a semiconductor integrated circuit H40 including a plurality of circuit blocks H41 to H45 as shown in FIG. This will be specifically described with reference to FIG. 20 which is a circuit diagram.

  The replacement circuit block element data 170 includes element information (M1a, M2a) of a circuit block having the same topology as the circuit block B shown in FIG. 17A defined in the database unit 150 in the net list 142 shown in FIG. 18B. Saved.

Using the correspondence table generated by the net list 130, the elements (M1z, M2z) corresponding to (M1a, M2a) are extracted from the net list 130 including the parasitic elements shown in FIG.
Further, the net names 132 of these elements are extracted from the net list 130 of FIG. 19, and M1z: (outz, inz, vddz) and M2z: (net1z, inz, gndz) are acquired.

  The net names 132 are searched one by one in the net list 130 including parasitic elements shown in FIG. 19, and the model name 133 of the parasitic element model name 133 is obtained as a model name 133 with the symbol having the net name 132. Extract things.

  More specifically, first, the M1z outz is searched in the netlist 130 of FIG. 19 to search for R1z having outz, and as a result of obtaining the model name 133, p_res which is the model name 133 of the parasitic element Therefore, R1z is extracted.

Subsequently, the same operation is performed for other net names of M1z and net names of other elements such as M2z.
As a result, in the case of the netlist 130 shown in FIG. 19, the parasitic element (R1z) is extracted.

  Next, the elements (M1z, M2z, R1z) extracted above are deleted from the net list 130 including parasitics, and the net list exemplified in FIG. 17B of the behavior model 154 of the circuit block B registered in the database unit 150. 151 is added.

At this time, for the net connected from the circuit block B to the other circuit block, the net name 151b is replaced so that the connection information of the circuit is not inconsistent.
More specifically, for nets (vdd, in, out, gnd) connected to an external circuit block in FIG. 17A, first, one net name 151b is acquired (eg, vdd), and the net name 151b is obtained. The symbol name 151a and the connection terminal name are acquired from the net list 151 (for example, symbol name M1, connection element name S).

  Next, the symbol (M1z) corresponding to the symbol name 131 is extracted from the net list 130 including parasitic elements, and the net name (vddz) of the connection terminal name (S) extracted above is acquired. For other net names, corresponding nets are acquired in the same manner.

  As a result, the net names 132 (vddz, inz, outz, gndz) corresponding to the nets (vdd, in, out, gnd) connected to the external circuit block in FIG. 17A are acquired from the net list 130 of FIG. , Convert each.

As a result of performing the above, the contents of the netlist 130 (behavior model 130M) including parasitic elements are changed like the behavior model 130MZ shown in FIG.
Compared with the net list 130 (behavior model 130M) shown in FIG. 19, it can be seen that the net list is a behavior model 130MZ from which parasitic elements are deleted.

Then, the circuit simulator 190 executes circuit simulation on the net list of the behavior model 130MZ and outputs an analysis result 200.
In this case, the behavior model 130MZ does not include information on redundant parasitic elements, so that the circuit simulation in the circuit simulator 190 is accelerated and the accuracy of the analysis result 200 is not reduced.

  That is, in the case of the second embodiment, when a circuit simulation is performed by describing a net list using a behavior model in the circuit simulator 190, an analysis result obtained by circuit simulation using the net list 130 including parasitic elements is obtained. In comparison, the simulation time can be shortened without lowering the accuracy of the analysis result 200.

  As described above, according to each embodiment of the present invention, when there is a circuit block that does not need to consider the influence of the parasitic element in the netlist including the parasitic element extracted from the layout data of the semiconductor integrated circuit. In addition, by replacing the net list including parasitic elements with a net list of a circuit block that does not include parasitic elements, unnecessary parasitic elements can be deleted, the net list can be simplified, and the simulation time can be shortened.

  In addition, when there is a circuit block that does not need to consider the influence of parasitic elements in the net list that includes parasitic elements extracted from the layout data of the semiconductor integrated circuit, the net list that includes parasitic elements is not included in the circuit that does not include parasitic elements. It is possible to further reduce the simulation time by replacing with a behavior model of the block.

  Needless to say, the present invention is not limited to the configuration exemplified in the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

10 Information processing device 11 Data storage device 12 CPU
13 Memory 14 Input device 15 Output device 16 Bus 17 Control program 100 Circuit simulation device 110 Layout data 120 Parasitic element extraction unit 130 Netlist 130Z Netlist 130M Behavior model 130MZ Behavior model 130a Element information data 131 Symbol name 132 Net name 133 Model name 134 Parameter information 140 Analysis target circuit information 141 Circuit diagram data 142 Net list 142a Symbol name 142b Net name 142c Simulation model name 142d Parameter information 150 Database unit 150A Database unit 151 Net list 151a Symbol name 151b Net name 151c Simulation model name 151d Parameter information 152 Parameter table 152a Symbol name 1 2b Simulation model name 152c Parameter information 153 Connection element information table 153a Symbol name 153b Connection element information 154 Behavior model 160 Circuit determination unit 170 Replacement circuit block element data 171 Circuit block name 172 Replacement circuit block element name 180 Netlist replacement unit 190 Circuit simulator 200 Analysis Result H10 Semiconductor Integrated Circuits H11 to H15 Circuit Block H20 Semiconductor Integrated Circuits H21 to H25 Circuit Block H30 Semiconductor Integrated Circuits H31 to H35 Circuit Block H40 Semiconductor Integrated Circuits H41 to H45 Circuit Block

Claims (6)

Preparing characteristic information including at least a first netlist for a first circuit block that does not need to consider the effects of parasitic elements;
A parasitic element extraction step of creating a second netlist including the parasitic elements from the layout data of the semiconductor integrated circuit;
A circuit determination step for determining whether or not a netlist of a second circuit block having the same topology as the first circuit block of the first netlist exists in the second netlist;
When it is determined that the net list of the second circuit block exists in the second net list, the portion of the net list of the second circuit block in the second net list is changed to the first of the first circuit block. A netlist replacing step of replacing with one netlist to obtain a third netlist;
A simulation execution step of performing a circuit simulation on the third netlist;
A circuit simulation method comprising: The circuit simulation method according to claim 1,
In the simulation execution step, when executing the circuit simulation using a behavior model describing the input / output characteristics of the circuit in a program language,
In the net list replacing step, the net list portion of the second circuit block in the second net list is replaced with a behavior model corresponding to the first net list of the first circuit block. Circuit simulation method. The circuit simulation method according to claim 1,
As the characteristic information, a parameter table storing parameter information of circuit constituent elements of each of the first circuit blocks, and a connecting element information table storing element information to which terminals of the circuit constituent elements are connected. A circuit simulation method comprising: preparing a circuit. A database unit storing characteristic information including at least a first netlist relating to a first circuit block that does not need to consider the influence of parasitic elements;
A parasitic element extraction unit that creates a second netlist including the parasitic elements from layout data of the semiconductor integrated circuit;
A circuit determination unit that determines whether a net list of a second circuit block having the same topology as the first circuit block of the first net list exists in the second net list;
When it is determined that the net list of the second circuit block exists in the second net list, the portion of the net list of the second circuit block in the second net list extracted from the layout data is A net list replacement unit for replacing the first net list of the first circuit block to obtain a third net list;
A simulation execution unit for performing circuit simulation on the third netlist;
A circuit simulation apparatus comprising: The circuit simulation apparatus according to claim 4,
In the simulation execution unit, when executing the circuit simulation using a behavior model describing the input / output characteristics of the circuit in a program language,
The net list replacement unit replaces the net list portion of the second circuit block in the second net list with a behavior model corresponding to the first net list of the first circuit block. Circuit simulation device. The circuit simulation apparatus according to claim 4,
The characteristic information further includes a parameter table storing parameter information of circuit constituent elements of each of the first circuit blocks, and a connection element information table storing element information to which terminals of the circuit constituent elements are connected. A circuit simulation apparatus comprising: