JP2012221138A - Information processor and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the frequency of the acquisition of invalid data in which a portion of information processing data is insufficient when a control part reads data transferred from a transfer source information processing circuit to a memory.SOLUTION: An information processor 1 is configured to, when transferring information processing data from a transfer source information processing circuit 12 to a transfer destination information processing circuit 13, make a memory 70 temporarily store the information processing data via an FIFO processing part 67 which outputs data in the order of acquisition. The information processor 1 includes: an interruption processing part 11 for, after the information processing data output by the transfer source information processing circuit reach the FIFO processing part, outputting status data to the FIFO processing part, and for generating an interruption signal; a DMA function part 202 for performing the DMA transfer of data between the FIFO processing part and the memory; and a control part 201 for determining whether or not the status data are stored in the memory after receiving the interruption signal, and for, when the status data are stored, making the DMA function part 202 perform the DMA transfer of the information processing data from the memory to the FIFO processing part.

Description

  The present invention relates to an information processing apparatus having a DMA (Direct Memory Access) function, and more particularly to an information processing apparatus that transfers data via a FIFO (First In First Out) memory and an image forming apparatus using the information processing apparatus.

The DMA control circuit included in the burst data transfer processing device of Patent Document 1 has a function of transferring the read data to the FIFO memory and outputting a data transfer end signal after the data transfer is completed. The FIFO memory has a function of outputting a memory empty signal when the memory area becomes empty.
The interrupt signal generation circuit outputs an interrupt signal to the processor when the data transfer end signal from the DMA control circuit is ON and the memory empty signal of the FIFO memory is ON. Thereby, the processor can recognize that the data transfer is completed. Then, the processor acquires data from the memory.

Japanese Unexamined Patent Publication No. 5-28093 ([0002] to [0009], FIG. 2)

  However, in the burst data transfer processing device (information processing device) of Patent Document 1, information processing is performed due to the size of data (information processing data) transferred by the DMA control circuit (transfer information processing circuit), the influence of the communication environment, and the like. It takes time for all of the data to be stored in the memory, and at the time when the processor (control unit) receives the interrupt signal, not all of the transferred information processing data may be stored in the memory. It was. At this time, since the control unit recognizes that the transfer of the information processing data has been completed by receiving the interrupt signal, the control unit acquires the information processing data from the memory. Thus, there is a problem that the control unit acquires invalid data for which a part of the information processing data is insufficient.

  The present invention has been made to solve the above problems, and when the control unit reads data transferred from the transfer source information processing circuit to the memory, a part of the information processing data is insufficient. It is an object to provide an information processing apparatus and an image forming apparatus that reduce the number of times invalid data is acquired.

  In order to solve the above-described problem, the first invention provides the information processing data via a FIFO processing unit that outputs data in the order of acquisition when the information processing data is transferred from the transfer source information processing circuit to the transfer destination information processing circuit. Is temporarily stored in a memory, and after the information processing data output from the transfer source information processing circuit reaches the FIFO processing unit, status data is output to the FIFO processing unit, and further interrupts are generated. An interrupt processing unit that generates a signal, a DMA function unit that performs DMA transfer of data between the FIFO processing unit and the memory, and the status data is stored in the memory after receiving the interrupt signal When the data is stored, the information processing data is transferred to the DMA function unit from the memory to the FIFO processing unit. And a control unit for A transfer.

  According to this configuration, the control unit can confirm that all the information processing data output from the transfer source information processing circuit is stored in the memory by storing the status data.

  In a second invention, an image forming apparatus includes the information processing apparatus according to any one of claims 1 to 4 and an image forming unit that forms an image on a medium based on the information processing data. .

  According to the present invention, when the control unit causes the FIFO processing unit to acquire the information processing data stored in the memory from the transfer source information processing circuit, the number of times the FIFO processing unit acquires invalid data can be reduced.

1 is a block diagram of an image forming apparatus including an image processing apparatus according to the present invention. 1 is a block diagram illustrating a configuration of a CPU interrupt processing circuit according to a first embodiment and a partial configuration of an image processing apparatus according to the CPU interrupt processing circuit. 6 is a time chart of an intermediate data read operation of the image processing apparatus according to the first embodiment. It is a block diagram which shows the structure of the CPU interrupt processing circuit which concerns on 2nd Embodiment, and a part structure of the image processing apparatus which concerns on the CPU interrupt processing circuit. 10 is a time chart of an intermediate data read operation of the image processing apparatus according to the second embodiment. It is a time chart of the transfer data read-out operation | movement of the conventional image processing apparatus.

  Hereinafter, an embodiment of the present invention (hereinafter referred to as “the present embodiment”) will be described in detail with reference to the drawings. Each figure is only schematically showing the present invention. Therefore, the present invention is not limited to the illustrated example. Moreover, in each figure, the same code | symbol is attached | subjected about the common component and the same component, and those overlapping description is abbreviate | omitted.

[Configuration of Image Forming Apparatus]
FIG. 1 is a block diagram of an image forming apparatus including an image processing apparatus according to the first embodiment. As shown in FIG. 1, an image forming apparatus 100 includes an image processing apparatus 1 serving as an information processing apparatus, a mechanism unit 2 including a motor 2a, a sensor 2b, and the like, and a mechanism control ASIC 3 that controls the mechanism unit 2. The image forming unit 4 and the communication connection unit 5 are provided.

  The image processing apparatus 1 acquires image data from the print job received by the communication connection unit 5, converts the image data into a data format that can be formed by the image forming unit 4, and generates print data. And output to the image forming unit 4. Details will be described later. Here, when the image processing apparatus 1 converts the image data into print data, the image processing apparatus 1 converts the image data into intermediate data once, and converts the intermediate data into print data.

(Mechanism part 2)
The mechanism unit 2 is a drive unit such as a motor 2a or a sensor 2b provided in the image forming apparatus 100, and is controlled by a mechanism control ASIC 3 described later. For example, the motor 2a is a motor that operates a fixing device, a photosensitive drum, a transfer roller, and a paper transport roller (not shown). The sensor 2b is a sensor that detects passage of a sheet, a sensor that detects the shape of a sheet, or the like.

(Mechanism control ASIC3)
The mechanism control ASIC 3 is a control unit that controls the mechanism unit 2, for example, controls the motor 2a to execute sheet conveyance, and acquires sheet position information obtained from the sensor 2b.
Here, the mechanism control ASIC 3 is connected to the image processing apparatus 1 (image processing ASIC 10 to be described later) via a signal line Lm, and is also connected to the image forming unit 4 via a signal line Lp. As a result, the mechanism control ASIC 3 generates a timing signal for requesting output of print data based on the acquired sheet position information, and outputs it to the image processing apparatus 1 (image processing ASIC 10) and the image forming unit 4.
The mechanism control ASIC 3 is connected to a message processing circuit 14 to be described later via a message bus 31 (indicated by a bold line), and controls the motor 2a when receiving a sheet conveyance start message from the message processing circuit 14, for example. To carry the paper.

(Image forming unit 4)
The image forming unit 4 is a mechanism unit that forms an image on a medium such as paper based on print data acquired from the image processing apparatus 1. The image forming unit 4 receives a timing signal from the mechanism control ASIC 3 via the signal line Lp, and receives print data from the image processing ASIC 10 via the print data bus 41 (shown by a bold line).
For example, when forming an image on a medium, the image forming unit 4 uses four colors (Cyan, Mazenda, Yellow, and Black) of ink to express colors using a CMYK color model (hereinafter referred to as CMYK). The print data at this time is CIELab color system color information [L ^* , a ^* , b ^* ] that can be expressed in CMYK, and the intermediate data is an XYZ color system. The image data is color data [R, G, B].

(Communication connection unit 5)
The communication connection unit 5 is connected to a network N such as a LAN (Local Area Network), and a computer (not shown) such as a PC (Personal Computer) is connected to the end of the communication connection unit 5. A print job including image data is transmitted from the computer. This print job includes an instruction to print an image based on the image data on a recording medium such as paper.

(Image processing apparatus 1)
Next, each component provided in the image processing apparatus 1 will be described. The image processing apparatus 1 includes an image processing ASIC 10 as an information processing unit, a CPU 20 as a control unit, and a memory 70 as a storage unit. The image processing ASIC 10 includes a CPU interrupt processing circuit 11, a first image processing circuit 12, a second image processing circuit 13, a message processing circuit 14, a print data output circuit 15, and a FIFO processing unit 67. It comprises a FIFO memory 16 and a PCIE connection processing circuit 17, a data transfer bus 18, and a PCIE bus 19.
The CPU interrupt processing circuit 11, the first image processing circuit 12, the second image processing circuit 13, the message processing circuit 14, and the print data output circuit 15 are respectively connected to the FIFO via the data transfer bus 18. Data is transmitted to and received from the memory 16. These are arranged in the order in which data is output to the FIFO memory 16 and at a distance such that data is stored (input) in the FIFO memory 16.
The PCIE bus 19 connects the PCIE connection processing circuit 17 and the CPU 20 so that they can communicate with each other.

Here, the so-called DMA controller includes a FIFO memory 16, a PCIE connection processing circuit 17, a data transfer bus 18, and a PCIE bus 19.
The PCIE connection processing circuit 17 and the CPU 20 are a PCI Express (hereinafter referred to as “PCIE”) bus standardized by PCI-SIG (Peripheral Component Interconnect-Special Interest Group) in order to realize high-speed data transfer. 19 is connected.

(PCIE connection processing circuit 17)
The PCIE connection processing circuit 17 is connected to a PCIE bus 19 via a PCIE bus bridge (not shown) provided therein, and the PCIE bus 19 is connected to the CPU 20 via a PCIE bus bridge 23 (FIG. 3) provided on the CPU 20 side. Connect with.

(FIFO memory 16)
The FIFO memory 16 is a storage unit that is arranged between the data transfer bus 18 and the PCIE connection processing circuit 17, accumulates data in the order of input, and acquires data in the order of input. As a result, the data accumulated (input) in the FIFO memory 16 via the data transfer bus 18 is acquired by the PCIE connection processing circuit 17 in the input order. By temporarily storing data in the FIFO memory 16, it has a function of absorbing a speed difference between the PCIE connection processing circuit 17 and the data transfer bus 18.
Here, the FIFO memory 16 has different operating frequencies on the input side and the output side, and can store data asynchronously.

(Memory 70)
The memory 70 is a storage unit that stores data, and is connected to the CPU 20 via the memory bus 71 so that data can be transmitted and received. The memory 70 is composed of, for example, a RAM (Random Access Memory), an HDD (Hard Disc Drive), or the like.

(CPU 20)
The CPU 20 is connected to the CPU interrupt processing circuit 11, the memory 70, and the PCIE connection processing circuit 17.
The CPU 20 is connected to a signal line interface (signal line IF) 21 (FIG. 3) connected to the signal line Ls, and the CPU 20 is connected to the CPU interrupt processing circuit 11 via the signal line IF 21 and the signal line Ls.
The CPU 20 is connected to a memory interface (memory IF) 22 (FIG. 3), and the CPU 20 is connected to the memory 70 via the memory IF 22 and the memory bus 23.
Further, the CPU 20 is connected to the PCIE bus bridge 23 (FIG. 3), and is connected to the PCIE connection processing circuit 17 via the PCIE bus bridge 23 and the PCIE bus 19.

The CPU 20 includes a control unit 201 and a DMA function unit 202.
Here, the control unit 201 controls each component included in the image processing apparatus 1. The control unit 201 reads and executes a program stored in a ROM (Read Only Memory) (not shown) or the like, and controls each component included in the image processing device 1 so that the image processing device 1 functions.

The DMA function unit 202 can access the memory 70 without causing the control unit 201 to perform processing, and transfers data between the FIFO memory 16 and the memory 70. For example, data can be stored in the memory 70 and data can be read from the memory 70. In addition, data can be deleted from the memory 70. Here, the memory IF 22 connecting the CPU 20 and the memory 70 mediates the DMA function.
Then, the control unit 201 causes the DMA function unit 202 to delete the status data in the memory 70 after the DMA function unit 202 reads the intermediate data and image data stored in the memory 70.

  When the control unit 201 acquires a print job from the network N via the communication connection unit 5, the control unit 201 temporarily stores the print job in the memory 70. This print job includes image data.

  When receiving a CPU interrupt signal from an image processing ASIC 10 (CPU interrupt processing circuit 11), which will be described later, the control unit 201 performs interrupt control and performs a predetermined monitoring program (interrupt program) from a storage unit (not shown). And monitoring processing of the memory 70 is executed. This monitoring process reads the storage area of the memory 70 and determines whether or not status data is stored in the memory 70. The control unit 201 repeatedly executes this monitoring process at a predetermined timing until it can be confirmed that the status data is stored in the memory 70.

  The control unit 201 reads information included in the header of the status data and determines whether the status data is the first status data or the second status data. If the status data is the first status data, the DMA function unit 202 transfers the intermediate data stored in the memory 70 to the image processing ASIC 10 (PCIE connection processing circuit 17). On the other hand, if it is the second status data, the DMA function unit 202 transfers the print data stored in the memory 70 to the image processing ASIC 10 (PCIE connection processing circuit 17). Details of the first status data and the second status data will be described later.

(Image processing ASIC 10)
The image processing ASIC 10 is a component that performs image processing for converting image data into print data. The image processing ASIC 10 includes a first image processing circuit 12 and a second image processing circuit 13, a PCIE connection processing circuit 17 and a FIFO memory 16 as a FIFO processing unit 67, and a CPU interrupt process as an interrupt processing unit. The circuit 11 includes a print data output circuit 15 and a message processing circuit 14. The CPU interrupt processing circuit 11 is connected to the first image processing circuit 12 via the signal line L1, and to the second image processing circuit 13 via the signal line L2.

  The image processing ASIC 10 performs image processing in which the first image processing circuit 12 converts image data into intermediate data before the image data is converted into print data, and the second image processing circuit 13 prints the intermediate data. It is assumed that image processing to be converted into data is performed. Here, when converting image data into intermediate data, the first image processing circuit 12 is a transfer source information processing circuit, and the second image processing circuit 13 is a transfer destination information processing circuit. When converting the intermediate data into print data, the second image processing circuit 13 is a transfer source information processing circuit, and the print data output circuit 15 is a transfer destination information processing circuit.

(First image processing circuit 12)
The first image processing circuit 12 is controlled by a control unit (not shown) to realize an image processing function for converting image data into intermediate data. This control unit (not shown) may be the control unit 201 of the CPU 20.
The first image processing circuit 12 acquires image data from the memory 70, performs predetermined processing on the image data, and converts it into intermediate data. This image data is acquired from the memory 70 by the CPU 20 (control unit 201) executing a program for printing the image data stored in the memory 70 by controlling each component of the image processing apparatus 1. It is.
The first image processing circuit 12 outputs the intermediate data to the FIFO memory 16 in order to store the intermediate data in the memory 70. Then, when the intermediate data is output, a DMA completion signal is generated and transmitted to the CPU interrupt processing circuit 11 via the signal line L1.

(Second image processing circuit 13)
The second image processing circuit 13 is controlled by a control unit (not shown) to realize an image processing function for converting intermediate data into print data. This control unit (not shown) may be the control unit 201 of the CPU 20.
The second image processing circuit 13 acquires the intermediate data stored in the memory 70 via the FIFO memory 16, performs a predetermined process on the intermediate data, and converts it into print data.
The second image processing circuit 13 outputs the print data to the FIFO memory 16 in order to store the print data in the memory 70. Then, when the print data is output, a DMA completion signal is generated and transmitted to the CPU interrupt processing circuit 11 via the signal line L2.

(CPU interrupt processing circuit 11)
When receiving a DMA completion interrupt signal from the first image processing circuit 12 or the second image processing circuit 13, the CPU interrupt processing circuit 11 generates status data. In order to store the status data in the memory 70, the status data is output to the FIFO memory 16. After outputting the status data, the CPU interrupt processing circuit 11 generates a CPU interrupt signal and outputs it to the CPU 20 via the signal line Ls. This CPU interrupt signal is, for example, a 1-bit signal indicating ON or OFF.

In this embodiment, when receiving a DMA completion interrupt signal from the first image processing circuit 12, the CPU interrupt processing circuit 11 generates first status data and outputs it to the FIFO memory 16. As a result, the first status data is stored in the memory 70. Further, when the CPU interrupt processing circuit 11 receives the DMA completion interrupt signal from the second image processing circuit 13, it generates second status data and outputs it to the FIFO memory 16. As a result, the second status data is stored in the memory 70.
When generating the first status data, the CPU interrupt processing circuit 11 includes information indicating that the status data is the first status data in the header. Similarly, the second status data includes information indicating the second status data in the header.
Here, the first status data is data indicating that the first image processing circuit 12 has output the intermediate data to the FIFO memory 16, and the second status data is printed by the second image processing circuit 13. This data indicates that the data has already been output to the FIFO memory 16.

<First Embodiment>
The CPU interrupt processing circuit according to the first embodiment will be described with reference to FIG.
The CPU interrupt processing circuit 11 includes a request processing unit 501 that outputs a CPU interrupt signal and a write DMA control unit 502 that outputs status data. The write DMA control unit 502 is connected to the FIFO memory 16 via the data transfer bus 18 so that data can be transmitted and received. The request processing unit 501 is connected to the CPU 20 via the signal line Ls, and is connected to the first image processing circuit 12 via the signal line L1 and to the second image processing circuit 13 via the signal line L2. Connected.

When the request processing unit 501 acquires a DMA completion interrupt signal from the first image processing circuit 12 via the signal line L1, the request processing unit 501 outputs a first request to the write DMA control unit 502. The write DMA control unit 502 that has acquired the first request generates first status data. Then, the write DMA control unit 502 outputs the first status data to the FIFO memory 16 via the data transfer bus 18.
After outputting the first status data, the write DMA control unit 502 outputs an output completion signal indicating that the first status data has been output to the request processing unit 501. Upon obtaining the output completion signal, the request processing unit 501 generates a CPU interrupt signal and outputs it to the CPU 20 via the signal line Ls.

Similarly, when receiving a DMA completion interrupt signal from the second image processing circuit 13 via the signal line L2, the request processing unit 501 outputs a second request to the write DMA control unit 502. The write DMA control unit 502 that has acquired the second request generates second status data. Then, the write DMA control unit 502 outputs the second status data to the FIFO memory 16 via the data transfer bus 18.
After outputting the second status data, the write DMA control unit 502 outputs an output completion signal indicating that the first status data has been output to the request processing unit 501. Upon obtaining the output completion signal, the request processing unit 501 generates a CPU interrupt signal and outputs it to the CPU 20 via the signal line Ls.
This is the end of the description of the CPU interrupt processing circuit according to the first embodiment.

Returning again to FIG.
(Print data output circuit 15)
The print data output circuit 15 is controlled by a control unit (not shown) to realize a function of transmitting print data to the image forming unit 4. This control unit (not shown) may be the control unit 201 of the CPU 20.
The print data output circuit 15 acquires the print data stored in the memory 70 via the FIFO memory 16. Then, a print data acquisition message is output to the message processing circuit 14 via the data transfer bus 18. Thereafter, the print data output circuit 15 transmits the print data to the image forming unit 4 via the print data bus 41 when receiving the timing signal from the mechanism control ASIC 3 via the signal line Lm.

(Message processing circuit 14)
The message processing circuit 14 is controlled by a control unit (not shown) to realize a function of outputting a sheet conveyance start message to the mechanism control ASIC 3. This control unit (not shown) may be the control unit 201 of the CPU 20.
The message processing circuit 14 acquires a print data acquisition message from the print data output circuit 15 and generates a paper conveyance start message. Then, the message processing circuit 14 outputs a sheet conveyance start message to the mechanism control ASIC 3 via the message bus 31.

<Overview of operation>
Processing operations performed by the image processing apparatus 1 having the above configuration will be described.
The image processing ASIC 10 is controlled by the CPU 20 (control unit 201) to start processing for converting image data for one page included in the print job into print data.
The image processing ASIC 10 that has acquired one page of image data from the memory 70 performs predetermined image processing on the acquired image data, and the DMA function unit 202 of the CPU 20 stores the data after image processing in the memory 70. The above series of operations is repeated as many times as necessary for converting image data into print data.
When the image processing ASIC 10 converts the image data for one page into print data, the image processing ASIC 10 outputs a paper conveyance start message to the mechanism control ASIC 3 and sends the print data to the image forming unit in accordance with the timing signal from the mechanism control ASIC 3. 4 through the print data bus 41. The above series of operations is repeated as many times as the number of pages designated as a print job.

<Operation>
The intermediate data reading operation of the image processing apparatus according to the first embodiment will be described with reference to FIG. In FIG. 3, time elapses from the top to the bottom of the page.
First, the first image processing circuit 12 outputs the intermediate data to the FIFO memory 16 in order to store the intermediate data in the memory 70 (step S101a). As a result, the intermediate data is accumulated at the head of the FIFO memory 16.
Next, the first image processing circuit 12 generates a DMA completion signal and transmits it to the CPU interrupt processing circuit 11 via the signal line L1 (step S102). Thereby, the CPU interrupt processing circuit 11 receives the DMA completion signal.

  Upon receiving the DMA completion signal, the CPU interrupt processing circuit 11 generates first status data, and outputs the first status data to the FIFO memory 16 (step S103a). As a result, the first status data is accumulated in the FIFO memory 16 after the intermediate data.

  Next, the CPU interrupt processing circuit 11 generates a CPU interrupt signal and outputs it to the CPU 20 via the signal line Ls (step S104). The CPU 20 receives this CPU interrupt signal via the signal line IF21, and the CPU 20 (control unit 201) activates a predetermined monitoring program and executes the monitoring process of the memory 70 (step S105a). In this monitoring process, the storage area of the memory 70 is read to determine whether or not the first status data is stored. Here, the CPU 20 (the control unit 201) executes the monitoring process at a predetermined timing until it is confirmed that the first status data is stored in the memory 70.

The DMA function unit 202 of the CPU 20 acquires the intermediate data accumulated at the head of the FIFO memory 16 and outputs the intermediate data to the memory 70 (step S101b). Thus, intermediate data is stored in the memory 70 without reducing the processing capability of the CPU 20 (control unit 201). Here, the hatched lines in FIG. 3 indicate that the intermediate data starts to be stored in the memory 70 at time t ₁ and all of the intermediate data is stored at time t ₂ . At this time, the first status data stored next to the intermediate data is located at the head of the FIFO memory 16.

After step S101b, the DMA function unit 202 of the CPU 20 acquires the first status data accumulated at the head of the FIFO memory 16, and outputs the first status data to the memory 70 (step S103b). Thus, the first status data is stored in the memory 70 without reducing the processing capability of the CPU 20 (control unit 201). The first status data is stored in the memory 70 at time t _2.

Thereafter (after time t ₂ ), the CPU 20 (control unit 201) checks whether or not the first status data is stored in the memory 70 at the timing of executing the next monitoring process (step S105b). If the first status data is stored in the memory 70, the CPU 20 (control unit 201) prompts the DMA function unit 202 to acquire intermediate data (step S106). Then, the DMA function unit 202 of the CPU 20 acquires the intermediate data from the memory 70 and outputs it to the FIFO memory 16 (step S107). Then, the CPU 20 (control unit 201) deletes the first status data stored in the memory 70 (step S108).
Thereafter, the second image processing circuit 13 acquires intermediate data via the FIFO memory 16 and executes a predetermined program to convert the intermediate data into print data.

Since the process shown below is the same process as step S101a-step S108, it demonstrates easily.
The second image processing circuit 13 outputs the print data to the FIFO memory 16 in order to store the print data in the memory 70 (see step S101a). Next, the second image processing circuit 13 transmits a DMA completion signal to the CPU interrupt processing circuit 11 (see step S102). The CPU interrupt processing circuit 11 that has received the DMA completion signal generates second status data, and outputs the second status data to the FIFO memory 16 (see step S103a). As a result, the second status data is accumulated in the FIFO memory 16 after the print data.
Next, the CPU interrupt processing circuit 11 generates a CPU interrupt signal and outputs it to the CPU 20 (see step S104). Receiving the CPU interrupt signal, the CPU 20 (control unit 201) activates a predetermined monitoring program and executes the monitoring process of the memory 70 (see step S105a).

  The DMA function unit 202 of the CPU 20 acquires the print data accumulated at the head of the FIFO memory 16 and outputs the print data to the memory 70 (see step S101b). Further, the DMA function unit 202 of the CPU 20 acquires the second status data accumulated at the head of the FIFO memory 16, and outputs the second status data to the memory 70 (see step S103b).

  The CPU 20 (control unit 201) executes a monitoring process at a predetermined timing and checks whether or not the second status data is stored in the memory 70 (see step S105b). If the second status data is stored in the memory 70, the CPU 20 (control unit 201) prompts the DMA function unit 202 to acquire intermediate data (see step S106). The DMA function unit 202 of the CPU 20 acquires print data from the memory 70 and outputs the print data to the FIFO memory 16 (see step S107). Then, the CPU 20 (control unit 201) deletes the second status data stored in the memory 70 (see step S108).

  Thereafter, the print data output circuit 15 acquires the print data via the FIFO memory 16, executes a predetermined program, and outputs the print data to the image forming unit 4 when receiving a timing signal from the mechanism control ASIC 3. To do.

<Second Embodiment>
A CPU interrupt processing circuit according to the second embodiment will be described with reference to FIG.
As shown in FIG. 4, the image processing apparatus 1A according to the second embodiment replaces the CPU interrupt processing circuit 11 (FIG. 2) of the image processing apparatus 1 according to the first embodiment. The point provided with the circuit 11A, the point provided with the FIFO memory 16A instead of the FIFO memory 16 (FIG. 2), and the point provided with the PCIE connection processing circuit 17A instead of the PCIE connection processing circuit 17 (FIG. 2) Is different. Since other configurations are the same, the description is omitted for convenience.

  The CPU interrupt processing circuit 11A includes a request processing unit 601 that outputs a CPU interrupt signal, a write DMA control unit 602 that outputs status data, and a read DMA control unit 603 that makes a read transfer request to the FIFO memory 16A. . The write DMA control unit 602 and the read DMA control unit 603 are connected to the FIFO memory 16A via the data transfer bus 18 so that data can be transmitted and received. The request processing unit 501 is connected to the CPU 20 via the signal line Ls, and is connected to the first image processing circuit 12 via the signal line L1 and to the second image processing circuit 13 via the signal line L2. Connected.

  The image processing apparatus 1A according to the second embodiment includes a read DMA control unit 603 in the CPU interrupt processing circuit 11A, and monitoring performed by the CPU 20 (control unit 201) of the image processing apparatus 1A according to the first embodiment. The read DMA control unit 603 performs the process (step S105a in FIG. 3).

(Request processing unit 601)
When the request processing unit 601 acquires a DMA completion interrupt signal from the first image processing circuit 12 through the signal line L1, the request processing unit 601 outputs a first request to the write DMA control unit 602.
Upon obtaining the output completion signal from the write DMA control unit 602, the request processing unit 601 outputs a first collection request to the read DMA control unit 603.
Upon obtaining the output completion signal from the read DMA control unit 603, the request processing unit 601 generates a CPU interrupt signal and outputs it to the CPU 20 via the signal line Ls.

(Write DMA control unit 602)
The write DMA control unit 602 generates first status data when the first request is acquired from the request processing unit 601. Then, the write DMA control unit 602 outputs the first status data to the FIFO memory 16A via the data transfer bus 18. After outputting the first status data, the write DMA control unit 602 outputs an output completion signal indicating that the first status data has been output to the request processing unit 601. The write DMA control unit 602 also outputs the output first status data to the read DMA control unit 603.

(Read DMA control unit 603)
When the read DMA control unit 603 obtains the first collection request from the request processing unit 601, the read DMA control unit 603 sends a transfer request (read transfer request) of the data stored in the memory 70 to the FIFO memory 16A as a DMA controller and the PCIE. The connection processing circuit 17A performs the processing.
The read DMA control unit 603 compares the data acquired from the FIFO memory 16A with the status data output from the write DMA control unit 602. If the data acquired from the FIFO memory 16A matches the status data, an output completion signal is output to the request processing unit 601. On the other hand, if they do not match, the read DMA control unit 603 makes a read transfer request to the FIFO memory 16A and the PCIE connection processing circuit 17A again.

  By performing the processing as described above, the read DMA control unit 603 compares the data transferred from the memory 70 in response to the read transfer request with the first status data output from the write DMA control unit 602 to the FIFO memory 16A. . As described above, the read DMA control unit 603 performs the monitoring process (step S105a in FIG. 3) performed by the CPU 20 (control unit 201) of the image processing apparatus 1A according to the first embodiment.

(FIFO memory 16A)
The FIFO memory 16A has the same function as the FIFO memory 16 (see FIG. 2) provided in the image processing apparatus 1 according to the first embodiment.
Furthermore, the FIFO memory 16A outputs all the data accumulated therein, and after the data becomes empty (that is, after the accumulated first status data is output), the read from the read DMA control unit 603 Accepts a read transfer request and executes processing. First, the FIFO memory 16A switches the switch set to output the data input via the data transfer bus 18 to the PCIE connection processing circuit 17A, and converts the data input from the PCIE connection processing circuit 17A to the data The output is set to the transfer bus 18 side. As a result, the FIFO memory 16A outputs the data acquired from the PCIE connection processing circuit 17A to the data transfer bus 18.

(PCIE connection processing circuit 17A)
The PCIE connection processing circuit 17A, which is a DMA controller, has the same function as the PCIE connection processing circuit 17 (see FIG. 2) provided in the image processing apparatus 1 according to the first embodiment.
Further, the PCIE connection processing circuit 17A, after no data is output from the FIFO memory 16A (after all the data accumulated in the FIFO memory 16A is output), the DMA function unit 202 of the CPU 20 (control unit 201). Starts acquiring data from the memory 70. The destination of the acquired data is set to the read DMA control unit 603 and output to the FIFO memory 16A.

By providing this configuration, the image processing apparatus 1A according to the second embodiment can obtain the following effects as compared to the image processing apparatus 1 according to the first embodiment.
The CPU 20 (control unit 201) included in the image processing apparatus 1 according to the first embodiment periodically reads data in the memory 70 after receiving the CPU interrupt signal. In other words, it may be read more than once.
In contrast, the CPU 20 (control unit 201) included in the image processing apparatus 1A according to the second embodiment ensures that status data is reliably received by the request processing unit 601, the write DMA control unit 602, and the read DMA control unit 603. Since the memory 70 is read after being stored, this reading process may be performed only once.
Therefore, the image processing apparatus 1A according to the second embodiment can further reduce the processing performed by the CPU 20 (control unit 201) than the image processing apparatus 1 according to the first embodiment.

<Operation>
The intermediate data reading operation of the image processing apparatus according to the second embodiment will be described with reference to FIG. In FIG. 5, time elapses from the top to the bottom of the page.
First, the first image processing circuit 12 outputs the intermediate data to the FIFO memory 16A in order to store the intermediate data in the memory 70 (step S201a). As a result, the intermediate data is accumulated at the head of the FIFO memory 16A.
Next, the first image processing circuit 12 generates a DMA completion signal and transmits it to the CPU interrupt processing circuit 11A via the signal line L1 (step S202). Thereby, the CPU interrupt processing circuit 11A receives the DMA completion signal.

  Upon receiving the DMA completion signal, the CPU interrupt processing circuit 11A generates first status data, and outputs the first status data to the FIFO memory 16A (step S203a). Thus, the first status data is accumulated after the intermediate data in the FIFO memory 16A. The steps so far are the same as steps S101a, S102, and S103a of FIG. 3 in the image processing apparatus 1 according to the first embodiment.

  Next, the CPU interrupt processing circuit 11A issues a read transfer request to the PCIE connection processing circuit 17A and the FIFO memory 16A, which are DMA controllers (step S204a). Thus, the PCIE connection processing circuit 17A and the FIFO memory 16A wait until all the data stored in the FIFO memory 16A is output and becomes empty. That is, after the intermediate data and the first status data accumulated therein are output by the DMA function unit 202 of the CPU 20 (control unit 201), the PCIE connection processing circuit 17A and the FIFO memory 16A perform processing corresponding to the read transfer request. Execute.

Thereafter, processing is performed in the same manner as in step S101b described in the image processing apparatus 1 according to the first embodiment, and intermediate data is stored in the memory 70 (step S201b). Further, the first status data is processed in the same manner as in step S103b, and the first status data is stored in the memory 70 (step S203b).
After the first status data is acquired from the FIFO memory 16A by the DMA function unit 202 of the CPU 20 (control unit 201) (step S203b), the data is not accumulated in the FIFO memory 16A (when empty). The PCIE connection processing circuit 17A and the FIFO memory 16A, which are DMA controllers, execute processing corresponding to the read transfer request requested from the CPU interrupt processing circuit 11A in step S204a, and the DMA function unit 202 receives data from the memory 70. It is acquired and output to the FIFO memory 16A (step S205a). By this process, the FIFO memory 16A is changed to a setting for outputting data input from the PCIE connection processing circuit 17A to the data transfer bus 18 side.
As a result, the DMA function unit 202 acquires the read data from the memory 70 and outputs it to the FIFO memory 16A. Then, the CPU interrupt processing circuit 11A can acquire read data from the FIFO memory 16A (step S205b).

The CPU interrupt processing circuit 11A compares the acquired read data with the first status data output in step S204a (step S206).
Here, when the read data and the first status data match (step S206, Yes), the CPU interrupt processing circuit 11A generates a CPU interrupt signal and outputs it to the CPU 20 via the signal line Ls ( Step S207).

  On the other hand, if they do not match (No at Step S206), the CPU interrupt processing circuit 11A performs the process at Step S204a again and outputs a read transfer request to the FIFO memory 16A. The process in step S206 is repeated until the read data acquired in step S205b matches the first status data output in step S204a.

  After the processing of step S207, the CPU 20 receives this CPU interrupt signal via the signal line IF21, and the CPU 20 (control unit 201) activates a predetermined program and executes the monitoring processing of the memory 70 (step). S208). Thereby, CPU20 (control part 201) reads the storage area of the memory 70, and determines whether 1st status data was memorize | stored.

The CPU 20 (control unit 201) prompts the DMA function unit 202 to acquire intermediate data (step S209). Then, the DMA function unit 202 of the CPU 20 acquires the intermediate data from the memory 70 and outputs it to the FIFO memory 16A (step S210). Then, the CPU 20 (control unit 201) deletes the first status data stored in the memory 70 (step S211).
Thereafter, the second image processing circuit 13 acquires intermediate data via the FIFO memory 16A, and executes a predetermined program to convert the intermediate data into print data. Thereafter, as the print data reading operation, processing similar to that in steps S201 to S211 is performed, and thus description thereof is omitted.

(Comparison with conventional technology)
Next, with reference to FIG. 6, it compares with a prior art.
The DMA control circuit 1004 included in the burst data transfer processing device (information processing device) described in Patent Document 1 transfers the read data (transfer data Sig 104a) to the FIFO memory 1005 (step S1001a), and after the data transfer is completed. The data transfer end signal Sig104b is output (step S1002). When the memory area becomes empty, the FIFO memory 1005 outputs a memory empty signal Sig105 (step S1003). Then, the interrupt signal generation circuit 1006 receives the data transfer end signal Sig104b from the DMA control circuit 1004 (ON) and receives the memory empty signal Sig105 of the FIFO memory 1005 (ON). Is supplied to the processor 1002 (step S1004). As a result, the processor 1002 can recognize that the data transfer has ended.

Here, in the information processing apparatus described in Patent Document 1, although the CPU (processor 1002) has received the interrupt signal Sig106, it is still transferred to the memory 1003 due to the influence of the size of the transferred data and the communication environment. In some cases, all of the data is not stored (in FIG. 6, t ₁ indicates the start of storage, t ₂ indicates the end of storage, and all of the transfer data Sig 104 a is stored at t ₂ ). At this time, since the CPU recognizes that the data transfer is completed by receiving the interrupt signal Sig106, the CPU acquires data (transferred data) from the memory 1003 (step S1005). As described above, according to the information processing apparatus described in Patent Document 1, there is a problem in that the CPU acquires invalid data for which a part of the data is insufficient (step S1006).

  According to the image processing apparatus 1 according to the first embodiment of the present invention and the image processing apparatus 1A according to the second embodiment, the CPU 20 transfers the transfer data (intermediate data, print data) via the FIFO memory 16 (16A). It is confirmed whether or not the status data (first status data, second status data) stored in the memory 70 after the data) is stored in the memory 70 (steps S105a and S105b, FIG. 3). That is, even if not all of the status data is stored in the memory 70, if a part of the status data is stored in the memory 70, all of the transfer data is already stored in the memory 70. . Therefore, the CPU 20 does not acquire invalid data from the memory 70.

  The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the gist of the present invention.

  In the first embodiment and the second embodiment, as an example in which the image forming apparatus 100 is built in a network printer, the CPU 20 acquires image data via the communication connection unit 5 connected to the network N. Here, the image forming apparatus 100 includes an image data generation unit that has a scanner function and reads one side of a document placed at a predetermined position to generate image data. The CPU 20 includes the image data generation unit. You may acquire image data from.

In the first embodiment and the second embodiment, when the CPU 20 performs the monitoring process of the memory 70 and the first status data is stored in the memory 70, the CPU 20 stores the intermediate data in the DMA function unit 202. (Step S106 in FIG. 3, step S209 in FIG. 5). Then, the DMA function unit 202 of the CPU 20 acquires intermediate data (or print data) from the memory 70.
If the first status data is stored in the memory 70 in the process of step S105b, the CPU 20 (control unit 201) performs a predetermined process on the intermediate data before performing the process of step S106. May be. This predetermined processing is performed by, for example, adding data or changing data in order to improve the processing speed when the second image processing circuit 13 that is the transmission destination of the intermediate data converts the intermediate data into print data. (Processing).
The data transferred from the transfer source information processing circuit to the transfer destination information processing circuit may not be intermediate data or print data. For example, numerical data when the first image processing circuit 12 (FIG. 1) performs image processing may be transferred. In addition, the CPU 20 (control unit 201) may output numerical data necessary for executing predetermined processing from the information processing circuit of the transfer source. As a result, the CPU 20 (control unit 201) acquires numerical data from the memory 70, and in the program executed by the CPU 20 (control unit 201), the processing of the next step is executed using the numerical data. Also good.

DESCRIPTION OF SYMBOLS 1,1A Image processing apparatus 2 Mechanism part 2a Motor 2b Sensor 3 Mechanism control ASIC
4 Image forming unit 5 Communication connecting unit 10 Image processing ASIC
11, 11A CPU interrupt processing circuit 12 First image processing circuit 13 Second image processing circuit 14 Message processing circuit 15 Print data output circuit 16, 16A FIFO memory 17, 17A PCIE connection processing circuit 18 Data transfer bus 19 PCIE bus 20 CPU
21 Signal line IF
22 Memory IF
23 PCIE bus bridge 31 Message bus 41 Print data bus 70 Memory 71 Memory bus 100 Image forming apparatus 201 Control unit 202 DMA function unit 501, 601 Request processing unit 502, 602 Write DMA control unit 601 Request processing unit L1, L2, Ls, Lm, Lp Signal line N Network

Claims (5)

An information processing apparatus that temporarily stores the information processing data in a memory via a FIFO processing unit that outputs the data in the order of acquisition when the information processing data is transferred from the transfer source information processing circuit to the transfer destination information processing circuit,
An interrupt processing unit that outputs status data to the FIFO processing unit and generates an interrupt signal after the information processing data output by the transfer source information processing circuit reaches the FIFO processing unit;
A DMA function unit for performing DMA transfer of data between the FIFO processing unit and the memory;
After receiving the interrupt signal, it is determined whether or not the status data is stored in the memory. When the status data is stored, the DMA function unit transmits the memory to the FIFO processing unit. An information processing apparatus comprising: a control unit that DMA-transfers information processing data.   The interrupt processing unit, after outputting the status data to the FIFO processing unit, reads read transfer request data for causing the DMA function unit to transfer the status data stored in the memory to the FIFO processing unit. The read data output to the FIFO processing unit, and then the read data transferred to the FIFO processing unit and the status data output to the FIFO processing unit are compared. The information processing apparatus according to claim 1, wherein a signal is output.   2. The control unit deletes the status data stored in the memory after causing the DMA function unit to DMA transfer the information processing data from the memory to the FIFO processing unit. Alternatively, an information processing apparatus according to claim 2.   The said control part processes the information processing data memorize | stored in the said memory, when the said status data is memorize | stored in the said memory, The Claim 1 thru | or 3 characterized by the above-mentioned. The information processing apparatus described. An information processing apparatus according to any one of claims 1 to 4,
An image forming apparatus comprising: an image forming unit that forms an image on a medium based on the information processing data.

Images