JP2012216868A - Package for electronic component and electronic component device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package which obtains sufficient coplanarity of a through electrode even through a cavity is provided in the package for an electronic component where the through electrode is provided.SOLUTION: A package for an electronic component includes: a package substrate part 11 including a first silicon substrate 10a provided with through holes TH, insulation layers 14 formed on upper and lower surfaces of the first silicon substrate 10a and inner surfaces of the through holes TH; and through electrodes 18 filling the through holes TH and in which an upper surface of each through electrode 18 and an upper surface of the insulation layer 14 are flush; and a frame part 23 which is formed by a second silicon substrate 20a including openings TP, penetrating from an upper surface to a lower surface, in the center part thereof, is laminated on a peripheral part of the package substrate part 11 through the insulation layer 14, and forms a cavity C on the first silicon substrate 10a. Each through electrode 18 is disposed in the opening TP of the frame part 23.

Description

  The present invention relates to an electronic component package and an electronic component device, and more particularly to an electronic component package and an electronic component device on which electronic components such as a MEMS element and an optical semiconductor element are mounted.

  2. Description of the Related Art Conventionally, there are electronic component packages on which electronic components such as MEMS elements and optical semiconductor elements are mounted. As such an electronic component package, there is a structure in which a cavity in which an electronic component is mounted is provided in the center of a silicon substrate, and a through electrode is provided in a silicon substrate below the cavity.

  As an example of a method for manufacturing such a package for electronic components, as shown in FIG. 1A, first, a first mask provided with an opening 200x for forming a through hole on a silicon wafer 100 is provided. Layer 200 is formed.

  Next, as shown in FIG. 1B, the through hole TH is formed by etching the silicon wafer 100 from the upper surface to the lower surface using the first mask layer 200 as a mask. Thereafter, the first mask layer 200 is removed.

  Subsequently, as shown in FIG. 1C, a second mask layer 300 provided with an opening 300 x for forming a cavity is formed on the silicon wafer 100. Further, as shown in FIG. 1D, the cavity C is formed by etching the silicon wafer 100 halfway through the thickness using the second mask layer 300 as a mask.

  Thereafter, the second mask layer 300 is removed. A plurality of package regions are defined in the silicon wafer 100, and through holes TH and cavities C are provided in each package region.

  Next, as shown in FIG. 2A, the silicon wafer 100 is thermally oxidized to form an insulating layer 400 made of a silicon oxide layer on the entire surface of the silicon wafer 100. Subsequently, as shown in FIG. 2B, a through electrode 500 is formed in the through hole TH of the silicon wafer 100 by plating.

  At this time, the through electrode 500 is formed so as to protrude from the upper surface and the lower surface of the silicon wafer 100. Thereafter, as shown in FIG. 2C, the silicon wafer 100 is cut to obtain individual electronic component packages.

  As an electronic component package using silicon as a substrate, Patent Document 1 discloses that a metal is filled in a through hole of a silicon substrate, both surfaces of the silicon substrate are polished and smoothed, and then the silicon substrate is subjected to high pressure annealing. It is described that the density and adhesion of the plug metal are improved by applying.

  In Patent Document 2, an insulating layer made of a relatively soft polymer such as polyimide is formed on both surfaces of a silicon substrate, and a wiring layer is further formed thereon, and an IC chip made of the same material as the silicon substrate is used as the wiring layer. It is described that the stress applied to the connecting portion is reduced by CCB connection.

JP 2004-22990 A JP-A-6-169031

  In the above-described conventional electronic component package, the through electrode 500 filled in the through hole TH is formed so as to protrude from the bottom of the cavity C, and further, the height thereof varies depending on the characteristics of plating. Accordingly, the coplanarity (flatness) of the through electrode 500 on which the electronic component is mounted is not sufficient, and connection failure may occur when a high-performance electronic component is mounted, which causes a decrease in yield.

  Therefore, a method for improving the coplanarity by flattening the through electrode 500 can be considered. However, since the through electrode 500 is formed after forming the cavity C, the silicon wafer 100 has irregularities due to the cavity C, so it is difficult to planarize the through electrode 500 in the cavity C by CMP or the like. . In addition, for the same reason, it is extremely difficult to form a fine wiring layer connected to the through electrode 500 on the bottom surface of the cavity C.

  In addition, there is a demand for incorporating various elements in a silicon substrate in a package for an electronic component that uses a silicon substrate, and it cannot be said that a method for manufacturing such a package has been sufficiently established.

  The present invention was created in view of the above problems, and in a package for an electronic component having a structure in which a through electrode is provided on a silicon substrate, sufficient coplanarity (flatness) of the through electrode is provided even if a cavity is provided. Another object of the present invention is to provide an electronic component package and an electronic component device which can be easily obtained even when various elements are incorporated.

  In order to solve the above problems, the present invention relates to an electronic component package, and includes a first silicon substrate provided with a through hole, and an insulating layer formed on the upper and lower surfaces of the first silicon substrate and the inner surface of the through hole. A package substrate portion including a through electrode filled in the through hole, the upper surface of the through electrode being flush with the upper surface of the insulating layer, and an opening penetrating from the upper surface to the lower surface in the central portion. A frame part that forms a cavity on the first silicon substrate, and is formed on a peripheral edge of the package substrate part via the insulating layer. It arrange | positions in the opening part of the said frame part, It is characterized by the above-mentioned.

  In the electronic component package of the present invention, a through electrode is formed on a silicon substrate via an insulating layer, and then the through electrode is planarized to obtain a package substrate portion. Thereafter, a frame part (silicon) is provided on the peripheral edge of the package substrate part to form a cavity.

  In the present invention, since the frame portion is provided after the through electrode is formed on the flat silicon substrate without the cavity, the through electrode can be flattened unlike the prior art. Accordingly, a flattened through electrode is disposed on the silicon substrate in the cavity. Further, the frame portion can be bonded to the package substrate portion by low-temperature bonding that does not damage the through electrode by using the plasma treatment.

  As a result, a package for an electronic component having a structure in which a cavity is provided on the package substrate portion by the frame portion and a through electrode having good coplanarity (flatness) is provided on the package substrate portion in the cavity is obtained.

  In a preferred aspect of the present invention, the frame part includes a silicon part, an element formed on the lower surface of the silicon part, and a connection electrode formed on the lower side of the element and connected to the element. Are connected to the through electrodes of the package substrate portion.

  Thereby, the electronic component connected to the through electrode in the cavity is electrically connected to the element formed in the frame portion through the through electrode or the like. For example, when the electronic component is an LED, a Zener diode is formed as an element. Then, the LED in the cavity is embedded in the phosphor or hermetically sealed by a cap member to constitute an electronic component device.

  As described above, in the electronic component package of the present invention, sufficient coplanarity (flatness) of the through electrode can be obtained even if the cavity is provided, and it can be easily handled even when various elements are incorporated. be able to.

1A to 1D are cross-sectional views (No. 1) showing a method for manufacturing a package for an electronic component according to the prior art. FIGS. 2A to 2C are sectional views (No. 2) showing a method for manufacturing a package for electronic components according to the prior art. 3A to 3E are cross-sectional views (No. 1) showing the method for manufacturing the electronic component package according to the first embodiment of the present invention. 4A and 4B are sectional views (No. 2) showing the method for manufacturing the electronic component package according to the first embodiment of the present invention. 5A to 5D are sectional views (No. 3) showing the method for manufacturing the electronic component package according to the first embodiment of the invention. 6A and 6B are sectional views (No. 4) showing the method for manufacturing the electronic component package according to the first embodiment of the invention. FIG. 7 is a sectional view showing the electronic component package according to the first embodiment of the present invention. FIG. 8 is a sectional view showing an electronic component package according to a modification of the first embodiment of the present invention. FIG. 9 is a sectional view showing the first electronic component device according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view showing the second electronic component device according to the first embodiment of the present invention. FIG. 11 is a cross-sectional view showing a third electronic component device according to the first embodiment of the present invention. 12A to 12D are cross-sectional views (part 1) showing the method for manufacturing the electronic component package of the second embodiment of the present invention. 13A and 13B are sectional views (No. 2) showing the method for manufacturing the electronic component package of the second embodiment of the present invention. FIG. 14 is a sectional view showing an electronic component device according to the second embodiment of the present invention. FIG. 15 is a sectional view showing an electronic component device according to a modification of the second embodiment of the present invention. 16A to 16D are cross-sectional views (No. 1) showing the method for manufacturing the electronic component package according to the third embodiment of the invention. FIG. 17: is sectional drawing (the 2) which shows the manufacturing method of the package for electronic components of 3rd Embodiment of this invention. FIG. 18 is a cross-sectional view showing an electronic component device according to a third embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
3 to 6 are sectional views showing a method for manufacturing an electronic component package according to the first embodiment of the present invention, FIGS. 7 and 8 are sectional views showing the electronic component package, and FIGS. 9 to 11 are electronic components. It is sectional drawing which shows a component apparatus.

  In the method for manufacturing an electronic component package according to the first embodiment, first, as shown in FIG. 3A, a first silicon wafer 10 having a thickness of 600 to 800 μm is prepared as a silicon substrate. The first silicon wafer 10 is defined with one or more package regions for obtaining individual packages.

  Thereafter, as shown in FIG. 3B, a mask layer 12 provided with an opening 12x for forming a through hole is formed on the first silicon wafer 10. As the mask layer 12, the resist may be patterned as a single layer, or the resist is patterned on a hard mask layer such as a silicon oxide layer, and the mask layer 12 is etched by using the resist as a mask. It is good.

  Next, as shown in FIG. 3C, the first silicon wafer 10 is etched through the opening 12x using the mask layer 12 as a mask, thereby forming a through hole TH penetrating from the upper surface to the lower surface. The through hole TH is formed in each package region of the first silicon wafer 10. Thereafter, the mask layer 12 is removed.

  Subsequently, as shown in FIG. 3D, by thermally oxidizing the first silicon wafer 10, the thickness of the silicon oxide layer on both surfaces of the first silicon wafer 10 and the inner surface of the through hole TH is about 500 nm. An insulating layer 14 is formed. The insulating layer 14 may be formed by forming a silicon oxide layer on the entire surface of the first silicon wafer 10 by the CVD method.

  Next, as shown in FIG. 3E, the first silicon wafer 10 is disposed on the plating power supply member 16 such as a copper foil via the adhesive layer 15. The adhesive layer 15 has an opening at a portion corresponding to the through hole TH of the first silicon wafer 10.

  Further, the through electrode 18 is formed by filling a metal (such as copper) from the bottom to the top of the through hole TH by electrolytic plating using the plating power supply member 16 as a plating power supply path. Thereafter, the plating power supply member 16 and the adhesive layer 15 are removed from the first silicon wafer 10.

  At this time, it is difficult to control the upper surface of the through electrode 18 to be flush with the upper surface side of the first silicon wafer 10 due to the characteristics of electrolytic plating. It is formed in a state where the protruding portion P protrudes from the insulating layer 14. In addition, the protrusions P of the through electrodes 18 are formed with variations in height due to in-plane variations in electrolytic plating. Similarly, on the lower surface side of the first silicon wafer 10, the through electrode 18 is formed in a state where the protruding portion P protrudes downward.

  Next, as shown in FIG. 4A, the protrusions P of the through electrodes 18 on both sides of the first silicon wafer 10 are polished by CMP (Chemical Mechanical Polishing) or the like. As a result, as shown in FIG. 4B, the upper surface of the through electrode 18 is flattened so as to be equal to the height of the insulating layer 14 on both sides of the first silicon wafer 10. That is, the upper surface and the lower surface of the through electrode 18 are flattened so as to be flush with the surfaces of the insulating layer 14 on both sides. The upper surface of the through electrode 18 serves as a connection portion 18a to which an electronic component is connected.

  As described above, as shown in the plan view of FIG. 4B, in the case where multiple surfaces are taken from the first silicon wafer 10, a plurality of package regions R are provided in the first silicon wafer 10, and the through electrode 18 is provided in each region. Are formed respectively.

  In the present embodiment, since the through electrode 18 is formed in the first silicon wafer 10 which is flat over the entire area where no cavity is provided, the through electrode 18 can be easily flattened unlike the conventional technique. Thereby, the coplanarity (flatness) of the connecting portion 18a of the through electrode 18 is improved, and the electronic component can be mounted with high reliability.

  Next, a method for providing a cavity on each package region R of the first silicon wafer 10 will be described. As shown in FIG. 5A, first, a second silicon wafer 20 similar to the first silicon wafer 10 is prepared. Next, as shown in FIG. 5B, the mask layer 12 having the opening 12 y provided in the portion corresponding to the central main portion of each package region R of the first silicon wafer 10 is formed on the second silicon wafer 20. Form.

  Further, as shown in FIG. 5C, the second silicon wafer 20 is etched from the upper surface to the lower surface through the opening 12y using the mask layer 12 as a mask to form a through portion TP. Thereby, the lattice-like frame part 22 which consists of the silicon | silicone part 20a mutually connected with the 2nd silicon wafer 20 is formed. Thereafter, the mask layer 12 is removed.

  Next, as shown in FIG. 5D, the second silicon wafer 20 is thermally oxidized to form the insulating layer 14 made of a silicon oxide layer on both surfaces of the second silicon wafer 20 and the inner surface of the through portion TP. Thereby, the lattice-like frame part 22 is comprised from the silicon | silicone part 20a and the insulating layer 14 which coat | covers it. Note that the lattice-like frame portion 22 may be formed only of the silicon portion 20a by omitting the insulating layer 14.

As shown in the plan view of FIG. 5D, the lattice-like frame portion 22 provided on the second silicon wafer 20 is a boundary portion of each package region R of the first silicon wafer 10 (the plane of FIG. 4B). The figure is formed so as to correspond to each. In this way, the second silicon wafer 20 is processed into a frame member.

  Next, as shown in FIG. 6A, a grid frame portion 22 is provided on the first silicon wafer 10 in which the through electrodes 18 are provided in each package region R of FIG. 4B described above. The second silicon wafer 20 is bonded. More specifically, first, ultrasonic waves are applied for 5 minutes while the first and second silicon wafers 10 and 20 are immersed in ozone water (ozone concentration: 8 ppm).

  Further, ultrasonic waves are applied for 5 minutes while the first and second silicon wafers 10 and 20 are immersed in water. Thereafter, the first and second silicon wafers 10 and 20 are dried by a spin dryer. As a result, organic substances attached to the surfaces of the first and second silicon wafers 10 and 20 are removed and cleaned.

Next, a first plasma process using oxygen (O ₂ ) gas is performed on the bonding surfaces of the first and second silicon wafers 10 and 20. As an example of the conditions of the first plasma treatment, conditions of pressure: 55 Pa, high frequency power (13.56 MHz): 70 W, and treatment time: 30 seconds are employed.

Subsequently, a second plasma process using nitrogen (N ₂ ) gas is performed on each bonding surface of the first and second silicon wafers 10 and 20. As an example of conditions for the second plasma treatment, conditions of pressure: 20 Pa, high-frequency power (13.56 MHz): 270 W, and treatment time: 15 seconds are employed.

  Thereby, each joint surface of the 1st, 2nd silicon wafers 10 and 20 becomes hydrophilic, and it will be in the surface state suitable for joining.

  Next, the second silicon wafer 20 is aligned on the first silicon wafer 10 so that the lattice-like frame portion 22 of the second silicon wafer 20 corresponds to the boundary portion of each package region R of the first silicon wafer 10. Arrange. (Refer to the plan views of FIGS. 4B and 5D).

  Further, the first and second silicon wafers 10 and 20 stacked are pressure-bonded by applying a pressure of 100 N / wafer for 5 seconds. Thereafter, the first and second silicon wafers 10 and 20 are heat-treated in an atmosphere of temperature: 150 ° C. for 8 hours. As a result, as shown in FIG. 6B, the lattice-like frame portion 22 of the second silicon wafer 20 is bonded onto the first silicon wafer 10.

  Since the through electrode 18 (copper) provided on the first silicon wafer 10 can sufficiently withstand heat treatment up to about 400 ° C., the heat treatment temperature can be arbitrarily set between 100 ° C. and 400 ° C. That is, by performing plasma treatment on the first and second silicon wafers 10 and 20, both can be bonded at a temperature lower than the heat resistance temperature of the through electrode 18.

  The lattice frame 22 of the second silicon wafer 20 is disposed at the boundary between the package regions R of the first silicon wafer 10, thereby providing the cavity C at the center of each package region R. In this way, the wafer-like package member 3 having a structure in which the lattice-like frame portions 22 are erected on the peripheral edge of each package region R of the first silicon wafer 10 is obtained.

  In the embodiment described above, the lattice frame 22 is formed from silicon, but any material that can be bonded to the first silicon wafer 10 by the bonding method described above can be used as the material of the lattice frame 2.

  In the present embodiment, the electronic component device may be configured by cutting the first and second silicon wafers 10 and 20 after mounting the electronic component in each package region R of the wafer-like package member 3, or Alternatively, after the first and second silicon wafers 10 and 20 are cut to obtain individual electronic component packages, the electronic components may be mounted to constitute an electronic component device.

  FIG. 7 shows the electronic component package 1 of the present embodiment obtained by cutting the package member 3 of FIG. As shown in FIG. 7, the first and second silicon wafers 10 and 20 are cut, whereby the first silicon wafer 10 becomes individual silicon substrates 10a, and the lattice-like frame portions 22 of the second silicon wafer 20 individually. The frame portion 23 becomes.

  As shown in FIG. 7, the electronic component package 1 according to the first embodiment is basically configured by a package substrate portion 11 and a frame portion 23 that stands and is joined to the peripheral portion thereof. In the package substrate portion 11, through holes TH are provided in the silicon substrate 10a, and an insulating layer 14 is formed on both sides of the silicon substrate 10a and on the inner surface of the through hole TH.

  A through electrode 18 is provided in the through hole TH, and the upper surface and the lower surface of the through electrode 18 are flattened at the same height as the surfaces of the insulating layer 14 on both sides of the silicon substrate 10a. .

  The frame portion 23 is configured by covering the upper and lower surfaces and the inner surface side of the silicon portion 20a with the insulating layer 14. The insulating layer 14 on the lower surface side of the frame portion 23 is bonded to the insulating layer 14 on the upper surface side of the package substrate portion 11. Thus, a cavity C is provided in the central main part on the package substrate part 11.

  As described above, in the method for manufacturing the electronic component package 1 according to the first embodiment, after the through electrode 18 is formed on the flat first silicon wafer 10 having no cavity through the insulating layer 14, the through electrode is formed. The 18 protrusions P are polished and flattened. Further, the cavity C is provided in each package region R of the first silicon wafer 10 by bonding the second silicon wafer 20 provided with the lattice frame 22 on the first silicon wafer 10.

  The bonding between the first silicon wafer 10 and the second silicon wafer 20 is achieved by cleaning each bonded surface, performing plasma processing, aligning and pressing, and heat-treating on the low temperature side (150 ° C.).

  Conventionally, a technique for bonding silicon wafers by thermocompression bonding at a considerably high temperature of about 1000 ° C. is known, but in the present embodiment, the first silicon wafer 10 is provided with a through electrode 18 (such as copper). The through electrode 18 cannot withstand such high temperature processing.

  The bonding method between the silicon wafers of the present embodiment has been devised in view of such a problem. Even if the first silicon wafer 10 is provided with the through electrode 18, the plasma treatment is used to form the through electrode 18. The second silicon wafer 20 can be bonded onto the first silicon wafer 10 by a low temperature treatment (for example, 150 ° C.) that does not cause damage.

  By adopting such a manufacturing method, the cavity C is provided on the package substrate portion 11 by the frame portion 23, and the through electrode 18 having good coplanarity (flatness) is formed on the package substrate portion 11 in the cavity C. The electronic component package 1 having the provided structure can be easily manufactured.

  8, the insulating layer 14 is omitted from the frame portion 23 of the electronic component package 1 in FIG. 7, and the frame portion 23 including only the silicon portion 20 a is provided. The cavity C may be configured by being bonded onto the package substrate portion 11.

  In the case of this embodiment, a similar bonding method is employed in which the second silicon wafer 20 provided with the lattice-like frame portion 22 composed only of the silicon portion 20a is formed on the first silicon wafer 10 in the step of FIG. Joined by.

  Next, an electronic component device configured using the electronic component package 1 of the present embodiment will be described. As shown in FIG. 9, in the first electronic component device 2 of the present embodiment, bumps 30a of LEDs (Light Emitting Diodes) 30 are connected to the connecting portions 18a of the through electrodes 18 in the cavity C of the electronic component package 1 of FIG. Are flip-chip connected, whereby the LED 30 is accommodated in the cavity C.

  Further, the phosphor 32 is filled in the cavity C, and the LED 30 is embedded in the phosphor 32. In addition, a solder ball or the like is mounted below the through electrode 18 and an external connection terminal 26 is provided.

  By mounting the LED 30 in the cavity C of the electronic component package 1, the phosphor 32 having a uniform film thickness can be easily formed on the upper surface (light emitting surface) side of the LED 30. The LED 30 emits blue or violet light, for example, and is emitted to the outside as white light by the action of the phosphor 32. In FIG. 9, a transparent cap member may be further provided on the phosphor 32.

  FIG. 10 shows the second electronic component device 2a of the first embodiment. As shown in FIG. 10, the bump 40a of the electronic component 40 is mounted on the connection portion 18a of the through electrode 18 in the cavity C of the electronic component package 1a (FIG. 8) of the above-described modification by flip chip connection. . As the electronic component 40, an optical semiconductor element such as an LED or a MEMS element such as an acceleration sensor is used.

  Further, a cap member 24 is joined on the frame portion 23 of the electronic component package 1a. The package substrate portion 11, the frame portion 23, and the cap member 24 constitute a housing portion S, and the electronic component 40 is housed in the housing portion S in an airtightly sealed state. In addition, a solder ball or the like is mounted below the through electrode 18 and an external connection terminal 26 is provided.

  FIG. 10 illustrates a form in which the electronic component 40 is made of an optical semiconductor element. The cap member 24 is formed of a transparent glass cap, and the glass cap is bonded to the frame portion 23 (silicon portion 20a) of the electronic component package 1a by anodic bonding. The optical semiconductor element emits light to the outside through the glass cap or receives light from the outside.

  7 is used, and the glass cap is anodically bonded to the frame portion 23 by partially removing the insulating layer 14 on the upper surface of the frame portion 23 to expose the silicon portion 20a. Is also possible.

  Alternatively, when the electronic component 40 is a MEMS element, the cap member 24 can be formed of an opaque material such as a silicon cap in addition to the glass cap. The silicon cap is bonded to the frame portion 23 of the electronic component package 1a by the bonding method using the plasma processing described above. When a silicon cap is used, the electronic component package 1 including the frame portion 23 whose surface shown in FIG. 7 is covered with the insulating layer 14 may be used.

  FIG. 11 shows the third electronic component device 2b of the first embodiment. As shown in FIG. 11, in the third electronic component device 2b, the frame portion 23 is omitted from the electronic component package 1 of FIG. The bump 40a of the electronic component 40 is mounted on the connecting portion 18a of the through electrode 18 of the package substrate portion 11 by flip chip connection.

  Further, the cap member 24 having a structure in which the cavity C (concave portion) is provided in the central portion and the protruding joint portion 24a is provided in the peripheral portion is formed on the package substrate portion 11 with the cavity C on the lower side. Is arranged. The tip end surface of the protruding joint portion 24 a of the cap member 24 is joined to the package substrate portion 11.

  A housing part S is constituted by the cavity C of the cap member 24, and the electronic component 40 is housed in the housing part S in an airtightly sealed state. FIG. 11 illustrates a form in which the electronic component 40 is made of an optical semiconductor element. The cap member 24 is formed of a transparent glass cap, the insulating layer 14 at the peripheral edge of the package substrate portion 11 is partially removed, and the glass cap is anodically bonded to the exposed silicon substrate 10.

  Alternatively, when a MEMS element is used as the electronic component 40, the cap member 24 can be formed of an opaque material such as a silicon cap in addition to the glass cap. In this case, the bonding portion of the package substrate portion 11 is an insulating layer. 14 may be covered.

  In the first to third electronic component devices 2, 2 a, 2 b of the present embodiment, the package substrate portion 11 is formed based on processing the first silicon wafer 10 that can be processed with high accuracy. 18 can be formed easily. Further, the cavity C (accommodating portion) is configured by the frame portion 23 and the cap member 24 without forming a cavity in the first silicon wafer 10.

  Thereby, since the 1st silicon wafer 10 is in the flat state over the whole, the penetration electrode 18 can be planarized easily and the coplanarity (flatness) of the connection part 18a can be set favorable. it can. Therefore, a high-performance electronic component having a large number of terminals with a narrow pitch can be mounted with high reliability.

  Further, although not particularly illustrated, a fine wiring pattern layer connected to the through electrode 18 can be formed after the through electrode 18 is planarized (after the step of FIG. 4B). Therefore, it becomes possible to cope with mounting of various electronic components, and the degree of freedom of design can be expanded.

(Second Embodiment)
12 to 13 are cross-sectional views illustrating a method for manufacturing an electronic component package according to a second embodiment of the present invention, and FIG. 14 is a cross-sectional view illustrating the same electronic component device.

  A feature of the second embodiment resides in that an element (such as a diode) connected to the electronic component is formed on a silicon substrate constituting the electronic component package. In the second embodiment, detailed description of the same elements and steps as those in the first embodiment is omitted.

  In the electronic component package manufacturing method of the second embodiment, as shown in FIG. 12A, first, the same structure as that of the first silicon wafer 10 of FIG. A thing is created and it is set as the upper package member 3a. That is, after the through hole TH is formed in the first silicon wafer 10 and the insulating layer 14 is formed on the entire surface thereof, the through electrode 18 is formed in the through hole TH, and both surface sides thereof are flattened.

  Next, as shown in FIG. 12B, a second silicon wafer 20 having a Zener diode ZD formed on the upper surface side is prepared. The zener diode ZD is formed by ion-implanting p-type conductivity impurities (such as boron) into the n-type second silicon wafer 20. On the second silicon wafer 20, a first insulating layer 50 having an opening on the Zener diode ZD is formed.

  An electrode pad 52 connected to the Zener diode ZD is formed on the first insulating layer 50. The electrode pad 52 is configured by forming a Ti (titanium) layer / TiN (titanium nitride) layer / Al (aluminum) layer in order from the bottom.

  Further, a second insulating layer 54 having an opening 54 x provided on the electrode pad 52 is formed on the first insulating layer 50. An insulating layer 51 is formed on the lower surface of the second silicon wafer 20.

  Next, as shown in FIG. 12C, a Ti layer / Cu (copper) layer is formed in order from the bottom on the second insulating layer 54 and the electrode pad 52 to obtain a metal layer 56a. Subsequently, the metal layer 56a is polished by CMP or the like until the second insulating layer 54 is exposed. Thereby, as shown in FIG. 12D, the metal layer 56a is embedded in the opening 54x of the second insulating layer 54, and the connection electrode 56 connected to the electrode pad 52 is obtained.

  Thus, the connection electrode 56 electrically connected to the Zener diode ZD is provided on the upper surface side of the second silicon wafer 20 in an exposed state. Then, the second silicon wafer 20 in FIG. 12D is used as the lower package member 3b.

  Subsequently, as shown in FIG. 13A, the connection electrode 56 (copper layer) of the lower package member 3b of FIG. 12D is connected to the through electrode 18 of the upper package member 3a of FIG. The lower connecting portion 18a (copper layer) is joined.

  As this joining method, a method similar to the step of FIG. 6A of the first embodiment is employed. That is, after each joint surface of the upper package member 3a and the lower package member 3b is cleaned and subjected to plasma treatment, it is aligned, pressure-bonded, and heat-treated at a temperature of 150 ° C.

  The method of bonding on the low temperature side using plasma treatment is not only between silicon, silicon and silicon oxide layer (insulating layer), or silicon oxide layer (insulating layer) but also various metal materials such as copper and copper. It is possible to join.

  As a result, as shown in FIG. 13B, the connection electrode 56 of the lower package member 3b and the connection portion 18a of the through electrode 18 of the upper package member 3a are joined and electrically connected.

  That is, the Zener diode ZD provided in the lower package member 3 b is electrically connected to the through electrode 18 of the upper package member 3 a through the electrode pad 52 and the connection electrode 56.

  As described above, the package member 3 of the second embodiment configured by stacking the upper package member 3a on the lower package member 3b is obtained.

  Also in the second embodiment, each electronic component device may be configured by cutting the package member 3 after each electronic component is mounted in each package region of the wafer-like package member 3, or the package member. An electronic component device may be configured by mounting electronic components after cutting 3 to obtain individual packages.

  FIG. 14 shows an electronic component device configured using the electronic component package of the second embodiment. As shown in FIG. 14, the electronic component package 1b of the electronic component device 2c of the second embodiment is obtained by cutting the package member 3 of FIG. 13B, and the upper package on the lower package portion 4b. The portion 4a is laminated to form a basic configuration.

  In the lower package portion 4 b, a Zener diode ZD is formed on the upper surface side of the silicon substrate 20 a, and the Zener diode ZD is connected to the connection electrode 56 through the electrode pad 52. Further, in the upper package portion 4a, the insulating layer 14 is formed on both sides of the silicon substrate 10a and the inner surface of the through hole TH provided therein, and the through electrode 18 whose both sides are flattened is filled in the through hole TH. Has been.

  The lower connection portion 18a of the through electrode 18 of the upper package portion 4a is joined to the connection electrode 56 on the upper surface side of the lower package portion 4b.

  Further, the bumps 30a of the LEDs 30 are mounted on the connection portions 18a on the upper surface side of the through electrodes 18 of the upper package portion 4a by flip chip connection. The LED 30 is embedded in the phosphor 32, and the upper surface (light emitting surface) of the LED 30 is covered with the phosphor 32. Similar to the electronic component device 1 of FIG. 9 of the first embodiment, the LED 30 emits light such as blue or purple, and is emitted to the outside as white light by the action of the phosphor 32.

  The LED 30 is connected to a Zener diode ZD provided on the silicon substrate 20a of the lower package part 4b through the through electrode 18 of the upper package part 4a, the connection electrode 56 of the lower package part 4b, and the electrode pad 52. ing. The Zener diode ZD functions as a power regulator by being connected in parallel with the LED 30 in the power line.

  In addition, like the electronic component device 2d of the modification shown in FIG. 15, the cavity C is provided in the central portion and the protruding joint portion 24a is provided in the peripheral portion on the electronic component package 1b of the second embodiment. The cap member 24 made of transparent glass having the structure described above may be joined and disposed. The insulating layer 14 at the peripheral edge of the upper package part 4a is partially removed, and the cap member 24 (glass cap) is anodically bonded to the silicon substrate 10a of the upper package part 4a.

  Thereby, the LED 30 mounted on the upper package part 4 a is hermetically sealed and accommodated in the accommodating part S constituted by the cap member 24.

  Alternatively, the LED 30 may be embedded with the phosphor 32 and a transparent cap member may be further provided thereon.

  In the second embodiment, an example in which the Zener diode ZD connected to the LED 30 is built in the silicon substrate 20a of the lower package part 4b is shown. However, instead of the LED 30 on the upper package part 4a, a MEMS such as an acceleration sensor is used. An element may be mounted, and a semiconductor element or the like for driving the MEMS element may be incorporated in the silicon substrate 20a of the lower package portion 4b.

  That is, various electronic components can be mounted on the upper package portion 4a, and various elements (semiconductor elements, diodes, capacitors, resistors, resistors, etc.) connected to the electronic components are formed on the silicon substrate 20a of the lower package portion 4b. Inductors etc. can be built in.

  When the MEMS element is mounted on the upper package part 4a, the electronic component device 2d including the cap member 24 of FIG. 15 is employed, and the MEMS element is hermetically sealed in the housing part S. In that case, an opaque material such as a silicon cap can be used as the cap member 24 in addition to the transparent glass.

  Also in the second embodiment, as in the first embodiment, the through electrodes 18 provided in the upper package portion 4a are formed with the upper and lower connection portions 18a being flattened and formed at a narrow pitch. it can. Therefore, it can be applied to a package on which high-performance electronic components are mounted.

  By the way, a method of incorporating the Zener diode ZD in the upper package part 4a and omitting the lower package part 4b is conceivable. However, when the Zener diode ZD is built in the upper package portion 4a, it is necessary to form the through hole TH after forming the Zener diode ZD and form the insulating layer 14 by thermal oxidation.

  For this reason, the characteristic of the Zener diode ZD often deviates from the design value particularly in the process of thermal oxidation, and it is extremely difficult to correct the deviation with the process conditions. In addition, after the Zener diode ZD is formed, it is necessary to cover it with a protective layer so that foreign matter does not adhere to it, or to set the cleanness of the process environment to be high, resulting in a problem of complicated process management.

  In the present embodiment, in order to avoid such a problem, a Zener diode ZD is provided in another lower package part 4b without forming a Zener diode ZD in the upper package part 4a provided with the through electrode 18, The Zener diode ZD is connected to the through electrode 18 of the upper package portion 4a by a low-temperature bonding method using plasma processing.

  Accordingly, in the present embodiment, it is not necessary to consider the deviation in the characteristics of the Zener diode ZD, and it is not necessary to set a high degree of cleanness until the final process. Therefore, a package incorporating various elements can be manufactured with high yield and low cost. Can do. The same applies when various elements are incorporated in addition to the Zener diode ZD.

(Third embodiment)
16 is a cross-sectional view showing a method for manufacturing an electronic component package according to a third embodiment of the present invention, FIG. 17 is a cross-sectional view showing the electronic component package, and FIG. 18 is a cross-sectional view showing the electronic component device.

  A feature of the third embodiment is that, in the second embodiment, a lattice frame is formed on the second silicon wafer on which the Zener diode is formed, and the second silicon wafer is formed on the first silicon wafer on which the through electrode is provided. It is to manufacture a package for an electronic component provided with a cavity. In the third embodiment, detailed description of the same elements and steps as those in the second embodiment is omitted.

  As shown in FIG. 16 (a), the manufacturing method of the electronic component package of the third embodiment first has the same structure as the lower package member 3b shown in FIG. 12 (d) of the second embodiment. The upper package member 5a is created. Next, as shown in FIG. 16B, a mask layer 12 having an opening 12z is formed in the central main part of each package region of the upper package member 5a.

  Further, as shown in FIG. 16 (c), the mask layer 12 is used as a mask to penetrate through the opening 12z from the uppermost second insulating layer 54 to the lowermost insulating layer 51 of the upper package member 5a. The part TP is formed. Thereafter, the mask layer 12 is removed. As a result, the lattice frame portion 22 is formed on the silicon wafer 10 and the Zener diode ZD is left in the lattice frame portion 22. In this way, the upper package member 5a is processed into a frame member.

  Next, as shown in the lower diagram of FIG. 16D, a wafer having the same structure as that of the first silicon wafer 10 provided with the through electrode 18 of FIG. A lower package member 5b is obtained by forming a wiring pattern layer 19 for connecting a required through electrode 18 on the lower surface side of the wafer 10.

  Similarly, as shown in FIG. 16 (d), the upper package member 5a of FIG. 16 (c) is placed on the lower package member 5b in a vertically inverted state, and the through electrode 18 of the lower package member 5b is placed. The connection electrode 56 of the lattice frame portion 22 of the upper package member 5a is joined to the connection portion 18a. As a bonding method, a method using plasma processing is employed as in the first and second embodiments.

  Thereby, as shown in FIG. 17, the connection electrode 56 of the upper package part 5a is joined and electrically connected to the connection part 18a of the upper side of the penetration electrode 18 of the lower package member 5b. In addition, a cavity C constituted by the lattice frame 22 is provided in each package region of the lower package member 5b. Thereby, the package member 5 of 3rd Embodiment is obtained.

  Also in the third embodiment, after electronic components are mounted on the wafer-like package member 5, the grid-like frame portion 22 and the lower package member 5b may be cut to constitute individual electronic component devices, or Alternatively, the electronic component device may be configured by mounting the electronic components after the lattice-shaped frame portion 22 and the lower package member 5b are cut to obtain individual packages.

  FIG. 18 shows an electronic component device configured using the electronic component package of the third embodiment. As shown in FIG. 18, the electronic component package 1c of the electronic component device 2e according to the third embodiment is obtained by cutting the package member 5 shown in FIG. 17, and is erected on the package substrate 11 and its peripheral portion. The frame portion 23 is basically configured.

  In the package substrate part 11, as in the first embodiment, the through holes TH are provided in the silicon substrate 10a, and the insulating layer 14 is formed on both sides of the silicon substrate 10a and on the inner surface of the through hole TH. A through electrode 18 is provided in the through hole TH, and the upper surface and the lower surface of the through electrode 18 are flattened at the same height as the upper surface and the lower surface of the insulating layer 14 on the silicon substrate 10a.

  Further, the frame portion 23 is joined to the peripheral edge portion on the package substrate portion 11, and thereby the cavity C is provided in the central main portion on the silicon substrate 10 a. A Zener diode ZD is formed on the lower surface side of the silicon portion 20a of the frame portion 23, and the connection electrode 56 connected to the Zener diode ZD is joined to the connection portion 18a on the upper side of the through electrode 18 of the package substrate portion 11. Yes.

  Further, a wiring pattern layer 19 that connects the through electrodes 18 is provided on the lower surface side of the silicon substrate 10 a of the package substrate portion 11.

  The bump 30 a of the LED 30 is flip-chip connected to the connection portion 18 a on the upper side of the through electrode 18 of the package substrate portion 11. Further, the cap member 24 is joined to the frame portion 23 and the LED 30 is accommodated in the accommodation portion S in an airtightly sealed state. An external connection terminal 26 connected to the through electrode 18 is provided on the lower surface of the package substrate portion 11.

  In the example of FIG. 18, the cap member 24 is made of a transparent glass cap, the insulating layer 51 on the upper surface of the frame portion 23 is removed at a predetermined stage, and the cap member 24 (glass cap) is anodically bonded to the silicon portion 20a. Yes.

  Alternatively, as in the first electronic component device 2 (FIG. 9) of the first embodiment, the cap member 24 may be omitted and the LED 30 may be embedded with a phosphor. Alternatively, the LED 30 may be embedded with a phosphor, and a transparent cap member may be further provided thereon.

  The LED 30 is connected to the Zener diode ZD of the frame portion 23 through the through electrode 18 to which the bump 30a is connected, the wiring pattern layer 19 connected to the through electrode 18 and another through electrode 18 connected to the through electrode 18 and the like. It is connected.

  A wiring pattern layer 19 that connects the through electrodes 18 may be formed on the upper surface side of the package substrate portion 11.

  The third embodiment has the same effect as the second embodiment. Furthermore, in the third embodiment, since the frame portion 23 provided with the Zener diode ZD is joined to the package substrate portion 11 provided with the through electrode 18 having good coplanarity, the cavity C is provided. Thus, the electronic component package 1c in which the Zener diode ZD is incorporated can be easily manufactured. Thus, the LED 30 is hermetically sealed in the housing portion S by the cap member 24 in a state where the LED 30 is reliably connected to the through electrode 18 in the cavity C and the Zener diode ZD of the frame portion 23.

  In the third embodiment, instead of the LED 30, a MEMS element or another optical semiconductor element may be mounted. When the MEMS element is mounted, the cap member 24 is formed of an opaque material such as a silicon cap. You may be made to do.

DESCRIPTION OF SYMBOLS 1,1a-1c ... Electronic component package, 2, 2a-2e ... Electronic component apparatus, 3, 5 ... Package member, 3a, 5a ... Upper package member, 3b, 5b ... Lower package member, 4a ... Upper package part 4b: lower package part, 10 ... first silicon wafer, 11 ... package substrate part, 10a ... silicon substrate, 12 ... mask layer, 12x, 12y, 12z ... opening, 14 ... insulating layer, 15 ... adhesive layer , 16 ... plating power supply material, 18 ... penetrating electrode, 18a ... connection part, 19 ... wiring pattern layer, 20 ... second silicon wafer, 20a ... silicon part (or silicon substrate), 22 ... grid-like frame part, 23 ... frame 24, cap member, 24a, projecting joint, 26 ... external connection terminal, 30 ... LED, 30a, 40a ... bump, 40 ... electronic component, 50, 51, 54 ... insulating layer, 2 ... electrode pad, 56 ... connection electrode, 56a ... metal layer, C ... cavity, S ... accommodating portion, P ... protrusion, ZD ... Zener diode, TH ... through hole, TP ... through portion, R ... package areas.

Claims (5)

A first silicon substrate provided with a through hole; an insulating layer formed on upper and lower surfaces of the first silicon substrate and an inner surface of the through hole; and a through electrode filled in the through hole. A package substrate part in which the upper surface of the electrode and the upper surface of the insulating layer are flush with each other;
It is formed from a second silicon substrate having an opening penetrating from the upper surface to the lower surface in the central portion, and is laminated on the periphery of the package substrate portion via the insulating layer, and a cavity is formed on the first silicon substrate. Having a frame portion to constitute,
The package for an electronic component, wherein the through electrode is disposed in an opening of the frame portion. The frame portion has an insulating layer formed on the upper and lower surfaces of the second silicon substrate and the inner surface of the opening,
2. The electronic component package according to claim 1, wherein an insulating layer on a lower surface of the frame portion is in contact with an insulating layer on an upper surface of the package substrate portion. The electronic component package according to claim 1 or 2,
An electronic component device comprising: an electronic component mounted and connected to a connection portion on an upper surface of the through electrode.   The electronic component device according to claim 3, wherein a cap member for hermetically sealing the electronic component is provided on the electronic component package.   The electronic component device according to claim 3, wherein the electronic component is an LED, and the LED is coated with a phosphor.

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