JP2012213076A - Digital signal processing apparatus and digital signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal processing apparatus and a digital signal processing method that employ a filter comprising a multistage series connection of IIR filters having a shelving characteristic (or stepping characteristic), set a plurality of set points each comprising a set of frequency and gain values, and implement an arbitrary frequency response characteristic passing the set points.SOLUTION: In the digital signal processing apparatus, a filter setting section includes an error calculation section for calculating an implemented frequency response characteristic H of the filter section and calculating an error E from a desired frequency response characteristic D, and sets the filter section comprising a multiple N-stage series connection of M-order IIR filters Sn having a shelving characteristic Hn indicating a cutoff frequency fc and a gain gn, by changing the cutoff frequency fc of each of the plurality of IIR filters Sn of the filter section and changing the order of each IIR filter Sn from M in response to an output from the error calculation section to reduce the error E.

Description

  The present invention relates to a digital signal processing apparatus and a digital signal processing method that give a predetermined frequency response characteristic to an audio signal, and more particularly, a plurality of IIR type filters (Shelving Filters, shelving filters) having shelf type characteristics (or staircase characteristics). A digital signal processing device that includes a filter configured by connecting in series, sets a plurality of set values including a set of frequency values and gain values, and realizes an arbitrary frequency response characteristic that passes these set values And a digital signal processing method.

  In audiovisual equipment such as an AV receiver that reproduces audio signals, or an electronic computer such as a personal computer, an equalizer that gives a predetermined frequency response characteristic to an audio signal by inputting a plurality of sets of desired frequency values and gain values is realized. Some include a digital signal processing apparatus or a digital signal processing method. As an equalizer that gives a predetermined frequency response characteristic, there is typically a graphic equalizer whose frequency is fixed, and a parametric equalizer whose frequency can be varied. These equalizers often include a plurality of bandpass filters (or peaking filters).

  However, in a conventional parametric equalizer using a peak filter or a bandpass filter, an attempt is made to realize an equalizer having a desired frequency response characteristic by freely setting a plurality of set values including a set of arbitrary frequency values and gain values. However, individual peak filters or bandpass filters may affect each other, and a frequency response characteristic that passes through these set values may not be realized. In other words, in a configuration using a plurality of bandpass filters that pass a predetermined band, there is a band in which the pass frequency band is superimposed between adjacent filters, so that an arbitrary frequency value and gain can be obtained at one point with frequency response characteristics. Even if the value is passed, it may deviate from an arbitrary frequency value and gain value at other points.

  For example, conventionally, the gain is variably set for each of a plurality of predetermined frequency bands of the input signal so that the gain adjustment is performed so that the target characteristic can be appropriately obtained even when the leakage gain from other bands is affected. When the target gain value is set to one frequency band at least for the frequency bands adjacent to each other in order to obtain the target gain for each frequency band, the gain setting means configured as described above and the other Processing for obtaining a gain value to be set to the other frequency band based on a leakage gain value from the one frequency band to the other frequency band as update processing Based on the leakage gain value from the other frequency band when this updated gain value is set. Based on the result of alternately repeating the process of updating the gain value to be set for one frequency band, the gain adjustment means for adjusting the gain value to be set for each frequency band by the gain setting means, There is a signal processing device characterized by comprising (Patent Document 1).

  Conventionally, a plurality of shelving filters having shelf type characteristics (or staircase characteristics) are connected in series instead of the bandpass filter, and a plurality of set values including a set of arbitrary frequency values and gain values are passed. There is an equalizer that realizes frequency response characteristics (Patent Document 2). For example, in an equalizer for a digital signal having n adjacent frequency ranges divided by n-1 frequency limit points, as a low pass filter and a high pass filter that connect shelving filters in parallel, The equalizer includes n-1 filter circuits connected in cascade and a control unit, and each of the n-1 filter circuits connected in cascade is each of the n-1 frequency limit points. Each filter circuit is constituted by a parallel circuit of one digital low-pass filter and one digital high-pass filter whose frequency limit is a frequency limit point corresponding to the filter circuit. These digital low-pass filters and digital high-pass filters each have complementary transfer functions, The gains of the passbands of these digital low-pass filters and digital high-pass filters are configured to be adjustable by means for weighting their outputs, and each filter circuit outputs the outputs of the digital low-pass filters in parallel via the means for further weighting And the output of the digital high-pass filter are combined and output as the output of the filter circuit, and the control unit is provided in each of the n-1 filter circuits connected in cascade. It is configured to control the weight of the output of the digital low pass filter and the digital high pass filter, and when the frequency range having an increased frequency increases the amplitude in two adjacent frequency ranges on both sides of each frequency limit point, Corresponding to the frequency limit point by the control unit The output signal from the digital high-pass filter of the filter circuit is assigned a higher weight than the output signal from the digital low-pass filter, and in the two adjacent frequency ranges on either side of each frequency limit point, the frequency range with increased frequency is better. When the amplitude is reduced, the control unit is configured so that the output signal from the digital low-pass filter of the filter circuit corresponding to the frequency limit point can be assigned a higher weight than the output signal from the digital high-pass filter. There is a device (Patent Document 3).

JP 2007-166195 A (FIGS. 1 to 10) International Publication No. 2009/112825 (FIGS. 1 to 11) Japanese Patent No. 4259626 (FIGS. 1 to 10)

  In an equalizer in which a plurality of shelving filters of Patent Document 2 are connected in series, a frequency response that passes a plurality of set values consisting of a set of arbitrary frequency values and gain values as compared with a conventional bandpass filter or peaking filter. There is an advantage that it is easy to realize the characteristics. However, in the equalizer design method of Patent Document 2, after determining all the shelving filters connected in series, the error between the realized frequency response characteristic and the desired frequency response characteristic is measured and corrected. Therefore, there is a problem that it is not easy to mount as a digital signal processing device that realizes an equalizer. Further, when a shelving filter is realized by digital signal processing, a cutoff frequency of a shelf type characteristic is specified particularly when a high-order IIR filter (recursive filter or recursive filter) having an order M of 2 or more is used. When the calculation method is employed, there is a problem that it is difficult to appropriately determine the order M of the IIR filter.

  The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a filter configured by connecting a plurality of stages of IIR filters having a shelf type characteristic (or a step characteristic) in series. A digital signal processing device and a digital signal processing method for setting a plurality of set values including a set of frequency values and gain values, and realizing an arbitrary frequency response characteristic that passes these set values It is in.

  A digital signal processing device according to the present invention is a digital signal processing device that gives a predetermined frequency response characteristic to an audio signal, an input unit that inputs the audio signal, an output unit that outputs the audio signal, an input unit and an output unit N-stage (N: integer greater than or equal to 2) N-stage (M: integer greater than or equal to M) IIR filters Sn having a shelf-type characteristic Hn indicating a cutoff frequency fc and a gain gn. A desired frequency response characteristic D of the filter unit is set by setting a plurality of (N + 1) set values (Fn, Gn) including a filter unit configured in series and a set of the frequency value Fn and the gain value Gn. A filter setting that sets a desired frequency setting unit and a cutoff frequency fc and a gain gn corresponding to the set values (Fn, Gn) of the desired characteristic setting unit and sets each IIR filter Sn of the filter unit. An error calculating unit that calculates an actual frequency response characteristic H of the filter unit and calculates an error E between the desired frequency response characteristic D and the actual frequency response characteristic H. The cutoff frequency fc of each of the plurality of IIR filters Sn in the filter unit is increased or decreased in response to the output from the filter unit, and each error of the IIR filter Sn is increased or decreased from the M order to reduce the error E. Set the filter part to.

  Preferably, in the digital signal processing device according to the present invention, the filter setting unit causes the error E to be an absolute value En of a difference between the gain value Dn of the desired frequency response characteristic D and the gain value Hn of the realized frequency response characteristic H at the frequency value Fn. The cutoff frequency value fc of the corresponding IIR filter Sn is changed and set so that the error value En becomes smaller than a predetermined value, and the gain of the desired frequency response characteristic D at the adjacent frequency value Fn + 1 The absolute value En + 1 of the difference between the value Dn + 1 and the gain value Hn + 1 of the realized frequency response characteristic H is calculated, the order M of the IIR filter Sn is increased so that the error value En + 1 is smaller than a predetermined value, and the IIR filter Sn When the order M is changed, the error value En and the error value En + 1 are recursively calculated, and the error E is smaller than a predetermined value. To set the filter unit to so that.

  The digital signal processing method of the present invention is a digital signal processing method that gives a predetermined frequency response characteristic to an audio signal, and has an M-th order (M: 1) having a shelf-type characteristic Hn indicating a cutoff frequency fc and a gain gn. A plurality of N stages (N: integer greater than or equal to 2) of IIR type filters Sn connected in series, a step of inputting an audio signal to the filter unit, an audio signal from the filter unit In the output step and the desired characteristic setting unit of the filter unit, a plurality of (N + 1) sets of set values (Fn, Gn) including a set of the frequency value Fn and the gain value Gn are set, and the desired frequency response characteristic D of the filter unit is set. And the filter setting unit of the filter unit corresponding to the set values (Fn, Gn) of the desired characteristic setting unit and the cutoff frequency fc and the gain determining gn and setting each IIR filter Sn of the filter unit, wherein the filter setting unit calculates an actual frequency response characteristic H of the filter unit, and a desired frequency response characteristic D and an actual frequency response characteristic H A step of calculating an error E of the filter unit, a step of increasing / decreasing the cutoff frequency fc of each of the plurality of IIR filters Sn of the filter unit in response to the error E, and an increase / decrease of the respective orders of the IIR filter Sn And setting the filter unit so as to reduce the error E.

  Preferably, in the digital signal processing method of the present invention, in the filter setting unit, the error E is an absolute value En of the difference between the gain value Dn of the desired frequency response characteristic D and the gain value Hn of the realized frequency response characteristic H at the frequency value Fn. , A step of changing and setting the cutoff frequency value fc of the corresponding IIR filter Sn so that the error value En becomes smaller than a predetermined value, and a desired frequency response characteristic D at the adjacent frequency value Fn + 1. Calculating the absolute value En + 1 of the difference between the gain value Dn + 1 of the actual frequency response characteristic H and the gain value Hn + 1 of the realized frequency response characteristic H, and increasing the order M of the IIR filter Sn so that the error value En + 1 is smaller than a predetermined value. When the order M of the IIR filter Sn is changed, the error value En and the error value En + 1 are reproduced again. Repeatedly calculated involve setting a filter unit so as to be smaller than a predetermined value an error E, a.

  The operation of the present invention will be described below.

  The digital signal processing apparatus and digital signal processing method of the present invention have an Mth order having a shelf-type characteristic Hn indicating a cutoff frequency fc and a gain gn so as to output an input audio signal with a predetermined frequency response characteristic. A filter unit is configured by connecting a plurality of N stages (N: an integer of 2 or more) IIR type filters Sn (M: an integer of 1 or more) in series. The filter unit includes a desired characteristic setting unit that sets a desired frequency response characteristic D of the filter by setting a plurality of (N + 1) sets of set values (Fn, Gn) including a set of the frequency value Fn and the gain value Gn. A filter setting unit that sets a cutoff frequency fc and a gain gn corresponding to setting values (Fn, Gn) of the characteristic setting unit and sets each IIR filter Sn of the filter unit.

  When the user sets a plurality of (N + 1) sets of setting values (Fn, Gn) and sets the desired frequency response characteristic D of the filter, the digital signal processing apparatus and the digital signal processing method receive the output from the error calculation unit. By increasing or decreasing the cutoff frequency fc of each of the N-stage IIR filters Sn connected in series in the filter unit and increasing or decreasing the respective orders of the IIR filter Sn from the M order, the error E It is possible to set the filter unit so as to reduce the.

  Specifically, the filter setting unit calculates the error E as the absolute value En of the difference between the gain value Dn of the desired frequency response characteristic D and the gain value Hn of the realized frequency response characteristic H at the frequency value Fn. The cutoff frequency value fc of the corresponding IIR filter Sn is changed and set so that the value En becomes smaller than the predetermined value. Further, the filter setting unit calculates an absolute value En + 1 of the difference between the gain value Dn + 1 of the desired frequency response characteristic D and the gain value Hn + 1 of the realized frequency response characteristic H at the adjacent frequency value Fn + 1, and the error value En + 1 is greater than a predetermined value. When the order M of the IIR filter Sn is increased and the order M of the IIR filter Sn is changed so as to decrease, the error value En and the error value En + 1 are recursively calculated, and the error E is predetermined. The filter unit is set to be smaller than the value.

  As described above, in the digital signal processing device and the digital signal processing method of the present invention, when the filter unit is configured by connecting a plurality of N-stage high-order IIR filters Sn having the shelf-type characteristics Hn in series, the cutoff frequency Even when the IIR filters adjacent to each other in the value fc influence each other, the order M is changed to minimize an error caused by the influence, and therefore, a plurality of sets of set values including a set of frequency values and gain values are set. Only, it is possible to realize an arbitrary frequency response characteristic that passes through these set values. Also, it is a shelf-type filter using a high-order IIR filter, and when the filter characteristic is asymmetrical between the low frequency side and the high frequency side, a frequency response characteristic that passes a plurality of desired set values is realized. Can do.

  The digital signal processing apparatus and the digital signal processing method of the present invention are a combination of a frequency value and a gain value, even if the filter is configured by connecting a plurality of stages of IIR filters having shelf-type characteristics (or staircase characteristics). By setting a plurality of set values consisting of the above, any frequency response characteristic that passes through these set values can be realized.

1 is a block diagram illustrating a digital signal processing apparatus 1 according to a preferred embodiment of the present invention. Example 1 It is a figure explaining operation | movement of the several shelf type filter connected in series in the filter part 4 of the digital signal processing apparatus 1 by preferable embodiment of this invention. Example 1 It is a figure explaining the step which determines the cut-off frequency fc of a shelf type filter in the digital signal processing method by preferable embodiment of this invention. Example 1 FIG. 4 is a diagram illustrating a step of determining an order M of an IIR filter in a digital signal processing method according to a preferred embodiment of the present invention. Example 1 It is a graph explaining the realization frequency response characteristic H at the time of changing the order M of an IIR type filter in the filter part 4 of the digital signal processing apparatus 1 by preferable embodiment of this invention. Example 1 6 is a flowchart illustrating steps for determining a shelf filter cutoff frequency fc and an IIR filter order M in a digital signal processing method according to a preferred embodiment of the present invention. Example 1 It is a graph explaining the realization frequency response characteristic H in the filter part 4 of the digital signal processing apparatus 1 by preferable embodiment of this invention. Example 1 It is a graph explaining the other realization frequency response characteristic H in filter part 4 of digital signal processor 1 by a desirable embodiment of the present invention. (Example 2) It is a list | wrist of the order M of each IIR type filter Sn connected in series in the filter part 4 of the digital signal processing apparatus 1 by preferable embodiment of this invention. (Example 2) It is a graph explaining the realization frequency response characteristic H at the time of using a peak characteristic filter or a band pass type filter in filter part 4 of other digital signal processor 10 of a comparative example. (Comparative Examples 1-4)

  Hereinafter, a digital signal processing apparatus and a digital signal processing method according to preferred embodiments of the present invention will be described, but the present invention is not limited to these embodiments.

  FIG. 1 is a block diagram illustrating a digital signal processing apparatus 1 according to a preferred embodiment of the present invention. For example, the digital signal processing apparatus 1 is an electronic computer such as a personal computer (not shown), and when a content file including an audio signal is reproduced, a user uses a GUI to specify a desired frequency value and gain value. An equalizer program that inputs a plurality of sets and gives a predetermined frequency response characteristic to the audio signal is included. The equalizer program is executed by a central processing circuit (CPU) or a digital signal processor (DSP) of a personal computer (not shown), and a plurality of IIR filters having shelf type characteristics are connected in series to form the filter unit 4 A digital signal processing method. For easy understanding of the drawings and the description, the entire configuration of the personal computer (not shown) and a part of the configuration unnecessary for the description of the digital signal processing apparatus 1 are omitted.

  The digital signal processing apparatus 1 includes an input unit 2 that inputs an audio signal, an output unit 3 that outputs an audio signal, a filter unit 4 connected between the input unit and the output unit, and a desired frequency of the filter unit 4 A desired characteristic setting unit 5 that sets the response characteristic D and a filter setting unit 6 that sets each IIR filter Sn of the filter unit 4 are provided. The input unit 2 may include a DIR circuit when the audio signal is a digital signal, and an A / D circuit when the audio signal is an analog signal. The output unit 3 may include a D / A circuit that converts the digital signal output from the filter unit 4 into an analog signal.

  The filter unit 4 includes a CPU or a DSP. The filter unit 4 is configured by connecting in series N-stage IIR filters Sn having shelf-type characteristics. The desired characteristic setting unit 5 includes a GUI (not shown), a setting unit 51 that sets a plurality of N + 1 sets of setting values (Fn, Gn) each including a set of a frequency value Fn and a gain value Gn, and a desired frequency of the filter unit And a calculation unit 52 that calculates the response characteristic D. The user can freely set the desired desired frequency response characteristic D on the screen by operating a key or the like on the display unit (not shown).

  Further, the filter setting unit 6 determines the cutoff frequency fc and the gain gn of each IIR filter Sn corresponding to the set values (Fn, Gn) of the desired characteristic setting unit 5, and sets each of the filter units 4. A setting unit 61 that sets the IIR filter Sn, a calculation unit 62 that calculates the realized frequency response characteristic H of the filter unit 4, and an error calculation unit that calculates an error E between the desired frequency response characteristic D and the realized frequency response characteristic H 63. As will be described later, the filter setting unit 6 receives and outputs the output from the error calculation unit 63, increases or decreases the cutoff frequency fc of each of the plurality of IIR filters Sn of the filter unit 4, and each of the IIR filters Sn. The filter unit 4 is set so as to reduce the error E by increasing or decreasing the order of M from the M order.

  FIG. 2 is a diagram illustrating the operation of a plurality of shelf-type filters connected in series in the filter unit 4 of the digital signal processing device 1. In FIG. 2, when realizing a filter having a desired frequency response characteristic D that passes through three sets of setting values (Fn, Gn), (Fn + 1, Gn + 1), (Fn + 2, Gn + 2), respectively, gn and Two shelf type filters Sn and Sn + 1 having gn + 1 as a gain are connected in series. The frequency characteristic of the shelf type filter Sn is Hn, and the cutoff frequency fcn is an intermediate value on the logarithmic scale of the frequency values Fn + 1 and Fn, and the gain is gn. The frequency characteristic of the second shelf filter Sn + 1 is Hn + 1, and the cutoff frequency fcn + 1 is an intermediate value on the logarithmic scale of the frequency values Fn + 1 and Fn + 2, and the gain is gn + 1. In the method in which the shelf filters are connected in series, adjacent shelf filters interfere with each other only in the vicinity of the illustrated frequency value Fn + 1. Therefore, the sum of the gains of these two shelf filters (gn) + (gn + 1) Is set equal to the desired gain difference (Gn + 2), the realized frequency response characteristic H can be brought close to the desired frequency response characteristic D.

  FIG. 3 is a diagram for explaining steps for determining the cutoff frequency fcn of the shelf filter, and FIG. 4 is a diagram for explaining steps for determining the order M of the IIR filter. In this digital signal processing method, the cut-off frequency of the shelf-type filter is such that the characteristic Hn (gain gn) of the filter Sn to be obtained at the predetermined frequency value Fn becomes the desired value Gn, and the error Error becomes smaller than the predetermined value. Is changed from fcn (FIG. 3A) to fcn ′ (FIG. 3B) to set the characteristic Hn ′ of the filter Sn. Further, in this digital signal processing method, the IIR of the shelf-type filter Sn for obtaining the error Error to be smaller than the predetermined value so that the characteristic Hn (gain gn) becomes the desired value Gn + 1 at the predetermined frequency value Fn + 1. The characteristic Hn ′ of the filter Sn is set by changing the order of the type filter from M (FIG. 4A) to M + 1 (FIG. 4B). When the order M of the IIR filter of the shelf filter Sn is changed, the step of determining the cutoff frequency fcn of the shelf filter is performed again, and the parameters of the shelf filter are recursively repeated. Make adjustments.

  FIG. 5 is a graph for explaining the realized frequency response characteristic H when the order M of the IIR filter is changed in the filter unit 4 of the digital signal processing device 1. Specifically, FIG. 5A shows the order when the order M of the IIR type filters connected in series of N = 5 stages is commonly changed so as to realize the desired frequency response characteristic D passing through six points. FIG. 5B shows the realized frequency response characteristic H when M = 2, FIG. 5B shows the order M = 4, FIG. 5C shows the order M = 6, and FIG. 5D shows the order M = 8. As shown in FIG. 5, in the shelf type filter Sn using the IIR type filter, when the realized frequency response characteristic Hn passing through any two points before and after the cut-off frequency is determined, a low frequency range having a stepped difference is obtained. If the level difference between the high frequency side and the high frequency side is large, the error E with the desired frequency response characteristic D increases unless the order M of the IIR filter is increased. That is, in a frequency section where the amount of gain change is large, a frequency response characteristic that passes through a plurality of desired set values can be realized by using a steeper high-order shelf filter.

  FIG. 6 is a flowchart for explaining the steps of determining the cutoff frequency fcn of the shelf filter Sn and the order M of the IIR filter in this digital signal processing method. The counter n is set to 1 as the first passing point of the desired frequency response characteristic D (passing point N + 1 point) of the N stages of IIR filters connected in series (S1). The counter n corresponds to the number in the order of the number of stages of the shelf-type filters connected in series, and if the counter n is equal to the value (N + 1), that is, if the filters for N stages have been set, the process ends. (S2: Yes). If S2 is No, the cutoff frequency fcn of the IIR filter is set to a predetermined frequency value sqrt (Fn + 1 * Fn), and is further initialized to the order M = 2 (S3). Note that the order may be initialized as the order M = 1.

Next, the filter coefficient of the shelf type IIR filter Sn that realizes the shelf type characteristic Hn is determined using the cutoff frequency fcn and the order M (S4). Next, the gain gn at the set value Fn at the lower frequency of the cutoff frequency fcn is calculated (S5). The gain gn can be calculated as gn = | H (z) | (z = exp (i2πFn / fs), fs = sampling frequency). If the difference between the gain gn obtained in S5 and the gain D required for the frequency Fn (that is, the gain value Gn of the set value) is equal to or less than the predetermined value En (S6: Yes), the next step The process proceeds to S7. Otherwise (S6: No), the cutoff frequency fcn ′ is updated by multiplying by a predetermined α so as to change the cutoff frequency fcn (S10), and the process is returned to step S4. In step S7, the gain gn + 1 at the set value Fn + 1 at the higher frequency of the cutoff frequency fcn is calculated (S7). The gain gn + 1 is G1 = | H (z) | (z = exp (i2π (Fn + 1) / fs),
fs = sampling frequency). If the difference between the gain gn + 1 obtained in S7 and the gain D required for the frequency Fn + 1 (that is, the gain value Gn + 1 of the set value) is equal to or smaller than the predetermined value En + 1 (S8: Yes), the next In step S9, the counter n is set to n + 1, and the process returns to step S2. Otherwise (S8: No), the cutoff frequency fcn of the IIR filter is set to a predetermined frequency value sqrt (Fn + 1 * Fn), and the order M is further increased by 1 and set to M + 1. The process returns to step S4.

  That is, in this digital signal processing method, the filter setting unit 4 calculates the error E as the absolute value En of the difference between the gain value Dn of the desired frequency response characteristic D and the gain value Hn of the realized frequency response characteristic H at the frequency value Fn. Step (S6), a step (S10) of changing and setting the cut-off frequency value fc of the corresponding IIR filter Sn so that the error value En becomes smaller than a predetermined value, and a desired value at the adjacent frequency value Fn + 1. A step (S8) of calculating the absolute value En + 1 of the difference between the gain value Dn + 1 of the frequency response characteristic D and the gain value Hn + 1 of the realized frequency response characteristic H, and the IIR filter Sn so that the error value En + 1 is smaller than a predetermined value. When the order M of the IIR filter Sn is changed (S11) and the order M of the IIR filter Sn is changed, The difference values En and the error value En + 1 repeatedly calculated recursively includes a step (S4) for setting the filter unit so as to be smaller than a predetermined value an error E, a.

  FIG. 7 is a graph illustrating the realized frequency response characteristic H in the filter unit 4. That is, in the equalizer generated by the digital signal processing method described above, the graph in the case where the order M of the IIR filter is 6 in the frequency response section where the amount of change in the gain of the realized frequency characteristic is small (FIG. 5C). Or, the order M becomes smoother than the graph in the case where the order M is 8 (FIG. 5D), and the appropriate order M is determined in each shelf than when determining the order M of the IIR filters connected in series uniformly. It can be seen that the type filter is selected.

  FIG. 8 is a graph illustrating another realized frequency response characteristic H in the filter unit 4. Specifically, the filter unit 4 is configured by N = 19 stages of IIR type filters Sn connected in series so as to realize a desired frequency response characteristic D that passes 20 points far more than the previous embodiment. With the digital signal processing method described in the previous embodiment, as shown in FIG. 8, a filter characteristic that smoothly passes 20 arbitrary points can be realized. FIG. 9 is a list of orders M of each IIR filter Sn connected in series with N = 19 stages. In the equalizer generated by the digital signal processing method described above, the order M changes from 2 to 14 in various values.

  On the other hand, FIG. 10 is a graph illustrating an actual frequency response characteristic H when a peak characteristic filter or a band-pass filter is used in the filter unit 4 of another digital signal processing apparatus 10 (not shown) of the comparative example. is there. (Comparative Examples 1-4). Specifically, FIGS. 10A and 10B show a case where a peak filter is used instead of the shelf type filter, and FIGS. 10C and 10D show a band instead of the shelf type filter. This is a case where a pass-type (bandpass) filter is used.

  In the case of using a plurality of peak filters connected in series, if the bandwidth of each peak filter is narrowed (bandwidth = 0.25) as shown in FIG. If a valley occurs, and the bandwidth of each peak filter is widened (bandwidth = 1 / sqrt (2)) as shown in FIG. 10B, the valley between the set values disappears but the adjacent band is There is a problem that an error occurs due to deviation from the specified characteristics due to interference. If the bandwidth of each peak filter is increased too much, it is necessary to adjust three adjacent peak filters, making it difficult to set the filter characteristics.

  When a plurality of band-pass filters connected in series are used, when the resonance sharpness Q of each band-pass filter is increased (Q = 4.0) as shown in FIG. If valleys occur between the values and the resonance sharpness Q of each bandpass filter is reduced (Q = 1.0) as shown in FIG. 10D, the valleys between the set values disappear, but adjacent bands. There is a problem that an error occurs due to a deviation from the specified characteristics due to interference with the sensor. In the band-pass filter, interference between adjacent bands is larger than in the case of the peak filter, so that it is difficult to set the filter characteristics regardless of the Q value used.

  In contrast to these comparative examples, in the digital signal processing method of the present embodiment, the filter unit is configured by a plurality of shelves of series-connected filters, and the IIR filters connected in series are adjusted in order from the beginning. Therefore, there is an advantage that adjustment is easy and time is not required. That is, in this digital signal processing method, the step of determining the cut-off frequency fcn of the shelf filter and the step of determining the order M of the IIR filter are recursively repeated, and adjustment is performed only between two adjacent filters. Therefore, it is not necessary to adjust the three adjacent shelf filters, and the filter characteristics can be easily set. Furthermore, since the step of determining the cutoff frequency fcn of the shelf type filter is included, even when the filter characteristic is asymmetric between the low frequency side and the high frequency side in the shelf type filter using the high-order IIR filter, By setting a plurality of sets of set values composed of sets of frequency values and gain values, it is possible to realize an arbitrary frequency response characteristic that passes through these set values.

  In the present embodiment, the initial value of the order M of the IIR filter is set to 2. However, the order M may be an integer equal to or greater than 2, and the initial value may be set to other values such as M = 4. Further, in the above-described embodiment, n = 1 (first) shelf-type characteristic filter S1 corresponding to the lowest band frequency is determined, the counter n is sequentially increased, and the shelf type corresponding to the next lowest band frequency. Although the characteristic filter S2 is determined, the present invention is not limited to the case where the counter n is increased by one. A shelf-type filter corresponding to a lower band frequency may be sequentially determined from a shelf-type filter corresponding to the highest band frequency. Alternatively, the n-th shelf-type characteristic filter Sn near the center band may be determined, and the shelf-type characteristic filters may be sequentially determined in bands adjacent to the low-frequency side or the high-frequency side.

  In addition, this invention is not limited to the said Example. The digital signal processing apparatus and the digital signal processing method can be applied not only to an electronic computer such as a personal computer but also to an audiovisual apparatus that realizes an arbitrary frequency response characteristic that passes an arbitrary plurality of set values.

DESCRIPTION OF SYMBOLS 1 Digital signal processor 2 Input part 3 Output part 4 Filter part 5 Desired characteristic setting part 6 Filter setting part

Claims (4)

A digital signal processing device for giving a predetermined frequency response characteristic to an audio signal,
An input unit for inputting the audio signal; an output unit for outputting the audio signal;
A plurality of M-order (M: integer of 1 or more) IIR filters Sn connected between the input section and the output section and having a shelf-type characteristic Hn indicating a cut-off frequency fc and a gain gn are arranged in a plurality of N stages ( N: an integer of 2 or more) a filter unit configured in series connection;
A desired characteristic setting unit that sets a desired frequency response characteristic D of the filter unit by setting a plurality of (N + 1) sets of set values (Fn, Gn) each consisting of a set of a frequency value Fn and a gain value Gn;
A filter setting unit that determines the cut-off frequency fc and the gain gn corresponding to the set values (Fn, Gn) of the desired characteristic setting unit, and sets each IIR filter Sn of the filter unit;
Have
The filter setting unit includes an error calculation unit that calculates an actual frequency response characteristic H of the filter unit and calculates an error E between the desired frequency response characteristic D and the actual frequency response characteristic H. From the error calculation unit The cutoff frequency fc of each of the plurality of IIR type filters Sn of the filter unit is increased or decreased, and the order of each of the IIR type filters Sn is increased or decreased from the Mth order to generate the error E Set the filter part to reduce
Digital signal processing device. The filter setting unit calculates the error E as an absolute value En of a difference between the gain value Dn of the desired frequency response characteristic D and the gain value Hn of the realized frequency response characteristic H at the frequency value Fn, and the error value The cutoff frequency value fc of the corresponding IIR filter Sn is changed and set so that En becomes smaller than a predetermined value, and the gain value Dn + 1 of the desired frequency response characteristic D at the adjacent frequency value Fn + 1 An absolute value En + 1 of a difference from the gain value Hn + 1 of the realized frequency response characteristic H is calculated, the order M of the IIR filter Sn is increased so that the error value En + 1 is smaller than a predetermined value, and the IIR type When the order M of the filter Sn is changed, the error value En and the error value En + 1 are recursively calculated, and the error E is more than a predetermined value. Setting the filter unit so as to fence,
The digital signal processing apparatus according to claim 1. A digital signal processing method for giving a predetermined frequency response characteristic to an audio signal,
A filter unit is configured by connecting a plurality of N stages (N: an integer of 2 or more) in series of M-th order (M: integer of 1 or more) IIR filters Sn having a shelf-type characteristic Hn indicating a cutoff frequency fc and a gain gn. And steps to
Inputting the audio signal to the filter unit; outputting the audio signal from the filter unit;
The desired characteristic setting unit of the filter unit sets a desired value response characteristic D of the filter unit by setting a plurality of (N + 1) sets of set values (Fn, Gn) including a set of the frequency value Fn and the gain value Gn. Steps,
The filter setting unit of the filter unit determines the cutoff frequency fc and the gain gn corresponding to the set values (Fn, Gn) of the desired characteristic setting unit, and sets each IIR filter Sn of the filter unit. Steps to set,
Including
The filter setting unit calculates an actual frequency response characteristic H of the filter unit, calculates an error E between the desired frequency response characteristic D and the actual frequency response characteristic H, and receives the error E to receive the filter Increasing or decreasing the cutoff frequency fc of each of the plurality of IIR type filters Sn, and increasing or decreasing the respective orders of the IIR type filters Sn from the Mth order to reduce the error E Setting a part, and
Digital signal processing method. In the filter setting unit, calculating the error E as an absolute value En of a difference between a gain value Dn of the desired frequency response characteristic D and a gain value Hn of the realized frequency response characteristic H at the frequency value Fn; Changing and setting the cut-off frequency value fc of the corresponding IIR filter Sn so that the error value En becomes smaller than a predetermined value, and the gain value of the desired frequency response characteristic D at the adjacent frequency value Fn + 1 Calculating the absolute value En + 1 of the difference between Dn + 1 and the gain value Hn + 1 of the realized frequency response characteristic H, and increasing the order M of the IIR filter Sn so that the error value En + 1 is smaller than a predetermined value. And when the order M of the IIR filter Sn is changed, the error value En and the error value En + 1 Repeatedly calculated recursively, comprises the steps of setting the filter unit so as to be smaller than a predetermined value said error E, and
The digital signal processing method according to claim 3.