JP2012212909A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability in wiring.SOLUTION: A semiconductor device manufacturing method comprises the steps of: sequentially forming a wiring layer 11 and an interlayer insulation film 12 on a semiconductor substrate; forming trench grooves 13 in the interlayer insulation film 12 and via holes 14 reaching the wiring layer 11 in the trench grooves 13; depositing a metal film 15 made from any one of titanium, zirconium and manganese or an alloy of titanium, zirconium and manganese in the trench grooves 13, in the via holes 14 and on the interlayer insulation film 12; etching the metal film 15 on bottoms of the via holes 14 by using a sputtering method, and depositing a metal film 16 made from any one of tantalum and tungsten, or an alloy of tantalum and tungsten on bottoms and sidewalls of the trench grooves 13 and sidewalls of the via holes 14; further generating a new metal film on the sidewalls of the via holes 14 by respective metals; and forming a wiring layer by filling a conductive material 17a in the via holes 14 and the trench grooves 13.

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure and a semiconductor device.

  In recent years, the number of transistors mounted on a single chip is increasing with the demand for higher performance and higher integration by miniaturization of transistor dimensions. When the number of transistors exceeds several thousand, it is impossible to make all connections with only one layer of metal wiring. Similarly, since the chip size increases, the wiring length between circuit blocks becomes long, and the propagation delay of the electric signal through the wiring increases.

  In order to solve these problems, a multilayer wiring structure in which metal wirings are interconnected via via holes is used. Further, low resistance copper (Cu) is adopted as a metal wiring material. When forming the Cu wiring, it is necessary to form a barrier layer for preventing the diffusion of Cu between the interlayer insulating film and the Cu wiring.

In the following, two conventional examples relating to a method for manufacturing a semiconductor device having a multilayer wiring structure will be described.
As Conventional Example 1, FIGS. 11 and 12 are schematic cross-sectional views of a method of manufacturing a semiconductor device having a conventional multilayer wiring structure. 11 and 12 show a semiconductor device having a Cu multilayer wiring structure disclosed in Non-Patent Document 1. FIG.

  First, a Cu layer 101d is further embedded on the entire surface of a tantalum (Ta) film 101c, which is a Cu diffusion prevention layer (barrier layer) formed on the entire surface of a trench groove opened using a hard mask film in the insulating layer 101a. The wiring layer 101 is formed using a CMP (Chemical Mechanical Polishing) method.

An interlayer insulating film 102 is further formed on the wiring layer 101 via a Cu barrier insulating film 102a.
An opening made of the via hole 103 and the trench groove 104 is formed in the interlayer insulating film 102 using the hard mask film 102b.

  Then, a Ta film 105 is formed as a barrier layer on the entire surface of the via hole 103, the trench groove 104, and the hard mask film 102b. The Ta film 105 is deposited using a long throw sputtering method on a hard mask film 102b where the target power source is 1 kW to 18 kW, the substrate bias is 0 W, and the flat portion, that is, the trench groove 104 is not formed. The Ta film 105 was deposited to a thickness of 15 nm under the conditions of a speed (Vd) of 1 nm / sec and an etching speed (Ve) of 0 nm / sec (above, FIG. 11A).

  Next, a process of sputter etching the Ta film 105 deposited on the bottom of the via hole 103 is performed while sputtering using a Ta target. That is, the Ta film 105 formed on the bottom of the via hole 103 is etched with Ta ions 106 or argon (Ar) ions (not shown). In this method, while the Ta film 105 is formed by the sputtering method, the deposited Ta film 105 and a part of the base are sputter-etched simultaneously with Ta ions 106 and Ar ions. Etching causes Ta ions scattered from the bottom of the via hole 103 to adhere to the sidewalls of the via hole 103 and the trench groove 104, and the Ta film 105 at the bottom of the via hole 103 is removed. Further, a part of the Cu layer 101d at the bottom of the via hole 103 may be removed. In this etching, sputtering is performed, the target power source is set to 1 kW to 5 kW, the substrate bias is set to 200 W to 400 W, and the ratio of Vd and Ve of the Ta film 105 on the flat portion, that is, the hard mask film 102b (Vd / Ve). ) Is sputtered so that Vd / Ve ≦ 1, for example, Vd is 0.7 nm / sec and Ve is 0.9 nm / sec (refer to FIG. 11B). Under these conditions, the Ta film 105 is intensively sputter-etched at the bottom of the via hole 103, and a shape as shown in FIG. 11B can be obtained. Here, the Ta film 105 formed in the via hole 103 is removed in order to suppress sheet resistance.

  Note that the Ta film 105 at the bottom of the via hole 103 removed by etching may not be completely removed and may remain a little. In this case, the film thickness at the bottom of the via hole 103 is thinner than the film thickness at the bottom of the trench groove 104. Further, the ions used in the etching are Ar ions as an example here, but it is also possible to perform etching in the same manner even if they do not react with Ta, for example, helium (He) or xenon (Xe). .

Next, after the removal of the Ta film 105 at the bottom of the via hole 103, a seed Cu film 107a is formed by sputtering (refer to FIG. 12A).
Then, the via hole 103 and the trench groove 104 are embedded on the seed Cu film 107a by plating the Cu layer 107 (refer to FIG. 12B).

Finally, the Cu layer 107 and the Ta film 105 on the hard mask film 102b are removed by using a CMP method to form a semiconductor device having a multilayer wiring structure (see FIG. 12C).
For reference, the results of evaluating a semiconductor device having a multilayer wiring structure formed in this way will be described below.

  First, the result of observing a semiconductor device having a multilayer wiring structure formed by the above method with a STEM (Scanning Transmission Electron Microscopy) will be described.

  FIG. 13 is a STEM observation photograph of a cross section of a semiconductor device having a Cu multilayer wiring structure. In addition, the shape of the trench groove 104 in the schematic cross-sectional views of FIGS. 11 and 12 is a T-shape, whereas in FIG. 13, the L-shape is inverted. The diameter of the via hole 103 is 100 nm, and the width of the trench groove 104 (in the direction perpendicular to the paper surface) is 100 nm.

By the above method, it can be confirmed from FIG. 13 that the Cu layer 107 is formed on the wiring layer 101 and the Ta film 105 is formed around the Cu layer 107.
Since the Ta film 105 at the bottom of the via hole 103 and the trench groove 104 is etched mainly using Ta ions 106, the Ta film 105 remains at the bottom of the via hole 103 as a result. The thickness of the film 105 is extremely thinner than that of the trench groove 104, and the wiring layer 101 below the bottom of the via hole 103 is also etched to form a recess. Then, when the Ta film 105 deposited on the bottom of the via hole 103 is etched, scattering of the etched Ta film 105 adheres to the sidewall of the via hole 103.

Next, the results of XRD (X-Ray Diffraction) performed on a semiconductor device having a multilayer wiring structure formed by the above method will be described.
FIG. 14 is a graph showing the results of XRD performed on a tantalum layer constituting a semiconductor device having a conventional multilayer wiring structure.

As can be seen from FIG. 14, the Ta film 105 on the interlayer insulating film 102 exhibits crystallinity, and the Ta film 105 is in the α phase.
Next, as a conventional example 2, a case of forming a wiring in which a titanium (Ti) layer and a Ta layer are stacked in via holes and trench groove openings formed in an interlayer insulating film and Cu is embedded thereon will be described. To do.

FIG. 15 is a schematic cross-sectional view of another method for manufacturing a semiconductor device having a conventional multilayer wiring structure. In FIG. 15, the same components as those in FIGS.
First, the wiring layer 101 is formed by further embedding a Cu layer 101d over the entire surface of the Ti film 101e and the Ta film 101c formed in the entire trench groove opened using the hard mask film 101b in the insulating layer 101a. Here, the Ti film 101e is formed because an improvement in adhesion between the Ta film 101c and the interlayer insulating film 102 is expected.

An interlayer insulating film 102 is further formed on the wiring layer 101 via a Cu barrier insulating film 102a.
An opening made of the via hole 103 and the trench groove 104 is formed in the interlayer insulating film 102 using the hard mask film 102b.

  Then, a Ti film 108 is formed on the entire surface of the via hole 103, the trench groove 104, and the hard mask film 102b. The Ti film 108 is formed using a long throw sputtering method under conditions where the target power source is 1 kW to 18 kW, the substrate bias is 0 W to 500 W, Vd is 2.0 nm / sec, and Ve is 0.3 nm / sec. Thus, the Ti film 108 was formed to a thickness of 13 nm.

  Further, a Ta film 105 is formed on the entire surface of the Ti film 108. The Ta film 105 is formed by using a long throw sputtering method under conditions where the target power source is 1 kW to 18 kW, the substrate bias is 0 W to 500 W, Vd is 1.4 nm / sec, and Ve is 0.8 nm / sec. Thus, the Ta film 105 was formed to have a thickness of 10 nm. Incidentally, since Vd / Ve> 1, the bottoms of the via holes 103 and the trench grooves 104 are hardly etched (depicted in FIG. 15A).

Next, a seed Cu film 107a is formed on the formed Ta film 105 by sputtering.
Then, the Cu layer 107 is plated and deposited so as to cover the entire surface of the seed Cu film 107a, thereby filling the via hole 103 and the trench groove 104 (FIG. 15B).

Finally, the Cu layer 107, the Ti film 108, and the Ta film 105 on the hard mask film 102b are removed using a CMP method, and a semiconductor device having a multilayer film structure is formed.
The results of evaluating a semiconductor device having a multilayer wiring structure formed in this way will be described below for reference.

Next, a case where XRD is performed on a semiconductor device having a multilayer wiring structure formed by the above method will be described.
FIG. 16 is a graph showing the results of XRD performed on a tantalum layer and a titanium layer constituting another semiconductor device having a conventional multilayer wiring structure.

When the Ta film 105 is formed on the Ti film 108, the crystallinity of the Ta film 105 becomes an α phase as shown in FIG. 16 (see, for example, Non-Patent Document 2).
A semiconductor device having a multilayer wiring structure can be obtained by the manufacturing method as described above.

H. H. Sakai, N.I. N. Ohtsuka, T. T. Tabira, T. T. Kouno, M.C. M. Nakaishi, M.N. Miyajima, “Nobel PVD process of barrier metal for Cu interconnects extendable to 45 nm node and beyond”, Advanced Metallization Conference (AMC), San Diego, October 17, 2006 19th, p. 33-p. 34 G. S. G. S. Chen, P.A. Y. Lee, P. Y. Lee T.A. S. T. Chen, “Phase formation behavior and diffusion barrier property of reactively sputtered tantalum-based thin films used in semiconductor metallization”, Thin Solid Films, 1999, 353, p. 264-p. 273

However, the above-described conventional semiconductor device manufacturing methods 1 and 2 have a problem that the seed Cu layer is poorly embedded in the via hole.
The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device manufacturing method and a semiconductor device with improved wiring reliability.

  In the present invention, in order to solve the above problems, a step of forming a first wiring layer on a semiconductor substrate, a step of forming an interlayer insulating film on the first wiring layer, and a trench groove in the interlayer insulating film And a step of forming a via hole in the trench groove reaching the first wiring layer, and a first metal made of a first metal in the trench groove, in the via hole and on the interlayer insulating film Etching the first metal film at the bottom of the via hole using a first deposition step for forming a film and a sputtering method, and forming the bottom and sidewall of the trench groove and the sidewall of the via hole A second film forming step of forming a second metal film made of a second metal, and a step of filling the via hole and the trench groove with copper to form a second wiring layer. And the first metal is titanium, zirconium and manga. Is any, or an alloy thereof of said second metal is tantalum, or tungsten, or a method of manufacturing a semiconductor device which is characterized in that an alloy thereof is provided.

  In the present invention, in order to solve the above-mentioned problem, a first wiring layer formed on a semiconductor substrate, an interlayer insulating film formed on the first wiring layer, and the interlayer insulating film are formed. The trench groove, the via hole reaching the first wiring layer formed in the trench groove, and the first metal formed on the bottom and side walls of the trench groove and the side walls of the via hole. A first metal film, a second metal film made of a second metal formed on the bottom and side walls of the trench groove and the side wall of the via hole, and formed on the side wall of the via hole; A third metal film having the first metal and the second metal; and a second wiring layer made of copper embedded in the via hole and the trench groove. The metal is one of titanium, zirconium and manganese, or these An alloy, said second metal is tantalum, or tungsten, or a semiconductor device which is characterized in that an alloy thereof is provided.

  In such a semiconductor device manufacturing method and semiconductor device, diffusion of the element of the first metal film into the copper of the embedded second wiring layer can be prevented, and an increase in resistance can be suppressed. Since the elements of the first metal film and the copper element react with each other to improve the copper coverage, the wiring reliability can be improved.

It is a cross-sectional schematic diagram about the outline | summary of the manufacturing method of the semiconductor device of this invention. It is a cross-sectional schematic diagram (the 1) of the manufacturing method of the semiconductor device in embodiment of this invention. It is a cross-sectional schematic diagram (the 2) of the manufacturing method of the semiconductor device in embodiment of this invention. It is the graph which showed the resistance value of the semiconductor device in this Embodiment. It is a STEM observation photograph of the section of the semiconductor device which has the multilayer wiring structure in an embodiment. It is a phase diagram of copper and titanium, copper and tantalum. It is a graph of the film thickness of seed Cu with respect to the aspect ratio of a via hole. It is a cross-sectional schematic diagram of the via hole in which the EDX analysis in this Embodiment is performed. It is the observation photograph by STEM of the cross section of the via hole in which FIB processing was performed. It is an EDX analysis result of the trench groove | channel in this Embodiment. It is a cross-sectional schematic diagram of the manufacturing method of the semiconductor device which has the conventional multilayer wiring structure (the 1). It is a cross-sectional schematic diagram (the 2) of the manufacturing method of the semiconductor device which has the conventional multilayer wiring structure. It is a STEM observation photograph of the section of the semiconductor device which has Cu multilayer wiring structure. It is a graph which shows the result of having performed XRD with respect to the tantalum layer which comprises the semiconductor device which has the conventional multilayer wiring structure. It is a cross-sectional schematic diagram of another manufacturing method of a semiconductor device having a conventional multilayer wiring structure. It is a graph which shows the result of having performed XRD with respect to the tantalum layer and titanium layer which comprise another semiconductor device which has the conventional multilayer wiring structure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments.
First, an outline of the present invention will be described, and then an embodiment of the present invention will be described.

FIG. 1 is a schematic cross-sectional view of an outline of a method for manufacturing a semiconductor device of the present invention.
In the method for manufacturing the semiconductor device 10 of the present invention, first, the wiring layer 11 is formed by embedding a conductive material in the insulating layer formed on the semiconductor substrate.

An interlayer insulating film 12 is formed on the wiring layer 11, and a trench groove 13 and a via hole 14 reaching the wiring layer 11 are formed in the trench groove 13.
Then, for example, a Ti film is formed as a metal film 15 on the surfaces of the trench groove 13, the via hole 14, and the interlayer insulating film 12 (the above, FIG. 1A).

  Next, while etching the metal film 15 at the bottom of the via hole 14 using a sputtering method, a Ta film, for example, which is a barrier layer is formed as a metal film 16 on the surface of the metal film 15. In this step, since the metal film 16 is formed while etching the metal film 15 at the bottom of the via hole 14, the metal film 16 is hardly formed at the bottom of the via hole 14, and the metal film 15 is removed. Then, the wiring layer 11 is also etched (above, FIG. 1B). However, the metal film 15 may be partially removed without being completely eliminated.

  Finally, the via hole 14 and the trench groove 13 are filled with a conductive material 17a to form a metal wiring. Then, by removing the upper portion of the conductive material 17a, the metal film 16, and the metal film 15 by CMP, the semiconductor device 10 having a multilayer wiring structure can be obtained (FIG. 1C).

  In the above manufacturing method, after the metal film 15 is formed, the metal film 16 is formed while etching the metal film 15 at the bottom of the via hole 14. However, the metal film 16 is formed on the metal film 15. After that, the metal film 15 and the metal film 16 at the bottom of the via hole 14 may be etched.

  In the manufacturing method of the semiconductor device 10 as described above, the metal film 16 is formed on the metal film 15 while etching the metal film 15 at the bottom of the via hole 14, thereby forming the metal film on the sidewall of the via hole 14. A metal alloy film is formed on the element 16 by the elements of the metal film 15 and the metal film 16 scattered by etching. Further, even when the metal film 16 is formed on the metal film 15 and then the metal film 15 and the metal film 16 at the bottom of the via hole 14 are etched, a metal alloy film is similarly formed.

Next, embodiments of the present invention will be described in more detail with reference to the drawings.
In the embodiment of the present invention, a case where etching is performed after the formation of the second metal film is taken as an example.

2 and 3 are schematic cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
First, the insulating layer 21a is etched to form a trench groove in the insulating layer 21a.
Next, a Ti film 21b and a Ta film 21c are sequentially formed on the entire surface, and a Cu layer 21d is laminated so as to cover the Ti film 21b and the Ta film 21c.

Then, the wiring layer 21 is formed by the CMP method.
On the wiring layer 21, a Cu barrier insulating film 22c, an interlayer insulating film 22a, an interlayer insulating film 22b, and a hard mask film 22d are sequentially formed.

  Next, the interlayer insulating film 22a and the interlayer insulating film 22b are opened, and a trench groove 23 and a via hole 24 are formed. The interlayer insulating film 22a and the interlayer insulating film 22b may be different layers or a single layer made of the same material.

  A Ti film 25 is formed on the entire surface of the trench groove 23, the via hole 24, and the hard mask film 22d. For forming the Ti film 25, for example, using a long throw sputtering method, the target power source is 1 kW to 18 kW, the substrate bias is 0 W to 500 W, Vd is 2.0 nm / sec, and Ve is 0.3 nm / sec. Under the conditions, the Ti film 25 was formed to a thickness of 13 nm (FIG. 2A).

  Further, a Ta film 26 is formed on the entire surface of the Ti film 25. The Ta film 26 is formed by using, for example, a long throw sputtering method, a target power source of 1 kW to 18 kW, a substrate bias of 0 W, a flat portion, that is, a Vd in a region where the trench groove 23 is not formed. Under the conditions of 1.0 nm / sec and Ve of 0 nm / sec, the Ta film 26 was formed to a thickness of 10 nm (FIG. 2B).

  Next, the Ti film 25 and the Ta film 26 formed on the bottom of the via hole 24 are etched with Ta ions 26a, Ar ions (not shown) or the like by sputtering using a Ta target. For example, the target power supply is 1 kW to 5 kW, the substrate bias is 200 W to 400 W, Vd is 0.7 nm / sec and Ve is 0.9 nm / sec, that is, Vd in the flat portion, that is, the region where the trench groove 23 is not formed. Sputtering was performed under the conditions of / Ve ≦ 1.

  Under such conditions, sputter etching is concentrated on the bottom of the via hole 24, and the Ti film 25 and the Ta film 26 formed on the bottom of the via hole 24 are removed. That is, a condition that the Vd / Ve ratio at the bottom of the via hole 24 is smaller than the Vd / Ve ratio at the flat part may be selected. In this case, it varies depending on the aspect ratio of the via hole 24 and other conditions. In that sense, the above-described sputtering conditions are merely examples. Then, the Ta film 26 and the Ti film 25 scattered from the bottom of the via hole 24 and the Ta ions 26a scattered from the target are deposited as a titanium tantalum (TiTa) film 27 on the sidewall of the via hole 24 (FIG. 3A). )).

  As shown in FIG. 3A, a Ta film 26 which is a Cu barrier layer is formed on the sidewall and bottom surface of the trench groove 23 and the sidewall of the via hole 24. Further, a TiTa film 27 is formed on the Ta film 26 on the side wall of the via hole 24. Since the Ta film 26 is formed on the bottom and side walls of the trench 23, the Ti film 25 does not directly contact the Cu layer 29 to be formed later. For this reason, Ti element can be prevented from diffusing into the Cu layer 29 of the metal wiring, and an increase in resistance due to the Ti element can be prevented.

  It should be noted that the Ti film 25 formed on the bottom of the via hole 24 may remain slightly after being etched due to the etching of the bottom of the via hole 24. In this case, the film thickness at the bottom of the via hole 24 is thinner than the film thickness at the bottom of the trench groove 23. On the other hand, the ions used in the etching are Ar ions as an example here, but it is also possible to perform etching in the same manner even when Ta or the like does not react with Ta, for example.

  Next, a seed Cu film 28 serving as an electrode when forming a Cu layer 29 of a metal wiring to be formed later is formed over the entire opening of the trench groove 23 and the via hole 24 by sputtering. At this time, the TaTi film 27 is formed on the side wall of the via hole 24, and the Cu element of the seed Cu film 28 reacts with the Ti element of the TaTi film 27, so the side wall of the seed Cu film 28 and the via hole 24. Is improved (FIG. 3B).

  Finally, the Cu layer 29 is deposited by plating to fill the via hole 24 and the trench groove 23, and the Cu layer 29, the Ta film 26, and the Ti film 25 on the hard mask film 22d are removed by using the CMP method. A semiconductor device 20 having a wiring structure is formed (FIG. 3C).

  When this step is used, the TiTa film 27 can be formed on the Ta film 26 on the side wall of the via hole 24, and the formation of the seed Cu film 28 in the via hole 24 is facilitated. Further, since the TiTa film 27 can be intensively formed on the inner wall of the via hole 24, Ti diffuses into the Cu layer 29 of the metal wiring formed inside the trench groove 23 and the resistance of the Cu layer 29 increases. The effect of suppressing this is also obtained.

  In the present embodiment, the Ta film 26 is formed in the shape of the Ti film 25, for example, 10 nm, and then the bottom of the via hole 24 is etched using a Ta target under the condition of Vd / Ve ≦ 1, Another embodiment is also conceivable in which the Ta film 26 is not deposited on the Ti film 25 and the bottom of the via hole 24 is etched using a Ta target under the condition of Vd / Ve ≦ 1. Also in this case, the TiTa film 27 can be deposited on the side wall of the via hole 24. In any embodiment, after etching the bottom of the via hole 24, a Ta film may be further deposited by sputtering from 3 nm to 7 nm, for example, 5 nm. This additional Ta film is formed to be about 20% of the thickness of the Ta film 26 formed on the sidewall and bottom of the trench groove 23 (for example, when 5 nm is deposited on the bottom of the trench groove 23). The additional Ta film is deposited on the side wall of the via hole 24 by about 1 nm.) Thus, since the Ta film deposited on the side wall of the via hole 24 is very thin, the effect of improving the Cu contact characteristics by the TiTa film 27 is not hindered. Note that this additional Ta film formation process may be applied to the embodiment described with reference to FIGS. In this case, the Ti film 25 and the Ta film 26 are formed, the bottom of the via hole 24 is sputter-etched, the additional Ta film is formed, and the Cu layer 29 is formed.

Next, the resistance value of the semiconductor device 20 shown in FIG. 3 will be described below.
FIG. 4 is a graph showing the resistance value of the semiconductor device in the present embodiment.
4, in the conventional example 1, the conventional example 2, and the semiconductor device according to the present embodiment, the x-axis indicates the chain resistance value [Ω], and the y-axis indicates the cumulative probability [%] with respect to the resistance value. 4A shows the state immediately after the wafer is completed, that is, immediately after the wafer process out, and FIG. 4B shows the case where the wafer is left in the high temperature environment of 100 to 250 ° C. for 400 to 600 hours after the wafer process out. After that, each case is shown.

  After the wafer process out of FIG. 4A, the chain resistance of the semiconductor device of Conventional Example 2 is higher than that of Conventional Example 1 and this embodiment. On the other hand, it can be seen that the semiconductor devices of Conventional Example 1 and the present embodiment both have stable chain resistance.

  Thereafter, when left in a high temperature environment for 400 hours to 600 hours, as shown in FIG. 4B, the chain resistance of Conventional Example 2 becomes higher, and it can be understood that the chain resistance of Conventional Example 1 also increases. On the other hand, it was found that the chain resistance of the semiconductor device of the present embodiment is still stable and hardly changed immediately after the wafer process out.

  That is, according to the manufacturing method of the present embodiment, the Ti film 25 is not directly exposed to the seed Cu film 28 or the Cu layer 29 by the Ta film 26 at the bottom of the trench groove 23, but the Ti element seed Cu film 28 or the Cu layer 29. The diffusion into the inside is prevented, and the increase in resistance due to the Ti element can be suppressed. Furthermore, by the manufacturing method of the present embodiment, the Ti element of the TiTa film 27 generated on the side wall portion of the via hole 24 and the Cu element of the seed Cu film 28a react to generate the CuTi film 28a, and the seed Cu The contact between the film 28a and the TiTa film 27 is improved, and the wiring reliability is improved.

The reason why such a result is shown will be described below in accordance with the evaluation result of the semiconductor device 20.
First, the result of observing the semiconductor device 20 formed by the manufacturing method according to the above embodiment with the STEM will be described. In the following description, the components used so far will be described using the same reference numerals.

  FIG. 5 is an STEM observation photograph of a cross section of a semiconductor device having a multilayer wiring structure in the embodiment. 2 and 3, the cross-sectional shape of the trench groove 23 and the via hole 24 in the schematic cross-sectional view is a T-shape, whereas in FIG. 5, the L-shape is inverted. Yes. The diameter of the via hole 24 is 100 nm, and the width of the trench groove 23 (in the direction perpendicular to the paper surface) is 100 nm. Further, the film thickness of the formed Ti film 25 is 13 nm in FIG. 5A and 10 nm in FIG. 5B, respectively.

  In FIG. 5A, since the Ta film 26 and the Ti film 25 at the bottom of the via hole 24 are etched mainly by Ta ions 26a, the film thickness of the Ta film 26 at the bottom of the via hole 24 is It can be confirmed that the thickness is extremely smaller than the thickness of the Ta film 26 at the bottom.

  On the other hand, in FIG. 5B as well, the Ta film 26 remains at the bottom of the via hole 24, but the bottom of the via hole 24 is less than the case where the Ti film 25 is 13 nm (FIG. 5A). The thickness of the Ta film 26 at the bottom of the via hole 24 is extremely smaller than the thickness of the Ta film 26 at the bottom of the trench groove 23, and the Cu layer 29 is also formed on the upper surface of the wiring layer 21. Can be confirmed.

Therefore, it can be confirmed that the Ta film 26 is formed at the bottom of the trench groove 23 and the Ti film 25 is prevented from being exposed to the seed Cu film 28a and the Cu layer 29.
Next, the relationship between Ta and Ti with Cu will be described.

FIG. 6 is a phase diagram of copper and titanium, copper and tantalum.
FIG. 6A is a graph showing a phase diagram of Cu and Ti. According to this graph, it can be seen that Ti reacts relatively easily with Cu. On the other hand, FIG. 6B is a graph showing a phase diagram of Cu and Ta, and it can be seen that Ta hardly reacts with Cu.

  From this, Ti and Cu are likely to react. For example, when the seed Cu film 28 is directly formed on the Ti film 25, it is expected that Ti element will be diffused. Upon reaction, the resistance is expected to increase in the via hole 24 and the Cu layer 29 of the metal wiring. However, in the present embodiment, as already described, the Ta film 26 serves as a barrier, the diffusion of the Ti element of the Ti film 25 in the Cu layer 29 is prevented, and the resistance does not increase. The TiTa film 27 generated on the side wall of the via hole 24 contains Ti element, so that the contact between the seed Cu film 28 and the side wall of the via hole 24 is improved. This point will be described below.

Next, the film thickness of the seed Cu film for these aspect ratios will be described.
FIG. 7 is a graph of the thickness of the seed Cu with respect to the aspect ratio of the via hole.
In FIG. 7, the x-axis indicates the aspect ratio of the via hole, and the y-axis indicates the film thickness of the seed Cu film formed on the sidewall of the via hole.

  According to this, in the via hole having an aspect ratio of 1.5 or less, the same result was obtained in Conventional Example 1 and this embodiment. On the other hand, in the via hole having an aspect ratio of 2.5, it was shown that the seed Cu film was formed thicker in this embodiment than in Conventional Example 1. When the seed Cu film on the side wall of the via hole is formed thick, the embedding performance is improved. Therefore, the present embodiment has a high embedding performance. In addition, when this embedding performance is low, voids (voids) are generated in the via holes and the wiring reliability is lowered. Therefore, it can be seen that this embodiment has a high wiring reliability.

Next, the analysis by the EDX (Energy Dispersive X-ray) of the cross section of the via hole of this Embodiment is demonstrated.
FIG. 8 is a schematic cross-sectional view of a via hole in which EDX analysis is performed in the present embodiment. In FIG. 8, the formation and formation of the seed Cu film 28 and the Cu layer 29 are omitted.

  In general, as shown in FIG. 8A, the planar cross section of the opening of the via hole formed in the semiconductor device is circular. However, when FIB (Focused Ion Beam) processing for performing EDX analysis is performed, interference occurs in the observation result due to the curvature of the opening of the via hole. Therefore, here, as shown in FIG. 8B, assuming that the cross section of the plane of the opening is a quadrangle, FIB processing was performed and EDX observation was performed. Further, in the embodiment of the present invention, the bottom of the via hole 24 is etched so that the Ta film 26 in the trench groove 23 remains. However, in this sample, the EDX analysis is performed by approximating the via hole to the trench groove. For the purpose, the bottom of the trench groove 23 was etched so that the Ta film 26 in the trench groove 23 did not remain. A trench groove 23 having a width of 70 nm is formed, and a Ti film 25 is formed to a thickness of 20 nm. A Ta film 26 is further formed on the Ti film 25. The Ta film 26 is formed by using a long throw sputtering method under the conditions of a target power supply of 1 kW to 18 kW, a substrate bias of 0 W, Vd of 1 nm / sec, and Ve of 0 nm / sec. Was formed to be 3 nm. Then, the Ta film 26 and the Ti film 25 formed on the bottom are etched. The conditions were a target power of 1 kW to 5 kW, a substrate bias power of 200 W to 400 W, a Ta film Vd = 0.7 nm / sec, Ve = 0.9 nm / sec, and a film formation time of 40 seconds.

And it shows about the STEM observation result of the cross section of the via hole which performed FIB processing.
FIG. 9 is an STEM observation photograph of a cross section of a via hole that has been subjected to FIB processing.
As already described, since the via hole is approximated to a trench groove, the shape is as shown in FIG. Moreover, the enlarged photograph of the bottom part of FIG. 9 (A) is FIG. 9 (B). It can be seen that the bottom of FIG. 9B is etched.

Next, an EDX analysis of the bottom of the trench groove subjected to the FIB processing in this way will be described.
FIG. 10 shows the EDX analysis result of the trench groove in the present embodiment. Note that the presence of various elements can be confirmed by EDX analysis, but attention is paid to the Ti element and the Ta element here.

  FIG. 10A is an enlarged view of FIG. 9B, in which a graph of the EDX analysis result is described corresponding to each film component. 10B and 10C, the x-axis indicates the distance from the FIB processing protection SOG film, and the y-axis indicates the number counted by the detector of the analyzer. Compared with the same element, the larger the counted number, the greater the atomic weight. FIG. 10C shows a low count number region in FIG. 10B.

  In particular, according to FIG. 10B, when the distance from the FIB processing protection SOG film increases, the presence of the TiTa film 27 can be confirmed first. Further, as the x-axis increases, Ta element peaks appear, and the presence of the Ta film 26 can be confirmed. In addition, the Ta element decreases, the Ti element peak appears, and the presence of the Ti film 25 can be confirmed. It can be seen that both the Ti element and the Ta element decrease, and the interlayer insulating film 22a exists.

  As described above, from the evaluation results of the semiconductor device according to the present embodiment, the Ti film and the Ta film formed on the bottom of the via hole while maintaining the structure of the Ta film covering the Ti film formed on the bottom of the trench groove. It can be seen that a TiTa film on the side wall of the via hole is formed by etching only. Therefore, the resistance increase due to the mixing of Ti element into the Cu layer filling the trench groove is suppressed, the Ti film and the Ta film which are high resistance films at the bottom of the via hole are removed, and the TiTa film generated on the sidewall of the via hole As a result, the embedding performance at the time of plating deposition is improved and the generation of voids (holes) is suppressed, and further, Ti elements are segregated at the grain interface of Cu due to the heat history applied by the process after plating deposition, and via holes are formed. It is possible to suppress the diffusion of voids (holes) and grain growth in the semiconductor layer and to improve the reliability between wirings.

  In the embodiment, the Ti film has good reactivity with Cu in addition to the Ti element, for example, zirconium (Zr), manganese (Mn), or two kinds of alloys of Ti, Zr, and Mn. May be. In addition to the Ta film, it may be, for example, tungsten (W) or an alloy of Ta and W having Cu diffusion preventing characteristics. In addition, the same effect can be obtained by combining the material systems that can constitute the present embodiment.

(Additional remark 1) The process of forming a 1st wiring layer on a semiconductor substrate,
Forming an interlayer insulating film on the first wiring layer;
Forming a trench groove in the interlayer insulating film and a via hole reaching the first wiring layer in the trench groove;
A first film forming step of forming a first metal film made of a first metal on the surfaces of the trench groove, the via hole, and the interlayer insulating film;
A second film forming step of etching the first metal film at the bottom of the via hole using a sputtering method and forming a second metal film made of a second metal on the entire surface;
A step of filling the via hole and the trench groove with a conductive material to form a second wiring layer;
A method for manufacturing a semiconductor device, comprising:

  (Additional remark 2) It has the 3rd film-forming process which forms the 3rd metal film which consists of the said 2nd metal on the whole surface after the said 1st film-forming process and before the said 2nd film-forming process. The method of manufacturing a semiconductor device according to appendix 1, wherein:

  (Supplementary Note 3) If the ratio of the deposition rate and the etching rate in the second film forming step is the deposition rate / etching rate, the deposition rate / etching rate at the bottom of the via hole is the deposition rate / etching in other regions. The method for manufacturing a semiconductor device according to appendix 1 or 2, wherein the second film forming step is performed under a condition smaller than the speed.

  (Additional remark 4) The 4th metal film which has the said 1st metal and the said 2nd metal is formed in the side wall of the said via hole by the said 2nd film-forming process, Additional remark 1 thru | or 1 characterized by the above-mentioned. 4. A method for manufacturing a semiconductor device according to any one of 3 above.

(Additional remark 5) Argon, helium, or xenon is used in the said 2nd film-forming process, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 4 characterized by the above-mentioned.
(Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the first metal is any one of titanium, zirconium, and manganese, or an alloy thereof. Method.

  (Additional remark 7) The said 2nd metal is either tantalum, tungsten, or these alloys, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 6 characterized by the above-mentioned.

(Additional remark 8) The said conductive material is copper, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 7 characterized by the above-mentioned.
(Supplementary note 9) The step of embedding the conductive material includes forming a seed copper film and depositing a copper wiring film on the seed copper film using a plating method. Production method.

(Additional remark 10) The said copper seed film | membrane is formed into a film by a sputtering method, The manufacturing method of the semiconductor device of Additional remark 9 characterized by the above-mentioned.
(Additional remark 11) After the said 2nd film-forming process, before the process of forming the said 2nd wiring layer, the process of depositing the 5th metal film which consists of said 2nd metal on the whole surface by sputtering method further 11. The method for manufacturing a semiconductor device according to any one of appendices 1 to 10, wherein the method includes:

(Additional remark 12) The 1st wiring layer formed on the semiconductor substrate,
An interlayer insulating film formed on the first wiring layer;
A trench groove formed in the interlayer insulating film;
A via hole reaching the first wiring layer formed in the trench groove;
A first metal film made of a first metal formed on the bottom and side walls of the trench groove and the surface of the side wall of the via hole;
A second metal film made of a second metal formed on the bottom and side walls of the trench groove and the surface of the side wall of the via hole;
A third metal film having the first metal and the second metal formed on the sidewall of the via hole;
A second wiring layer embedded in the via hole and the trench groove;
A semiconductor device comprising:

(Supplementary note 13) The semiconductor device according to supplementary note 12, wherein the first metal is any one of titanium, zirconium, and manganese, or an alloy thereof.
(Additional remark 14) The said 2nd metal is either tantalum, tungsten, or these alloys, The semiconductor device of Additional remark 12 or 13 characterized by the above-mentioned.

  (Additional remark 15) The said conductive material is copper, The semiconductor device of any one of Additional remark 12 thru | or 14 characterized by the above-mentioned.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Wiring layer 12 Interlayer insulation film 13 Trench groove 14 Via hole 15,16 Metal film 17a Conductive material

Claims (7)

Forming a first wiring layer on the semiconductor substrate;
Forming an interlayer insulating film on the first wiring layer;
Forming a trench groove in the interlayer insulating film and a via hole reaching the first wiring layer in the trench groove;
A first film forming step of forming a first metal film made of a first metal in the trench groove, in the via hole, and on the interlayer insulating film;
Using a sputtering method, the first metal film at the bottom of the via hole is etched, and a second metal film made of a second metal is formed on the bottom and side walls of the trench groove and the side wall of the via hole. A second film forming step of forming a film;
Filling the via hole and the trench groove with copper to form a second wiring layer;
Have
The first metal is any one of titanium, zirconium and manganese, or an alloy thereof.
The second metal is tantalum, tungsten, or an alloy thereof;
A method of manufacturing a semiconductor device.   After the first film forming step, and before the second film forming step, the method includes a third film forming step of forming a third metal film made of the second metal on the entire surface. A method for manufacturing a semiconductor device according to claim 1.   When the ratio between the deposition rate and the etching rate in the second film forming step is the deposition rate / etching rate, the deposition rate / etching rate at the bottom of the via hole is smaller than the deposition rate / etching rate in other regions. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second film forming step is performed under conditions.   4. The fourth metal film having the first metal and the second metal is formed on a side wall of the via hole by the second film forming step. A method for manufacturing a semiconductor device according to claim 1.   A step of depositing a fifth metal film made of the second metal on the second metal film by a sputtering method after the second film forming step and before the step of forming the second wiring layer. The method for manufacturing a semiconductor device according to claim 1, further comprising: A first wiring layer formed on the semiconductor substrate;
An interlayer insulating film formed on the first wiring layer;
A trench groove formed in the interlayer insulating film;
A via hole reaching the first wiring layer formed in the trench groove;
A first metal film made of a first metal formed on the bottom and side walls of the trench groove and the side walls of the via holes;
A second metal film made of a second metal formed on the bottom and side walls of the trench groove and the side walls of the via hole;
A third metal film having the first metal and the second metal formed on the sidewall of the via hole;
A second wiring layer made of copper embedded in the via hole and the trench groove;
Have
The first metal is any one of titanium, zirconium and manganese, or an alloy thereof.
The second metal is tantalum, tungsten, or an alloy thereof;
A semiconductor device characterized by the above.   7. The method according to claim 6, further comprising: a fourth metal film formed between the third metal film and the second wiring layer and made of the first metal and the copper. Semiconductor device.

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