JP2012212393A - Design method, design program, and design support device for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a design TAT of a semiconductor integrated circuit.SOLUTION: The design method for semiconductor integrated circuits according to the present invention implemented by a computer device 10 comprises: a step for disposing a logic cell 500 and a wiring cell 400 on a chip; a step for adding an antenna rule 122 for a gate 505 in the logic cell 500 to a first antenna library 101 of the wiring cell 400 to change the first antenna library 101 into a second antenna library 201; a step for connecting the wiring cell 400 to another logic cell 510 with a first wire 550; and a first verification step for verifying a ratio of the area of the first wire 550 to the area of the gate 505 according to the antenna rule 122 prescribed in the second antenna library 201.

Description

  The present invention relates to a semiconductor integrated circuit design method, a design program, and a design support apparatus, and more particularly to an automatic layout design of a semiconductor integrated circuit.

  Many plasma processes such as etching, ashing, ion implantation, and plasma CVD (Chemical Vapor Deposition) are used for manufacturing thin film devices such as semiconductor integrated circuits. In such a plasma process, there is a problem of destruction or damage (plasma damage) of the gate insulating film due to a charge-up phenomenon. Plasma damage occurs when charged particles in the plasma are captured by a conductor (for example, metal wiring) exposed in the plasma, and the captured charges reach the gate electrode of the transistor. For example, in an etching process for forming a signal wiring, the signal wiring functions as an antenna that captures charges from plasma. The charge current due to the charges captured by the signal wiring is concentrated on the gate insulating film through the gate electrode, and the gate insulating film is damaged.

  Since the magnitude of plasma damage is determined according to the current density of the charge current flowing through the gate insulating film, plasma damage in the manufacturing process can be reduced by controlling the area of the metal wiring that functions as the antenna and the area of the gate electrode. It becomes possible to do. Specifically, when designing a semiconductor integrated circuit, the layout pattern is designed so that the antenna ratio is equal to or less than a predetermined threshold value (antenna reference). Here, the antenna ratio indicates the ratio of the area of the signal wiring (metal wiring) connected to the gate to the area of the gate electrode (gate area) in the transistor. Usually, in the pattern verification after the layout design of the semiconductor integrated circuit, it is verified whether the antenna ratio satisfies the antenna standard. At this time, when the antenna ratio exceeds the antenna reference (antenna error), the layout pattern is corrected so that the antenna ratio satisfies the antenna reference. By such pattern verification and layout correction, it is possible to design a semiconductor integrated circuit that is less susceptible to plasma damage in the manufacturing process.

  A layout correction method performed to reduce plasma damage is described in, for example, Japanese Patent Application Laid-Open No. 2001-15605 (see Patent Document 1). Patent Document 1 describes a technique for removing an antenna error by changing a wiring connected to a cell having an antenna error to an upper layer and changing a terminal position of the cell.

  On the other hand, in an automatic layout design in a general logic product, placement and wiring are automatically performed so that an element-to-element timing error, a crosstalk noise error, and an antenna error (insulation breakdown) do not occur. However, in a large-capacity memory product, since the number of rows / columns of memory cells increases, the automatic placement and wiring area has a special shape such as a horizontally long shape or a cross shape. Therefore, the metal wiring in the memory product is a long distance wiring compared to a general logic product, and it is necessary to propagate the data signal at a high speed through the long distance wiring. When designing such a product, if random automatic wiring is performed, it is difficult to perform crosstalk noise convergence and timing synchronization of multi-bit bus wiring. For this reason, by using bus cells in which wiring is arranged in the order of signals in consideration of crosstalk noise and wiring cells that have idealized cells such as wiring only in the upper low-resistance layer, high-speed operation signal wiring, crosstalk Timing synchronization of noise countermeasure wiring or bus wiring is facilitated.

  For example, Japanese Patent Laid-Open No. 2005-268437 describes an automatic wiring layout method using wiring cells for the purpose of crosstalk countermeasures and wiring delay improvement (see Patent Document 2). In Patent Document 2, a wiring cell having wiring that does not cause an antenna error is prepared in advance, and this is inserted between circuit cells, thereby enabling automatic wiring without an antenna error.

  However, when the logic cells are connected using the wiring cells, it is necessary to connect the logic cells and the wiring cells by wiring depending on the cell size and the shape of the wiring area in which the cells are arranged. For example, when a wiring cell having a fixed shape is arranged in a wiring region having a special shape as described above, it is necessary to wire between the wiring cell and the logic cell. In Patent Document 2, since the antenna effect due to the wiring connecting the cells is not taken into consideration, an antenna error may occur in antenna verification after placement and routing, and layout correction may be required.

  The design TAT can be shortened by reducing the number of layout corrections after placement and routing. Therefore, in order to reduce the probability of an error in DRC (Design Rule Checking) after placement and routing, an automatic placement and routing tool capable of placement and routing that satisfies design rules and design constraints is desired.

  For example, a technique for performing antenna verification and crosstalk noise verification in the placement and routing phase is described in Japanese Patent Application Laid-Open No. 2004-171363 (see Patent Document 3). In Patent Document 3, wiring to a cell is performed while performing antenna verification so that a wiring area connected to a gate to be subjected to antenna verification satisfies an antenna standard set for the gate.

JP2001-15605 JP 2005-268437 A JP 2004-171363 A

  The technique described in Patent Document 3 describes a technique of performing wiring in consideration of the antenna effect, but does not describe arranging wiring cells in consideration of the antenna effect. In Patent Document 3, since wiring is performed so as not to cause an antenna error with respect to a gate in a logic cell, a wiring area is determined in consideration of an antenna rule (antenna standard) for the gate. For example, when a wiring cell is connected to a gate in a logic cell, a wiring cell having a wiring area connected to the gate is arranged so as to satisfy the antenna standard defined in the antenna library for the logic cell. . Further, when wiring is performed between the gate and the wiring cell, the wiring is performed with an area in consideration of the antenna reference. However, since the wiring area between the arranged wiring cell and another logic cell is determined based on the antenna library of the wiring cell, wiring having a size that causes an antenna error is formed for the gate. There is a risk.

  For example, as shown in FIG. 14, the wiring 503 connecting the gate 505 and the input terminal 501 in the logic cell 500, the wiring 551 between the input terminal 501 of the logic cell 500 and the wiring cell 400, and the wiring cell 400 are included. The total area of the wiring 403 to be set can be set at the time of automatic wiring in consideration of an antenna rule (antenna reference) defined for the gate 503. However, when automatic wiring is performed between the input terminal 401 of the wiring cell 400 and the output terminal 512 of the other logic cell 510, the wiring cell 400 does not have a gate, so the antenna rule defined for the gate 503 is taken into consideration. Wired without For this reason, when performing antenna verification after automatic placement and routing, the wiring 800 between the wiring cell 400 and another logic cell 510 may be determined as an antenna error.

  As described above, it is desired to reduce the number of locations that cause errors in the post-layout DRC in the placement and routing phase. However, when designing using a wiring cell in order to achieve a short TAT, there are cases where an antenna error portion cannot be removed in the placement and routing phase. Therefore, for further shortening the TAT, there is a demand for a technique that can eliminate an antenna error in the placement and routing phase even when a wiring cell is used.

  In order to solve the above problems, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Mode for Carrying Out the Invention] The number / symbol used in [Form] is added. However, the added numbers and symbols should not be used to limit the technical scope of the invention described in [Claims].

  A semiconductor integrated circuit design method according to the present invention is a semiconductor integrated circuit design method executed by a computer device (10), and according to a netlist (100) recorded in a storage device (13), a logic cell (500). ) And the wiring cell (400) on the chip, and the antenna rule (122) for the gate (505) in the logic cell (500) is added to the first antenna library (101) of the wiring cell (400). Thus, the step of changing the library for the first antenna (101) to the library for the second antenna (201), and the wiring cell (400) and the other logic cell (510) are connected by the first wiring (550). In accordance with the step and the antenna rule (122) defined in the second antenna library (201), the area of the gate (505) To comprise a first verification step of verifying the ratio of the area of the first wire (550).

  The design method is preferably realized by a design program executed by a computer.

  According to the present invention, the design TAT of a semiconductor integrated circuit can be shortened.

FIG. 1 is a plan view showing an example of the configuration of a design support apparatus for a semiconductor integrated circuit according to the present invention. FIG. 2 is a plan view showing an example of the structure of a wiring cell arranged by the design support apparatus according to the present invention. FIG. 3 is a diagram showing an example of the antenna library for the wiring cell shown in FIG. 2 recorded in advance in the design support apparatus according to the present invention. FIG. 4 is a diagram showing an example of the structure of a logic cell arranged by the design support apparatus according to the present invention. FIG. 5 is a diagram showing an example of the antenna library for the logic cell shown in FIG. FIG. 6 is a flowchart showing an example of the design operation of the semiconductor integrated circuit according to the present invention. FIG. 7A is a plan view showing an example of a chip layout during automatic placement and routing. FIG. 7B is a plan view showing an example of a chip layout during automatic placement and routing. FIG. 7C is a plan view showing an example of a chip layout after automatic placement and routing. FIG. 8 is a diagram showing an example of combination extraction data according to the present invention. FIG. 9 is a diagram illustrating an example of an antenna library of wiring cells changed during placement and routing. FIG. 10A is a plan view showing another example of a chip layout during automatic placement and routing. FIG. 10B is a plan view showing another example of the chip layout after automatic placement and routing. FIG. 11 is a diagram showing another example of a library for antennas of wiring cells changed during placement and routing. FIG. 12 is a flowchart showing another example of the design operation of the semiconductor integrated circuit according to the present invention. FIG. 13 is a diagram showing another example of the configuration of the design support apparatus for a semiconductor integrated circuit according to the present invention. FIG. 14 is a diagram showing an antenna error generation mechanism when wiring cells are arranged according to the prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same or similar reference numerals indicate the same, similar, or equivalent components.

  Embodiments of a semiconductor integrated circuit design method, a design program, and a design support apparatus according to the present invention will be described below with reference to the accompanying drawings. In the present embodiment, a semiconductor integrated circuit design support apparatus for designing a cell-based IC (Integrated Circuit) will be described as an example.

(Constitution)
With reference to FIGS. 1 to 5, the configuration of an embodiment of a semiconductor integrated circuit design support apparatus 10 (hereinafter referred to as a design support apparatus 10) according to the present invention will be described. FIG. 1 is a configuration diagram of an embodiment of a design support apparatus 10 according to the present invention. The design support apparatus 10 includes a CPU 11, a RAM 12, a storage device 13, an input device 14, and an output device 15 that are connected to each other via a bus 16. The storage device 13 is an external storage device exemplified by a hard disk and a memory. The input device 14 outputs various data to the CPU 11 and the storage device 13 by being operated by a user such as a keyboard and a mouse. The output device 15 is exemplified by a monitor and a printer, and outputs the layout result of the semiconductor device output from the CPU 11 so as to be visible to the user.

  The storage device 13 stores the placement and routing data 100, the antenna library 101 (hereinafter referred to as the antenna library 101), and the design program 300. In response to the input from the input device 14, the CPU 11 executes the design program 300 in the storage device 13 to perform cell layout and chip layout. At this time, various data and programs from the storage device 13 are temporarily stored in the RAM 12, and the CPU 11 executes various processes using the data in the RAM 12.

  The placement and routing data 100 includes a net list that is a logic circuit design result. More specifically, the placement and routing data 100 includes element information related to the connection relation, type, size (number of elements), etc. of elements and wirings constituting the cell (circuit), and diodes and transistors among the elements constituting the circuit. Element information relating to the operating conditions of the non-linear active element.

  The antenna library 101 includes information indicating the positions and wiring areas of terminals and wirings included in the cell. Specifically, the library for antenna 101 includes, among terminals included in a cell, terminal identifiers (terminal information 111) connected to wiring that can be antennas (antenna wiring), and wiring that can be antennas among wirings included in the cell. Antenna wiring information 112 including information for specifying a position (wiring layer) to be formed and an area (wiring area) of a region where the wiring is formed is provided. In addition to the terminal information 111 and the antenna wiring information 112, the logic cell antenna library 101 including the gate has an area of a region where the gate is formed (gate area 121) and a wiring layer with respect to the gate. A prescribed antenna rule 122 is provided.

  An example of the wiring cell antenna library 101 will be described with reference to FIGS. FIG. 2 is a diagram showing an example of the structure of the wiring cell 400 arranged by the design support apparatus according to the present invention. Referring to FIG. 2, the wiring cell 400 includes an input terminal 401, an output terminal 402, and a wiring 403 (second wiring). It is preferable that the wiring 403 is provided in the cell with a length and a wiring interval that do not cause, for example, a timing error or a crosstalk error.

  An example of the antenna library 101 of the wiring cell 400 shown in FIG. 2 is shown in FIG. In the antenna library 101 of the wiring cell 400, “Pin 401” indicating the input terminal 401 connected to the wiring 403 that can be the antenna wiring is defined as the terminal information 111, and the wiring 403 that can be the antenna wiring as the antenna wiring information 112. Information indicating the wiring area “7” and the first wiring layer “M1” in which the wiring 403 is formed is defined.

  An example of the logic cell antenna library 101 having a gate will be described with reference to FIGS. FIG. 4 is a plan view showing an example of the structure of a logic cell 500 (inverter cell) positioned by the design support apparatus according to the present invention. Referring to FIG. 4, the logic cell 500 includes an input terminal 501, an output terminal 502, a wiring 503 (third wiring), 504, a gate 505, and diffusion layers 506 and 507. The gate 505 is connected to the input terminal 501 through the wiring 503. The diffusion layers 506 and 507 are connected to the output terminal 502 by a wiring 504. With such a configuration, the logic cell 500 functions as an inverter that inverts an input signal from the input terminal 501 and outputs the inverted signal to the output terminal 502. Here, a wiring 503 connected to the gate 505 or a wiring (not shown) connected to the input terminal 501 can serve as an antenna wiring for the gate 505.

  An example of the antenna library 101 of the logic cell 500 shown in FIG. 4 is shown in FIG. In the antenna library 101 of the logic cell 500, “Pin 501” indicating the input terminal 501 connected to the gate 505 is defined as the terminal information 111, and the wiring area 503 of the wiring 503 that can be an antenna wiring is defined as the antenna wiring information 112. 2 ”and information indicating the first wiring layer“ M1 ”in which the wiring 503 is formed are defined. Further, in the antenna library 101 of the logic cell 500, the area “2” of the region in which the gate 505 is formed is defined as the gate area, and the antenna rule 122 includes the wiring connected to the gate 505 with respect to the area of the gate 505. A reference value of the area ratio is defined for each wiring layer. Here, the ratio of the wiring area of the first wiring layer “M1” to the gate area of the gate 505 (antenna reference) is defined as “500”, and the wiring area of the second wiring layer “M1” with respect to the gate area of the gate 505 is The ratio (antenna reference) is defined as “500”. As a result, the area of the wiring that can be connected to the gate 505 without an antenna error in both the first wiring layer and the second wiring layer is defined to be within 500 times “1000” of the gate area “2”. When the antenna rule 122 does not receive an evaluation (“0” is set for a wiring layer that is not subject to antenna verification).

(Operation)
The design support apparatus 10 according to the present invention executes the operation shown in FIG. 6 by executing the design program 300, and performs automatic placement and routing of the semiconductor integrated circuit. Details of the layout design operation (automatic placement and routing operation) according to the present invention will be described below with reference to FIGS. FIG. 6 is a flowchart showing an example of the design operation of the semiconductor integrated circuit according to the present invention.

  First, the design support apparatus 10 uses the placement and routing data 100 to place logic cells and wiring cells on the chip (step S10). Here, as shown in FIG. 7A, the wiring cell 400 is arranged between the logic cell 500 and the logic cell 510. In step S10, it goes without saying that cells (not shown) other than the logic cells 500 and 510 and the wiring cell 400 are also arranged on the chip.

  Referring to FIG. 7A, a logic cell 510 includes an input terminal 511, an output terminal 512, wirings 513 and 514, a gate 515, and diffusion layers 516 and 517. The gate 515 is connected to the input terminal 511 through the wiring 513. Diffusion layers 516 and 517 are connected to output terminal 512 by wiring 514. With such a configuration, the logic cell 510 functions as an inverter that inverts an input signal from the input terminal 511 and outputs the inverted signal to the output terminal 512. Here, a wiring 513 connected to the gate 515 and a wiring (not shown) connected to the input terminal 511 can serve as an antenna wiring for the gate 515.

  When the arrangement of the logic cells and the wiring cells is completed, the design support apparatus 10 extracts the combination of the input terminals of the arranged logic cells and the output terminals of the wiring cells serially (one to one) (step S11). Specifically, the design support apparatus 10 identifies a gate that requires antenna countermeasure wiring, and a combination of a terminal connected to the gate and a terminal of a wiring cell to be connected to the terminal is used as the combination extraction data 210. Extract. When there are a plurality of gates in a logic cell, a combination with a terminal of a wiring cell to be connected is extracted for each terminal connected to each of the plurality of gates. In the example shown in FIG. 7A, first, the gate 505 of the logic cell 500 is selected as the gate requiring the antenna countermeasure wiring. Then, the input terminal 501 connected to the gate 505 and the output terminal 402 of the wiring cell 400 to be connected to the input terminal 501 are extracted as the combination extraction data 210.

  FIG. 8 is a diagram showing an example of the combination extraction data 210 according to the present invention. The combination extraction data 210 includes a wiring cell name 211, a logic cell name 212, a net name 213, a wiring cell size 214, a wiring cell arrangement coordinate 215, a logic cell size 216, and a logic cell arrangement coordinate 217. The logic cell name 212 is the name of the logic cell having the gate selected as the antenna countermeasure wiring target, and the logic cell size 216 and the logic cell arrangement coordinates 217 indicate the size and arrangement position of the logic cell. The wiring cell name 211 is the name of the wiring cell connected to the gate selected as the antenna countermeasure wiring target, and the wiring cell size 214 and the wiring cell arrangement coordinates 215 indicate the size and arrangement position of the wiring cell. The net name 213 is information specifying the terminal pair extracted as a combination. For example, information “551” that associates the input terminal 501 of the logic cell 500 with the output terminal 402 of the wiring cell 400 is extracted as the net name 213.

  In step S11, a combination of a terminal in the logic cell connected to the gate to be antenna countermeasure wiring and a terminal of the wiring cell connected to the terminal is specified. Alternatively, a combination of a logic cell having a gate serving as an antenna countermeasure wiring target and a wiring cell connected to the logic cell is specified. In addition, the combination extraction data 210 includes information specifying a logic cell having a gate to be subjected to antenna countermeasure wiring and a position of the wiring cell connected to the gate on the chip.

  When the combination extraction data 210 is extracted in step S11, “1” is substituted into a variable N indicating that the combination extraction data 210 has been extracted. When the combination extraction data 210 is not extracted, “0” is substituted for the variable N. That is, when all the combinations of logic cells having gates that require antenna countermeasure wiring and wiring cells connected to the gates are extracted from all the arranged cells, “0” is assigned to the variable N. .

  The design support apparatus 10 has a variable N of “1” or “0”, and among the cells arranged on the chip, a combination of a logic cell having a gate serving as an antenna countermeasure wiring target and a wiring cell connected to the logic cell It is determined whether all of the above are extracted (step S12). More specifically, when the combination extraction data 210 is extracted in the combination extraction step (step S11) (the variable N is “1”), the design support apparatus 10 finishes extracting all cell combinations (terminal combinations). It is determined that the two extracted cells are adjacent to each other with reference to the extracted combination extraction data 210 (step S15). On the other hand, if the combination extraction data 210 is not extracted in the combination extraction step (step S11) (variable N is “0”), it is determined that the extraction of all cell combinations (terminal combinations) has been completed, and the process proceeds to step S23. To do. That is, when all the combinations of the terminals in the logic cell connected to the gate requiring the antenna countermeasure wiring and the terminals of the wiring cell are extracted on the chip where the cell arrangement is completed, the process proceeds to step S23.

  In the adjacent cell confirmation step (step S15), the positional relationship between the logic cell and the wiring cell is confirmed from the wiring cell size 214, the wiring cell arrangement coordinate 215, the logic cell size 216, and the logic cell arrangement coordinate 217 of the combination extraction data 210. Is done. At this time, when the logic cell and the wiring cell are adjacent, the design support apparatus 10 substitutes “1” for the variable M, and substitutes “0” for the variable M when the logic cell and the wiring cell are separated. In the example shown in FIG. 7A, since the logic cell 500 and the wiring cell 400 are separated by a predetermined interval, “1” is assigned to the variable M. In addition, the confirmation process of an adjacent cell may be performed after the wiring area extraction process (step S17) of the wiring cell mentioned later.

  The design support apparatus 10 extracts the antenna wiring information 112, the gate area 121, and the antenna rule 122 from the antenna library 101 of the logic cell specified in step S11 (step S16). Here, as an example, from the antenna library 101 of the logic cell 500 shown in FIG. 5, the antenna wiring information 112 indicating that the wiring area of the first wiring layer is “2” and the gate area is “2”. And an antenna rule 122 indicating that the antenna reference of the first wiring layer is “500” and the antenna reference of the second wiring layer is “500”.

  The design support apparatus 10 extracts the wiring area in the wiring cell extracted in step S11 from the antenna library 101 of the wiring cell (step S17). Here, as an example, the antenna wiring information 112 indicating that the wiring area of the first wiring layer is “7” is extracted from the antenna library 101 of the wiring cell 400 shown in FIG.

  Subsequently, the design support apparatus 10 determines whether the logic cell and the wiring cell are adjacent to each other based on whether the variable M substituted in step S15 is “0” or “1” (step S18). When the variable M is set to “0”, the design support apparatus 10 determines that the logic cell and the wiring cell are separated from each other, and shifts to a process of connecting the terminals of the cell with wiring (step S20). ). Here, as an example, since the variable M is set to “0”, as illustrated in FIG. 7B, the wiring 551 (fourth fourth) is connected between the input terminal 501 of the logic cell 500 and the output terminal 402 of the wiring cell 400. Connect by wiring. In the wiring process of step S20, wiring is performed using the placement and routing data 100 and the antenna library 101. Specifically, the design support apparatus 10 refers to the antenna library 101 of the logic cell 500 so that the wiring area connected to the input terminal 501 (Pin 501) of the logic cell 500 becomes an area according to the antenna rule 122. In addition, the output terminal 501 and the wiring cell 400 (output terminal 402) are wired. For example, referring to FIG. 5, the product “1000” of the gate area “2” connected to the input terminal “Pin 501” indicated by the terminal information 111 and the wiring area “500” defined by the antenna rule 122 is This is the maximum wiring area for each wiring layer connectable to the input terminal “Pin 501”. The design support apparatus 10 performs wiring between the input terminal “Pin 501” and the output terminal “Pin 402” of the wiring cell 400 so as not to exceed the maximum value. In step S20, wiring is performed only between the terminals extracted in step S11.

  After the wiring, the design support device 10 calculates the area of the wiring that connects the cells (step S21). Here, the area of the wiring 551 shown in FIG. 7B is calculated.

  Subsequently, the design support apparatus 10 changes the antenna library 101 of the wiring cell based on the antenna rules of the logic cell (step S22). Specifically, the design support apparatus 10 includes the antenna wiring information 112, the gate area 121, and the antenna rule 122 of the logic cell extracted in step S16, and the antenna wiring information 112 of the wiring cell extracted in step S17. The wiring area calculated in S21 is added to the antenna library 101 of the wiring cell to generate a new antenna library 201. At this time, the wiring area of the logic cell and the wiring area calculated in step S21 are added to the wiring area of the wiring cell for each same wiring layer. The antenna library 201 is recorded in the storage device 13.

  For example, for the antenna library 101 of the wiring cell 400 shown in FIG. 3, the antenna wiring information 112 “2 (first wiring layer)” of the logic cell 500 shown in FIG. 5, the gate area 121 “2”, and the antenna rule 122 “ 500 (first wiring layer) ”and“ 500 (second wiring layer) ”are added, and the area“ 2 ”of the wiring 551 shown in FIG. 7B is added. Here, the wiring area “2” of the wiring 503 of the same first wiring layer as the wiring 403 is added to the wiring area “7 (first wiring layer)” of the wiring 403 of the wiring cell 400. When the added wiring 553 is formed in the first wiring layer in step S20, the area “2” of the wiring 553 is further added to the total “9” of the areas of the wiring 403 and the wiring 503. In this way, the antenna library 101 of the wiring cell 400 is changed to a new antenna library 201 as shown in FIG.

  Referring to FIG. 9, in the antenna library 201 after the change, “Pin 401” indicating the input terminal 401 is defined as the terminal information 111, and the wiring 503, the wiring 553, which can be the antenna wiring, as the antenna wiring information 112, Information indicating the total wiring area “11” of the wiring 403 and the first wiring layer “M1” in which the wiring 503, the wiring 553, and the wiring 403 are formed is defined. Further, in the antenna library 201 after the change, the area “2” of the region where the gate 505 is formed is defined as the gate area, and the area of the wiring connected to the gate 505 relative to the area of the gate 505 is defined as the antenna rule 122. A reference value for the ratio is defined for each wiring layer. Here, the ratio of the wiring area of the first wiring layer “M1” to the gate area of the gate 505 (antenna reference) is defined as “500”, and the wiring area of the second wiring layer “M1” with respect to the gate area of the gate 505 is The ratio (antenna reference) is defined as “500”. As a result, the area of the wiring that can be connected to the gate 505 without an antenna error in both the first wiring layer and the second wiring layer is defined to be within 500 times “1000” of the gate area “2”.

  On the other hand, when the combination of the output terminal 402 of the wiring cell 400 and the input terminal 501 of the logic cell 500 shown in FIG. 10A is extracted in step S11, the design support apparatus 10 determines that the wiring cell 400 and the logic cell in step S15. Assuming that 500 is adjacent, “1” is assigned to variable M. In this case, in step S18, the design support apparatus 10 determines that the logic cell and the wiring cell are adjacent to each other, and performs a change process of the antenna library for the wiring cell without performing wiring between the cells (step S18). S19).

  In step S19, the design support apparatus 10 changes the antenna library 101 of the wiring cell 400 based on the antenna rule of the logic cell 500 and the like, similarly to step S22. However, since no wiring is formed between the logic cell 500 and the wiring cell 400 here, the process of adding the area of the additional wiring performed in step S22 to the wiring area of the wiring cell 400 is omitted.

  For example, for the antenna library 101 of the wiring cell 400 shown in FIG. 3, the antenna wiring information 112 “2 (first wiring layer)” of the logic cell 500 shown in FIG. 5, the gate area 121 “2”, and the antenna rule 122 “ 500 (first wiring layer) "and" 500 (second wiring layer) "are added. Here, the wiring area “2” of the wiring 503 of the same first wiring layer as the wiring 403 is added to the wiring area “7 (first wiring layer)” of the wiring 403 of the wiring cell 400. In this way, the antenna library 101 of the wiring cell 400 is changed to a new antenna library 201 as shown in FIG.

  Referring to FIG. 11, in the antenna library 201 after the change, “Pin 401” indicating the input terminal 401 is defined as the terminal information 111, and the antenna wiring information 112 includes the wiring 503 and the wiring 403 that can be the antenna wiring. Information indicating the total wiring area “9” and the first wiring layer “M1” in which the wirings 503 and 403 are formed is defined. Further, in the antenna library 201 after the change, the area “2” of the region where the gate 505 is formed is defined as the gate area, and the area of the wiring connected to the gate 505 relative to the area of the gate 505 is defined as the antenna rule 122. A reference value for the ratio is defined for each wiring layer. Here, the ratio of the wiring area of the first wiring layer “M1” to the gate area of the gate 505 (antenna reference) is defined as “500”, and the wiring area of the second wiring layer “M1” with respect to the gate area of the gate 505 is The ratio (antenna reference) is defined as “500”. As a result, the area of the wiring that can be connected to the gate 505 without an antenna error in both the first wiring layer and the second wiring layer is defined to be within 500 times “1000” of the gate area “2”.

  When the antenna library 101 of the wiring cell is changed in step S19 or step S22, the process proceeds to the combination extraction step in step S11, and has a terminal of a logic cell having a gate to be verified and a terminal connected to the gate. The above process is repeated until no combination with the wiring cell is extracted. Note that in steps S19 and S22, only the antenna library 101 of the wiring cell extracted in step S11 is changed as the antenna library 201, and the antenna library 101 of other cells is not changed, and wiring processing (described later) This is used for step S24) and antenna verification (step S25).

  Through the above operation, the gate area 121 and the antenna rule 122 defined in the antenna library 101 of the logic cell 500 and the wiring area in the logic cell 500 are added to the antenna library 101 of the wiring cell 400, and the antenna Library 201 is generated.

  When the combination extraction data 210 is not extracted in the combination extraction step (step S11) (the variable N is “0”), the design support apparatus 10 determines that the extraction of all cell combinations (terminal combinations) has been completed, Control goes to step S23. The design support apparatus 10 adds the arrangement coordinates of the cells and wiring arranged in steps S10 to S22 to the arrangement wiring data 100, and outputs them as arrangement wiring data 200 (step S23).

  Subsequently, the design support apparatus 10 performs wiring in the unwired area using the placement and routing data 200 and the antenna libraries 101 and 201, and performs antenna verification (steps S24 and S25). In this case, a portion requiring wiring other than the region wired in step S20 is wired. For example, the input terminal 401 of the wiring cell 400 shown in FIG. 7B and the output terminal 513 of the logic cell 510 are connected by the wiring 550 (first wiring) based on the information in the antenna library 201, and shown in FIG. 7C. It becomes a layout. Alternatively, the input terminal 401 of the wiring cell 400 shown in FIG. 10A and the output terminal 513 of the logic cell 510 are connected by the wiring 550 based on the information in the antenna library 201, resulting in the layout shown in FIG. 10B. Further, the terminals other than the terminal pair extracted in step S11 are wired. At this time, if necessary, wiring is performed with a wiring area according to the antenna library 101 as in step S20.

  When all wiring is completed, the design support apparatus 10 performs antenna verification on the wiring connected in step S24 (step S25). Here, it is confirmed whether or not the cell, the wiring, and the wiring replaced by the timing standard arranged before step S24 satisfy the antenna rule. Specifically, the design support device 10 extracts the antenna library of the cell to which the wiring is connected in step S24 from the antenna libraries 101 and 201 recorded in the storage device 13, and uses this to extract the antenna of the wiring. Perform verification. Here, the design support apparatus 10 identifies the gate and antenna rule to be verified from the extracted antenna library, and determines whether the wiring area connected to the gate satisfies the antenna rule. Verify for each wiring layer.

  For example, when the first logic cell and the second logic cell are connected by wiring in step S24, the antenna library 101 of the first logic cell is extracted, and the gate of the first logic cell becomes the antenna verification target. In this case, the design support apparatus 10 verifies the area of the wiring according to the antenna library 101 of the first logic cell.

  On the other hand, when the wiring is connected to the wiring cell in step S24, the antenna library 201 of the wiring cell is extracted, and the gate defined in the antenna library 201 becomes the antenna verification target. In this case, the design support apparatus 10 verifies the area of the connected wiring in step S24 according to the antenna library 201 of the wiring cell changed in step S19 or step S22. For example, in the antenna verification for the gate 505 shown in FIG. 7C, the area of the wiring 550 is verified according to the antenna library 201 of the wiring cell 400 shown in FIG. Since the antenna library 201 shown in FIG. 9 includes the area “11” of the antenna wiring of the first wiring layer connected to the gate 505, the area “X” of the wiring 550 with respect to the gate area 121 “2” It is verified whether the ratio of the sum of the area “11” is equal to or less than “500” defined by the antenna rule 122. Alternatively, in the antenna verification for the gate 505 shown in FIG. 10B, the area of the wiring 550 is verified according to the antenna library 201 of the wiring cell 400 shown in FIG. Since the antenna library 201 shown in FIG. 11 includes the area “9” of the antenna wiring of the first wiring layer connected to the gate 505, the area “Y” of the wiring 550 with respect to the gate area 121 “2” It is verified whether the ratio of the sum of the area “9” is equal to or less than “500” defined by the antenna rule 122.

  If an antenna error is detected in the antenna verification process in step S25, the design support apparatus 10 reports the error location and corrects the wiring of the error location (step S25 Yes, step S26). After the correction of the wiring, the process proceeds to the antenna verification process (step S25) again. The design support apparatus 10 repeats the wiring (correction) process (step S24) and the antenna verification process (step S25) until no antenna error is detected, and the placement and wiring result at the time when the antenna error is not detected is, for example, GDS. This is recorded in the storage device 13 as chip layout information in the form of (Graphic Data System).

  For example, in the layout shown in FIG. 7C, the ratio “(X + 11) / 2” of the area “X” and the area “11” of the wiring 550 to the gate area 121 “2” is “500” as the antenna rule. If larger, it is determined as an antenna error, and the wiring 550 is corrected. If “(X + 11) / 2” is “500” or less, it is determined that there is no antenna error. Alternatively, in the layout shown in FIG. 10B, the ratio “(Y + 9) / 2” of the area “Y” and the area “9” of the wiring 550 to the gate area 121 “2” is “500” as the antenna rule. If larger, it is determined as an antenna error, and the wiring 550 is corrected. If “(Y + 9) / 2” is “500” or less, it is determined that there is no antenna error.

  Conventionally, the antenna library of the wiring cell does not define the area of the gate to be verified and the antenna rule. For this reason, it has not been possible to verify in the placement and routing phase whether or not the wiring connecting the input terminal of the wiring cell and the output terminal of the logic cell causes an antenna error. However, according to the present invention, the wiring area of the existing wiring connected to the gate (antenna wiring information 112), the gate area 121, and the antenna rule 122 are defined in the antenna library 201 of the wiring cell. By using the antenna library 201, the design support apparatus 10 can perform antenna verification on the wiring extended from the wiring cell. That is, according to the present invention, in the placement and routing phase, the placement of the wiring cell and the wiring between the wiring cell and another logic cell can be performed while satisfying the antenna rule. As described above, according to the present invention, the antenna error can be converged in the automatic placement and routing process. Therefore, the rework due to the antenna error is eliminated in the DRC after the GDS output, and the design man-hour is reduced.

  In the above-described embodiment, the antenna verification for the wiring cell 400 and the wiring 551 that connects the antenna verification target gate and the wiring cell 400 is performed at the same time as the antenna verification for the other wirings after the wiring process in step S24. However, it is not limited to this. For example, the antenna verification for the wiring cell 400 and the wiring 551 may be performed before the antenna library changing step in step S19 or step S22 as in the design method shown in FIG.

  FIG. 12 is a flowchart showing an example of a design operation in the case where antenna verification is performed before the process of changing the antenna library of the wiring cell. Referring to FIG. 12, steps S10 to S18 are the same as the design operation shown in FIG.

  If the variable M is set to “0” in the cell adjacency confirmation step in step S18, the design support apparatus 10 determines that the logic cell and the wiring cell are separated from each other, and the terminals of the cell are wired. The process proceeds to the connection process (step S20). Steps S20 and after will be described by taking an example of processing for the layout shown in FIG. 7A. In the wiring process of step S20, similarly to the example shown in FIG. 6, the wiring 551 is connected between the output terminal 402 of the wiring cell 400 and the input terminal 501 of the logic cell 500 using the placement and routing data 100 and the antenna library 101. Connected by.

  Subsequently, according to the antenna library 101 of the logic cell 500, antenna verification is performed on the wiring 403 and the wiring 551 in the wiring cell 400 (step S72). For example, the sum of the areas of the wiring 551 and the wiring 403 is verified according to the antenna library 101 of the logic cell 500 shown in FIG. Here, since the antenna library 101 shown in FIG. 5 includes the area “7” of the antenna wiring of the first wiring layer connected to the gate 505, the wiring 551 and the wiring 403 for the gate area 121 “2”. It is verified whether the ratio of the sum of the total area “X1” and the area “7” is equal to or less than “500” defined by the antenna rule 122.

  When an antenna error is detected in the antenna verification process in step S72, the design support apparatus 10 reports the error location and returns to the arrangement process in step S10, and adjusts the arrangement position of the wiring cell 400 and the logic cell 500, The cell 500 is changed (step S72 Yes, step S73). Here, it is preferable that the design support apparatus 10 shortens the arrangement distance between the wiring cell 400 and the logic cell 500 or changes the logic cell 500 to a logic cell having a large area of the input gate 505.

  If no antenna error is detected in the antenna verification process in step S72, the design support apparatus 10 calculates the area of the wiring connecting the cells (No in steps S72 and S21). Here, the area of the wiring 551 shown in FIG. 7B is calculated.

  Subsequently, the design support apparatus 10 changes the antenna library 101 of the wiring cell based on the antenna rule of the logic cell and the like as in the example shown in FIG. 6 (step S22). Specifically, the design support apparatus 10 includes the antenna wiring information 112, the gate area 121, and the antenna rule 122 of the logic cell extracted in step S16, and the antenna wiring information 112 of the wiring cell extracted in step S17. The wiring area calculated in S21 is added to the antenna library 101 of the wiring cell to generate a new antenna library 201. At this time, the wiring area of the logic cell and the wiring area calculated in step S21 are added to the wiring area of the wiring cell for each same wiring layer. The antenna library 201 is recorded in the storage device 13.

  On the other hand, when the combination of the output terminal 402 of the wiring cell 400 and the input terminal 501 of the logic cell 500 shown in FIG. 10A is extracted in step S11, the design support apparatus 10 determines that the wiring cell 400 and the logic cell in step S15. Assuming that 500 is adjacent, “1” is assigned to variable M. In this case, in step S18, the design support apparatus 10 determines that the logic cell and the wiring cell are adjacent to each other, and performs antenna verification for the wiring cell 400 connected to the gate 505 without performing wiring between the cells. (Step S70).

  In step S70, for example, the total area of the wiring 551 and the wiring 403 is verified according to the antenna library 101 of the logic cell 500 shown in FIG. Here, since the antenna library 101 shown in FIG. 5 includes the area “7” of the antenna wiring of the first wiring layer connected to the gate 505, the area “of the wiring 403 with respect to the gate area 121“ 2 ”“ It is verified whether the ratio of the sum of Y1 ”and area“ 7 ”is equal to or less than“ 500 ”defined by the antenna rule 122.

  If an antenna error is detected in the antenna verification process in step S70, the design support apparatus 10 reports the error location and returns to the placement process in step S10, and changes to the wiring cell 400 having a small wiring area or the logic cell 500. Is changed to a logic cell having a large area of the input gate 505 (step S70 Yes, step S71). Here, adjustment of the arrangement position of the wiring cell 400 and the logic cell 500 and size adjustment of the logic cell 500 may be performed.

  On the other hand, if no antenna error is detected in the antenna verification process in step S72, the design support apparatus 10 changes the antenna library 101 of the wiring cell based on the antenna rules of the logic cell, etc., as in the example shown in FIG. (Step S19). In step S19, the design support apparatus 10 changes the antenna library 101 of the wiring cell 400 based on the antenna rule of the logic cell 500 and the like, similarly to step S22. However, since no wiring is formed between the logic cell 500 and the wiring cell 400 here, the process of adding the area of the additional wiring performed in step S22 to the wiring area of the wiring cell 400 is omitted.

  When the antenna library 101 of the wiring cell is changed in step S19 or step S22, the process proceeds to the combination extraction step in step S11, and has a terminal of a logic cell having a gate to be verified and a terminal connected to the gate. The above process is repeated until no combination with the wiring cell is extracted. Note that in steps S19 and S22, only the antenna library 101 of the wiring cell extracted in step S11 is changed as the antenna library 201, and the antenna library 101 of other cells is not changed, and wiring processing (described later) This is used for step S24) and antenna verification (step S25).

  Through the above operation, the gate area 121 and the antenna rule 122 defined in the antenna library 101 of the logic cell 500 and the wiring area in the logic cell 500 are added to the antenna library 101 of the wiring cell 400, and the antenna Library 201 is generated. The antenna library 201 generated in the present embodiment includes a wiring area determined as having no antenna error by the antenna verification.

  When the combination extraction data 210 is not extracted in the combination extraction step (step S11) (the variable N is “0”), the design support apparatus 10 determines that the extraction of all cell combinations (terminal combinations) has been completed, Control goes to step S23. The processing after step S23 is performed in the same manner as the example shown in FIG. 6, but in this embodiment, the wiring area from the gate 505 to the wiring cell 400 is defined in the gate 505 before the wiring process in step S24. Is set in advance so as to satisfy the antenna rule. For this reason, the possibility of an antenna error in step S25 is reduced. As a result, the number of rework from step S25 to step S25 is reduced, and the design TAT can be further shortened.

  As described above, according to the present invention, since the gate area and the antenna rule are added to the antenna library for the wiring cell, the antenna verification can be performed on the wiring extending from the wiring cell even in the placement and wiring process. It becomes possible. As a result, the possibility of an antenna error in the DRC after the layout information (GDS data) is output is reduced, and the number of reversions from the DRC to the placement and routing process is reduced.

  In the manufacturing process after the layout design, a mask is formed on the surface of the silicon substrate using the layout information after the DRC, and a semiconductor integrated circuit is manufactured through a process such as etching.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. . For example, in the antenna verification in steps S19, S22, S25, S70, and S72, not only the wiring area but also the via size can be considered. In this case, the size of the via formed from the gate 505 to the wiring cell 400 is also added to the antenna library 201.

  As illustrated in FIG. 13, the design support apparatus 10 may be connected to a server 30 having a storage device 13 via the Internet 20. In this case, the design support apparatus 10 acquires the placement and routing data 100 and the antenna library 101 from the storage device 13 in the server 30 and performs layout design.

10: Design support device 13: Storage device 14: Input device 15: Output device 16: Bus 20: Internet 30: Server 100, 200: Placement and wiring data 101, 201: Library for antenna 111: Terminal information 112: Antenna wiring information 121 : Gate area 122: Antenna rule 210: Combination extraction data 211: Wiring cell name 212: Logic cell name 213: Net name 214: Wiring cell size 215: Wiring cell arrangement coordinates 216: Logic cell arrangement coordinates 217: Logic cell arrangement coordinates 300: Design program 400: wiring cell 401, 501, 511: input terminal 402, 502, 512: output terminal 403, 503, 504, 513, 514, 550, 551: wiring 500: logic cell 505, 515: gate 506, 507 516, 517 : Diffusion layer

Claims (8)

A method for designing a semiconductor integrated circuit executed by a computer device, comprising:
Placing logic cells and wiring cells on a chip according to a netlist recorded in a storage device;
Changing the first antenna library to a second antenna library by adding an antenna rule for the gate in the logic cell to the first antenna library of the wiring cell;
Connecting the wiring cell and another logic cell with a first wiring;
A method for designing a semiconductor integrated circuit, comprising: a first verification step of verifying a ratio of an area of the first wiring to an area of the gate in accordance with an antenna rule defined in the second antenna library. The method for designing a semiconductor integrated circuit according to claim 1,
In the first antenna library, an area of the second wiring in the wiring cell is defined,
In the third antenna library of the logic cell, the area of the gate, the area of the third wiring connected to the gate in the logic cell, and the antenna rule are defined,
The step of changing to the second antenna library includes:
Adding the gate area and the antenna rule to the first antenna library;
Adding the area of the third wiring to the area of the second wiring in the first antenna library;
In the first verification step, a ratio of the sum of the wiring area defined in the second antenna library and the first area and the gate area defined in the second antenna library satisfies the antenna rule. A method for designing a semiconductor integrated circuit, comprising the step of verifying whether to do so. The method of designing a semiconductor integrated circuit according to claim 2,
A step of connecting the logic cell and the wiring cell by a fourth wiring;
The step of changing to the second antenna library includes:
Calculating an area of the fourth wiring;
A method for designing a semiconductor integrated circuit, comprising: adding an area of the third wiring and an area of the fourth wiring to the area of the second wiring in the first antenna library. The method of designing a semiconductor integrated circuit according to claim 3,
Identifying the logic cell comprising the gate;
Identifying the wiring cell connected to the gate;
Determining whether or not the logic cell and the wiring cell are separated from each other; and
A method for designing a semiconductor integrated circuit, comprising: connecting the gate and the wiring cell by the fourth wiring when the logic cell and the wiring cell are separated from each other. The method of designing a semiconductor integrated circuit according to any one of claims 2 to 4,
Prior to the step of changing to the second antenna library, the ratio of the area sum of the second wiring and the fourth wiring to the area of the gate is verified according to the antenna rule defined in the third antenna library. Further comprising a second verification step;
A method of designing a semiconductor integrated circuit, wherein, in the second verification step, when it is determined that an antenna error has occurred, at least one of the logic cell and the wiring cell is changed. The method for designing a semiconductor integrated circuit according to any one of claims 2 to 5,
Before the step of changing to the second antenna library, further comprising a third verification step of verifying a ratio of the second wiring to the area of the gate according to the antenna rule defined in the third antenna library;
A method of designing a semiconductor integrated circuit, wherein, in the third verification step, when it is determined that an antenna error has occurred, at least one of the logic cell and the wiring cell is changed.   A design program for causing a computer to execute the method for designing a semiconductor integrated circuit according to claim 1. A storage device in which the design program according to claim 7 is recorded;
A design support apparatus for a semiconductor integrated circuit, comprising: a CPU that executes the design program.

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