JP2012209550A - Microcrystalline semiconductor film and manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a microcrystalline semiconductor film with high crystallinity, and a method for manufacturing a semiconductor device having excellent electric characteristics with high productivity.SOLUTION: A seed crystal including highly crystalline mixed-phase grains at low grain density is formed on an insulation film under a first condition. Then, a first microcrystalline semiconductor film is formed on the seed crystal so as to fill the space between the mixed-phase grains by growing the mixed-phase grains under a second condition. A second microcrystalline semiconductor film is formed on the first microcrystalline semiconductor film under a third condition for forming the microcrystalline semiconductor film with high crystallinity without expanding the space between the mixed-phase grains included in the first microcrystalline semiconductor film. A third microcrystalline semiconductor film is stacked on the second microcrystalline semiconductor film under a fourth condition for promoting the crystal growth while filling the space between the mixed-phase grains included in the second microcrystalline semiconductor film.

Description

The present invention relates to a method for manufacturing a microcrystalline semiconductor film, a method for manufacturing a semiconductor device using the microcrystalline semiconductor film, and a display device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and a display device, an electro-optical device, a photoelectric conversion device, a semiconductor circuit, and an electronic device are all semiconductor devices. .

As a kind of field effect transistor, a thin film transistor in which a channel region is formed using a semiconductor film formed over a substrate having an insulating surface is known. Techniques using amorphous silicon, microcrystalline silicon, and polycrystalline silicon for a semiconductor film used for a channel region of a thin film transistor are disclosed (see Patent Documents 1 to 5). A typical application example of a thin film transistor is a liquid crystal television device, which is put into practical use as a switching transistor of each pixel constituting a display screen.

In addition, development of a photoelectric conversion device using microcrystalline silicon as a crystalline silicon that can be manufactured by a plasma CVD method in a semiconductor film that performs photoelectric conversion is underway (see, for example, Patent Document 6).

JP 2001-053283 A JP-A-5-129608 JP 2005-049832 A Japanese Patent Laid-Open No. 7-131030 JP 2005-191546 A JP 2000-277439 A

A thin film transistor in which a channel region is formed using an amorphous silicon film has a problem that field-effect mobility and on-state current are low. On the other hand, a thin film transistor in which a channel region is formed using a microcrystalline silicon film has improved field effect mobility but higher off-state current than a thin film transistor in which a channel region is formed using an amorphous silicon film. Therefore, there is a problem that sufficient switching characteristics cannot be obtained.

A thin film transistor in which a channel region is formed using a polycrystalline silicon film has characteristics that field effect mobility is remarkably higher than that of the above two types of thin film transistors, and a high on-current can be obtained. This thin film transistor can be used as a switching transistor provided in a pixel due to its characteristics, and can also constitute a driver circuit that requires high-speed operation.

However, a manufacturing process of a thin film transistor in which a channel region is formed using a polycrystalline silicon film has a crystallization process of a semiconductor film compared to a manufacturing process of a thin film transistor in which a channel region is formed using an amorphous silicon film. It is necessary and the manufacturing cost increases. For example, the laser annealing technique necessary for manufacturing a polycrystalline silicon film has a problem that the irradiation area of the laser beam is small and a large-screen liquid crystal panel cannot be efficiently produced.

By the way, the glass substrate used for manufacturing the display panel is the third generation (550 mm × 650 mm), the 3.5th generation (600 mm × 720 mm, or 620 mm × 750 mm), the fourth generation (680 mm × 880 mm, or 730 mm). × 920 mm), 5th generation (1100 mm × 1300 mm), 6th generation (1500 mm × 1850 mm), 7th generation (1870 mm × 2200 mm), 8th generation (2200 mm × 2400 mm), 9th generation (2400 mm × 2800 mm), 1st The area has been increased to 10 generations (2950 mm × 3400 mm). The increase in size of the glass substrate is based on the idea of cost minimum design.

On the other hand, a technology capable of manufacturing a thin film transistor capable of high-speed operation with high productivity on a mother glass substrate having a large area as in the 10th generation (2950 mm × 3400 mm) has not yet been established. This is a problem for industry.

Thus, an object of one embodiment of the present invention is to provide a method for manufacturing a microcrystalline semiconductor film with high crystallinity. It is another object of the present invention to provide a method for manufacturing a semiconductor device with favorable electrical characteristics with high productivity.

In one embodiment of the present invention, a seed crystal having high crystalline mixed phase grains with a low grain density is formed on an insulating film according to the first condition, and then the mixed phase grains are grown on the seed crystal according to the second condition. The first microcrystalline semiconductor film is formed so as to fill the gap between the mixed phase grains, and the mixed phase grains included in the first microcrystalline semiconductor film are formed on the first microcrystalline semiconductor film according to the third condition. A microcrystalline semiconductor film having high crystallinity is formed without widening the gap, and the third phase is formed so that the mixed phase grains are grown on the second microcrystalline semiconductor film according to the fourth condition to fill the gaps of the mixed phase grains. The gist of the invention is to stack microcrystalline semiconductor films.

The first condition for providing the mixed phase grains having high crystallinity at a low grain density is to dilute the deposition gas by increasing the flow rate of hydrogen to 50 to 1000 times the flow rate of the deposition gas containing silicon or germanium, and The conditions are such that the pressure in the processing chamber is 67 Pa to 50000 Pa, more preferably 67 Pa to 13332 Pa. The second condition for growing the mixed-phase grains to fill the gaps between the mixed-phase grains is to dilute the deposition gas by increasing the flow rate of hydrogen to 100 to 2000 times the flow rate of the deposition gas containing silicon or germanium. The condition is that the pressure in the room is 1333 Pa to 50000 Pa, more preferably 1333 Pa to 13332 Pa. The third condition for forming a microcrystalline semiconductor film with high crystallinity without widening the interphase grains contained in the first microcrystalline semiconductor film is that the pressure in the treatment chamber is 1333 Pa to 50000 Pa, more preferably A first period of 1333 Pa to 13332 Pa and a microcrystalline semiconductor is deposited and a second period longer than the first period of selectively etching an amorphous semiconductor region included in the microcrystalline semiconductor This is an alternating condition. A fourth condition for growing a mixed phase grain contained in the second microcrystalline semiconductor film on the second microcrystalline semiconductor film to fill a gap between the mixed phase grains is the same as the second condition.

According to one embodiment of the present invention, a seed crystal having a mixed phase grain including an amorphous semiconductor region and a crystallite that can be regarded as a single crystal is formed by a plasma CVD method according to a first condition. To form a first microcrystalline semiconductor film on the seed crystal by a plasma CVD method, to form a second microcrystalline semiconductor film on the first microcrystalline semiconductor film under the third condition, and according to the fourth condition. A method for forming a third microcrystalline semiconductor film over a second microcrystalline semiconductor film, wherein the first condition includes a deposition gas containing silicon or germanium and hydrogen as a source gas supplied into a processing chamber The deposited gas is diluted by increasing the flow rate of hydrogen with respect to the flow rate of the deposition gas by 50 times or more and 1000 times or less, and the pressure in the processing chamber is 67 Pa or more and 50000 Pa or less, more preferably 67 Pa or more and 13332P. It is a condition to the following. Further, the second condition and the fourth condition are that the flow rate of hydrogen is 100 times to 2000 times the flow rate of the deposition gas containing silicon or germanium to dilute the deposition gas, and the pressure in the processing chamber is set to 1333 Pa. It is characterized in that the conditions are not less than 50000 Pa and more preferably not less than 1333 Pa and not more than 13332 Pa. The third condition is that the pressure in the treatment chamber is 1333 Pa to 50000 Pa, more preferably 1333 Pa to 13332 Pa, the first cycle in which the microcrystalline semiconductor is deposited, and the amorphous contained in the microcrystalline semiconductor. This is a condition for alternately performing a second period longer than the first period for selectively etching the semiconductor region.

In a seed crystal, a plurality of mixed phase grains may be in a dispersed state or a continuous state (that is, a film shape). The power for generating plasma is preferably selected as appropriate in accordance with the ratio of the flow rate of hydrogen to the flow rate of the deposition gas containing silicon or germanium.

In one embodiment of the present invention, a rare gas can be added to the source gas used in at least one of the first to fourth conditions.

In one embodiment of the present invention, a seed crystal having high crystalline mixed-phase grains with a low grain density is formed by a plasma CVD method on an insulating film under a first condition, and the seed crystal is formed on the seed crystal according to a second condition. A first microcrystalline semiconductor film is formed by a plasma CVD method so as to grow mixed phase grains to fill a gap between the mixed phase grains, and the first microcrystalline semiconductor film is formed on the first microcrystalline semiconductor film under a third condition. A second microcrystalline semiconductor film having high crystallinity is formed by a plasma CVD method without expanding a gap between mixed phase grains included in the semiconductor film, and the mixed phase grains are formed on the second microcrystalline semiconductor film under a fourth condition. The third microcrystalline semiconductor film is formed by plasma CVD so as to fill the gaps in the mixed phase grains.

Another embodiment of the present invention uses a microcrystalline semiconductor film including the stacked seed crystal, the first microcrystalline semiconductor film, the second microcrystalline semiconductor film, and the third microcrystalline semiconductor film. And a method for manufacturing a semiconductor device including a thin film transistor that forms a channel region.

Another embodiment of the present invention includes a microcrystalline semiconductor film including the stacked seed crystal, the first microcrystalline semiconductor film, the second microcrystalline semiconductor film, and the third microcrystalline semiconductor film. This is a method for manufacturing a photoelectric conversion device used for one or more of a semiconductor film exhibiting p-type conductivity, a semiconductor film exhibiting n-type conductivity, and a semiconductor film performing photoelectric conversion.

By applying one embodiment of the present invention, a microcrystalline semiconductor film with high crystallinity can be manufactured. In addition, a semiconductor device with favorable electrical characteristics can be manufactured with high productivity.

10A to 10D are cross-sectional views illustrating a method for manufacturing a microcrystalline semiconductor film according to an embodiment of the present invention. 10 is a timing chart illustrating a method for manufacturing a microcrystalline semiconductor film according to an embodiment of the present invention. FIG. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A to 8D are top views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a photoelectric conversion device. It is a perspective view which shows an example of an electronic book. It is a figure explaining the average surface roughness and the maximum height difference of a microcrystalline semiconductor film. It is a figure explaining the electrical property of a thin-film transistor. It is a figure explaining the electrical property of a thin-film transistor.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments and examples. Note that in describing the structure of the present invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

(Embodiment 1)
In this embodiment, a method for manufacturing a microcrystalline semiconductor film in which the surface is flat and crystallinity is improved by reducing gaps between mixed phase grains will be described with reference to FIGS.

As shown in FIG. 1A, an insulating film 55 is formed over the substrate 51, and a seed crystal 57 is formed over the insulating film 55.

As the substrate 51, a glass substrate, a ceramic substrate, a plastic substrate having heat resistance enough to withstand the processing temperature in the manufacturing process, or the like can be used. In addition, when the substrate does not require translucency, a metal substrate such as stainless steel may be used. As the glass substrate, for example, a non-alkali glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass may be used. The size of the substrate 51 is not limited, and for example, a 3rd generation to 10th generation glass substrate often used in the field of the flat panel display described above can be used.

The insulating film 55 is formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film by a CVD method, a sputtering method, or the like. The film can be formed as a single layer or stacked layers.

Note that, here, silicon oxynitride has a composition containing more oxygen than nitrogen, and preferably Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). : Hydrogen Forward Scattering Spectrometry), the composition ranges from 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 0.1 to 10 for hydrogen. It is included in the atomic% range. In addition, silicon nitride oxide has a composition containing more nitrogen than oxygen, and preferably has a composition range of 5 to 30 atomic% when measured using RBS and HFS. Nitrogen is contained in the range of 20 to 55 atomic%, silicon is contained in the range of 25 to 35 atomic%, and hydrogen is contained in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

The seed crystal 57 is formed using a microcrystalline semiconductor, typically, microcrystalline silicon, microcrystalline silicon germanium, microcrystalline germanium, or the like. The seed crystal 57 includes a state where a plurality of mixed phase grains are dispersed, a state where the mixed phase grains are continuous, or a state where the mixed phase grains and the amorphous semiconductor region are continuous. For this reason, the seed crystal 57 includes a crystal in which the mixed phase grains 57a and the amorphous semiconductor are not adjacent to each other and a gap 57b is provided between the mixed phase grains 57a. Furthermore, the particle density of the mixed phase grains (the ratio of the mixed phase grains in the plane) is low, and the crystallinity of the mixed phase grains is high.

In the processing chamber of the plasma CVD apparatus, the seed crystal 57 is a mixture of a deposition gas containing silicon or germanium and hydrogen using a first condition that provides mixed crystal grains having high crystallinity at a low grain density. It is formed by glow discharge plasma. Alternatively, a deposition gas containing silicon or germanium, hydrogen, and a rare gas such as helium, neon, argon, krypton, or xenon are mixed and formed by glow discharge plasma. Here, the flow rate of hydrogen with respect to the flow rate of the deposition gas containing silicon or germanium is 50 to 1000 times to dilute the deposition gas, and the pressure in the processing chamber is 67 Pa to 50000 Pa (0.5 Torr to 370 Torr or less). More preferably, microcrystalline silicon, microcrystalline silicon germanium, microcrystalline germanium, or the like is formed as the seed crystal 57 under a first condition of 67 Pa to 13332 Pa (0.5 Torr to 100 Torr). The deposition temperature at this time is preferably room temperature to 350 ° C., more preferably 150 to 280 ° C. Note that the interval between the upper electrode and the lower electrode in the treatment chamber may be an interval at which plasma can be generated. By forming using the first condition, crystal growth is promoted, and the crystallinity of the mixed phase grains 57a included in the seed crystal 57 is increased. That is, the size of the crystallites included in the mixed phase grains 57a included in the seed crystal 57 increases. Further, a gap 57b is formed between adjacent mixed phase grains 57a, and the mixed phase grains 57a are formed with a low grain density. Note that the flow rate of hydrogen relative to the flow rate of the deposition gas containing silicon or germanium is the flow rate of hydrogen relative to the deposition gas containing 100% silicon or germanium which is not diluted. For this reason, when the deposition gas containing silicon or germanium is diluted, the hydrogen flow rate may be adjusted by setting the deposition gas containing silicon or germanium to 100%.

Typical examples of the deposition gas containing silicon or germanium include SiH ₄ , Si ₂ H ₆ , GeH ₄ , and Ge ₂ H ₆ .

By adding a rare gas such as helium, neon, argon, krypton, or xenon to the source gas of the seed crystal 57, the deposition rate of the seed crystal 57 is increased. As a result, since the amount of impurities mixed in the seed crystal 57 is reduced, the crystallinity of the seed crystal 57 can be improved. Further, by adding a rare gas such as helium, neon, argon, krypton, or xenon to the source gas of the seed crystal 57, it is possible to generate a stable plasma without supplying high power. Plasma damage of the crystal 57 can be reduced, and the crystallinity of the seed crystal 57 can be increased.

The generation of glow discharge plasma when forming the seed crystal 57 is from 3 MHz to 30 MHz, typically 13.56 MHz, 27.12 MHz, HF band high frequency power, or VHF band high frequency power from 30 MHz to about 300 MHz. Typically, it is performed by applying 60 MHz. Further, it is performed by applying microwave high frequency power of 1 GHz or more. Note that the high frequency power can be pulse oscillation applied in a pulsed manner or continuous oscillation applied continuously. In addition, by superimposing high frequency power in the HF band and high frequency power in the VHF band, plasma unevenness can be reduced even in a large-area substrate, and the uniformity of film thickness and film quality can be increased, and the deposition rate can be increased. be able to.

As described above, by increasing the flow rate of hydrogen relative to the flow rate of the deposition gas containing silicon or germanium, etching of the amorphous semiconductor region included in the seed crystal 57 occurs simultaneously with the deposition of the seed crystal 57, and the crystallinity is increased. High mixed phase grains 57a are formed, and gaps 57b are formed between adjacent mixed phase grains 57a. The optimum conditions differ depending on the device configuration and the chemical state of the coating surface, but if the mixed phase grains 57a are hardly deposited, the ratio of the flow rate of hydrogen to the flow rate of the deposition gas containing silicon or germanium is reduced, or the RF power is Just make it smaller. On the other hand, when the particle density of the mixed phase grains 57a is high, or when the amorphous semiconductor region is larger than the crystalline semiconductor region, the ratio of the flow rate of hydrogen to the flow rate of the deposition gas containing silicon or germanium is increased, or The RF power may be increased. The state of deposition of the seed crystal 57 can be evaluated by SEM (Scanning Electron Microscopy) and Raman spectroscopy. Depending on the flow rate ratio and the pressure condition in the processing chamber, the seed crystal 57 having good crystallinity and maintaining a preferable gap between the mixed phase grains 57a can be formed. As a result, the mixed phase grain 57a is formed while etching the amorphous semiconductor region included in the seed crystal 57, so that crystal growth is promoted and the crystallinity of the mixed phase grain 57a is increased. That is, the size of the crystallites contained in the mixed phase grain 57a increases. Further, since the amorphous semiconductor region between the adjacent mixed phase grains 57a is etched, the adjacent mixed phase grains 57a have gaps 57b, and thus the mixed phase grains 57a are formed with a low grain density. Note that if the seed crystal 57 is formed under the first condition in the present embodiment, the particle size of the mixed phase grain 57a may vary.

Next, as illustrated in FIG. 1B, a first microcrystalline semiconductor film 59 is formed over the seed crystal 57. The first microcrystalline semiconductor film 59 is formed under the condition that the crystallites of the seed crystal 57 are grown to fill the gaps of the mixed phase grains.

The first microcrystalline semiconductor film 59 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium with hydrogen under a second condition in a processing chamber of a plasma CVD apparatus. Alternatively, a rare gas such as helium, neon, argon, krypton, or xenon is mixed with the source gas under the second condition, and formed by glow discharge plasma. Here, the second condition is that the flow rate of hydrogen with respect to the flow rate of the deposition gas containing silicon or germanium is 100 to 2000 times to dilute the deposition gas, and the pressure in the processing chamber is 1333 Pa to 50000 Pa ( 10 Torr to 370 Torr), more preferably 1333 Pa to 13332 Pa (10 Torr to 100 Torr). Note that the flow rate of hydrogen relative to the flow rate of the deposition gas containing silicon or germanium is the flow rate of hydrogen relative to the deposition gas containing 100% silicon or germanium which is not diluted. For this reason, when the deposition gas containing silicon or germanium is diluted, the hydrogen flow rate may be adjusted by setting the deposition gas containing silicon or germanium to 100%.

Under the second condition, a microcrystalline silicon film, a microcrystalline silicon germanium film, a microcrystalline germanium film, or the like is formed as the first microcrystalline semiconductor film 59. The deposition temperature at this time is preferably room temperature to 350 ° C., more preferably 150 to 280 ° C. Note that the interval between the upper electrode and the lower electrode in the treatment chamber may be an interval at which plasma can be generated.

When the first microcrystalline semiconductor film 59 is formed, the conditions for the seed crystal 57 can be used as appropriate for the generation of glow discharge plasma. Note that the generation of glow discharge plasma in the seed crystal 57 and the first microcrystalline semiconductor film 59 can be improved under the same conditions, but may be different.

The first microcrystalline semiconductor film 59 is formed under a second condition in which crystallites of the seed crystal 57 are grown to fill the gaps 57b of the mixed phase grains 57a. When the second condition is the above condition, since the pressure in the processing chamber is high, the mean free path is short, and hydrogen radicals and hydrogen ions lose energy each time they collide, so the energy of hydrogen radicals and hydrogen ions is reduced, The coverage is improved and ion damage is reduced, contributing to defect reduction. In addition, since the dilution ratio of the deposition gas containing silicon or germanium is high and the amount of hydrogen radicals generated increases, the crystal growth is performed using the crystallites contained in the mixed phase grains 57a as nuclei while etching the amorphous semiconductor region. . As a result, the ratio of the crystalline region to the amorphous semiconductor region in the first microcrystalline semiconductor film 59 is increased, and the crystallinity is improved. In addition, this contributes to reducing defects in the first microcrystalline semiconductor film 59 being deposited.

Note that a new mixed phase grain of the first microcrystalline semiconductor film 59 is generated in the gap 57b of the mixed phase grain 57a of the seed crystal 57, so that the size of the mixed phase grain of the first microcrystalline semiconductor film 59 is reduced. Therefore, it is preferable that the generation frequency of the mixed phase grains of the first microcrystalline semiconductor film 59 is lower than the generation frequency of the mixed phase grains 57a of the seed crystal 57. As a result, it is possible to give priority to crystal growth from the seed crystal 57 using the crystallites contained in the mixed phase grains 57a of the seed crystal 57 as nuclei.

At this time, the first microcrystalline semiconductor film 59 grows using crystallites contained in the mixed phase grains 57 a of the seed crystal 57 as nuclei. The size of the mixed phase grains of the first microcrystalline semiconductor film 59 depends on the interval between the mixed phase grains 57 a of the seed crystal 57. For this reason, when the grain density of the mixed phase grains 57a of the seed crystal 57 is low, the interval between the mixed phase grains 57a is widened, so that the crystal growth distance of the mixed phase grains of the first microcrystalline semiconductor film 59 is extended, and the first microcrystalline semiconductor The mixed phase grains of the film 59 can be enlarged.

Next, as illustrated in FIG. 1C, a second microcrystalline semiconductor film 61 is formed over the first microcrystalline semiconductor film 59. As the second microcrystalline semiconductor film 61, a microcrystalline semiconductor film having a higher crystallinity than the first microcrystalline semiconductor film 59 is formed without increasing a gap between mixed phase grains included in the first microcrystalline semiconductor film. It is formed by conditions.

The second microcrystalline semiconductor film 61 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium with hydrogen under a third condition in a processing chamber of a plasma CVD apparatus. Alternatively, a deposition gas containing silicon or germanium, hydrogen, and a rare gas such as helium, neon, argon, krypton, or xenon are mixed under the third condition, and formed by glow discharge plasma. Here, the third condition is that the pressure in the treatment chamber is 1333 Pa to 50000 Pa, more preferably 1333 Pa to 13332 Pa, the first period in which the microcrystalline semiconductor is deposited, and the amorphous contained in the microcrystalline semiconductor. This is a condition for alternately performing a second period longer than the first period for selectively etching the quality semiconductor region.

In order to alternately perform the first period for depositing the microcrystalline semiconductor and the second period longer than the first period for selectively etching the amorphous semiconductor region included in the microcrystalline semiconductor, The flow rate ratio between the deposition gas containing silicon or germanium and hydrogen may be increased or decreased alternately. Specifically, the flow rate of the deposition gas or hydrogen containing silicon or germanium may be increased or decreased. When the flow ratio of hydrogen to a deposition gas containing silicon or germanium is low, typically, the flow rate of hydrogen with respect to the deposition gas flow is set to 100 to 2000 times to deposit microcrystalline semiconductors and grow crystals. Occurs preferentially. On the other hand, when the flow ratio of hydrogen to the flow rate of the deposition gas containing silicon or germanium is high, typically, the deposition gas containing silicon or germanium is set to 0 sccm or more and 0.3 sccm or less, and the hydrogen flow rate is set higher than 1000 sccm. Thus, etching of the amorphous semiconductor region included in the microcrystalline semiconductor occurs preferentially. At this time, in the case where the flow rate of hydrogen is constant and the flow rate of the deposition gas containing silicon or germanium is increased or decreased, hydrogen having a flow rate similar to that in the first cycle is introduced into the treatment chamber, so that the first cycle and Since the pressure in the treatment chamber can be kept constant in the second period, the uniformity of the film quality of the second microcrystalline semiconductor film can be improved. Note that when the pressure in the treatment chamber is 1333 Pa to 50000 Pa, more preferably 1333 Pa to 13332 Pa, the flow rate of hydrogen to the deposition gas containing silicon or germanium is high, the crystallites included in the microcrystalline semiconductor The amorphous semiconductor region is preferentially etched rather than. Note that the flow rate ratio of hydrogen to the flow rate of the deposition gas containing silicon or germanium is the flow rate ratio of hydrogen to the deposition gas containing 100% silicon or germanium without dilution. For this reason, when the deposition gas containing silicon or germanium is diluted, the hydrogen flow rate may be adjusted by setting the deposition gas containing silicon or germanium to 100%.

Under the third condition, a microcrystalline silicon film, a microcrystalline silicon germanium film, a microcrystalline germanium film, or the like is formed as the second microcrystalline semiconductor film 61. As a result, the second microcrystalline semiconductor film 61 does not widen the gap between the mixed phase grains of the first microcrystalline semiconductor film 59 and has higher crystallinity than the first microcrystalline semiconductor film. The deposition temperature at this time is preferably room temperature to 350 ° C., more preferably 150 to 280 ° C. Note that the interval between the upper electrode and the lower electrode in the treatment chamber may be an interval at which plasma can be generated.

Note that a rare gas such as helium, neon, argon, krypton, or xenon may be added to the source gas of the second microcrystalline semiconductor film 61.

The conditions for the seed crystal 57 can be used as appropriate for generating glow discharge plasma when forming the second microcrystalline semiconductor film 61. Note that the throughput can be improved by generating glow discharge plasma of the seed crystal 57, the first microcrystalline semiconductor film 59, and the second microcrystalline semiconductor film 61 under the same conditions. Also good.

Here, a method for alternately increasing or decreasing the flow ratio of the deposition gas containing silicon or germanium and hydrogen will be described with reference to FIG. FIG. 2 is a timing chart showing temporal changes in the source gas and the power supplied to the apparatus in the method for forming the second microcrystalline semiconductor film 61 shown in this embodiment. In FIG. 2, a solid line 71 indicates the on / off state of the power source of the plasma CVD apparatus, a solid line 73 indicates the flow rate of hydrogen, and a solid line 75 indicates the flow rate of the deposition gas containing silicon or germanium (FIG. 2 is silane). The solid line 79 indicates the flow rate of the rare gas (argon in FIG. 2).

A deposition gas containing silicon or germanium, which is a source gas, and hydrogen are introduced into a processing chamber of the plasma CVD apparatus, and the processing chamber is set to a predetermined pressure. Further, the temperature of the substrate 51 is set to a predetermined temperature. At this time, hydrogen is supplied to the processing chamber at a constant flow rate (flow rate a in FIG. 2).

Next, the power source of the high frequency power source is turned on to perform plasma discharge. A deposition gas containing silicon or germanium is supplied to the processing chamber while alternately increasing or decreasing the flow rate. Here, alternately increasing or decreasing the flow rate ratio between the deposition gas containing silicon or germanium and hydrogen is referred to as a cycle flow. In this embodiment, after turning on the power, a first period in which a deposition gas containing silicon or germanium at a flow rate c is supplied for t1 seconds, and a deposition property containing silicon or germanium at a flow rate b (0 <b <c) is used. The second period of flowing the gas for t2 seconds is repeated. Here, t2 seconds of the second period is longer than t1 seconds of the first period. Since the flow rate of the deposition gas containing silicon or germanium is smaller in the second period than in the first period, the deposition period containing silicon or germanium is more in the second period than in the first period. The flow ratio of hydrogen to gas is large. In the first cycle, when the flow rate of hydrogen with respect to the deposition gas is set to 100 times or more and 2000 times or less, the subsequent plasma discharge causes preferential deposition and crystal growth of the microcrystalline semiconductor, and in the second cycle, Etching of the amorphous semiconductor region occurs preferentially.

In the plasma in the first period and the second period, radicals generated from a deposition gas containing silicon or germanium are formed together with hydrogen radicals. When the pressure in the treatment chamber is 1333 Pa to 50,000 Pa (10 Torr to 370 Torr or less), more preferably 1333 Pa to 13332 Pa (10 Torr to 100 Torr), the mean free path of the deposition gas is short because hydrogen is high. Since radicals and hydrogen ions lose energy each time they collide, when they reach the first microcrystalline semiconductor film 59, the energy of hydrogen radicals or hydrogen ions decreases.

In the first period in which the flow rate of the deposition gas containing silicon or germanium under the above pressure is large (in FIG. 2, the period where the flow rate is c), silicon or germanium is compared with the second period where the flow rate is b. Since there are a large number of radicals generated from the deposition gas containing, on the surface of the first microcrystalline semiconductor film 59, the deposition and crystal growth of the microcrystalline semiconductor are superior to the etching action. Further, when the pressure in the treatment chamber is set to the above pressure, energy of ions and radicals is reduced, so that plasma damage to the second microcrystalline semiconductor film 61 during deposition is reduced, which contributes to reduction of defects.

Further, in the second period (the period of flow rate b in FIG. 2) in which the flow rate of the deposition gas containing silicon or germanium under the pressure is small, hydrogen radicals dissociated in the plasma are subjected to the second condition. The first microcrystalline semiconductor film 59 formed in step 1 and the amorphous semiconductor region included in the microcrystalline semiconductor deposited on the first microcrystalline semiconductor film 59 are selectively etched to expose crystallites.

By repeating the first period and the second period, the crystallites are exposed by preferential etching of the amorphous semiconductor region in the second period, and the exposed crystallites are used as nuclei in the first period. Since crystal growth occurs alternately, the size of crystallites of mixed phase grains increases, and further crystal growth having an orientation plane occurs. In addition, since the second period is longer than the first period, the amorphous semiconductor region included in the microcrystalline semiconductor is sufficiently etched, so that the amorphous state included in the second microcrystalline semiconductor film is obtained. It is possible to reduce the amount of quality semiconductor. As a result, the second microcrystalline semiconductor film having higher crystallinity than the first microcrystalline semiconductor film can be formed without widening the gap between the mixed phase grains contained in the first microcrystalline semiconductor film. In addition, defects in the second microcrystalline semiconductor film 61 can be reduced.

In addition, in the second period, a small amount of radicals generated from the deposition gas by flowing a deposition gas containing silicon or germanium at a slight flow rate, typically greater than 0 sccm and less than or equal to 0.3 sccm. Since (typically, silyl radicals) are bonded to dangling bonds of crystallites exposed by etching of the amorphous semiconductor region, crystal growth with high crystallinity occurs. That is, crystal growth occurs with etching, so that the crystallinity of the second microcrystalline semiconductor film 61 becomes higher.

First, after the first period in which the flow rate of the deposition gas containing silicon or germanium is the flow rate c, the flow rate is changed to the second cycle in which the flow rate of the deposition gas containing silicon or germanium is the flow rate b. However, you may change into the 1st period set as the flow volume c after the 2nd period which flows the deposition gas containing the silicon | silicone or germanium of the flow volume b first. T1 and t2 are preferably several seconds to several tens of seconds. When t1 and t2 become several minutes, for example, a microcrystalline semiconductor film having a low crystallinity of several nanometers is formed at t1, and then only the surface of the microcrystalline semiconductor film reacts at t2, This is because it is difficult to increase crystallinity inside the microcrystalline semiconductor film.

Here, the first period, that is, the time for flowing the deposition gas containing silicon or germanium at the flow rate c is all t1 seconds, but may be different. In addition, the second period, that is, the flow time of the deposition gas containing silicon or germanium at the flow rate b (b <c) is all t2 seconds, but may be varied.

Further, as shown by the solid line 79 in FIG. 2, no rare gas such as helium, neon, argon, krypton, or xenon is introduced into the source gas, but as shown by the broken line 77, the rare gas is introduced into the processing chamber. Also good. Alternatively, the rare gas may be introduced into the processing chamber while alternately increasing or decreasing the number.

Note that although the flow rate of hydrogen is constant here, the flow rate may be changed as long as it is an amount of hydrogen necessary for forming the second microcrystalline semiconductor film 61. Alternatively, the deposition gas containing silicon or germanium may be set to a constant flow rate, and the hydrogen flow rate may be alternately increased or decreased.

In addition, the deposition rate of the second microcrystalline semiconductor film 61 can be improved by switching the flow rate of the source gas while the high frequency power source is turned on.

Further, the high frequency power supply may be turned off after setting the flow rate of the deposition gas containing silicon or germanium to the processing chamber as c, that is, after the first period. Alternatively, after setting the flow rate of the deposition gas containing silicon or germanium to the processing chamber as b, that is, after the second period, the high frequency power supply may be cut off.

Here, the flow rate b of the deposition gas containing silicon or germanium is 0 <b <c, but the flow rate b may be b = 0 sccm. That is, the period for introducing the deposition gas containing silicon or germanium and the period for not introducing the deposition gas may be alternately provided. In addition, as indicated by a broken line 72, the high-frequency power supply increases power to increase the deposition rate during the first period and reduces etching of crystallites contained in the microcrystalline semiconductor during the second period. Therefore, the power may be lowered.

If the pressure in the processing chamber is 1333 Pa to 50000 Pa (10 Torr to 370 Torr or less), more preferably 1333 Pa to 13332 Pa (10 Torr to 100 Torr), the pressure in the second condition is higher than the pressure in the first condition. Also good. Alternatively, the pressure of the first condition may be higher than the second condition. Alternatively, the pressures in the first condition and the second condition may be the same.

Next, as shown in FIG. 1D, a third microcrystalline semiconductor film 63 is formed over the second microcrystalline semiconductor film 61. The third microcrystalline semiconductor film 63 is formed under the condition that the mixed phase grains are grown to fill the gaps in the mixed phase grains.

The third microcrystalline semiconductor film 63 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium with hydrogen under a fourth condition in a processing chamber of a plasma CVD apparatus. Alternatively, a deposition gas containing silicon or germanium, hydrogen, and a rare gas such as helium, neon, argon, krypton, or xenon are mixed under the fourth condition and formed by glow discharge plasma. The fourth condition is the same as the second condition.

Under the fourth condition, a microcrystalline silicon film, a microcrystalline silicon germanium film, a microcrystalline germanium film, or the like is formed as the third microcrystalline semiconductor film 63.

If the fourth condition is the same as the second condition, the pressure in the processing chamber is high, the mean free path is short, and hydrogen radicals and hydrogen ions lose energy each time they collide. Becomes lower and the coverage is improved. In addition, since the deposition ratio of the deposition gas containing silicon or germanium is high and the amount of hydrogen radicals generated is increased, the crystallites included in the second microcrystalline semiconductor film 61 are etched while the amorphous semiconductor region is etched. Crystal grows as a nucleus. As a result, the ratio of the crystal region to the amorphous semiconductor region in the third microcrystalline semiconductor film 63 is increased, and the crystallinity is increased. In addition, this contributes to planarization of the second microcrystalline semiconductor film 61 and the third microcrystalline semiconductor film 63 being deposited.

Through the above steps, the microcrystalline semiconductor film 64 can be formed.

Here, FIGS. 1E to 1H are conceptual diagrams of forming the microcrystalline semiconductor film 64 described in this embodiment. FIGS. 1E to 1H are enlarged views schematically illustrating the deposition states in FIGS. 1A to 1D, respectively.

As shown in FIG. 1E, the seed crystal 57 deposition step is a step of interspersing the mixed phase grains 57a in order to increase the size of the mixed phase grains contained in the microcrystalline semiconductor film 63 to be formed later. . Therefore, as shown in FIG. 1E, the seed crystal 57 is deposited with mixed phase grains 57a with a gap 57b.

As shown in FIG. 1F, the deposition process of the first microcrystalline semiconductor film 59 is a process of growing a crystal based on seed crystal particles to form a film having mixed phase grains with very few gaps. Therefore, the microcrystalline semiconductor 58 is deposited while crystal growth is performed using the mixed phase grains 57a as seeds. Note that when the pressure in the treatment chamber is 1333 Pa to 50,000 Pa (10 Torr to 370 Torr or less), more preferably 1333 Pa to 13332 Pa (10 Torr to 100 Torr), the microcrystalline semiconductor 58 is not only in the film thickness direction but also in the planar direction. Since crystal growth also occurs, the gap between the microcrystalline semiconductors 58 is filled and the microcrystalline semiconductors 58 are in contact with each other.

As shown in FIG. 1G, the deposition process of the second microcrystalline semiconductor film 61 is a process of depositing a microcrystalline semiconductor 60 with higher crystallinity on the microcrystalline semiconductor 58. In the step of depositing the second microcrystalline semiconductor film 61, the steps of depositing and growing the microcrystalline semiconductor and the amorphous semiconductor region included in the microcrystalline semiconductor are preferentially etched to be included in the microcrystalline semiconductor. The process of exposing the crystallites is alternately performed. In addition, since the pressure in the treatment chamber is 1333 Pa to 50000 Pa (10 Torr to 370 Torr), more preferably 1333 Pa to 13332 Pa (10 Torr to 100 Torr), the amorphous semiconductor region included in the microcrystalline semiconductor is preferentially used. Etched. For these reasons, epitaxial growth is likely to occur when a microcrystalline semiconductor is deposited on the exposed crystallites. As a result, in the deposition process of the second microcrystalline semiconductor film 61, the orientation of the microcrystalline semiconductor becomes high, and the microcrystalline semiconductor 60 having an orientation surface is deposited.

As shown in FIG. 1H, in the step of depositing the third microcrystalline semiconductor film 63, crystal growth is performed based on the second microcrystalline semiconductor film 61, and the mixed phase grains of the second microcrystalline semiconductor film 61 are formed. In this step, the unevenness of the second microcrystalline semiconductor film 61 is reduced and planarized while filling the gap. Therefore, the microcrystalline semiconductor 62 is deposited while growing the crystal using the microcrystalline semiconductor 60 as a seed.

Through the steps of FIGS. 1E to 1H, the microcrystalline semiconductor film 64 having high crystallinity, extremely small gaps between mixed phase grains, and mixed phase grains having orientation planes can be formed. it can. Note that mixed phase grains contained in the microcrystalline semiconductor film 64 are microcrystals deposited by the seed crystal 57, the first microcrystalline semiconductor film 59, the second microcrystalline semiconductor film 61, or the third microcrystalline semiconductor film 63. It may be a semiconductor. Alternatively, there is a case where two or more of the seed crystal 57, the first microcrystalline semiconductor film 59, the second microcrystalline semiconductor film 61, and the third microcrystalline semiconductor film 63 are microcrystalline semiconductors deposited while growing crystals. .

The thickness of the seed crystal 57 is preferably 1 nm or more and 10 nm or less. If the thickness of the seed crystal 57 is greater than 10 nm, it is difficult to fill the gaps of the mixed phase grains 57a even if the first microcrystalline semiconductor film 59 is deposited, and an amorphous material included in the seed crystal 57 is formed. Etching of the crystalline semiconductor becomes difficult, and the crystallinity of the seed crystal 57 and the first microcrystalline semiconductor film 59 is reduced. On the other hand, since the seed crystal 57 needs to form mixed phase grains, the thickness of the seed crystal 57 is preferably 1 nm or more.

The seed crystal 57, the first microcrystalline semiconductor film 59, the second microcrystalline semiconductor film 61, and the third microcrystalline semiconductor film 63 include a microcrystalline semiconductor. A microcrystalline semiconductor is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). For this reason, the microcrystalline semiconductor has an amorphous semiconductor region. A microcrystalline semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline semiconductor having a short-range order and lattice distortion, and a mixed phase particle size of 2 nm to 200 nm, preferably 10 nm. Columnar or needle-like mixed phase grains having a size of 80 nm or more and more preferably 20 nm or more and 50 nm or less grow in a normal direction with respect to the substrate surface. For this reason, a grain boundary may be formed at the interface between the columnar or needle-like mixed phase grains. Here, the crystal grain size refers to the maximum diameter of crystal grains in a plane parallel to the substrate surface.

Microcrystalline silicon, which is a typical example of a microcrystalline semiconductor, has its Raman spectrum peak shifted to a lower wave number side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. It also contains at least 1 atomic% or more of hydrogen or halogen to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, neon, argon, krypton, or xenon to further promote the lattice distortion, the stability can be improved and a good microcrystalline semiconductor can be obtained. A description of such a microcrystalline semiconductor is disclosed in, for example, US Pat. No. 4,409,134.

According to this embodiment, a microcrystalline semiconductor film with a flat surface and improved crystallinity by reducing the gaps between mixed phase grains can be manufactured.

(Embodiment 2)
In this embodiment, a method for manufacturing a thin film transistor formed in a semiconductor device which is one embodiment of the present invention will be described with reference to FIGS. Note that in the thin film transistor, the n-type has higher carrier mobility than the p-type. In addition, it is preferable that all the thin film transistors formed over the same substrate have the same polarity because the number of steps can be reduced. Therefore, in this embodiment, a method for manufacturing an n-type thin film transistor is described.

Note that the on-state current refers to a current that flows between a source electrode and a drain electrode when a thin film transistor is on. For example, in the case of an n-type thin film transistor, the current flows between the source electrode and the drain electrode when the gate voltage is higher than the threshold voltage of the transistor.

The off current refers to a current that flows between the source electrode and the drain electrode when the thin film transistor is in an off state. For example, in the case of an n-type thin film transistor, the current flows between the source electrode and the drain electrode when the gate voltage is lower than the threshold voltage of the thin film transistor.

As shown in FIG. 3A, the gate electrode 103 is formed over the substrate 101. Next, a gate insulating film 105 is formed to cover the gate electrode 103 (also referred to as a first gate electrode), and the seed crystal 107, the first microcrystalline semiconductor film 108, and the second microcrystal are formed over the gate insulating film 105. A semiconductor film 109 and a third microcrystalline semiconductor film 110 are formed.

As the substrate 101, the substrate 51 described in Embodiment 1 can be used as appropriate.

The gate electrode 103 is formed as a single layer or a stacked layer using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or nickel, or an alloy material containing these as a main component. be able to. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, an Ag—Pd—Cu alloy, an Al—Nd alloy, an Al—Ni alloy, or the like may be used.

For example, the gate electrode 103 has a two-layer structure in which a molybdenum film is stacked on an aluminum film, a two-layer structure in which a molybdenum film is stacked on a copper film, or titanium nitride on a copper film. A two-layer structure in which a film or a tantalum nitride film is laminated, a two-layer structure in which a titanium nitride film and a molybdenum film are laminated, a two-layer structure in which a copper-magnesium alloy film containing oxygen and a copper film are laminated, copper containing oxygen A two-layer structure in which a manganese alloy film and a copper film are stacked, a two-layer structure in which a copper-manganese alloy film and a copper film are stacked, and the like are preferable. The three-layer structure is preferably a three-layer structure in which a tungsten film or a tungsten nitride film, an alloy film of aluminum and silicon or an alloy film of aluminum and titanium, and a titanium nitride film or a titanium film are stacked. By laminating a metal film functioning as a barrier film over a film with low electrical resistance, the electrical resistance of the gate electrode 103 can be lowered and diffusion of the metal element from the metal film to the semiconductor film can be prevented. it can.

The gate electrode 103 is formed by forming a conductive film using the above material on the substrate 101 by a sputtering method or a vacuum evaporation method, forming a mask on the conductive film by a photolithography method, an inkjet method, or the like. Can be formed by etching the conductive film. Alternatively, a conductive nano paste such as silver, gold, or copper can be formed by discharging onto a substrate by an ink jet method and baking. Note that a nitride film of the above metal material may be provided between the substrate 101 and the gate electrode 103 for the purpose of improving adhesion between the gate electrode 103 and the substrate 101. Here, a conductive film is formed over the substrate 101, and the conductive film is etched using a mask formed of a resist formed by a photolithography process.

Note that the side surface of the gate electrode 103 is preferably tapered. This is for preventing an insulating film, a semiconductor film, and a wiring formed over the gate electrode 103 from being cut at a step portion of the gate electrode 103 in a later step. In order to taper the side surface of the gate electrode 103, etching may be performed while a mask formed of a resist is retracted.

In addition, a gate wiring (scanning line) and a capacitor wiring can be formed at the same time by the step of forming the gate electrode 103. Note that a scanning line refers to a wiring for selecting a pixel, and a capacitor wiring refers to a wiring connected to one electrode of a storage capacitor of the pixel. However, the present invention is not limited to this, and one or both of the gate wiring and the capacitor wiring may be provided separately from the gate electrode 103.

The gate insulating film 105 (also referred to as a first gate insulating film) can be formed using the insulating film 55 described in Embodiment 1 as appropriate. Note that when the gate insulating film 105 is formed using an oxide insulating film such as silicon oxide or silicon oxynitride, variation in threshold voltage of the thin film transistor can be reduced.

The gate insulating film 105 can be formed by a CVD method, a sputtering method, or the like. In the formation process of the gate insulating film 105 by the CVD method, the conditions of the seed crystal 57 described in Embodiment 1 can be used as appropriate for generating glow discharge plasma. In addition, when the gate insulating film 105 is formed using a microwave plasma CVD apparatus with a high frequency of 1 GHz or more, the breakdown voltage between the gate electrode, the drain electrode, and the source electrode can be improved; A high thin film transistor can be obtained.

In addition, by forming a silicon oxide film by a CVD method using an organosilane gas as the gate insulating film 105, crystallinity of a semiconductor film to be formed later can be increased; The degree can be increased. Examples of the organic silane gas include tetraethoxysilane (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetra Use of silicon-containing compounds such as siloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ) Can do.

The seed crystal 107, the first microcrystalline semiconductor film 108, the second microcrystalline semiconductor film 109, and the third microcrystalline semiconductor film 110 are the seed crystal 57 and the first microcrystalline semiconductor described in Embodiment 1, respectively. The film 59, the second microcrystalline semiconductor film 61, and the third microcrystalline semiconductor film 63 are formed using the same conditions.

In this embodiment mode, the seed crystal 107 is formed using the first condition and the first microcrystalline semiconductor film 108 is formed using the second condition, so that the crystallinity is high and the mixed phase grains are formed. A dense microcrystalline semiconductor film with reduced gaps can be formed. In addition, the second microcrystalline semiconductor film 109 is formed over the first microcrystalline semiconductor film 108 using the third condition, so that the crystallinity higher than that of the first microcrystalline semiconductor film 108 can be obtained. A crystalline semiconductor film can be formed. In addition, although the third microcrystalline semiconductor film 110 is formed over the second microcrystalline semiconductor film 109 using the fourth condition, crystallinity is slightly lower than that of the second microcrystalline semiconductor film 109. A microcrystalline semiconductor film having higher crystallinity and higher flatness than the first microcrystalline semiconductor film 108 can be formed while filling a gap between mixed phase grains included in the second microcrystalline semiconductor film 109. it can.

Next, as illustrated in FIG. 3B, a semiconductor film 111 is formed over the third microcrystalline semiconductor film 110. The semiconductor film 111 includes a microcrystalline semiconductor region 111a and an amorphous semiconductor region 111b. Next, the impurity semiconductor film 113 is formed over the semiconductor film 111. Next, a mask 115 formed of a resist is formed over the impurity semiconductor film 113.

Using the third microcrystalline semiconductor film 110 as a nucleus, the semiconductor film 111 including the microcrystalline semiconductor region 111a and the amorphous semiconductor region 111b is formed under a condition for partial crystal growth (a condition for suppressing crystal growth). Can do.

The semiconductor film 111 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium with a gas containing hydrogen and nitrogen in a processing chamber of a plasma CVD apparatus. Examples of the gas containing nitrogen include ammonia, nitrogen, nitrogen fluoride, nitrogen chloride, chloroamine, and fluoroamine. The glow discharge plasma can be generated in the same manner as the seed crystal 107.

At this time, a flow rate ratio between a deposition gas containing silicon or germanium and hydrogen is formed as a microcrystalline semiconductor film similar to the seed crystal 107 and the first microcrystalline semiconductor film 108 to the third microcrystalline semiconductor film 110. By using the flow rate ratio and the conditions for using nitrogen-containing gas as the source gas, the crystal condition is higher than the deposition conditions of the seed crystal 107 and the first microcrystalline semiconductor film 108 to the third microcrystalline semiconductor film 110. Growth can be suppressed. Specifically, in the initial deposition of the semiconductor film 111, since the source gas contains a gas containing nitrogen, crystal growth is partially suppressed, and a conical microcrystalline semiconductor region grows and is amorphous. A semiconductor region is formed. Further, in the middle or later stage of deposition, the crystal growth of the cone-shaped microcrystalline semiconductor region stops, and only the amorphous semiconductor region is deposited. As a result, the semiconductor film 111 is formed using a microcrystalline semiconductor region 111a and a highly ordered semiconductor film with few defects and a steep inclination of a level tail at the band edge of the valence band. A crystalline semiconductor region 111b can be formed.

Here, as a typical example of the conditions for forming the semiconductor film 111, the flow rate of hydrogen is 10 to 2000 times, preferably 10 to 200 times that of the deposition gas containing silicon or germanium. Note that as a typical example of a condition for forming a normal amorphous semiconductor film, the flow rate of hydrogen is 0 to 5 times the flow rate of a deposition gas containing silicon or germanium.

In addition, the deposition rate can be increased by adding a rare gas such as helium, neon, argon, krypton, or xenon to the source gas of the semiconductor film 111.

The thickness of the semiconductor film 111 is preferably 50 to 350 nm, and more preferably 120 to 250 nm.

Here, an enlarged view between the gate insulating film 105 and the impurity semiconductor film 113 illustrated in FIG. 3B is illustrated in FIG.

As shown in FIG. 4A, the microcrystalline semiconductor region 111a of the semiconductor film 111 is uneven, and the protrusion narrows from the gate insulating film 105 toward the amorphous semiconductor region 111b (the protrusion of the protrusion). It has a convex shape (cone shape) with a sharp tip. Note that the microcrystalline semiconductor region 111a may have a convex shape (inverted cone shape) whose width increases from the gate insulating film 105 toward the amorphous semiconductor region 111b.

The thickness of the seed crystal 107, the first microcrystalline semiconductor film 108, the second microcrystalline semiconductor film 109, the third microcrystalline semiconductor film 110, and the microcrystalline semiconductor region 111a, that is, the gate insulating film 105 and the seed crystal The distance from the interface 107 to the tip of the protrusion (convex portion) of the microcrystalline semiconductor region 111a is 5 nm or more and 310 nm or less, so that the protrusion (projection) of the microcrystalline semiconductor region 111a is formed later. Since it is not in contact with the film, the off-state current of the thin film transistor can be reduced.

Further, the concentration of oxygen contained in the semiconductor film 111 measured by secondary ion mass spectrometry (SIMS) is less than 1 × 10 ¹⁸ atoms / cm ³ , so that the microcrystalline semiconductor region 111a It is preferable because the crystallinity can be improved. The peak concentration of the nitrogen concentration profile of the semiconductor film 111 measured by secondary ion mass spectrometry is 1 × 10 ²⁰ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less, preferably 2 × 10 ²⁰ atoms. / Cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less.

The amorphous semiconductor region 111b is formed using an amorphous semiconductor containing nitrogen. Nitrogen contained in an amorphous semiconductor having nitrogen may exist as, for example, an NH group or an NH ₂ group. Amorphous silicon is used as the amorphous semiconductor.

An amorphous semiconductor containing nitrogen is a semiconductor with a small amount of defect absorption spectrum and a low energy at the Urbach edge measured by constant photocurrent method (CPM) or photoluminescence spectroscopy, compared to a conventional amorphous semiconductor. is there. That is, an amorphous semiconductor containing nitrogen has a high degree of ordering with fewer defects and a steep slope of the level tail at the band edge of the valence band than a conventional amorphous semiconductor. It is a semiconductor. An amorphous semiconductor containing nitrogen has a steep inclination of a level tail at the band edge of the valence band, so that a band gap becomes wide and a tunnel current hardly flows. Therefore, by providing an amorphous semiconductor containing nitrogen between the microcrystalline semiconductor region 111a and the impurity semiconductor film 113, off-state current of the thin film transistor can be reduced. In addition, by providing an amorphous semiconductor containing nitrogen, on-state current and field-effect mobility can be increased.

Further, an amorphous semiconductor containing nitrogen has a spectrum peak by low temperature photoluminescence spectroscopy in the range of 1.31 eV to 1.39 eV. Note that a peak region of a spectrum of microcrystalline semiconductor, typically microcrystalline silicon measured by low-temperature photoluminescence spectroscopy, is 0.98 eV or more and 1.02 eV or less, and an amorphous semiconductor containing nitrogen is a microcrystalline semiconductor. Is different.

In addition to the amorphous semiconductor region 111b, the microcrystalline semiconductor region 111a may have an NH group or an NH ₂ group.

Further, as shown in FIG. 4B, by adding semiconductor mixed phase grains 111c having a grain size of 1 nm to 10 nm, preferably 1 nm to 5 nm, in the amorphous semiconductor region 111b, an on-current and an electric field are further increased. Effective mobility can be increased.

A convex (cone-shaped) microcrystalline semiconductor with a narrowed tip from the gate insulating film 105 toward the amorphous semiconductor region 111b is partially formed after the microcrystalline semiconductor film is formed under conditions where the microcrystalline semiconductor is deposited. Such a structure is obtained by crystal growth under crystal growth conditions and deposition of an amorphous semiconductor.

Since the microcrystalline semiconductor region 111a of the semiconductor film 111 has a conical shape or an inverted conical shape, the resistance in the vertical direction (film thickness direction) when a voltage is applied between the source electrode and the drain electrode in the on state, that is, The resistance of the semiconductor film 111 can be reduced. In addition, there is little defect between the microcrystalline semiconductor region 111a and the impurity semiconductor film 113, and the level tail at the band edge of the valence band is steep. Since it has a crystalline semiconductor, a tunnel current hardly flows. From the above, the thin film transistor described in this embodiment can increase on-state current and field-effect mobility and can reduce off-state current.

Here, the semiconductor film 111 including the microcrystalline semiconductor region 111a and the amorphous semiconductor region 111b is formed by including a gas containing nitrogen in the source gas of the semiconductor film 111; however, as another method for forming the semiconductor film 111, After exposing the surface of the microcrystalline semiconductor film 109 to a gas containing nitrogen and adsorbing the nitrogen to the surface of the microcrystalline semiconductor film 109, the microcrystalline semiconductor is formed using a deposition gas containing silicon or germanium and hydrogen as a source gas. A semiconductor film 111 including the region 111a and the amorphous semiconductor region 111b can be formed.

The impurity semiconductor film 113 is formed using amorphous silicon to which phosphorus is added, microcrystalline silicon to which phosphorus is added, or the like. Alternatively, a stacked structure of amorphous silicon to which phosphorus is added and microcrystalline silicon to which phosphorus is added can be used. Note that in the case where a p-type thin film transistor is formed as the thin film transistor, the impurity semiconductor film 113 is formed using microcrystalline silicon to which boron is added, amorphous silicon to which boron is added, or the like. Note that in the case where the semiconductor film 111 and the wirings 129a and 129b to be formed later are in ohmic contact, the impurity semiconductor film 113 is not necessarily formed.

The impurity semiconductor film 113 is formed by glow discharge plasma by mixing a deposition gas containing silicon, hydrogen, and phosphine (hydrogen dilution or silane dilution) in a processing chamber of a plasma CVD apparatus. Thus, amorphous silicon to which phosphorus is added or microcrystalline silicon to which phosphorus is added is formed. Note that in the case of manufacturing a p-type thin film transistor, the impurity semiconductor film 113 may be formed by glow discharge plasma using diborane instead of phosphine.

In the case where the impurity semiconductor film 113 is formed using microcrystalline silicon to which phosphorus is added or microcrystalline silicon to which boron is added, the microcrystalline semiconductor film is interposed between the semiconductor film 111 and the impurity semiconductor film 113. Typically, the interface characteristics can be improved by forming a microcrystalline silicon film. As a result, resistance generated at the interface between the impurity semiconductor film 113 and the semiconductor film 111 can be reduced. As a result, the amount of current flowing through the source region, the semiconductor film, and the drain region of the thin film transistor can be increased, and the on-current and the field effect mobility can be increased.

Further, the third microcrystalline semiconductor film 110 is formed over the second microcrystalline semiconductor film 109, whereby the flatness of the microcrystalline semiconductor film can be increased; thus, the semiconductor film 111 having flatness and The impurity semiconductor film 113 can be formed.

The mask 115 formed using a resist can be formed by a photolithography process.

Next, using the mask 115 formed of a resist, the seed crystal 107, the first microcrystalline semiconductor film 108, the second microcrystalline semiconductor film 109, the third microcrystalline semiconductor film 110, the semiconductor film 111, and The impurity semiconductor film 113 is selectively etched. Through this step, the seed crystal 107, the first microcrystalline semiconductor film 108, the second microcrystalline semiconductor film 109, the third microcrystalline semiconductor film 110, the semiconductor film 111, and the impurity semiconductor film 113 are separated for each element. Then, the island-shaped semiconductor stacked body 117 and the island-shaped impurity semiconductor film 121 are formed. Note that the semiconductor stacked body 117 includes part of the seed crystal 107, the first microcrystalline semiconductor film 108, the second microcrystalline semiconductor film 109, the third microcrystalline semiconductor film 110, and the semiconductor film 111. , A seed crystal 107, a first microcrystalline semiconductor film 108, a second microcrystalline semiconductor film 109, a third microcrystalline semiconductor film 110, and a microcrystalline semiconductor region that includes part of the microcrystalline semiconductor region 111 a of the semiconductor film 111. A region 117 a and an amorphous semiconductor region 117 b including part of the amorphous semiconductor region 111 b of the semiconductor film 111 are included. After that, the mask 115 formed with a resist is removed (see FIG. 3C).

Next, a conductive film 127 is formed over the impurity semiconductor film 121 (see FIG. 5A). The conductive film 127 can be formed as a single layer or a stacked layer using aluminum, copper, titanium, neodymium, scandium, molybdenum, chromium, tantalum, tungsten, or the like. Alternatively, an aluminum alloy to which a hillock prevention element is added (such as an Al—Nd alloy that can be used for the gate electrode 103) may be used. Crystalline silicon to which an impurity element which serves as a donor is added may be used. A film on the side in contact with crystalline silicon to which an impurity element serving as a donor is added is formed of titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and a stacked structure in which aluminum or an aluminum alloy is formed thereon. Also good. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed. The conductive film 127 is formed by a CVD method, a sputtering method, or a vacuum evaporation method. Alternatively, the conductive film 127 may be formed by discharging and baking a conductive nanopaste of silver, gold, copper, or the like using a screen printing method, an inkjet method, or the like.

By forming the conductive film 127 over the impurity semiconductor film 121 with high flatness, the flatness of the conductive film 127 can be improved.

Next, a mask formed of a resist is formed by a photolithography step, and the conductive film 127 is etched using the mask formed of the resist, so that wirings 129a and 129b functioning as a source electrode and a drain electrode are formed. (See FIG. 5B.) For the etching of the conductive film 127, dry etching or wet etching can be used. Note that one of the wirings 129a and 129b functions not only as a source electrode or a drain electrode but also as a signal line. However, the present invention is not limited to this, and the signal line, the source electrode, and the drain electrode may be provided separately.

Next, part of the impurity semiconductor film 121 and the semiconductor stacked body 117 is etched, so that a pair of impurity semiconductor films 131a and 131b functioning as a source region and a drain region are formed. In addition, the semiconductor stacked body 133 including the microcrystalline semiconductor region 133a and the pair of amorphous semiconductor regions 133b is formed. At this time, by etching the semiconductor stacked body 117 so that the microcrystalline semiconductor region 133a is exposed, the microcrystalline semiconductor region 133a and the amorphous semiconductor region 133b are stacked in a region covered with the wirings 129a and 129b. In a region that is not covered with 129a and 129b and overlaps at least with the gate electrode, a semiconductor stacked body 133 is formed in which the microcrystalline semiconductor region 133a is exposed.

Since the surfaces of the semiconductor stacked body 117, the impurity semiconductor film 121, and the conductive film 127 have flatness, the microcrystalline semiconductor region exposed by etching the semiconductor stacked body 117 so that the microcrystalline semiconductor region 133a is exposed. The surface of 133a has flatness.

Since the surface of the microcrystalline semiconductor region 133a has flatness, surface scattering of electrons in the channel region on the back gate electrode side can be reduced, and field effect mobility of a thin film transistor formed later can be increased. it can. In addition, since the electric field of the back gate electrode is uniformly applied in the channel region on the back gate electrode side, off-state current of a thin film transistor to be formed later can be reduced. In addition, residual impurities on the surface of the microcrystalline semiconductor region 133a can be reduced. Since the impurity can serve as a carrier leakage path, off-state current of a thin film transistor to be formed later can be reduced.

Note that here, the end portions of the wirings 129a and 129b and the end portions of the impurity semiconductor films 131a and 131b are aligned, but the end portions of the wirings 129a and 129b and the end portions of the impurity semiconductor films 131a and 131b are aligned. In the cross section, the ends of the wirings 129a and 129b may be located inside the ends of the impurity semiconductor films 131a and 131b.

Next, dry etching may be performed. The dry etching is performed under such a condition that the exposed microcrystalline semiconductor region 133a and the amorphous semiconductor region 133b are not damaged and the etching rate for the microcrystalline semiconductor region 133a and the amorphous semiconductor region 133b is low. Typically, Cl ₂ , CF ₄ , N ₂ , or the like is used as an etching gas. The etching method is not particularly limited, and an inductively coupled plasma (ICP) method, a capacitively coupled plasma (CCP) method, an electron cyclotron resonance (ECR) method is used. Alternatively, a reactive ion etching (RIE) method or the like can be used.

Next, plasma treatment, typically water plasma treatment, oxygen plasma treatment, ammonia plasma treatment, nitrogen plasma treatment, plasma treatment with a mixed gas of oxygen and hydrogen, is performed on the surfaces of the microcrystalline semiconductor region 133a and the amorphous semiconductor region 133b. Etc.

Thereafter, the resist mask is removed. Note that the mask formed using the resist may be removed before dry etching of the impurity semiconductor film 121 and the semiconductor stacked body 117.

As described above, after the microcrystalline semiconductor region 133a and the amorphous semiconductor region 133b are formed, further dry etching is performed under conditions that do not damage the microcrystalline semiconductor region 133a and the amorphous semiconductor region 133b. Impurities such as residues present on the exposed microcrystalline semiconductor region 133a and the amorphous semiconductor region 133b can be removed. Further, by performing water plasma treatment following dry etching or plasma treatment using a mixed gas of oxygen and hydrogen, a residue of a mask formed using a resist is removed and defects in the microcrystalline semiconductor region 133a are reduced. Can do. Further, by performing plasma treatment, insulation between the source region and the drain region can be improved, off-state current of a completed thin film transistor can be reduced, and variation in electrical characteristics can be reduced.

Note that a mask formed of a resist by a photolithography process is formed over the conductive film 127, and the conductive film 127 is etched using the mask formed of the resist, so that the wiring 129a functioning as a source electrode and a drain electrode is formed. 129b is formed. Next, the impurity semiconductor film 121 is etched to form a pair of impurity semiconductor films 131a and 131b functioning as a source region and a drain region. At this time, a part of the semiconductor stacked body 117 may be etched. Next, after removing the resist mask, a part of the semiconductor stacked body 117 is etched to form a semiconductor stacked body 133 having a microcrystalline semiconductor region 133a and a pair of amorphous semiconductor regions 133b. Also good. Further, after the semiconductor stacked body 133 is formed, the surface of the semiconductor stacked body 133 is cleaned with a cleaning solution such as a solution obtained by diluting hydrofluoric acid with pure water in order to remove etching residues remaining on the surface of the microcrystalline semiconductor region 133a. May be. Furthermore, plasma treatment, typically water plasma treatment, oxygen plasma treatment, ammonia plasma treatment, nitrogen plasma treatment, plasma treatment with a mixed gas of oxygen and hydrogen, or the like is performed on the surface of the semiconductor stacked body 133 from which residues are removed. May be performed. Since the microcrystalline semiconductor region 133a serves as a channel region on the back gate side of a thin film transistor to be formed later, by removing residue in the region, electric characteristics of the thin film transistor to be formed later, typically on It is possible to increase current, reduce off-current, and reduce reliability deterioration.

As a result, since the microcrystalline semiconductor region 117a is covered with the amorphous semiconductor region 117b in the step of removing the resist mask, the microcrystalline semiconductor region 117a is in contact with the peeling solution and the resist residue. There is nothing. Further, after removing the mask formed of a resist, the amorphous semiconductor region 117b is etched using the wirings 129a and 129b, so that the microcrystalline semiconductor region 133a is exposed. Therefore, the amorphous semiconductor region that has come into contact with the stripping solution and the resist residue does not remain in the back channel. As a result, the leakage current due to the stripping solution remaining in the back channel and the residue of the resist is not generated, so that the off current of the thin film transistor can be further reduced.

Through the above process, a single-gate thin film transistor can be manufactured. In addition, with the structure described in this embodiment, a single-gate thin film transistor with low off-state current, high on-state current, and high field-effect mobility can be manufactured with high productivity.

Next, an insulating film 137 (also referred to as a second gate insulating film) is formed over the semiconductor stacked body 133, the impurity semiconductor films 131a and 131b, and the wirings 129a and 129b. The insulating film 137 can be formed in a manner similar to that of the gate insulating film 105.

Next, a mask formed of a resist is formed by a photolithography process, and an opening (not shown) is formed in the insulating film 137 using the mask. Next, a back gate electrode 139 (also referred to as a second gate electrode) is formed over the insulating film 137 (see FIG. 5C). Through the above process, a dual-gate thin film transistor can be manufactured. Note that although not illustrated, a pixel electrode connected to one of the wirings 129 a and 129 b can be formed at the same time as the back gate electrode 139.

The back gate electrode 139 can be formed in a manner similar to that of the wirings 129a and 129b. The back gate electrode 139 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, and indium zinc oxide. Or a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added.

The back gate electrode 139 can be formed using a conductive composition including a light-transmitting conductive high molecule (also referred to as a conductive polymer). The back gate electrode 139 has a sheet resistance of 10,000 Ω / sq. The light transmittance at a wavelength of 550 nm is preferably 70% or more. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof.

The back gate electrode 139 is formed using a mask formed of a resist formed by a photolithography process after a thin film using any of the above materials is formed by a CVD method, a sputtering method, or a vacuum evaporation method. Can be formed by etching. Alternatively, the back gate electrode 139 may be formed by discharging and baking a conductive nanopaste of silver, gold, copper, or the like using a screen printing method, an inkjet method, or the like.

Next, the shape of the back gate electrode will be described with reference to FIG. 6 which is a top view of the thin film transistor.

As shown in FIG. 6A, the back gate electrode 139 can be formed in parallel with the gate electrode 103. In this case, the potential applied to the back gate electrode 139 and the potential applied to the gate electrode 103 can be arbitrarily controlled. For this reason, the threshold voltage of the thin film transistor can be controlled. Further, since a region where carriers flow, that is, a channel region is formed on the gate insulating film 105 side and the insulating film 137 side of the microcrystalline semiconductor region, the on-state current of the thin film transistor can be increased.

In addition, as illustrated in FIG. 6B, the back gate electrode 139 can be connected to the gate electrode 103. That is, the gate electrode 103 and the back gate electrode 139 can be connected to each other in the opening 150 formed in the gate insulating film 105 and the insulating film 137. In this case, the potential applied to the back gate electrode 139 and the potential applied to the gate electrode 103 are equal. As a result, in the semiconductor film, a region where carriers flow, that is, a channel region is formed on the gate insulating film 105 side and the insulating film 137 side of the microcrystalline semiconductor region, so that the on-state current of the thin film transistor can be increased.

Further, as illustrated in FIG. 6C, the back gate electrode 139 may be floating without being connected to the gate electrode 103. Even when no potential is applied to the back gate electrode 139, the channel region is formed on the gate insulating film 105 side and the insulating film 137 side of the microcrystalline semiconductor region, so that the on-state current of the thin film transistor can be increased.

Further, as illustrated in FIG. 6D, the back gate electrode 139 may overlap with the wirings 129a and 129b with the insulating film 137 interposed therebetween. Here, the back gate electrode 139 having the structure illustrated in FIG. 6A is used; however, the back gate electrode 139 illustrated in FIGS. 6B and 6C is also overlapped with the wirings 129a and 129b. May be.

In the single-gate thin film transistor and the dual-gate thin film transistor described in this embodiment, a channel region is formed using a microcrystalline semiconductor film which has a flat surface and improved crystallinity by reducing gaps between mixed phase grains. Is possible. Therefore, the amount of carrier movement of the single-gate thin film transistor and the dual-gate thin film transistor is increased, so that on-state current and field-effect mobility can be increased. In addition, since the channel region is a microcrystalline semiconductor film with improved crystallinity not only on the first gate insulating film side but also on the second gate insulating film side, the amount of carrier movement of the dual-gate thin film transistor increases. The on-current and the field effect mobility can be increased. Further, an amorphous semiconductor region 133b is provided between the microcrystalline semiconductor region 133a and the impurity semiconductor films 131a and 131b. Therefore, off current of the thin film transistor can be reduced. As described above, the areas of the single-gate thin film transistor and the dual-gate thin film transistor can be reduced, and the semiconductor device can be highly integrated. In addition, by using the thin film transistor described in this embodiment for a driver circuit of the display device, the area of the driver circuit can be reduced, so that the display device can be narrowed.

(Embodiment 3)
In this embodiment, a method for manufacturing a thin film transistor capable of further reducing off-state current as compared with Embodiment 2 will be described with reference to FIGS.

Similarly to Embodiment Mode 2, the semiconductor stacked body 117 is formed through the steps of FIGS. 3A to 3C as illustrated in FIG. 7A.

Next, plasma treatment is performed in which the side surface of the semiconductor stacked body 117 is exposed to the plasma 123 while the mask 115 formed of a resist is left. Here, plasma is generated in an oxidizing gas or nitriding gas atmosphere, and the semiconductor stacked body 117 is exposed to the plasma 123. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, water vapor, a mixed gas of oxygen and hydrogen. Examples of the nitriding gas include nitrogen, ammonia, nitrogen fluoride, nitrogen chloride, chloroamine, and fluoroamine. By generating plasma in an oxidizing gas or nitriding gas atmosphere, radicals are generated. The radical reacts with the semiconductor stacked body 117, and an insulating region that is an oxide or a nitride can be formed on the side surface of the semiconductor stacked body 117. Instead of plasma irradiation, ultraviolet light may be irradiated to generate radicals.

Further, when a mixed gas of oxygen, ozone, water vapor, oxygen, and hydrogen is used as the oxidizing gas, as shown in FIG. 7B, the mask 115a whose resist is retracted by plasma irradiation and the bottom area is reduced is formed. It is formed. For this reason, the exposed impurity semiconductor film 121 is oxidized together with the side surface of the semiconductor stacked body 117 by the plasma treatment, and an oxide or a part of the side surface of the semiconductor stacked body 117 and the side surface and upper surface of the impurity semiconductor film 121 are also oxidized. An insulating region 125 made of nitride is formed.

Next, as shown in Embodiment Mode 2, the same process as that in FIGS. 5A and 5B is performed, and as shown in FIG. 5C, the wiring 129a functioning as a source electrode and a drain electrode is formed. 129b, a semiconductor stacked body 133 including a pair of impurity semiconductor films 131a and 131b functioning as a source region and a drain region, a microcrystalline semiconductor region 133a and a pair of amorphous semiconductor regions 133b, and an insulating film 137 are formed. A single-gate thin film transistor can be manufactured.

In addition, by forming a back gate electrode over the insulating film 137, a dual-gate thin film transistor can be manufactured.

In the single-gate thin film transistor and the dual-gate thin film transistor described in this embodiment, a channel region is formed using a microcrystalline semiconductor film which has a flat surface and improved crystallinity by reducing gaps between mixed phase grains. Is possible. In addition, by providing an insulating region that is an oxide or nitride between the semiconductor stacked body 133 and the wirings 129a and 129b, injection of holes from the wirings 129a and 129b to the semiconductor stacked body 133 can be suppressed. A thin film transistor with low off-current, high field-effect mobility, and high on-current is obtained. Therefore, the area of the thin film transistor can be reduced, and high integration into a semiconductor device is possible. In addition, by using the thin film transistor described in this embodiment for a driver circuit of the display device, the area of the driver circuit can be reduced, so that the display device can be narrowed.

Note that although this embodiment has been described using Embodiment 2, other embodiments can be used as appropriate.

(Embodiment 4)
In this embodiment, a method for manufacturing a thin film transistor formed in a semiconductor device which is one embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a process corresponding to the process shown in FIG.

Similarly to Embodiment Mode 2, a conductive film 127 is formed through the steps of FIGS. 3A to 3C and FIG.

Next, as shown in FIG. 8, as in Embodiment 2, wirings 129a and 129b are formed, and part of the impurity semiconductor film 121 and the semiconductor stacked body 117 is etched to function as a source region and a drain region. A pair of impurity semiconductor films 131a and 131b are formed. In addition, the semiconductor stacked body 143 including the microcrystalline semiconductor region 143a and the amorphous semiconductor region 143b is formed. At this time, by etching part of the impurity semiconductor film and the amorphous semiconductor region, the microcrystalline semiconductor region 143a and the amorphous semiconductor region 143b are stacked in a region covered with the wirings 129a and 129b, and the wiring 129a, In a region that is not covered with 129b and overlaps with the gate electrode, the semiconductor semiconductor layer 143 is formed in which the microcrystalline semiconductor region 143a is not exposed and the amorphous semiconductor region 143b is exposed. Note that the etching amount of the semiconductor stacked body 117 here is smaller than that in FIG.

The subsequent steps are the same as those in the second embodiment.

Through the above process, a single-gate thin film transistor can be manufactured. Since this thin film transistor is amorphous on the back channel side, off-state current can be reduced as compared with the thin film transistor illustrated in FIG.

Further, in this embodiment, after the step illustrated in FIG. 5, the back gate electrode 139 may be formed through the insulating film 137 similarly to the step illustrated in FIG.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 5)
A thin film transistor is manufactured, and a semiconductor device having a display function (also referred to as a display device) can be manufactured using the thin film transistor in a pixel portion and further in a driver circuit. In addition, part or the whole of a driver circuit using a thin film transistor can be formed over the same substrate as the pixel portion to form a system-on-panel.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence) element, an organic EL element, and the like. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel. Further, in the process of manufacturing the display device, the element substrate which corresponds to one embodiment before the display element is completed is provided with a means for supplying current to the display element in each of the plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or after the conductive film to be the pixel electrode is formed and before the pixel electrode is formed by etching. It can be in any state, and all forms apply.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). In addition, a connector, for example, a module with an FPC (Flexible printed circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package), a module with a printed wiring board at the end of a TAB tape or TCP, or a display It is assumed that the display device includes all modules in which an IC (integrated circuit) is directly mounted on the element by a COG (Chip On Glass) method.

(Embodiment 6)
In this embodiment, a photoelectric conversion device which is one embodiment of a semiconductor device will be described. In the photoelectric conversion device described in this embodiment, a microcrystalline semiconductor film whose surface is flat and whose crystallinity is improved by reducing gaps between mixed phase grains as illustrated in Embodiment 1 is used for the semiconductor film. . Semiconductor films that employ a microcrystalline semiconductor film that has a flat surface and improved crystallinity by reducing gaps between mixed phase grains include semiconductor films that perform photoelectric conversion and semiconductor films that exhibit conductivity types. In particular, it is suitable for use in a semiconductor film that performs photoelectric conversion. Alternatively, a microcrystalline semiconductor film whose surface is flat at the interface between a semiconductor film that performs photoelectric conversion or a semiconductor film that exhibits conductivity type and another film and that has improved crystallinity by reducing gaps between mixed phase grains It can also be adopted.

By adopting the above-described configuration, resistance (series resistance) generated by a semiconductor film that performs photoelectric conversion or a semiconductor film exhibiting a conductivity type can be reduced and characteristics can be improved. In addition, optical and electrical losses at the interface between the semiconductor film that performs photoelectric conversion or the semiconductor film that exhibits conductivity type and another film can be suppressed, and photoelectric conversion efficiency can be improved. Hereinafter, one embodiment of a method for manufacturing a photoelectric conversion device will be described with reference to FIGS.

As shown in FIG. 9A, the first electrode 202 is formed over the substrate 200.

As the substrate 200, the substrate 51 described in Embodiment 1 can be used as appropriate. A plastic substrate can also be used. Plastic substrates include substrates containing thermosetting resins such as epoxy resins, unsaturated polyester resins, polyimide resins, bismaleimide triazine resins, cyanate resins, and thermoplastic resins such as polyphenylene oxide resins, polyetherimide resins, and fluorine resins. It is preferable to use a substrate including

The substrate 200 may have a texture structure. Thereby, it is possible to improve photoelectric conversion efficiency.

In this embodiment mode, a light-transmitting substrate is used because light enters from the back surface side (lower side of the drawing) of the substrate 200, but the second electrode 210 side to be formed later is used. However, the present invention is not limited to this when the light is incident from (upper side of the figure). In this case, a semiconductor substrate including a material such as silicon or a conductive substrate including a metal material may be used.

The first electrode 202 can be formed using the light-transmitting conductive material shown in the back gate electrode 139 described in Embodiment 2. The first electrode 202 is formed by a sputtering method, a CVD method, a vacuum evaporation method, a coating method, a printing method, or the like.

The first electrode 202 is formed to a thickness of 10 nm to 500 nm, preferably 50 nm to 100 nm. The sheet resistance of the first electrode 202 is 20 Ω / sq. To 200Ω / sq. It forms so that it may become.

Note that in this embodiment mode, the first electrode 202 is formed using a light-transmitting conductive material because light is incident from the back surface side (downward in the drawing) of the substrate 200. However, the present invention is not limited to this in the case where light is incident from the side of the second electrode 210 formed later (upper side in the drawing). In such a case, the first electrode 202 can be formed using a light-transmitting conductive material such as aluminum, platinum, gold, silver, copper, titanium, tantalum, or tungsten. In particular, when a material that easily reflects light such as aluminum, silver, titanium, or tantalum is used, the photoelectric conversion efficiency can be sufficiently improved.

Similar to the substrate 200, the first electrode 202 may have a texture structure. Further, an auxiliary electrode made of a low-resistance conductive material may be separately formed so as to be in contact with the first electrode 202.

Next, as illustrated in FIG. 9B, a semiconductor film 204 having the first conductivity type is formed over the first electrode 202. The semiconductor film 204 having the first conductivity type is typically formed using a semiconductor film containing a semiconductor material to which an impurity element imparting conductivity is added. As a semiconductor material, it is preferable to use silicon in terms of productivity and price. In the case of using silicon as the semiconductor material, phosphorus, arsenic, p-type boron, aluminum, or the like that imparts n-type conductivity is used as the impurity element that imparts conductivity type.

Note that in this embodiment mode, light enters from the back surface side (lower side of the drawing) of the substrate 200, and thus the conductivity type (first conductivity type) of the semiconductor film 204 indicating the first conductivity type is p. It is desirable to use a mold. This is because the lifetime of holes is as short as about half of the lifetime of electrons, and as a result, the diffusion length of holes is short, and the formation of electrons and holes is often performed on the light incident side of the semiconductor film 206 that performs photoelectric conversion. It is due to that. In this manner, by setting the first conductivity type to be p-type, it is possible to extract the current before the holes disappear, and thus it is possible to suppress a decrease in photoelectric conversion efficiency. Note that in a situation where the above does not cause a problem, for example, when the semiconductor film 206 that performs photoelectric conversion is sufficiently thin, the first conductivity type may be n-type.

Other semiconductor materials that can be used for the semiconductor film 204 having the first conductivity type include silicon carbide, germanium, gallium arsenide, indium phosphide, zinc selenide, gallium nitride, and silicon germanium. Alternatively, a semiconductor material containing an organic material, a semiconductor material containing a metal oxide, or the like can be used. The material can be selected as appropriate in relation to the semiconductor film 206 that performs photoelectric conversion.

There is no particular requirement on the crystallinity of the semiconductor film 204 having the first conductivity type; however, the semiconductor film 204 having the first conductivity type has a flat surface and gaps between mixed phase grains as described in Embodiment 1. When a microcrystalline semiconductor film with improved crystallinity is reduced, the series resistance is reduced compared to the case of using a conventional microcrystalline semiconductor film, and the interface with other films is reduced. This is preferable because optical and electrical losses can be suppressed. Of course, other crystalline semiconductors such as amorphous, polycrystalline, and single crystals can be used.

Note that the semiconductor film 204 having the first conductivity type may have a texture structure as in the case of the substrate 200.

The semiconductor film 204 having the first conductivity type can be formed by a plasma CVD method using a deposition gas containing silicon and diborane. The semiconductor film 204 having the first conductivity type is formed to have a thickness of 1 nm to 100 nm, preferably 5 nm to 50 nm.

Further, after a silicon film to which an impurity element imparting conductivity is not added is formed by a plasma CVD method or the like, boron is added by a method such as ion implantation to form the semiconductor film 204 having the first conductivity type. May be.

Next, as illustrated in FIG. 9C, a semiconductor film 206 that performs photoelectric conversion is formed over the semiconductor film 204 having the first conductivity type. As the semiconductor film 206 that performs photoelectric conversion, a semiconductor film using a semiconductor material similar to that of the semiconductor film 204 is used. That is, silicon, silicon carbide, germanium, gallium arsenide, indium phosphide, zinc selenide, gallium nitride, silicon germanium, or the like is used as a semiconductor material. Among these, it is preferable to use silicon. In addition, a semiconductor material containing an organic material, a metal oxide semiconductor material, or the like can be used.

As the semiconductor film 206 that performs photoelectric conversion, it is more preferable to use a microcrystalline semiconductor film that has a flat surface and improved crystallinity by reducing gaps between mixed-phase grains as shown in Embodiment Mode 1. It is. A conventional microcrystalline semiconductor film is adopted as the semiconductor film by adopting a microcrystalline semiconductor film having a flat surface and improved crystallinity by reducing gaps between mixed phase grains as shown in the first embodiment. The series resistance can be reduced as compared with the case where optical and electrical losses are made at the interface with other films.

Note that the semiconductor film 206 that performs photoelectric conversion is required to have sufficient light absorption; therefore, the thickness is preferably about 100 nm to 10 μm.

Next, as illustrated in FIG. 9D, a semiconductor film 208 having a second conductivity type is formed over the semiconductor film 206 that performs photoelectric conversion. In the present embodiment, the second conductivity type is n-type. The semiconductor film 208 having the second conductivity type can be formed using a material such as silicon to which phosphorus is added as an impurity element imparting a conductivity type. A semiconductor material that can be used for the semiconductor film 208 having the second conductivity type is similar to that of the semiconductor film 204 having the first conductivity type.

The semiconductor film 208 having the second conductivity type can be formed in a manner similar to that of the semiconductor film 204 having the first conductivity type. For example, it can be formed by a plasma CVD method using a deposition gas containing silicon and phosphine. For the semiconductor film 208 having the second conductivity type, it is preferable to employ the microcrystalline semiconductor film which has a flat surface and has improved crystallinity by reducing gaps between mixed phase grains as described in Embodiment 1. It is.

Note that in this embodiment mode, light is incident from the back surface side (downward in the drawing) of the substrate 200; therefore, the conductivity type of the semiconductor film 208 showing the second conductivity type is n-type, but is disclosed. One embodiment of the invention is not limited to this. When the semiconductor film 204 having the first conductivity type is n-type, the semiconductor film 208 having the second conductivity type is p-type.

Next, as illustrated in FIG. 9E, the second electrode 210 is formed over the semiconductor film 208 having the second conductivity type. The second electrode 210 is formed using a conductive material such as metal. For example, it can be formed using a material that easily reflects light, such as aluminum, silver, titanium, or tantalum. In this case, light that could not be absorbed by the semiconductor film 206 can be incident again on the semiconductor film 206, which is preferable because photoelectric conversion efficiency can be improved.

Examples of a method for forming the second electrode 210 include a sputtering method, a vacuum evaporation method, a CVD method, a coating method, and a printing method. The second electrode 210 is formed to a thickness of 10 nm to 500 nm, preferably 50 nm to 100 nm.

Note that in this embodiment mode, the second electrode 210 is formed using a material that does not have a light-transmitting property because light is incident from the back surface side (lower side in the drawing) of the substrate 200. The configuration of the second electrode 210 is not limited to this. For example, in the case where light is incident from the second electrode 210 side (the upper side in the drawing), the second electrode 210 is formed using a light-transmitting conductive material shown in the first electrode 202. Can be formed.

Note that an auxiliary electrode formed of a low-resistance conductive material may be formed so as to be in contact with the second electrode 210.

A microcrystalline semiconductor film whose surface is flat and crystallinity is improved by reducing gaps between mixed phase grains by the above-described method is converted into a semiconductor film that performs photoelectric conversion, a semiconductor film that exhibits a first conductivity type, and a second film A photoelectric conversion device used for any of the semiconductor films exhibiting the above conductivity type can be manufactured. And thereby, the conversion efficiency of a photoelectric conversion apparatus can be improved. Note that a microcrystalline semiconductor film having a flat surface and improved crystallinity by reducing gaps between mixed phase grains includes a semiconductor film that performs photoelectric conversion, a semiconductor film that exhibits a first conductivity type, and a second conductivity type. As long as it is used in any of the semiconductor films showing the above, it can be changed as appropriate. Further, it is more effective when a microcrystalline semiconductor film whose surface is flat and crystallinity is improved by reducing gaps between mixed phase grains is used for a plurality of the semiconductor films.

Note that although a photoelectric conversion device having one unit cell is described in this embodiment, a photoelectric conversion device in which two or more unit cells are appropriately stacked can be used.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 7)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). ), Large game machines such as portable game machines, portable information terminals, sound reproducing devices, and pachinko machines, and electronic paper. Electronic paper can be used for electronic devices in various fields as long as they display information. For example, it can be applied to electronic books (electronic books), posters, digital signage, PID (Public Information Display), advertisements in vehicles such as trains, displays on various cards such as credit cards, etc. using electronic paper. . An example of the electronic device is illustrated in FIG.

FIG. 10 illustrates an example of an electronic book. For example, the electronic book 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated with a shaft portion 2711 and can be opened / closed using the shaft portion 2711 as an axis. With such a configuration, an operation like a paper book can be performed.

A display portion 2705 and a photoelectric conversion device 2706 are incorporated in the housing 2701, and a display portion 2707 and a photoelectric conversion device 2708 are incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration that displays different screens, for example, a sentence can be displayed on the right display unit (display unit 2705 in FIG. 10) and an image can be displayed on the left display unit (display unit 2707 in FIG. 10). .

FIG. 10 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2701 is provided with a power supply 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned with the operation keys 2723. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, and the like may be provided on the back and side surfaces of the housing. . Further, the e-book reader 2700 may have a structure having a function as an electronic dictionary.

Further, the e-book reader 2700 may have a configuration capable of transmitting and receiving information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

In this example, after forming the seed crystal using the first condition described in Embodiment Mode 1, the first microcrystalline semiconductor film is formed using the second condition, and the third condition is set. The second microcrystalline semiconductor film is used to form the second microcrystalline semiconductor film, and the third microcrystalline semiconductor film is formed using the fourth condition, so that the surface is flat. Next, it will be described that a microcrystalline semiconductor film with improved crystallinity can be formed by reducing the gap between mixed phase grains.

First, a method for manufacturing a microcrystalline semiconductor film using the method described in Embodiment 1 is described.

A silicon nitride film having a thickness of 300 nm was formed as an insulating film on a glass substrate (Corning EAGLE XG), and the silicon nitride film was exposed to plasma generated by a mixed gas of hydrogen and oxygen. Next, a seed crystal having a thickness of 5 nm is formed thereon by a plasma CVD method, and then a first microcrystalline semiconductor film having a thickness of 15 nm is formed on the silicon nitride film and the seed crystal by a plasma CVD method. A second microcrystalline semiconductor film having a thickness of 30 nm is formed over the first microcrystalline semiconductor film by a plasma CVD method, and a third microcrystalline semiconductor having a thickness of 20 nm is formed over the second microcrystalline semiconductor film. A film was formed by a plasma CVD method.

The deposition of the silicon nitride film is stabilized by introducing a source gas at a flow rate of silane of 15 sccm, a flow rate of hydrogen of 200 sccm, a flow rate of nitrogen of 180 sccm, and a flow rate of ammonia of 500 sccm, a pressure in the processing chamber of 100 Pa, and an RF power frequency. Was 13.56 MHz and the power of the RF power source was 200 W, and plasma discharge was performed. The silicon nitride film is deposited using a parallel plate type plasma CVD apparatus, the upper electrode temperature is 200 ° C., the lower electrode temperature is 300 ° C., and the distance (gap) between the upper electrode and the lower electrode is 26 mm. did.

In the plasma treatment of the silicon nitride film, hydrogen and oxygen were introduced into the treatment chamber at flow rates of 800 sccm and 200 sccm, the pressure in the treatment chamber was stabilized at 1250 Pa, and the plasma discharge was performed for 3 minutes at an electric power of 900 W. The plasma treatment was performed using a parallel plate type plasma treatment apparatus. The upper electrode temperature was 200 ° C., the lower electrode temperature was 300 ° C., and the distance between the upper electrode and the lower electrode was 15 mm.

The seed crystal is deposited with a silane flow rate of 3 sccm, a hydrogen flow rate of 750 sccm, and an argon flow rate of 750 sccm to stabilize the material gas introduced, the processing chamber pressure is 1250 Pa, the RF power frequency is 13.56 MHz, and the RF power source. The plasma discharge was performed at a power of 100 W. The seed crystal was deposited using a parallel plate type plasma CVD apparatus, the temperature of the lower electrode was 300 ° C., and the distance between the upper electrode and the lower electrode was 7 mm. This condition is the first condition.

The deposition of the first microcrystalline semiconductor film is stabilized by introducing a source gas with a silane flow rate of 1 sccm and a hydrogen flow rate of 3000 sccm, a pressure in the processing chamber of 10,000 Pa, an RF power source frequency of 13.56 MHz, and an RF power source Plasma discharge was performed at an electric power of 300 W. Note that the first microcrystalline semiconductor film was deposited using a parallel plate type plasma CVD apparatus, the temperature of the lower electrode was set to 300 ° C., and the distance between the upper electrode and the lower electrode was set to 7 mm. This condition is the second condition.

The deposition of the second microcrystalline semiconductor film is the same as the deposition conditions of the first microcrystalline semiconductor film except for the flow rate of silane and the power of the RF power source. A condition was used in which a first cycle in which silane with a flow rate of 1 sccm was flown for 10 seconds and a second cycle in which silane with a flow rate of 0.1 sccm was flowed for 60 seconds were repeated. The power of the RF power source was set to 700W. This condition is the third condition.

The deposition of the third microcrystalline semiconductor film is the same as the deposition condition of the first microcrystalline semiconductor film except for the flow rate of silane and the power of the RF power source. The flow rate of silane was 2 sccm, and the power of the RF power source was 700 W. This condition is the fourth condition.

The microcrystalline semiconductor film formed under the above conditions is referred to as Sample 1.

Further, as Comparative Example 1, Sample 2 was formed using the first condition and the second condition of Sample 1. Specifically, a silicon nitride film having a thickness of 300 nm was formed as an insulating film on a glass substrate (Corning EAGLE XG), and the silicon nitride film was exposed to plasma generated by a mixed gas of hydrogen and oxygen. Next, a seed crystal having a thickness of 5 nm is formed thereon by the plasma CVD method using the first condition, and then a thickness of 65 nm is formed on the silicon nitride film and the seed crystal using the second condition. The first microcrystalline semiconductor film was formed by a plasma CVD method.

Further, as Comparative Example 2, Sample 3 was formed using the first condition, the second condition, and the third condition of Sample 1. Specifically, a silicon nitride film having a thickness of 300 nm was formed as an insulating film on a glass substrate (Corning EAGLE XG), and the silicon nitride film was exposed to plasma generated by a mixed gas of hydrogen and oxygen. Next, a seed crystal having a thickness of 5 nm is formed thereon by the plasma CVD method using the first condition, and then a thickness of 15 nm is formed on the silicon nitride film and the seed crystal using the second condition. The first microcrystalline semiconductor film was formed by a plasma CVD method, and a second microcrystalline semiconductor film having a thickness of 50 nm was formed on the first microcrystalline semiconductor film by a plasma CVD method.

Next, Raman spectroscopic analysis was performed on the crystallinity of the microcrystalline semiconductor film. Table 1 shows the three-point crystal / amorphous peak intensity ratio (Ic / Ia) of each microcrystalline semiconductor film and the average value of the full width at half maximum (FWHM) of the peak at 520 cm ⁻¹ in the Raman spectrum.

From Table 1, by using the third condition, as shown in Sample 1 and Sample 3, Ic / Ia of the microcrystalline semiconductor film increases and the value of FWHM decreases. In addition, compared to sample 3, Ic / Ia of sample 1 is slightly decreased, and the value of FWHM is slightly decreased. From these, it can be seen that the crystallinity of the microcrystalline semiconductor film is increased by using the third condition, but the crystallinity of the microcrystalline semiconductor film is slightly decreased by using the fourth condition.

Next, planarity of the microcrystalline semiconductor films shown in Samples 1 to 3 is described with reference to FIGS.

Next, the average surface roughness and the maximum height difference of Samples 1 to 3 were measured by AFM (Atomic Force Microscopy). FIG. 11 is a graph showing the AFM measurement results. The left y-axis and bar graph show the average surface roughness at 5 μm ² , and the right y-axis and square mark show the maximum height difference at 5 μm ² . From FIG. 11, the average surface roughness and the maximum height difference are smaller in the sample 1 than in the sample 3.

From Table 1 and FIG. 11, it is found that the microcrystalline semiconductor film formed using the first to fourth conditions has flatness and high crystallinity.

Next, a dual-gate thin film transistor (TFT1) having a microcrystalline semiconductor film formed using conditions similar to those of Sample 1 and a dual-gate thin film transistor having a microcrystalline semiconductor film formed using conditions similar to Sample 3 The electrical characteristics of (TFT2) will be described with reference to FIGS. 3, 5, 12, and 13. FIG.

First, a method for manufacturing the thin film transistor of this example is described with reference to FIGS. In this embodiment, a dual-gate thin film transistor is manufactured.

First, a base insulating film (not shown here) was formed over the substrate 101, and a gate electrode 103 was formed over the base insulating film.

Here, a glass substrate (Corning EAGLE XG) was used as the substrate 101.

The gate electrode 103 has a structure in which an aluminum layer is sandwiched between titanium layers. Specifically, first, a titanium target was sputtered with argon ions to form a first titanium film having a thickness of 50 nm on the base insulating film. At this time, the flow rate of argon introduced was 20 sccm, the pressure in the processing chamber was 0.1 Pa, the applied voltage was 12 kW, and the temperature was room temperature. And the aluminum target was sputtered | spattered with argon ion on it, and the 100-nm-thick aluminum film was formed. At this time, the flow rate of argon introduced was 50 sccm, the pressure in the processing chamber was 0.4 Pa, the applied voltage was 4 kW, and the temperature was room temperature. Then, a titanium target was sputtered with argon ions thereon to form a second titanium film having a thickness of 50 nm. The second titanium film was formed by the same method as the first titanium film. That is, the flow rate of argon to be introduced was 20 sccm, the pressure in the processing chamber was 0.1 Pa, the applied voltage was 12 kW, and the temperature was room temperature.

Next, a resist was applied onto the second titanium film, exposed using the first photomask, and then developed to form a mask formed of resist.

Next, etching was performed using a mask formed of the resist, so that the gate electrode 103 was formed. Here, two-stage etching was performed using an ICP (Inductively Coupled Plasma) apparatus. That is, after ICP power 600 W, bias power 250 W, boron trichloride as an etching gas is introduced at a flow rate of 60 sccm, chlorine is introduced at a flow rate of 20 sccm, the pressure in the processing chamber is 1.2 Pa, and the first etching is performed. Then, ICP power 500 W, bias power 50 W, pressure 2.0 Pa, carbon tetrafluoride was introduced as an etching gas at a flow rate of 80 sccm, the pressure in the processing chamber was 2.0 Pa, and the second etching was performed. Thereafter, the mask formed of the resist was removed.

Next, after the gate insulating film 105 was formed over the gate electrode 103 and the base insulating film, the gate insulating film 105 was subjected to plasma treatment.

In this embodiment, a silicon nitride film having a thickness of 300 nm is deposited as the gate insulating film 105 by a plasma CVD method, and then plasma treatment is performed. The deposition of the silicon nitride film is stabilized by introducing a source gas at a flow rate of silane of 15 sccm, a flow rate of hydrogen of 200 sccm, a flow rate of nitrogen of 180 sccm, and a flow rate of ammonia of 500 sccm, a pressure in the processing chamber of 100 Pa, and an RF power frequency. Was 13.56 MHz and the power of the RF power source was 200 W, and plasma discharge was performed. The gate insulating film 105 was deposited using a parallel plate type plasma processing apparatus. The upper electrode temperature was 200 ° C., the lower electrode temperature was 300 ° C., and the distance between the upper electrode and the lower electrode was 30 mm.

In the plasma treatment of the formed silicon nitride film, a hydrogen flow rate of 800 sccm and an oxygen flow rate of 200 sccm are introduced into the treatment chamber, the pressure in the treatment chamber is stabilized at 1250 Pa, power is 900 W, and plasma discharge is performed for 3 minutes. It was. The plasma treatment was performed using a parallel plate type plasma treatment apparatus. The upper electrode temperature was 200 ° C., the lower electrode temperature was 300 ° C., and the distance between the upper electrode and the lower electrode was 15 mm.

Next, in TFT 1, a seed crystal 107 having a thickness of 5 nm is formed on the gate insulating film 105 using the plasma CVD method on the first condition, and then the first crystal having a thickness of 15 nm is formed using the second condition. The microcrystalline semiconductor film 108 is formed using a plasma CVD method, the second microcrystalline semiconductor film 109 having a thickness of 30 nm is formed using a plasma CVD method, and the fourth condition is applied. A third microcrystalline semiconductor film 110 having a thickness of 20 nm was formed using a plasma CVD method.

In the TFT 2, a seed crystal 107 having a thickness of 5 nm is formed on the gate insulating film 105 by the plasma CVD method on the first condition, and then the first condition having a thickness of 15 nm is formed by using the second condition. A microcrystalline semiconductor film 108 was formed by a plasma CVD method, and a second microcrystalline semiconductor film 109 having a thickness of 50 nm was formed by a plasma CVD method using a third condition.

The structure obtained through the steps up to here is illustrated in FIG.

Next, a semiconductor film 111 with a thickness of 80 nm was formed over the third microcrystalline semiconductor film 110 or the second microcrystalline semiconductor film 109, and an impurity semiconductor film 113 with a thickness of 50 nm was formed over the semiconductor film 111. The semiconductor film 111 and the impurity semiconductor film 113 were formed using a plasma CVD method.

The deposition of the semiconductor film 111 is stabilized by introducing a material gas at a flow rate of silane of 25 sccm, a flow rate of 1000 ppm ammonia (hydrogen dilution) of 100 sccm, a flow rate of hydrogen of 650 sccm, and a flow rate of argon of 750 sccm. Plasma discharge was performed with 1250 Pa, RF power frequency of 13.56 MHz and RF power of 150 W. The semiconductor film 111 was deposited using a parallel plate type plasma processing apparatus. The upper electrode temperature was 200 ° C., the lower electrode temperature was 300 ° C., and the distance between the upper electrode and the lower electrode was 15 mm.

As the impurity semiconductor film 113, an amorphous silicon film to which phosphorus was added was formed. The deposition of the impurity semiconductor film 113 is stabilized by introducing a material gas with a silane flow rate of 82 sccm, a 5% phosphine (silane dilution) flow rate of 18 sccm, and a hydrogen flow rate of 1400 sccm, a processing chamber pressure of 1050 Pa, and an RF power source. Plasma discharge was performed with a frequency of 13.56 MHz and an RF power supply of 60 W (pulse discharge with a duty ratio of 30% at 10 kHz). The impurity semiconductor film was deposited using a parallel plate type plasma processing apparatus. The upper electrode temperature was 200 ° C., the lower electrode temperature was 300 ° C., and the distance between the upper electrode and the lower electrode was 15 mm.

Next, after applying a resist over the impurity semiconductor film 113, exposure was performed using a second photomask, and development was performed to form a mask 115 formed of a resist. The structure obtained through the steps up to here is illustrated in FIG.

Next, etching was performed using the mask 115 formed of a resist, so that the semiconductor stacked body 117 including the microcrystalline semiconductor region 117 a and the amorphous semiconductor region 117 b and the impurity semiconductor film 121 were formed.

In this embodiment, in this embodiment, an ICP apparatus is used to introduce an ICP power of 450 W, a bias power of 100 W, boron trichloride as an etching gas at a flow rate of 36 sccm, carbon tetrafluoride at 36 sccm, and oxygen at 8 sccm. Etching was performed at a pressure of 2 Pa.

After that, oxygen plasma treatment is performed to form an oxide film on the sidewalls of the semiconductor stacked body 117 and the impurity semiconductor film 121 including the microcrystalline semiconductor region 117a and the amorphous semiconductor region 117b, and then the resist mask 115 is removed. (Not shown).

In the oxygen plasma treatment, the flow rate of oxygen was 100 sccm, the pressure in the treatment chamber was stabilized at 0.67 Pa, the substrate temperature was −10 ° C., the plasma discharge was performed at an ICP power of 2000 W, and a bias power of 350 W.

The structure obtained through the steps up to here is illustrated in FIG.

Next, a conductive film 127 was formed so as to cover the gate insulating film 105, the semiconductor stacked body 117, and the impurity semiconductor film 121. The structure obtained in this step is shown in FIG.

In this example, the conductive film 127 was formed using a titanium film with a thickness of 300 nm under the same conditions as the titanium film formed using the gate electrode 103.

Next, after applying a resist over the conductive film 127, exposure was performed using a third photomask, and development was performed to form a mask formed of a resist. The conductive film 127, the impurity semiconductor film 121, and part of the semiconductor stacked body 117 are dry-etched using the mask formed of the resist, so that the wiring 129a and the wiring 129b and the pair of impurity semiconductor films 131a and 131b are formed. .

In this process, using an ICP apparatus, etching is performed with an ICP power of 450 W, a bias power of 100 W, boron trichloride as an etching gas at a flow rate of 60 sccm, chlorine at 20 sccm, and a pressure in the processing chamber of 1.9 Pa. It was.

Next, after removing the mask formed of the resist, the partially etched semiconductor stacked body 117 is further etched to form a semiconductor stacked body 133 having a microcrystalline semiconductor region 133a and a pair of amorphous semiconductor regions 133b. did.

In this process, ICP power is 500 W, bias power is 50 W, hydrogen bromide is flowed at 125 sccm, sulfur fluoride is flowed at 10 sccm, and oxygen is flowed at 5 sccm, and the pressure in the processing chamber is 1.7 Pa. It was.

Note that 100 nm was etched from the surface of the semiconductor stacked body 117. In this embodiment, the planar shape of the wirings 129a and 129b functioning as the source electrode and the drain electrode is a linear type.

Next, the surface of the semiconductor stacked body 133 was subjected to water plasma treatment to remove impurities remaining on the surface of the semiconductor stacked body 133. In this step, water plasma treatment was performed at a power of 1800 W with water vapor introduced at a flow rate of 300 sccm and a pressure in the treatment chamber of 66.5 Pa.

The structure obtained through the steps up to here is illustrated in FIG.

Next, as the insulating film 137, a silicon nitride film with a thickness of 300 nm was formed. The insulating film 137 is deposited by introducing a material gas with a silane flow rate of 20 sccm, an ammonia flow rate of 220 sccm, a nitrogen flow rate of 450 sccm, and a hydrogen flow rate of 450 sccm, a pressure in the processing chamber of 160 Pa, an RF power supply frequency of 27 MHz, Plasma discharge was performed with the power of the RF power source set at 200 W. The insulating film 137 was deposited using a parallel plate type plasma processing apparatus. The upper electrode temperature was 250 ° C., the lower electrode temperature was 290 ° C., and the distance between the upper electrode and the lower electrode was 21 mm.

Next, after a resist was applied over the insulating film 137, exposure was performed using a fourth photomask, and development was performed to form a resist mask. A part of the insulating film was dry etched using a mask formed of the resist to expose the wirings 129a and 129b functioning as a source electrode and a drain electrode. Further, the insulating film 137 and part of the gate insulating film 105 were dry etched to expose the gate electrode 103. Thereafter, the resist mask was removed.

Next, after a conductive film was formed over the insulating film 137, a resist was applied over the conductive film, exposed using a fifth photomask, and developed to form a resist-formed mask. A part of the conductive film is wet-etched using the mask formed using the resist, so that a conductive film connected to the wiring 129a, a conductive film connected to the wiring 129b, and a back gate electrode 139 connected to the gate electrode 103 are formed. did. Note that the conductive film functions as a pad when measuring electrical characteristics of the thin film transistor.

Here, as a conductive film, indium tin oxide having a thickness of 50 nm was formed by a sputtering method, and then a back gate electrode 139 was formed by wet etching. Although not shown here, the back gate electrode 139 is connected to the gate electrode 103. Thereafter, the resist mask was removed.

Through the above process, a dual-gate thin film transistor was manufactured (see FIG. 5C).

FIG. 12 shows the results of measuring the electrical characteristics of TFT1 and TFT2 manufactured in this example.

12A shows electrical characteristics of a dual-gate thin film transistor (TFT1) having a microcrystalline semiconductor film formed using conditions similar to those of Sample 1. FIG. 12B shows the same characteristics as Sample 3 This is an electrical characteristic of a dual-gate thin film transistor (TFT2) having a microcrystalline semiconductor film formed using conditions.

In the thin film transistors (TFT1 and TFT2), the same voltage was applied to the gate electrode 103 and the back gate electrode 139. Note that the opposing interval (channel length) of the wirings 129a and 129b of the thin film transistor of this embodiment is 3.2 μm, the opposing width (channel width) of the wirings 129a and 129b is 19.9 μm, and the width of the semiconductor stacked body 133 in the channel width direction. Was 22.2 μm. Further, the field effect mobility was calculated when the thickness of the gate insulating film 105 was 300 nm, the average dielectric constant was 6.85, and the drain voltage was 10V.

Further, when the drain voltage is 10 V and the voltage of the gate electrode 103 is 15 V, the on-state current (shown as Ion), the minimum off-state current (shown as Ioff (min.)), And the minimum off-state gate voltage of −10 V Off-current (denoted as Ioff), ratio of on-current to minimum off-current (denoted as Ion / Ioff (min.)), Threshold voltage (denoted as Vth), S value (denoted as S-value and Table 2 shows the field effect mobility (denoted as μFE_sat.) When the drain voltage is 10V.

In addition, two substrates in which 16 TFTs 1 are formed on one substrate and two substrates in which 16 TFTs 2 are formed on one substrate, when the drain voltage of each thin film transistor is 10V The field effect mobility (μFE_sat.) Is shown in FIG. FIG. 13B shows the minimum off-state current (Ioff (min.)) Of a thin film transistor over the same substrate and the off-state current (Ioff) when the gate voltage is −10 V with the minimum off-state current. In FIG. 13B, Ioff is indicated by a triangular mark, and Ioff (min.) Is indicated by a circular mark. In addition, the average values of μFE, Ioff, and Ioff_min of each substrate are shown in the graph.

From FIG. 13A, a thin film transistor (TFT1) having a microcrystalline semiconductor film formed using the first to fourth conditions is a microcrystalline semiconductor formed using the first to third conditions. It can be seen that the field effect mobility is higher than that of the thin film transistor (TFT2) having a film.

From FIG. 13B, a thin film transistor (TFT1) having a microcrystalline semiconductor film formed using the first condition to the fourth condition is thin film formed using the first condition to the third condition. It can be seen that the minimum off-state current and off-state current are lower than those of the thin film transistor (TFT2) having a crystalline semiconductor film.

Claims (8)

On the insulating film, the first condition is that the flow rate of hydrogen relative to the flow rate of the deposition gas containing silicon is 50 times or more and 1000 times or less to dilute the deposition gas, and the pressure in the processing chamber is 67 Pa or more and 50000 Pa or less. A seed crystal is formed by the plasma CVD method used,
A second gas flow is formed on the seed crystal by diluting the deposition gas by setting the flow rate of hydrogen to 100 to 2000 times the flow rate of the deposition gas containing silicon, and setting the pressure in the processing chamber to 1333 Pa to 50000 Pa. A first microcrystalline semiconductor film is formed by a plasma CVD method using conditions;
The pressure in the treatment chamber is set to 1333 Pa to 50000 Pa, and is longer than the first period for depositing the microcrystalline semiconductor and the first period for selectively etching the amorphous semiconductor region included in the microcrystalline semiconductor. A second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film by a plasma CVD method using a third condition that alternately performs the second period,
On the second microcrystalline semiconductor film, the deposition gas is diluted by increasing the hydrogen flow rate to 100 to 2000 times the flow rate of the deposition gas containing silicon, and the pressure in the processing chamber is set to 1333 Pa to 50000 Pa. A method for manufacturing a microcrystalline semiconductor film, wherein the third microcrystalline semiconductor film is formed by a plasma CVD method using the fourth condition. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate and the gate electrode;
Forming a seed crystal on the gate insulating film under a first condition;
Forming a first microcrystalline semiconductor film on the seed crystal under a second condition;
Forming a second microcrystalline semiconductor film on the first microcrystalline semiconductor film under a third condition;
Forming a third microcrystalline semiconductor film on the second microcrystalline semiconductor film under a fourth condition;
Forming a semiconductor film having a microcrystalline semiconductor region and an amorphous semiconductor region over the third microcrystalline semiconductor film;
Forming a first impurity semiconductor film on the semiconductor film;
A part of the first impurity semiconductor film is etched to form an island-like second impurity semiconductor film, and the seed crystal, the first microcrystalline semiconductor film, and the second microcrystalline semiconductor film Etching the third microcrystalline semiconductor film and a part of the semiconductor film to form an island-shaped first semiconductor stacked body;
A wiring functioning as a source electrode and a drain electrode is formed on the second impurity semiconductor film,
Etching the second impurity semiconductor film to form a pair of impurity semiconductor films functioning as a source region and a drain region;
The first condition is a condition in which the flow rate of hydrogen with respect to the flow rate of the deposition gas containing silicon is 50 times or more and 1000 times or less to dilute the deposition gas, and the pressure in the processing chamber is set to 67 Pa or more and 50000 Pa or less. ,
The second condition is a condition in which the flow rate of hydrogen with respect to the flow rate of the deposition gas containing silicon is 100 times or more and 2000 times or less to dilute the deposition gas, and the pressure in the processing chamber is 1333 Pa or more and 50000 Pa or less. Yes,
The third condition is that the pressure in the treatment chamber is set to 1333 Pa or more and 50000 Pa or less, and the first period for depositing the microcrystalline semiconductor and the amorphous semiconductor region included in the microcrystalline semiconductor are selectively etched. A condition for alternately performing a second period longer than the first period;
The fourth condition is a condition in which the flow rate of hydrogen with respect to the flow rate of the deposition gas containing silicon is 100 times or more and 2000 times or less to dilute the deposition gas, and the pressure in the processing chamber is 1333 Pa to 50000 Pa. There is provided a method for manufacturing a semiconductor device. In Claim 2, before forming the 1st semiconductor layered product and forming the wiring which functions as a source electrode and a drain electrode on the 1st semiconductor layered product,
A method for manufacturing a semiconductor device, comprising exposing a side surface of the first semiconductor stacked body to plasma to form an insulating region on the side surface of the first semiconductor stacked body. In Claim 2 or Claim 3, a part of the first semiconductor stacked body is etched to form a second semiconductor stacked body in which a microcrystalline semiconductor region and a pair of amorphous semiconductor regions are stacked,
Forming an insulating film on the wiring, the pair of impurity semiconductor films, the second semiconductor stacked body, and the gate insulating film;
A method for manufacturing a semiconductor device, comprising forming a back gate electrode and a pixel electrode over the insulating film.   5. The method for manufacturing a semiconductor device according to claim 4, wherein the gate electrode and the back gate electrode are parallel to each other.   5. The method for manufacturing a semiconductor device according to claim 4, wherein the gate electrode and the back gate electrode are connected to each other.   5. The method for manufacturing a semiconductor device according to claim 4, wherein the back gate electrode is floating.   8. The method for manufacturing a semiconductor device according to claim 4, wherein the back gate electrode and the pixel electrode are formed at the same time.

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