JP2012204524A - Solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS solid state image pickup device having high sensitivity and high image quality with a global electronic shutter function.SOLUTION: A solid state image pickup device comprises a semiconductor substrate 101, photodiodes 105, connection diodes 175, storage diodes 106 and overflow drains 109. The photodiodes 105 are formed two-dimensionally on a semiconductor substrate 101 on an upper principal surface side in a Z-axis direction along the principal surface with leaving a space between one photodiode and another. The storage diodes 106 are provided on the semiconductor substrate on a lower principal surface side in the Z-axis direction. The overflow drains 109 are provided on the semiconductor substrate on the lower principal surface side in the Z-axis direction. The connection diode 175 connected with the photodiode 105 is connected with the storage diode 106 and the overflow drain 109 via gates, respectively.

Description

  The present invention relates to a solid-state imaging device, and more particularly to a MOS type solid-state imaging device having a global electronic shutter function.

  In CCD image sensors and MOS type image sensors that are solid-state imaging devices, pixel size miniaturization (miniaturization of cells) associated with the increase in the number of pixels is required. At the same time, a solid-state imaging device is required to have an electrical high-speed shutter function (global electronic shutter function) capable of capturing images with high image quality even in shooting with movement such as a motion scene. In particular, a MOS type image sensor that employs a sequential readout method is also required to have a global electronic shutter function that electrically reads out signal charges of light receiving portions of all pixels in a batch.

  In response to the above request, various techniques have been proposed (for example, Non-Patent Document 1). As an example of the prior art, the configuration and operating potential of a solid-state imaging device (MOS type image sensor) proposed in Non-Patent Document 1 will be described with reference to FIG.

  As shown in the schematic plan view of FIG. 18A, in each pixel of the solid-state imaging device proposed in Non-Patent Document 1, a storage diode 904 is provided for the photodiode 903 via a transfer gate 906. ing. A floating diffusion 905 is provided for the storage diode 904 via a transfer gate 907.

  Further, an overflow drain 911 is provided for the photodiode 903 via a transfer gate 913 in the vertical direction toward the paper surface of FIG. Here, the photodiode 903 functions as a photoelectric conversion unit that converts incident light into charges, and the overflow drain 911 is a region for simultaneously resetting and discharging charges generated by the photodiode 903. The storage diode 904 is an area for temporarily accumulating signal charges that are simultaneously read from the photodiode 903 after being simultaneously discharged.

  Next, as shown in FIG. 18B, which is a cross section taken along line XX ′ in FIG. 18A, in the solid-state imaging device proposed in Non-Patent Document 1, the overflow drain 911, the photodiode 903, and the storage diode 904 and the floating diffusion 905 are all embedded in the semiconductor substrate 901 in which the p-type well region 902 is formed. A reset gate 908 is provided for the floating diffusion 905, and the reset gate 908 includes a drain. A voltage 909 is provided. The floating diffusion 905 is provided with an amplifier 909 that amplifies the potential change and reads it out.

The overflow drain 911 is provided with a drain voltage 912.
Next, a method for driving the solid-state imaging device proposed in Non-Patent Document 1 will be described with reference to FIG. FIG. 18C is a potential diagram of the XX ′ section in FIG. First, charges accumulated in the photodiode 903 due to incident light are swept out to the overflow drain 911 by turning on the transfer gates 913 all at once. Thereby, the photodiodes 903 of all the pixels are reset all at once ((i) PD-resetting in FIG. 18C).

  Next, the signal charges accumulated by the incident light for a predetermined time (shutter time) in the reset photodiode 903 are transferred to the storage diode 906 by turning on the transfer gates 906 all at once. Is done. Thus, signal charges are simultaneously read from the photodiodes 903 of all the pixels ((ii) First-transfer in FIG. 18C).

  Next, the signal charge transferred to the storage diode 904 is transferred to the floating diffusion 905 by turning on the transfer gate 907 according to the cycle of the normal reading method (sequential reading method) of the MOS image sensor ( (Iii) Second-transfer in FIG. Then, the potential change corresponding to the signal charge of the floating diffusion 905 is read out through the amplifier 910 connected to the floating diffusion 905.

  As described above, in the solid-state imaging device proposed in Non-Patent Document 1, the charge of the photodiode 903 is collectively reset to the overflow drain 911 in all the pixels, and then the photodiode 903 performs a predetermined time (shutter time). ) Are simultaneously read out and transferred to the storage diode 904, where they are temporarily stored. Then, the potential change is sequentially read out through the amplifier 910 in accordance with the signal charge transferred from the storage diode 904 to the floating diffusion 905. In this way, a global electronic shutter is realized.

“Two-Stage Charge Transfer Pixel Using Pinned Diodes for Low-Noise Global Shutter Imaging”, K. K. et al. Yasutomi et al. , 2009 Intl. Image Sensor Workshop, session11.

  However, in the solid-state imaging device proposed in Non-Patent Document 1, the photodiode 903 and the storage diode 904 are formed in the semiconductor substrate 901 in the unit pixel, and the area occupied by the photodiode 903 and the storage diode 904 are the same. There is a trade-off relationship with the occupied area (see FIGS. 18A and 18B). Since the areas of the photodiode 903 and the storage diode 904 need to be equal to each other, it is difficult to relatively increase the area occupied by the photodiode 903, resulting in a decrease in sensitivity.

  The present invention has been made to solve the above problems, and an object thereof is to provide a MOS type solid-state imaging device having high sensitivity while having a global electronic shutter function.

Therefore, in the present invention, the following configuration is adopted.
[I] A solid-state imaging device according to the present invention includes a semiconductor substrate, a photoelectric conversion unit, a connection diode, a storage diode, and an overflow drain.

(1) Photoelectric conversion unit: formed in a two-dimensional manner on the first main surface side in the semiconductor substrate in a state along the first main surface and with a space between each other.
(2) Connection diode; provided on the second main surface side opposite to the first main surface in the semiconductor substrate, corresponding to each of the plurality of photoelectric conversion units, and corresponding to the photoelectric conversion units It is connected.

(3) Storage diode; provided on the second main surface side in the semiconductor substrate, corresponding to each of the connection diodes and via the corresponding connection diode and the first gate.
(4) Overflow drain; provided on the second main surface side in the semiconductor substrate, corresponding to each of the connection diodes and via the corresponding connection diode and the second gate.

[II] A solid-state imaging device according to the present invention includes a semiconductor substrate, a photoelectric conversion unit, a connection diode, a storage diode, and an overflow drain.
(1) Photoelectric conversion unit: formed in a two-dimensional manner on the first main surface side in the semiconductor substrate in a state along the first main surface and with a space between each other.

    (2) Connection diode; provided on the second main surface side opposite to the first main surface in the semiconductor substrate, corresponding to each of the plurality of photoelectric conversion units, and corresponding to the photoelectric conversion units It is connected.

(3) Storage diode; provided on the second main surface side in the semiconductor substrate, corresponding to each of the connection diodes and via the corresponding connection diode and the first gate.
(4) Overflow drain; provided on the first main surface side in the semiconductor substrate between adjacent photoelectric conversion portions.

    First, in both solid-state imaging devices [I] and [II], the photoelectric conversion film is formed on the first main surface side in the semiconductor substrate and is formed on the second main surface side in the semiconductor substrate. There is no trade-off between the storage diode and the occupied area. For this reason, it is possible to achieve both a sufficient light receiving unit capacitance and a sufficient storage diode capacitance. Therefore, in the solid-state imaging device according to the present invention, in a solid-state imaging device having a global electronic shutter function, a sufficient area of the photoelectric conversion unit can be ensured even by reducing the pixel size, and high sensitivity can be realized. Can do.

  In the solid-state imaging device of the present invention according to [I], in each pixel, an overflow drain is formed via a second gate with respect to the connection diode. Therefore, in the solid-state imaging device of the present invention according to [I], in all pixels, the charge of the photoelectric conversion film is collectively reset to the overflow drain via the lower electrode, the connection plug, and the connection diode, Signal charges generated during a predetermined time (shutter time) by the photoelectric conversion film can be read out all at once and transferred to a storage diode for temporary storage. Thereafter, similarly to the solid-state imaging device proposed in Non-Patent Document 1, signal charges are transferred from the storage diode to the floating diffusion, and potential changes are sequentially read out via the amplifier in accordance with the signal charges. . Thus, the solid-state imaging device according to the present invention also has a global electronic shutter function.

  On the other hand, in the solid-state imaging device of the present invention according to [II], the overflow drain is not formed on the second main surface side in the semiconductor substrate, but adjacent photoelectric conversion on the first main surface side in the semiconductor substrate. It is formed between the parts. For this reason, since the overflow drain is not formed on the second main surface side in the semiconductor substrate, the area occupied by the storage diode can be further increased.

  As described above, both [I] and [II] of the solid-state imaging device according to the present invention have a global electronic shutter function, and can capture images with high image quality even in moving shooting. Therefore, the solid-state imaging device according to the present invention has high sensitivity while having a global electronic shutter function.

In the solid-state imaging device according to the present invention, for example, the following variation configuration can be adopted.
In the solid-state imaging device according to the present invention, the floating diffusion provided on the second main surface side in the semiconductor substrate corresponding to each of the storage diodes and provided via the corresponding storage diode and the third gate. It is possible to adopt a configuration having When such a configuration is adopted, the storage diode and the floating diffusion can be efficiently arranged in each pixel, which is effective for miniaturization of the pixel.

  In the solid-state imaging device according to the present invention, a light-shielding metal film is formed in a portion corresponding to between adjacent photoelectric conversion units above the second main surface of the semiconductor substrate, and is floating. The diffusion may employ a configuration in which at least a part of the semiconductor substrate at the upper part on the first main surface side is covered with a metal film. In the case of adopting such a configuration, it is possible to suppress the generation of a false signal in the floating diffusion caused by the leaked light by shielding the leaked light passing between the adjacent photoelectric conversion units. Therefore, high image quality performance can be obtained.

  In the solid-state imaging device according to the present invention, a light-shielding metal film is formed in a portion corresponding to between adjacent photoelectric conversion units above the second main surface of the semiconductor substrate, The storage diode can employ a configuration in which at least a part of the upper side of the first main surface of the semiconductor substrate is covered with a metal film. When such a configuration is employed, generation of a false signal in the storage diode due to the leaked light can be suppressed by shielding the leaked light passing between the adjacent photoelectric conversion units. Therefore, high image quality performance can be obtained.

  In the solid-state imaging device of the present invention according to [II] above, a light-shielding metal film is formed in a portion corresponding to between adjacent photoelectric conversion units above the second main surface of the semiconductor substrate. The overflow drain is connected to the metal film, and a configuration in which a bias voltage is applied from the bias voltage application unit via the metal film can be employed. When such a configuration is adopted, the charge state of the overflow drain can be reset by applying a bias voltage to the metal film, which is effective for realizing a global electronic shutter.

It is a schematic block diagram which shows the structure of the solid-state imaging device 1 which concerns on Embodiment 1 of this invention. 2 is a schematic plan view showing a part of a pixel array 10 in the solid-state imaging device 1. FIG. 2 is a schematic cross-sectional view showing a part of a pixel array 10 in the solid-state imaging device 1. FIG. (A) is an equivalent circuit diagram of one pixel portion in the solid-state imaging device 1, and (b) is a potential diagram. 3 is a schematic timing chart when the solid-state imaging device 1 is driven. It is a model potential diagram which shows the potential in each node at the time of a drive. 3 is a schematic cross-sectional view showing each step in manufacturing the solid-state imaging device 1. FIG. 3 is a schematic cross-sectional view showing each step in manufacturing the solid-state imaging device 1. FIG. 3 is a schematic cross-sectional view showing each step in manufacturing the solid-state imaging device 1. FIG. It is a schematic plan view which shows a part of pixel array in the solid-state imaging device 2 which concerns on Embodiment 2 of this invention. 3 is a schematic cross-sectional view showing a part of a pixel array in the solid-state imaging device 2. FIG. (A) is an equivalent circuit diagram of one pixel portion in the solid-state imaging device 2, and (b) is a potential diagram. 4 is a schematic timing chart when the solid-state imaging device 2 is driven. 3 is a schematic potential diagram showing potentials at each node when the solid-state imaging device 2 is driven. FIG. 5 is a schematic cross-sectional view showing each step in manufacturing the solid-state imaging device 2. FIG. 5 is a schematic cross-sectional view showing each step in manufacturing the solid-state imaging device 2. FIG. It is a schematic cross section which shows a part of pixel array in the solid-state imaging device 3 which concerns on Embodiment 3 of this invention. It is a schematic diagram which shows the structure of the solid-state imaging device which has a global electronic shutter function based on a prior art.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. Each of the following embodiments is an example used for easily explaining the configuration of the present invention and the operations and effects produced therefrom, and the present invention is not limited to the following essential features. The form is not limited.

[Embodiment 1]
1. Overall Configuration of Solid-State Imaging Device 1 The overall configuration of the solid-state imaging device 1 according to Embodiment 1 will be described with reference to FIG.

  As shown in FIG. 1, in the solid-state imaging device 1 according to the first embodiment, a plurality of pixel units 100 are arranged in a matrix (matrix) in the XY plane direction, thereby forming a pixel array 10. Yes. A pulse generation circuit 21, a horizontal shift register 22, and a vertical shift register 23 are connected to the pixel array 10. The horizontal shift register 22 and the vertical shift register 23 sequentially output drive pulses to each pixel unit 100 in response to the application of the timing pulse from the pulse generation circuit 21.

2. Configuration of Pixel Array 10 Of the configuration of the solid-state imaging device 1, the configuration of the pixel array 10 will be described with reference to FIGS. FIG. 2 is a schematic plan view showing a part of the pixel array 10 extracted. FIG. 3 is a schematic cross-sectional view showing the AA ′ cross section and the AA ″ cross section. FIG. 5 is a schematic diagram combining the AA ′ cross section showing the structure of the readout circuit section on the side and the AA ″ cross section showing the structure of the upper part (light incident side) after the back surface photodiode, and the arrangement relationship of the constituent parts Is different from the actual arrangement.

  As shown in FIG. 2, in the solid-state imaging device 1, a pixel separation unit 300 is provided between regions (pixel units) where the photodiode 105 is formed. Each pixel unit 100 is provided with a connection diode 175, a storage diode 106, a floating diffusion 107, an amplification transistor 116, and a reset drain 108. An overflow drain 109 is provided above the connection diode 175 in the Y-axis direction, and an amplification transistor (Tr) drain 115 is provided on the right side of the amplification transistor 116 in the X-axis direction.

  A transfer gate 110 is provided between the connection diode 175 and the storage diode 106, and a transfer gate 114 is provided between the connection diode 175 and the overflow drain 109. Similarly, a transfer gate 111 is provided between the storage diode 106 and the floating diffusion 107, and a transfer gate 113 is provided between the floating diffusion 107 and the reset drain 108. The amplification Tr gate 112 of the amplification transistor 116 is connected to the floating diffusion 107 through the opening 117 of the gate oxide film.

  Contact plugs 119 and 118 are connected to the overflow drain 109 and the reset drain 108, respectively, and a contact plug 135 is connected to the amplification transistor 116. Contact plugs 136 are connected to the transfer gates 114 and 110, respectively.

Here, the storage diode 106, the floating diffusion 107, and the like are arranged in a region (pixel separation unit 300) between adjacent photodiodes 105.
Next, the configuration of the pixel array 10 of the solid-state imaging device 1 will be described with reference to cross-sectional views.

As shown in FIG. 3, the solid-state imaging device 1 includes a p-type semiconductor substrate 101, and a gate oxide film 104 is stacked on the main surface on the lower side in the Z-axis direction in the figure. An STI (Shallow Trench Isolation) 102 and a p ⁺ type channel stopper 103 are formed on the lower main surface side of the semiconductor substrate 101 in units of 100 pixel units.

  For the gate oxide film 104, interlayer insulating films 120, 121, and 122 are sequentially stacked on the lower side in the Z-axis direction. The interlayer insulating films 120, 121, and 123 are oxide films formed by using, for example, a CVD (Chemical Vapor Deposition) method. Wirings 126 and 127 are formed at the boundary between the interlayer insulating film 120 and the interlayer insulating film 121 and at the boundary between the interlayer insulating film 121 and the interlayer insulating film 122, respectively. Contact plugs 123, 124, and 125 are connected to the wirings 126 and 127, respectively.

  Further, a protective film 129 is stacked on the lower side in the Z-axis direction with respect to the interlayer insulating film 122, and a support substrate 160 is bonded to the lower side of the protective film 129 in the Z-axis direction. A wiring 128 connected to the contact plug 125 is provided at a boundary portion between the protective film 129 and the interlayer insulating film 122.

  The wirings 126, 127, and 128 are formed using, for example, aluminum (Al) or copper (Cu). The contact plugs 123, 124, and 125 are formed by embedding tungsten (W) plugs in contact holes formed in the interlayer insulating films 120, 121, and 122. In order to reduce the contact resistance with the impurity layer (reset drain 108, overflow drain 109), titanium (Ti) and TiN in order to reinforce adhesion with tungsten (W) are inserted in the boundary portion. (Not shown).

  In the surface layer region inward from the main surface on the gate insulating film 104 side in the semiconductor substrate 101, an overflow drain 109, a connection diode 175, a storage diode 106, a floating diffusion 107, and a reset drain 108 are provided for each pixel unit 100. Are provided spaced apart from each other. A contact plug 123 that passes through the gate oxide film 104 is connected to the overflow drain 109 and the reset drain 108.

  Further, on the lower side of the gate oxide film 104 in the Z-axis direction, a gate electrode of the transfer gate 114 is provided in a region between the connection diode 175 and the overflow drain 109, and a region between the connection diode 175 and the storage diode 106. The gate electrode of the transfer gate 110 is provided. Similarly, on the lower side of the gate oxide film 104 in the Z-axis direction, a gate electrode of the transfer gate 111 is provided in a region between the storage diode 106 and the floating diffusion 107, and between the floating diffusion 107 and the reset drain 108. A gate electrode of the transfer gate 113 is provided in the region.

  Further, the floating diffusion 107 is connected to the gate electrode of the amplification Tr gate 112 that is inserted through the gate oxide film 104. In FIG. 3, the gate electrodes of the transfer gates 110, 111, 113, 114 and the amplifying Tr gate 112 are shown in black, and corresponding portions between the impurity diffusion layers are gates. The gate electrodes of the transfer gates 110, 111, 113, 114 and the amplification Tr gate 112 are made of, for example, Poly-Si.

The connection diode 175, the storage diode 106, the floating diffusion 107, the reset drain 108, and the overflow drain 109 are n-type impurity diffusion layers. As shown in FIG. 3, a pinning layer 130 that is a p ⁺ -type impurity layer is formed in a region between the connection diode 175 and the gate oxide film 104. Thereby, the connection diode 175 is a buried diode. Similarly, for the storage diode 106, a pinning layer 131 which is a p ⁺ -type impurity layer is formed in a region between the storage diode 106 and the gate oxide film 104. As a result, the storage diode 106 is also a buried diode.

Although not shown, the reset drain 108 is connected to a drain voltage (V _DD ).
On the other hand, a photodiode 105 is formed for each pixel unit 100 in the surface layer portion on the upper side in the Z-axis direction in the semiconductor substrate 101. The photodiode 105 is composed of an n-type impurity diffusion layer, and is arranged in a matrix along the main surface on the upper side in the Z-axis direction of the semiconductor substrate 101. The photodiodes 105 are connected to the corresponding connection diodes 175, respectively.

  The entire upper surface of the photodiode 105 and the semiconductor substrate 101 in the Z-axis direction is covered with a pinning layer 140, and an antireflection film 141 and a protective film 143 are sequentially stacked thereon. A metal wiring 142 is formed in a boundary portion with the protective film 143 on the antireflection film 141 and in a region corresponding to each pixel separation unit 300. The metal wiring 142 has a mesh shape so as to pass between adjacent pixel portions 100 when the pixel array 10 is viewed in plan.

  On the upper side of the protective film 143 in the Z-axis direction, a planarizing film 150, a color filter layer 151, a planarizing film 152, and a microlens 153 are sequentially stacked. Among these, the color filter layer 151 has a transmission wavelength region set for each pixel unit 100.

  Light incident from above in the Z-axis direction is collected by the microlens 153 for each pixel unit 100 and is photoelectrically converted by the photodiode 105 as a photoelectric conversion unit. Since the metal wiring 142 has a light shielding property, incident light is prevented from entering each impurity diffusion layer (storage diode 106, floating diffusion 107) formed in the semiconductor substrate 101.

  In FIG. 3, for the sake of convenience, in order to explain the configuration of the pixel array 10 of the solid-state imaging device 1, the photodiode 105 is illustrated so as to exist above the storage diode 106 and the floating diffusion 107 in the Z-axis direction. In reality, however, it has the arrangement relationship shown in FIG.

3. Driving of Solid-State Imaging Device 1 The solid-state imaging device 1 having the above configuration has a global electronic shutter function. The driving thereof will be described with reference to FIGS.

  FIG. 4A is an equivalent circuit of one pixel unit 100 in the solid-state imaging device 1 according to Embodiment 1 of the present invention, and FIG. 4B is a potential diagram showing the potential of each node. is there. FIG. 5 is a schematic diagram of a timing chart of the global electronic shutter operation of the solid-state imaging device 1, and FIG. 6 is a schematic diagram of the operation potential of the pixel unit 100 during the global electronic shutter operation of the solid-state imaging device 1.

  As shown in FIG. 4A, the photodiode (PD) 105 is provided with an overflow drain (OFD) 109 via a transfer gate (GR) 114 and stored via a transfer gate (GS) 110. A diode (SD) 106 is provided.

In FIG. 4A and the like, the connection diode 175 is omitted.
A floating diffusion (FD) 107 is provided for the storage diode (SD) 106 via a transfer gate (TX) 111. The floating diffusion (FD) 107 is connected to the gate (amplification Tr gate 112) of the amplification transistor (SF) 116, and a reset drain (RD) 108 is provided via the transfer gate (RS) 113. Yes. A drain voltage (V _DD ) is connected to the drain (SFD) 115 of the amplification transistor (SF).

Next, as shown in the potential diagram of FIG. 4B, the potentials are low in the transfer gates 114, 110, 111, and 113, and are high in the other regions.
As shown in FIG. 5, the period from the application start timing of the transfer pulse GS to the start of application of the next transfer pulse GS is 1 frame, and the application of the next transfer pulse GS is started immediately after the application of the transfer pulse GR is completed. The accumulation time is the time until

  Specifically, as shown in FIG. 5, at the beginning of 1 frame, the transfer pulse GS is applied to the gate electrodes of the transfer gate (GS) 110 in a batch for all the pixel units 100. As a result, charges existing in the photodiode (PD) 105 are transferred to the storage diode (SD) 106 all at once.

Next, a reset pulse GR is applied to all the pixel portions 100 at once to the gate electrode of the transfer gate (GR) 114. As a result, the signal charges of the photodiode (PD) 105 are simultaneously swept out to the overflow drain (OFD) 109 (timing t ₁ ). After the charge is discharged to the overflow drain (OFD) 109, the accumulation time is started.

Next, a reset pulse RS _n is applied to the gate electrode of the transfer gate (RS) 113 of the pixel unit 100 located in the n-th row, whereby the charge of the floating diffusion (FD) 107 in the n-th row. The state is reset (timing t ₃ ). Next, as described above, the gate electrode of the transfer gate (TX) 111 is applied to the pixel portion 100 in the n-th row where the reset pulse RS _n is applied to the gate electrode of the transfer gate (RS) 113. On the other hand, the transfer pulse TX _n is applied. As a result, the signal charge is transferred from the storage diode (SD) 106 to the floating diffusion (FD) 107 (timing t ₄ ).

Similarly, the reset pulse RS _{n + 1} and the transfer pulse TX _{n + 1} are respectively applied to the gate electrodes of the transfer gates (RS, TX) 113 and 111 in the pixel unit 100 in the (n + 1) th row. As a result, the charge state of the floating diffusion (FD) 107 of the pixel unit 100 in the (n + 1) th row is reset, and the signal charge is transferred from the storage diode (SD) 106 to the floating diffusion (FD) 107.

In the above description, the pulses GR and GS are pulses applied to all the pixel units 100 all at once, and the other pulses RS _n , TX _n , RS _{n + 1} , TX _{n + 1} ,. The pulse is applied to each row unit according to.

Next, the global electronic shutter operation of the solid-state imaging device 1 will be described with reference to the schematic diagrams of the operation potentials of FIGS.
Here, FIG. 6A shows the state of the pixel unit 100 when the charge states of the photodiodes (PD) 105 of all the pixel units 100 are collectively reset (signal charges of the light receiving unit are collectively reset) (t = t ₁ ). FIG. 6B shows the operating potential. FIG. 6B shows the signal charges newly accumulated in the photodiodes (PD) 105 after collectively resetting the charge states of the photodiodes (PD) 105 of all the pixel units 100. The operation potential of the pixel portion 100 when collectively transferred to the storage diode (SD) 106 (t = t ₂ ) is shown.

Further, FIG. 6C illustrates a case where the signal charge of the storage diode (SD) 106 in the n-th row (here, the row to which the pulses TX _n and RS _n are applied) is transferred to the floating diffusion (FD) 107. FIG. 6D shows the operating potential of the pixel unit 100 when the floating diffusion (FD) 107 is reset (t = t ₃ ). FIG. 6D shows the storage diode (SD) 106 in the n-th row according to the sequential readout timing. The operating potential of the pixel portion 100 when the signal charge is transferred to the floating diffusion (FD) 107 (t = t ₄ ) is shown.

FIG. 6E shows a state before transferring the signal charge of the storage diode (SD) 106 in the (n + 1) th row (here, the row to which the pulses TX _{n + 1} and RS _{n + 1} are applied) to the floating diffusion (FD) 107. The operating potential of the pixel unit 100 when the floating diffusion (FD) 107 is reset (t = t ₅ ) is shown.

As shown in FIG. 6 (a), at time _{t 1,} (see Figure 5) by applying a pulse GR, a transfer gate (GR) 114 is ON. As a result, the charges existing in the photodiodes (PD) 105 in all the pixel portions 100 are transferred to the overflow drain (OFD) 109 all at once and are swept out. Thereby, reading of the global electronic shutter (start of accumulation time) is started.

Next, as shown in FIG. 6 (b), at timing _{t 2,} the pulse GS is ON, the pulse GR is OFF. And the pulse TX (TX _n , TX _{n + 1} ,...) Is also OFF. By applying the pulse GS, the transfer gate (GS) 110 is turned ON, and the pulses are applied to the transfer gates (GS) 110 of all the pixel units 100 all at once, so that the photodiodes (PD) 105 of the all pixel units 100 are connected. The signal charges are transferred all at once to the storage diode (SD) 106 and temporarily stored. This completes the reading of the global electronic shutter (end of the accumulation time).

Further, the accumulation time from timing t ₁ ′ immediately after the pulse GR is turned off to timing t ₂ ′ immediately after the pulse GS is turned on is the electronic shutter time, and can be set to an arbitrary time.

  Next, all the pixel units 100 are transferred to the storage diode (SD) 106 all at once, and signal charges stored in the storage diode (SD) 106 are read out to the outside through the floating diffusion (FD) 107 by sequential reading. Move on.

As shown in FIG. 6 (c), at time _{t 3,} a pulse GS and pulse GR has become a OFF, pulse RS _n is ON, the pulse TX _n is turned OFF. In this case, the pulse RS _n is in an ON state and is applied to the gate electrode of the transfer gate (RS) 113, whereby unnecessary charges in the floating diffusion (FD) 107 are reset, and the potential after the reset is the drain voltage. V _DD .

Next, the signal charge of the storage diode (SD) 106 is transferred to the floating diffusion (FD) 107.
As shown in FIG. 6 (d), at time _{t 4,} the pulse GS, GR is OFF, the pulse TX _n ON, pulse RS _n is OFF. In this case, when the pulse TX _n is turned on and applied to the gate electrode of the transfer gate (TX) 111, the signal charge after the electronic shutter of the storage diode (SD) 106 in the row to which the pulse TX _n is applied is changed. , And transferred to the floating diffusion (FD) 107. Here, the potential of the floating diffusion (FD) 107 changes from V _DD in accordance with the amount of signal charge transferred. This potential change is read out to the outside as a video signal through an amplification transistor (SF) 116 formed of a source follower.

Here, as shown above, a period other than the timing of transfer of the signal charge accumulation diode (SD) 106 to the floating diffusion (FD) 107, a pulse RS _n In the ON state, the gate of the transfer gate (RS) 113 By being applied to the electrodes, unnecessary charges in the floating diffusion (FD) 107 continue to be reset.

Next, in the (n + 1) th row, the process proceeds to sequential reading of signal charges accumulated in the storage diode (SD) 106.
As shown in FIG. 6 (e), at time _{t 5,} a pulse GS, GR is OFF, the pulse _{RS n + 1} is ON, the pulse _{TX n + 1} is OFF. In this case, the pulse RS _{n + 1} is turned on and applied to the gate electrode of the transfer gate (RS) 113, so that unnecessary charges in the floating diffusion (FD) 107 are reset, and the potential after the reset is the drain voltage V It becomes _DD . Thereafter, the sequential readout driving cycle shown in FIGS. 6C to 6E is repeated until all rows are read out, and the readout of the image captured in an arbitrary accumulation time by the electronic shutter operation is completed.

4). Effect In the solid-state imaging device 1 according to the present embodiment, the photodiode 105 is provided on one main surface side (the main surface side on the upper side in the Z-axis direction in FIG. 3) in the semiconductor substrate 101, and the other in the semiconductor substrate 101. Since the storage diode 106 is formed on the main surface side (main surface side on the lower side in the Z-axis direction in FIG. 3), the photodiode 105 and the storage diode 106 are in a trade-off relationship with respect to the occupied area. There is no. For this reason, it is possible to achieve both a sufficient capacity of the light receiving section and a sufficient capacity of the storage diode 106. Therefore, in the solid-state imaging device 1, in a solid-state imaging device having a global electronic shutter function, a sufficient area of the photoelectric conversion unit can be ensured even by miniaturization of the size of the pixel unit 100. A range can be realized.

  In the solid-state imaging device 1, in each pixel unit 100, an overflow drain 109 is formed with respect to the connection diode 175 via the transfer gate 114. For this reason, in the solid-state imaging device 1, in all the pixel units 100, the accumulated charges of the photodiode 105 and the connection diode 105 are collectively reset via the overflow drain 109, and then the photodiode 105 performs a predetermined time (shutter time). Signal charges generated between them can be read all at once and transferred to the storage diode 106 for temporary storage. Thereafter, as described above, the signal charge is transferred from the storage diode 106 to the floating diffusion 107, and the potential change is sequentially read out via the amplification transistor 116 according to the signal charge. Thus, the solid-state imaging device 1 according to the present embodiment also has a global electronic shutter function.

  As described above, the solid-state imaging device 1 according to the present embodiment has a global electronic shutter function, and can capture images with high image quality even in moving shooting. Has sensitivity.

  In the solid-state imaging device 1 according to the present embodiment, a metal wiring 142 having a light shielding property is formed in the pixel separation unit 300, and the connection diode 175, the storage diode 106, and the floating diffusion 107 are arranged below the metal wiring 142. The storage diode 106 and the floating diffusion 107 are formed below the metal wiring 142. For this reason, in the solid-state imaging device 1, light is prevented from entering between adjacent photodiodes 105 (pixel separation unit 300), and false signal charges are generated in the connection diode 175, the storage diode 106, and the floating diffusion 107. Can be prevented, and deterioration of image quality due to this can be prevented. Therefore, in the solid-state imaging device 1 according to the present embodiment, high image quality can be obtained without mixing of false signal charges.

5. Manufacturing Method of Solid-State Imaging Device 1 A manufacturing method of the solid-state imaging device 1 according to the present embodiment will be described with reference to FIGS.

As shown in FIG. 7A, an alignment mark for lithography is formed on a semiconductor substrate 1010 (not shown), and then a photodiode 105 that is an n ⁺ -type impurity diffusion layer is provided for each pixel unit 100. To form. The photodiode 105 includes, for example, phosphorus (P) or arsenic (As) ions of 300 [keV] to 500 [keV], 1 × 10 ¹² [cm ⁻² ] to 1 × 10 ¹³ [cm ⁻² ], It is formed by injection.

Next, an STI (Shallow Trench Isolation) 102 for separating transistors and diffusion layer elements is formed. Specifically, by performing dry etching on a corresponding portion of the semiconductor substrate 1010, for example, a groove having a depth of 200 [nm] to 400 [nm] serving as an isolation region is formed. Next, in order to reduce the defect region at the interface between the formed groove and the semiconductor substrate 1010, sacrificial oxidation of, for example, an oxide film thickness of 10 nm to 20 nm is performed by thermal oxidation or the like. Boron (B) ions are implanted at keV] to 20 [keV] and 1 × 10 ¹³ [cm ⁻² ] to 3 × 10 ¹³ [cm ⁻² ] to form the P ⁺ layer channel stopper 103.

  Next, for example, a gate oxide film 1040 having a film thickness of 5 nm to 10 nm is formed by thermal oxidation, plasma oxidation, or the like. The gate oxide film 1040 becomes a gate oxide film of a transistor constituting each transfer gate 110, 111, 113, 114 described later.

  Next, as shown in FIG. 7B, a Poly-Si film having a thickness of, for example, 100 [nm] to 200 [nm] is deposited by thermal CVD, plasma oxidation, or the like. A predetermined resist pattern is formed. Then, the poly-Si film is selectively etched to form the transfer gates 110, 111, 113, 114 and the amplification Tr gate 112 made of the poly-Si film.

Next, phosphorus (P) or arsenic (As), which are n-type impurity layers, are formed on the p-type semiconductor substrate 1010 through a predetermined resist mask opening at a position corresponding to the photodiode 105 formation region in the semiconductor substrate 1010. Are ion-implanted at, for example, 100 [keV] to 200 [keV], 1 × 10 ¹² [cm ⁻² ] to 1 × 10 ¹³ [cm ⁻² ]. Thereby, a connection path between the connection diode 175 and the photodiode 105 described later is formed.

Next, phosphorus (P) or arsenic (As) is applied to the p-type semiconductor substrate 1010 by, for example, 50 [keV] to 80 [keV], 1 × 10 ¹⁴ [cm ⁻² ] to 2 × 10 ¹⁵ [cm ^{−]. 2} ], ion implantation is performed to form an n-type impurity region. The formed impurity regions correspond to the overflow drain 109, the connection diode 175, the storage diode 106, the floating diffusion 107, and the reset drain 108, respectively.

Next, boron (B) is applied to the corresponding surface layer portions of the connection diode 175 and the storage diode 106 through the opening of the resist mask, for example, 5 [keV] to 10 [keV], 1 × 10 ¹¹ [cm ⁻² ] to Ion implantation is performed at 2 × 10 ¹² [cm ⁻² ], whereby the pinning layers 130 and 131 are formed. Here, after the formation of the gate oxide film 104, a part of the floating diffusion 107 is opened to form a gate electrode of the amplification Tr gate 112 composed of a Poly-Si film, and the floating diffusion 107 and the amplification Tr gate are formed. Electrical connection is made with the 112 gate electrode.

  Next, as shown in FIG. 7C, an interlayer insulating film 120 made of a CVD oxide film is formed with a film thickness of, for example, 500 [nm] to 1000 [nm]. Then, a contact hole is formed at a predetermined position by a photolithography technique and an etching technique. The locations where the contact holes are formed correspond to the respective locations of the contact plugs 118, 119, and 135 shown in FIG. A tungsten (W) plug is embedded in the opened contact hole to form a contact plug 123. Each contact plug 123 forms an electrical connection with the overflow drain 109 and the reset drain 108.

  Next, for example, a wiring 126 made of copper (Cu) having a thickness of 150 nm to 200 nm is formed by a damascene method. In forming the wiring 126, aluminum (Al) can be used, and in that case, the wiring film thickness is 200 [nm] to 300 [nm]. By repeating the same, interlayer insulating films 121 and 122, contact plugs 124 and 125, and wirings 127 and 128 are formed, and the formation of the multilayer wiring is completed. Then, a protective film 129, which is a CVD oxide film having a thickness of 500 [nm] to 1000 [nm], for example, is formed so as to cover the upper surface of the interlayer insulating film 122 on which the wiring 128 is formed.

  Next, as shown in FIG. 8A, after planarizing the protective film 129 by CMP, the surface is plasma-treated, and the support substrate 160 is bonded to the surface on which the oxide film is formed. The support substrate 160 is made of, for example, a Si substrate or a glass substrate, and the support substrate 160 is bonded while applying pressure in a nitrogen atmosphere of 200 [° C.] to 300 [° C.]. As a result, the protective film 129 and the support substrate 160 are bonded together at a low temperature on the basis of the Vandiawales force. Then, the semiconductor substrate 1010 is turned upside down together with the support substrate 160.

  Next, as shown in FIG. 8B, the photodiode 105 is formed by back grinding the back side of the semiconductor substrate 1010 (upper side in the Z-axis direction in FIG. 8B) with the support substrate 160 attached. Polish to near the depth of the area. Next, as a finish, polishing is performed to the depth of the photodiode 105 by CMP or wet etching (KOH etching).

Next, as shown in FIG. 9A, after the polishing process as described above, the defect layer at the substrate interface of the photodiode 105 exposed on the outermost surface 101f of the semiconductor substrate 101 (see FIG. 8B). In order to prevent dark current due to the interface state, boron (B) is, for example, 5 [keV] to 10 [keV], 1 × 10 ¹¹ [cm ⁻² ] to ² on the photodiode 105. Ion implantation is performed at × 10 ¹² [cm ⁻² ] to form a pinning layer 140 that is a p ⁺ -type impurity diffusion layer. Next, annealing is performed by laser annealing or the like for the purpose of recovery of defects by ion implantation of boron (B) as described above and carrier activation. Thereby, the dark current of the photodiode 105 can be reduced and the short-wavelength quantum efficiency can be improved by forming the pinning layer 140 and annealing for defect recovery.

  Next, an antireflection film 141 that is a low-temperature CVD film having a thickness of several tens [nm] to several hundreds [nm] is formed on the pinning layer 140. Next, a metal film such as aluminum (Al), tungsten (W), molybdenum (Mo) or the like having a film thickness of 100 [nm] to 300 [nm] is deposited by sputtering or CVD. The metal film 142 is etched by the etching technique to form the mesh-like metal wiring 142 on the antireflection film 141 in the pixel separation unit 300. Next, a protective film 143 made of a CVD oxide film or a plasma oxide film is formed.

  Here, in the pixel separation unit 300, the storage diode 106 is positioned below. However, the formation of the metal wiring 142 can prevent light from entering the storage diode 106.

  Next, a flattening film 150 made of a transparent organic film, a color filter layer 151 made of an organic film containing a pigment, and a flattening film 152 made of a transparent organic film are laminated on the protective film 143. On top of this, the microlenses 153 are sequentially formed (see FIG. 3), and the solid-state imaging device 1 is completed.

[Embodiment 2]
1. Configuration of Pixel Array in Solid-State Imaging Device 2 The configuration of the pixel array in the configuration of the solid-state imaging device 2 will be described with reference to FIGS. 10 and 11. FIG. 10 is a schematic plan view showing a partial region in the pixel array, and FIG. 11 is a schematic cross-sectional view showing the BB ′ cross section and the BB ″ cross section. FIG. 6 is a schematic diagram in which a BB ′ section showing the structure of the readout circuit section and a BB ″ section showing the structure of the upper part (light incident side) after the back surface photodiode are combined. The actual arrangement is different.

  As shown in FIG. 10, also in the solid-state imaging device 2, a pixel separation unit 500 is provided between regions (pixel units) where the photodiodes 405 are formed. Each pixel portion includes a connection diode 475, a storage diode 406, a floating diffusion 407, an amplification transistor 416, and a reset drain 408. An amplification transistor (Tr) drain 415 is provided on the right side of the amplification transistor 416 in the X-axis direction. However, in this embodiment, an overflow drain is not provided in a region adjacent to the connection diode 475. The overflow drain 445 is provided on the side of the semiconductor substrate where the photodiode 405 is formed.

  Also in this embodiment, transfer gates 410, 411, 413, and 414 are provided, and the amplification Tr gate 412 of the amplification transistor 416 is connected to the floating diffusion 407 through the opening 417 of the gate oxide film. A contact plug 418 is connected to the reset drain 408, and a contact plug 435 is connected to the amplification transistor 416. Similarly to the above, contact plugs are connected to the transfer gate 410 and the like.

  Here, as in the first embodiment, the storage diode 406, the floating diffusion 407, and the like are arranged in a region (pixel separation unit 500) between adjacent photodiodes 405.

Next, as shown in FIG. 11, the solid-state imaging device 2 also includes a p-type semiconductor substrate 401, and a gate oxide film 404 is formed on the main surface on the lower side in the Z-axis direction in the figure. A STI (Shallow Trench Isolation) 402 and a p ⁺ -type channel stopper 403 are formed on the lower main surface side in FIG. In addition, with respect to the gate oxide film 404, interlayer insulating films 420, 421, and 422 are sequentially stacked on the lower side in the Z-axis direction, and further, a protective film 429 is stacked on the lower side, and is supported thereunder. A substrate 460 is attached.

  Contact plugs 423, 424, and 425 are formed in the interlayer insulating films 420, 421, and 423, and wirings 426, 427, and 428 are provided at the boundary portions thereof. About these, the material and the formation method are the same as above. As for the contact plug 423, titanium (Ti) is inserted in the boundary portion to reduce contact resistance with the impurity layer (reset drain 408), and TiN is inserted in the boundary portion in order to strengthen adhesion with tungsten (W). (Not shown).

  In the surface layer region inward from the main surface on the gate insulating film 404 side in the semiconductor substrate 401, the connection diode 475, the storage diode 406, the floating diffusion 407, and the reset drain 408 are spaced apart from each other for each pixel portion. It is provided in an open state. Further, on the lower side of the gate oxide film 404 in the Z-axis direction, the gate electrode of the transfer gate 410 is provided in the region between the connection diode 475 and the storage diode 406, and the region between the storage diode 406 and the floating diffusion 407. The gate electrode of the transfer gate 411 is provided, and the gate electrode of the transfer gate 413 is provided in the region between the floating diffusion 407 and the reset drain 408.

  Further, the floating diffusion 407 is connected to the gate electrode of the amplification Tr gate 412 that passes through the gate oxide film 404. In FIG. 11, the gate electrodes of the transfer gates 410, 411, and 413 and the amplification Tr gate 412 are shown in black, and corresponding portions between the impurity diffusion layers are gates. The gate electrodes of the transfer gates 410, 411, 413 and the amplification Tr gate 412 are made of, for example, Poly-Si.

The connection diode 475, the storage diode 406, the floating diffusion 407, and the reset drain 408 are n-type impurity diffusion layers. As shown in FIG. 11, a pinning layer 430 that is a p ⁺ -type impurity layer is formed in a region between the connection diode 475 and the gate oxide film 404. Thereby, the connection diode 475 is a buried diode. Similarly, a pinning layer 431 that is a p ⁺ -type impurity layer is formed in the region between the storage diode 406 and the gate oxide film 404. Thereby, the storage diode 406 is also a buried diode.

Although not shown in the present embodiment, a drain voltage (V _DD ) is connected to the reset drain 408.
On the other hand, in the surface layer portion on the upper side in the Z-axis direction in the semiconductor substrate 401, a photodiode 405 is formed for each pixel portion as in the first embodiment. The photodiodes 405 are arranged in a matrix along the upper main surface of the semiconductor substrate 401 in the Z-axis direction, and each is connected to a corresponding connection diode 475.

  The entire upper surface of the photodiode 405 and the semiconductor substrate 401 in the Z-axis direction is covered with a pinning layer 440, and an antireflection film 441 and a protective film 443 are sequentially stacked thereon. A metal wiring 442 is formed in a boundary portion with the protective film 443 on the antireflection film 441 and in a region corresponding to each pixel separation unit 500. Similar to the first embodiment, the metal wiring 442 has a mesh shape so as to pass between adjacent pixel portions when the pixel array is viewed in plan.

  Here, in the pixel separation unit 500, an overflow drain 445 is inserted at a position corresponding to between adjacent photodiodes 405. The overflow drain 445 is made of an n-type impurity diffusion layer, and is connected to the metal wiring 442 by a contact plug 444. A positive bias voltage can be applied to the metal wiring 442. By applying a positive bias voltage to the overflow drain 445 via the metal wiring 442, the signal charge of the photodiode 405 can be reset.

  On the upper side of the protective film 443 in the Z-axis direction, a planarizing film 450, a color filter layer 451, a planarizing film 452, and a microlens 453 are sequentially stacked. Light incident from above in the Z-axis direction is collected by the microlens 453 for each pixel unit, and is photoelectrically converted by the photodiode 405 as a photoelectric conversion unit. Since the metal wiring 442 has a light shielding property, incident light is prevented from entering each impurity diffusion layer (storage diode 406, floating diffusion 407) formed in the semiconductor substrate 401.

  In FIG. 11, in order to explain the configuration of the pixel array of the solid-state imaging device 2, for the sake of convenience, the photodiode 405 is illustrated above the storage diode 406 and the floating diffusion 407 in the Z-axis direction. However, in actuality, it has the arrangement relationship shown in FIG.

2. Driving of Solid-State Imaging Device 2 The solid-state imaging device 2 having the above-described configuration has a global electronic shutter function. The driving thereof will be described with reference to FIGS.

  FIG. 12A is an equivalent circuit of one pixel unit in the solid-state imaging device 1 according to Embodiment 1 of the present invention, and FIG. 12B is a potential diagram showing the potential of each node. . FIG. 13 is a schematic diagram of a timing chart of the global electronic shutter operation of the solid-state imaging device 1, and FIG. 14 is a schematic diagram of the operation potential of the pixel unit during the global electronic shutter operation of the solid-state imaging device 2.

  As shown in FIG. 12A, an overflow drain (OFD) 445 is formed adjacent to the photodiode (PD) 405, and a storage diode (SD) 406 is provided via a transfer gate (GS) 410. ing. Note that the connection diode 475 is also omitted in FIG.

The storage diode (SD) 406 is provided with a floating diffusion (FD) 407 via a transfer gate (TX) 411, and the floating diffusion (FD) 407 is connected to the gate (amplification Tr) of the amplification transistor (SF) 416. And a reset drain (RD) 408 is provided via a transfer gate (RS) 413. A drain voltage (V _DD ) is connected to the drain (SFD) 415 of the amplification transistor (SF) 416.

  Next, as shown in the potential diagram of FIG. 12B, the potential is low in each of the transfer gates 410, 411, and 413 as in the first embodiment, and is high in the other regions. Yes.

As shown in FIG. 13, the period from the application start timing of the transfer pulse GS to the start of application of the next transfer pulse GS is 1 frame, and immediately after the application of the reset pulse V _OFD to the overflow drain (OFD) 445 is completed, The accumulation time is until the next transfer pulse GS starts to be applied.

  Specifically, as shown in FIG. 13, at the beginning of 1 frame, the transfer pulse GS is applied to the gate electrode of the transfer gate (GS) 410 for all the pixel portions at once. As a result, charges existing in the photodiode (PD) 405 are transferred to the storage diode (SD) 406 all at once.

Next, a reset pulse V _OFD is applied to the overflow drain (OFD) 445 through the metal electrode 442 all at once. As a result, the signal charges of the photodiode (PD) 405 are simultaneously swept out to the overflow drain (OFD) 445 (timing t ₁₁ ). After the charge is discharged to the overflow drain (OFD) 445, the accumulation time is started.

Next, with respect to the gate electrode of the transfer gate (RS) 413 of a pixel portion located in the n-th row, the reset pulse RS _n is applied, thereby, the charge state of the n-th row of the floating diffusion (FD) 407 Is reset (timing t ₁₃ ). Next, as described above, for the pixel portion in the n-th row where the reset pulse RS _n is applied to the gate electrode of the transfer gate (RS) 413, the gate electrode of the transfer gate (TX) 411 is applied. Thus, the transfer pulse TX _n is applied. As a result, signal charges are transferred from the storage diode (SD) 406 to the floating diffusion (FD) 407 (timing t ₁₄ ).

Similarly, the reset pulse RS _{n + 1} and the transfer pulse TX _{n + 1} are respectively applied to the gate electrodes of the transfer gates (RS, TX) 413 and 411 in the pixel portion in the (n + 1) th row. As a result, the charge state of the floating diffusion (FD) 407 in the pixel portion in the (n + 1) th row is reset, and the signal charge is transferred from the storage diode (SD) 406 to the floating diffusion (FD) 407.

In the above, the pulses V _OFD and GS are pulses applied to all the pixel portions all at once, and the other pulses RS _n , TX _n , RS _{n + 1} , TX _{n + 1} ,. The pulse is applied to each row unit according to.

Next, the global electronic shutter operation of the solid-state imaging device 2 will be described using the conceptual diagrams of the operation potentials shown in FIGS. 14 (a) to 14 (e).
As shown in FIG. 14 (a) discharged at the timing t _{= t 11,} the pulse _{V OFD} is turned ON, the signal charge of the photodiode (PD) 405 of all pixel portions, all at once to the overflow drain (OFD) 445 Is done. Thereby, reading of the global electronic shutter (start of accumulation time) is started.

Next, at a timing t _{= t 12} as shown in FIG. 14 (b), the pulse GS is ON, the pulse _{V OFD} is OFF, the pulse _{TX (TX n, TX n +} 1, ···) is also OFF It is. Then, the pulse GS is turned on and applied simultaneously to the gate electrodes of the transfer gates (GS) 410 in all the pixel portions, whereby the signal charges of the photodiodes (PD) 405 in all the pixel portions are simultaneously stored in the storage diode ( SD) 406 and temporarily accumulated. This completes the reading of the global electronic shutter (end of the accumulation time).

Further, as described above, the accumulation time from the timing t = t ₁₁ ′ immediately after the pulse V _OFD is turned off to the timing t = t ₁₂ ′ immediately after the pulse GS is turned on becomes the electronic shutter time, An arbitrary time can be set (see FIG. 13).

  Next, a description will be given of a case where all the pixel portions are simultaneously transferred to the storage diode 406 and the signal charge stored in the storage diode 406 is read out to the outside through the floating diffusion 407 by sequential reading.

As shown in FIG. 14 (c), at time t _{= t 13,} the pulse GS and pulse _{V OFD} is OFF, the pulse RS _n is ON, the pulse TX _n is OFF. Then, the pulse RS _n is in an ON state and is applied to the gate electrode of the reset gate (RS) 413, whereby unnecessary charges in the floating diffusion (FD) 407 are reset, and the potential after the reset is the drain voltage V _DD . Become.

Next, the signal charge of the storage diode (SD) 406 is transferred to the floating diffusion (FD) 407.
As shown in FIG. 14 (d), at time t _{= t 14,} the pulse GS and pulse _{V OFD} is OFF, the pulse TX _n is ON, the pulse RS _n is OFF. When the pulse TX _n is turned on and applied to the gate electrode of the transfer gate (TX) 411, the signal charge after the electronic shutter of the storage diode (SD) 406 in the row to which the pulse TX _n is applied is floating. Transfer to diffusion (FD) 407. Here, the potential of the floating diffusion (FD) 407 changes from V _DD in accordance with the amount of signal charge transferred. This potential change is amplified via an amplification transistor (SF) 416 made of a source follower and read out as a video signal.

Here, as shown above, a period other than the timing of transfer of the signal charge accumulation diode (SD) 406 to the floating diffusion (FD) 407, a pulse RS _n In the ON state, the gate of the transfer gate (RS) 413 By being applied to the electrodes, unnecessary charges in the floating diffusion (FD) 407 continue to be reset.

Next, in the (n + 1) th row, the process shifts to sequential readout of signal charges stored in the storage diode (SD) 406.
As shown in FIG. 14 (e), at time t _{= t 15,} the pulse GS and pulse _{V OFD} is OFF, the pulse _{RS n + 1} is ON, the pulse _{TX n + 1} is OFF. Then, the pulse RS _{n + 1} is turned on and applied to the gate electrode of the reset gate (RS) 413 in the pixel portion of the (n + 1) -th row, so that the floating diffusion (FD) in the pixel portion of the (n + 1) -th row is in the floating diffusion (FD). Unnecessary charges are reset, and the reset potential becomes the drain voltage V _DD .

  Thereafter, the sequential readout driving cycle shown in FIGS. 14C to 14E is repeated until all rows are read out, and the readout of the image captured in an arbitrary accumulation time by the electronic shutter operation is completed.

3. Effect Also in the solid-state imaging device 2 according to the present embodiment, the photodiode 405 is provided on one main surface side (the main surface side on the upper side in the Z-axis direction in FIG. 11) in the semiconductor substrate 401. Since the storage diode 406 is formed on the other main surface side (main surface side on the lower side in the Z-axis direction in FIG. 11), the photodiode 405 and the storage diode 406 are in a trade-off relationship with respect to the occupied area. Not. For this reason, it is possible to achieve both a sufficient light receiving unit capacitance and a sufficient storage diode 406 capacitance. Therefore, in the solid-state imaging device 2 as well, in a solid-state imaging device having a global electronic shutter function, a sufficient area of the photoelectric conversion unit can be secured even by miniaturization of the size of the pixel unit, and high sensitivity and a large dynamic range are achieved. And can be realized.

  In the solid-state imaging device 2, the overflow drain 445 in each pixel portion is provided between adjacent photodiodes 405. For this reason, also in the solid-state imaging device 2 according to the present embodiment, the accumulated charges of the photodiodes 405 are collectively reset via the overflow drain 445 in all the pixel units, and then the photodiode 405 performs a predetermined time (shutter time). The signal charges generated between the pixels can be read all at once and transferred to the storage diode 406 for temporary storage. Thereafter, as described above, the signal charge is transferred from the storage diode 406 to the floating diffusion 407, and the potential change is sequentially read out via the amplification transistor 416 in accordance with the signal charge. Thus, the solid-state imaging device 2 according to the present embodiment also has a global electronic shutter function.

  Furthermore, in the solid-state imaging device 2 according to the present embodiment, the overflow drain 445 is provided in the surface layer portion of the semiconductor substrate 401 on the side where the photodiode 405 is formed, so that compared with the first embodiment, The area occupied by the storage diode 406 can be increased by the amount corresponding to the region where the overflow drain 445 is formed.

  As described above, the solid-state imaging device 2 according to the present embodiment has a global electronic shutter function, and can capture images with high image quality even in moving shooting. Has sensitivity.

  Also in the solid-state imaging device 2 according to the present embodiment, a metal wiring 442 having a light shielding property is formed in the pixel separating unit 500, and the storage diode 406 and the floating diffusion 407 are formed below the metal wiring 442. (See FIG. 10 and FIG. 11). For this reason, also in the solid-state imaging device 2, the incidence of light through the adjacent photodiodes 405 (pixel separation unit 500) is prevented, and generation of false signal charges in the storage diode 406 and the floating diffusion 407 is prevented. It is possible to prevent the deterioration of the image quality due to this. Therefore, even in the solid-state imaging device 2 according to the present embodiment, it is possible to obtain a high image quality without mixing of false signal charges.

4). Manufacturing Method of Solid-State Imaging Device 2 A manufacturing method of the solid-state imaging device 2 according to the present embodiment will be described with reference to FIGS. 15 and 16 mainly with respect to differences from the first embodiment.

  As shown in FIG. 15A, a photodiode 405 is formed in the upper portion of the semiconductor substrate 401 in the Z-axis direction by the same method as in the first embodiment, and the photodiode 405 is polished by the same manner as described above. Is exposed on the top surface. Similarly to the above, the STI 402, the channel stopper 403, the connection diode 475, the storage diode 406, the floating diffusion 407, and the reset drain 408 are formed on the other main surface side (the lower side in the Z-axis direction) in the semiconductor substrate 401. The connection diode 475 and the storage diode 406 are buried diodes by forming the pinning layers 430 and 431.

  Further, a gate oxide film 404 is formed on the lower main surface of the semiconductor substrate 401, and gate electrodes of transfer gates 410, 411, and 413 and an amplification Tr gate 412 are formed. Further, interlayer insulating films 420, 421, 422 and a protective film 429 are stacked on the gate oxide film 404, and contact plugs 423, 424, 425 and wirings 426, 427, 428 are provided. Further, a support substrate 460 is attached to the lower main surface of the protective film 429. These manufacturing methods are as described above.

Next, as illustrated in FIG. 15B, the main surface 401 f on the upper side in the Z-axis direction of the semiconductor substrate 401 is polished to the depth of the photodiode 405 by back grinding, CMP, and chemical etching, and then the photodiode 405. On top, boron (B), which is a p ⁺ type impurity, is ion-implanted. The injection conditions are, for example, 5 [keV] to 10 [keV], 1 × 10 ¹¹ [cm ⁻² ] to 2 × 10 ¹² [cm ⁻² ]. By this implantation, a pinning layer 4400 which is a p ⁺ type impurity diffusion layer is formed.

Next, as shown in FIG. 16A, phosphorus (P), which is an n-type impurity, is applied to the semiconductor substrate 401 (pinning layer 4400) in the region corresponding to the pixel isolation portion 500 through a resist opening mask. ) And arsenic (As), for example, at 50 [keV] to 80 [keV], 1 × 10 ¹⁴ [cm ⁻² ] to 2 × 10 ¹⁵ [cm ⁻² ]. Thereby, an overflow drain 445 can be formed between adjacent photodiodes 405 in the semiconductor substrate 401. Here, the overflow drain 445 is formed in a state where the pinning layer 440 is also inserted.

  Next, as shown in FIG. 16B, an antireflection film 441 that is a low-temperature CVD film is formed on the pinning layer 440 and the overflow drain 445, for example, a film of several tens [nm] to several hundreds [nm]. Form with thickness. Next, a resist opening mask having a predetermined pattern is formed on the portion corresponding to the overflow drain 445 on the antireflection film 441, the corresponding portion is opened by dry etching technique, and contact is made on the n-type overflow drain 445. Form holes. Then, by sputtering or CVD, for example, a metal film made of aluminum (Al), tungsten (W), molybdenum (Mo), TiN or the like having a film thickness of 100 [nm] to 300 [nm] is deposited, and then The metal film is etched by photolithography technique and etching technique, and contact plugs 444 connected to the overflow drain 445 and mesh-like metal wirings 442 are formed in a region corresponding to the pixel separation portion 500 of the antireflection film 441. To do.

Next, a protective film 443 made of a CVD oxide film or a plasma oxide film is formed.
Although the illustration of the subsequent steps is omitted, as in the first embodiment, a flattening film 450 made of a transparent organic film and a color made of an organic film containing a pigment are formed on the protective film 443. A filter layer 451, a planarizing film 452 made of a transparent organic film, and a microlens 453 made of a transparent organic film are formed in this order to complete the solid-state imaging device 2 (see FIG. 11).

[Embodiment 3]
1. Configuration of Pixel Array in Solid-State Imaging Device 3 Among the configurations of the solid-state imaging device 3, the configuration of the pixel array will be described with reference to FIG. In FIG. 17, a part of the pixel portion 600 in the pixel array is extracted and schematically shown.

As shown in FIG. 17, the configuration of the solid-state imaging device 3 is the same as that of the second embodiment in the basic part. That is, as shown in FIG. 17, a gate oxide film 604 is laminated on the main surface on the lower side in the Z-axis direction on the p-type semiconductor substrate 601, and the lower main surface side portion in the semiconductor substrate 601 is formed on the lower main surface side. In addition, an STI (Shallow Trench Isolation) 602 and a p ⁺ type channel stopper 603 are formed for each pixel unit. Further, with respect to the gate oxide film 604, interlayer insulating films 620, 621, and 622 are sequentially stacked on the lower side in the Z-axis direction, and a protective film 629 is further stacked on the lower side, and a support is provided therebelow. A substrate 660 is attached.

  Contact plugs 623, 624, and 625 are formed in the interlayer insulating films 620, 621, and 623, and wirings 626, 627, and 628 are provided in the boundary portions of each other. About these, the material and the formation method are the same as above. As for the contact plug 623, titanium (Ti) is inserted in the boundary portion to reduce contact resistance with the impurity layer (reset drain 608), and TiN is inserted in the boundary portion to strengthen adhesion with tungsten (W). (Not shown).

  A connection diode 675, a storage diode 606, a floating diffusion 607, and a reset drain 608 are provided for each pixel portion in a surface layer region inward from the main surface on the gate insulating film 604 side in the semiconductor substrate 601. The gate electrodes of transfer gates 610, 611, 613 and amplification Tr gate 612 are provided. Each gate electrode is made of, for example, Poly-Si.

The connection diode 675 and the storage diode 606 are buried diodes by forming the pinning layers 630 and 631. Although not shown in the present embodiment, a drain voltage (V _DD ) is connected to the reset drain 608.

  On the other hand, in the surface layer portion on the upper side in the Z-axis direction in the semiconductor substrate 601, a photodiode 605 is formed for each pixel portion as in the first embodiment, and each is connected to a corresponding connection diode 675. On the upper side of the photodiode 605 and the semiconductor substrate 601 in the Z-axis direction, a pinning layer 640, an antireflection film 641 and a protective film 643 are sequentially stacked, and further, a planarization film 650 and a color filter layer 651 are formed thereon. The planarization film 452 and the microlens 653 are sequentially stacked.

  In the present embodiment, similarly to the second embodiment, a metal wiring 642 is formed in a boundary portion with the protective film 643 on the antireflection film 641 and in a region corresponding to each pixel separation portion 700. Has been. Similarly to the first embodiment, the metal wiring 642 has a mesh shape so as to pass between adjacent pixel portions when the pixel array is viewed in plan.

Here, in the pixel separation unit 700, an overflow drain 645 is inserted at a position corresponding to between adjacent photodiodes 605, and is connected to the metal wiring 642 by a contact plug 644. Similar to the second embodiment, a positive bias voltage can be applied to the metal wiring 642. The solid-state imaging device 3 according to the present embodiment differs from the solid-state imaging device 2 according to the second embodiment in that an overflow drain (OFD) that is an n ⁻ type impurity diffusion layer corresponds to each overflow drain 645. The barrier layer 646 is formed.

  In the solid-state imaging device 3 according to the present embodiment, the potential of the overflow drain 645 is controlled by applying a positive bias voltage to the overflow drain 645 from the outside via the metal wiring 642, and the OFD barrier layer 646. It is possible to reset the charge of the photodiode 605 via

2. Effects The solid-state imaging device 3 according to the present embodiment also has the same effects as the solid-state imaging device 2 according to the second embodiment. In addition to this, in the solid-state imaging device 3 according to the present embodiment, the formation of the OFD barrier layer 646 enables the charge of the photodiode 605 to be reset more reliably, has a global electronic shutter function, and further High image quality performance.

3. Manufacturing Method of Solid-State Imaging Device 3 The manufacturing method of the solid-state imaging device 3 according to the present embodiment is generally the same as that of the second embodiment, but only the difference will be described. Specifically, the manufacturing method of the solid-state imaging device 3 according to the present embodiment is different from the manufacturing method of the solid-state imaging device 2 according to the second embodiment, and the OFD barrier layer 646 is formed.

Specifically, phosphorus (P) or arsenic (As), which are n-type impurities, are applied to the semiconductor substrate 601 in a region corresponding to the pixel separation portion 700 through a resist opening mask, for example, from 50 [keV] to Overflow drain 645 is formed by ion implantation at 80 [keV], 1 × 10 ¹⁴ [cm ⁻² ] to 2 × 10 ¹⁵ [cm ⁻² ]. Then, depending on the implantation conditions in which the impurity concentration is lower than the implantation condition of the overflow drain 645 and the implantation depth is deep, for example, phosphorus (P) or arsenic (As) is changed from 60 [keV] to 90 [keV], 1 × The OFD barrier layer 646 can be formed by ion implantation at 10 ¹³ [cm ⁻² ] to 2 × 10 ¹⁴ [cm ⁻² ].

  Note that the OFD barrier layer 646 may be formed without any special treatment, but the same function can still be obtained. Since the other steps are the same as those in the second embodiment, description thereof is omitted.

[Other matters]
In the solid-state imaging devices 1, 2, and 3 according to the first, second, and third embodiments, the overflow drains 109, 445, and 645 are provided for each of the pixel units 100, 600,. Alternatively, a configuration in which one overflow drain is shared by a larger number of pixel portions may be employed. Similarly, the reset drains 108, 408, and 608 may be configured to share one reset drain with one pixel portion or more pixel portions.

  In the solid-state imaging device according to the first, second, and third embodiments, a plurality of pixel units 100, 600,... Are arranged in a matrix in the pixel array 10,. However, the arrangement configuration of the pixel portions is not limited to this, and may be arranged in a honeycomb shape, for example.

  In the solid-state imaging devices 1, 2, and 3 according to the first, second, and third embodiments, the microlenses 153, 453, and 653 are each provided on the top side. Or a combination of a convex lens and a convex lens, or a combination of a concave lens and a concave lens.

  The present invention is useful for realizing a solid-state imaging device having a global electronic shutter function, capable of capturing a moving subject with high image quality, and capable of capturing with high sensitivity. is there.

1,2,3. Solid-state imaging device 10. Pixel array 21. Pulse generation circuit 22. Horizontal shift register 23. Vertical shift register 100,700. Pixel part 101,401,601,1010. Semiconductor substrate 102, 402, 602. STI
103, 403, 603. Channel stoppers 104, 404, 604, 1040. Gate oxide film 105,405,605. Photodiode 106,406,606. Storage diode 107,407,607. Floating diffusion 108,408,608. Reset drain 109,445,645. Overflow drain 110,111,113,114,410,411,413,610,611,613. Transfer gate 112,412,612. Amplification Tr gate 115,415. Amplified Tr drain 116,416. Amplifying transistors 117, 417. Gate oxide opening 118,119,123,124,125,135,136,418,423,424,425,435,444,623,624,625,644. Contact plug 120,121,122,420,421,422,620,621,622. Interlayer insulating film 126, 127, 128, 426, 427, 626, 627, 628. Wiring 130, 131, 140, 430, 431, 440, 4400, 630, 631, 640. Pinning layer 142,442,642. Metal wiring 129, 143, 429, 443, 629, 643. Protective film 141,441,641. Antireflection film 150, 152, 450, 452, 650, 652. Planarization film 151,451,651. Color filter layer 153,453,653. Microlens 160, 460, 660. Support substrate 175,475,675. Connecting diode 300, 500, 700. Pixel separation unit 646. OFD barrier layer

Claims (6)

A semiconductor substrate;
A plurality of photoelectric conversion units that are two-dimensionally formed on the first main surface side in the semiconductor substrate in a state along the first main surface and with a space between each other;
A second main surface side opposite to the first main surface in the semiconductor substrate is provided corresponding to each of the plurality of photoelectric conversion units and connected to the corresponding photoelectric conversion unit. Connected diodes,
A storage diode provided on the second main surface side in the semiconductor substrate, corresponding to each of the connection diodes, and provided via the corresponding connection diode and the first gate;
An overflow drain corresponding to each of the connection diodes on the second main surface side in the semiconductor substrate and provided via the corresponding connection diode and the second gate;
A solid-state imaging device characterized by comprising: A semiconductor substrate;
A plurality of photoelectric conversion units that are two-dimensionally formed on the first main surface side in the semiconductor substrate in a state along the first main surface and with a space between each other;
A second main surface side opposite to the first main surface in the semiconductor substrate is provided corresponding to each of the plurality of photoelectric conversion units and connected to the corresponding photoelectric conversion unit. Connected diodes,
A storage diode provided on the second main surface side in the semiconductor substrate, corresponding to each of the connection diodes, and provided via the corresponding connection diode and the first gate;
An overflow drain provided between the adjacent photoelectric conversion units on the first main surface side in the semiconductor substrate;
A solid-state imaging device characterized by comprising: further,
The floating diffusion provided on the second main surface side in the semiconductor substrate, corresponding to each of the storage diodes, and provided via the corresponding storage diode and a third gate. Item 3. The solid-state imaging device according to Item 1 or 2. Above the second main surface of the semiconductor substrate, a light-shielding metal film is formed in a portion corresponding to the space between the adjacent photoelectric conversion portions,
4. The solid-state imaging device according to claim 3, wherein at least a part of the floating diffusion above the first main surface side of the semiconductor substrate is covered with the metal film. Above the second main surface of the semiconductor substrate, a light-shielding metal film is formed in a portion corresponding to the space between the adjacent photoelectric conversion portions,
4. The solid according to claim 1, wherein at least a part of the storage diode above the first main surface side of the semiconductor substrate is covered with the metal film. 5. Imaging device. Above the second main surface of the semiconductor substrate, a light-shielding metal film is formed in a portion corresponding to the space between the adjacent photoelectric conversion portions,
The solid-state imaging device according to claim 2, wherein the overflow drain is connected to the metal film and receives a bias voltage from the bias voltage application unit via the metal film.

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