JP2012199711A - Evaluation device and evaluation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an evaluation device and an evaluation method capable of evaluating behavior of a wireless communication terminal device in the case that bit inversion of a signal occurs.SOLUTION: A DBB-LSI 11 outputs a first signal indicating logic of respective bits included in communication data by means of potential. An RF-LSI 12 determines the logic based on the potential of respective bits of an inputted signal, and acquires data having the logic. An SW 16 switches between a signal transmission path for inputting the first signal outputted from the DBB-LSI 11 to the RF-LSI 12, and a predetermined voltage input path for inputting a signal having a predetermined voltage as substitute for the first signal to the RF-LSI 12. In response to designation of a predetermined bit included in the communication data, a control circuit 10 makes the SW 16 switch over to the predetermined voltage input path to change the potential of a part where the predetermined bit of the first signal is located inputted to the RF-LSI 12, to a predetermined value.

Description

  The present invention relates to an evaluation apparatus and an evaluation method.

  In recent years, wireless communication terminals such as mobile phones and PDAs (Personal Digital Assistants) are rapidly spreading due to their convenience. In the development of such a wireless communication terminal product, communication is evaluated using a wireless communication terminal evaluation device, which is a wireless communication terminal evaluation device, and a pseudo base station. Hereinafter, the evaluation device may be referred to as a wireless communication terminal evaluation device. In this communication evaluation, a wireless communication terminal evaluation apparatus and a pseudo base station are connected by a coaxial cable, and simulated wireless communication is performed via the coaxial cable. In the development stage, the communication state can be maintained without problems by simulated wireless communication using the wireless communication terminal evaluation apparatus and the pseudo base station, and the development is completed when the evaluation is completed. Products that have been developed through these processes are shipped to the market.

  In addition, after a product is shipped, the cause of the failure may be identified for a product that is individually returned due to a failure or the like. In that case, first, the cause of failure is identified at the product development stage, the error log remaining in the product is checked, the data in the product is checked using a logic analyzer, and the cause is specified to some extent. Thereafter, reproduction confirmation is performed using the wireless communication terminal evaluation apparatus. If the reproduction can be confirmed, the firmware is corrected. Then, by using the corrected firmware for the wireless communication terminal evaluation device and performing validity confirmation, the cause of the failure is identified and a countermeasure method for the failure is determined.

  As described above, the wireless communication terminal evaluation apparatus is used for development of wireless communication terminals, confirmation and correction of defects, and the like. This wireless communication terminal evaluation apparatus is an apparatus for performing pseudo wireless communication with a pseudo base station and using the result for operation evaluation. This pseudo base station has a conventional technique for communicating with a wireless communication terminal using a virtual terminal. As a wireless communication terminal evaluation apparatus, there is a conventional technique that changes the signal level of a communication signal by changing the distance from a pseudo base station.

  Such a wireless communication terminal evaluation apparatus is an apparatus in which components necessary for a final product, which is a product on the market, are connected by a cable or a connector. Here, each component is, for example, a liquid crystal screen, a keypad, a wireless signal transmission / reception unit, a digital processing unit, or the like. Among components provided in such a wireless communication evaluation apparatus, there are RF (Radio Frequency) -LSI (Large Scale Integration) and DBB (Digital Base Band) -LSI. The RF-LSI converts a radio signal from an analog signal to a digital signal. The DBB-LSI performs digital processing such as demodulation, modulation, spreading, and despreading on the digital signal generated by the RF-LSI. The RF-LSI and the DBB-LSI provided in the wireless communication terminal evaluation apparatus are connected by an LVDS (Low Voltage Differential Signaling) interface. Both the RF-LSI and the DBB-LSI are incorporated in a wireless communication terminal as a product, and are connected to each other through an LVDS interface.

  Here, since the current wireless communication terminal incorporates many functions, use of other functions may cause malfunction. For example, when the DBB-LSI sends a reception start signal to the RF-LSI, the operator is performing another operation such as watching a terrestrial digital broadcast or using it as a music player. There is. When another operation is performed in this manner, a lot of power supply noise is generated in the wireless communication terminal device as compared with a case where such an operation is not performed. Further, the wireless communication terminal is smaller and more densely mounted than the wireless communication terminal evaluation apparatus. For this reason, in an actual wireless communication terminal, the intervals of components such as LSIs are close to each other, so that it is conceivable that the power supply noise increases as compared with the evaluation performed by the wireless communication terminal evaluation apparatus. If the power supply noise increases, the data on the LVDS transmission path is bit-inverted and normal data may not reach the RF-LSI.

  Here, the reason why bit inversion tends to occur when the power supply noise increases will be described. When comparing the Eye pattern of the LVDS interface when there is power noise and when there is no power noise, the Eye pattern when there is power noise is narrower than the Eye pattern when there is no power noise. Therefore, it can be seen that bit inversion tends to occur when power supply noise occurs.

  If normal data does not arrive normally, the RF-LSI makes a retransmission request to the DBB-LSI, and the DBB-LSI sends a reception start signal again. However, if the RF-LSI is receiving bit-reversed data, the RF-LSI will be in an unexpected state due to the garbled data, and the subsequent data will not be accepted. There is a risk of falling into.

  When such a failure occurs, the above-described failure is confirmed and corrected. However, it takes a lot of time to check and correct defects. In particular, when each LSI is supplied from an overseas manufacturer, it takes one to two days to obtain the test program.

  In addition, in the case of products that have already been shipped, if such a problem occurs, after confirming and correcting the problem, we distribute the firmware that has been validated to address the problem of each product. Yes. Therefore, the defect is not corrected until the firmware is distributed, which causes inconvenience to the user of the wireless communication terminal.

  Therefore, in order to avoid such a problem caused by bit inversion, it is necessary to verify the operation when bit inversion occurs using a wireless communication terminal evaluation apparatus at the development stage. Also, when dealing with a failure, it is necessary to quickly determine whether or not the failure is caused by bit inversion.

JP 2005-244651 A JP 2006-101141 A

  However, it is difficult for the conventional wireless communication terminal evaluation apparatus to forcibly cause bit inversion. Therefore, in the conventional wireless communication terminal evaluation apparatus, what kind of wireless communication terminal is used when the signal is bit-reversed while the signal is being exchanged between the RF-LSI and the DBB-LSI? It was difficult to confirm whether to perform the operation. For example, it is difficult to cause bit inversion even by using the conventional technique of changing the signal level by changing the positional relationship with the pseudo base station or the conventional technique of the pseudo base station having a virtual terminal.

  Further, fine timing control is performed in the exchange of signals between the DBB-LSI and the RF-LSI. Therefore, when changing data bits in accordance with the timing control between the DBB-LSI and the RF-LSI, it is difficult to achieve synchronization at that timing. For example, in the case of a system in which a signal output from a DBB-LSI is captured by an FPGA (Field Programmable Gate Array), and data bits of the signal captured in the FPGA are changed and transmitted to the RF-LSI, There will be a time difference in delivery. Therefore, in such a system, there is a possibility that communication cannot be performed because the timing control between the DBB-LSI and the RF-LSI is not in time.

  The disclosed technology has been made in view of the above, and an object thereof is to provide an evaluation device and an evaluation method capable of evaluating the behavior of a wireless communication terminal device when a signal causes bit inversion. .

  In one aspect of the evaluation device and the evaluation method disclosed in the present application, the baseband processing unit outputs a first signal that represents the logic of each bit included in the communication data by a potential. The RF unit determines the logic of each bit based on the potential of the input signal, and acquires data having the logic. The first switch is a signal transmission path for inputting the first signal output from the baseband processing unit to the RF unit, and a predetermined signal for inputting a signal having a predetermined voltage instead of the first signal to the RF unit. Switches to the voltage input path. The control unit represents the predetermined bit of the first signal input to the RF unit by switching the first switch to the predetermined voltage input path in response to designation of the predetermined bit included in the communication data. The potential of the part is changed to a predetermined value. The information acquisition unit receives data in which the logic of the predetermined bit of the communication data is inverted by receiving the input of the first signal in which the potential of the portion representing the predetermined bit is changed to a predetermined value. The behavior information of the RF unit is acquired.

  According to one aspect of the evaluation device and the evaluation method disclosed in the present application, it is possible to evaluate the behavior of the wireless communication terminal device when the signal undergoes bit inversion.

FIG. 1 is an overall view of an evaluation system for evaluating a wireless communication terminal. FIG. 2 is a circuit configuration diagram illustrating an outline of the mobile phone evaluation apparatus according to the first embodiment. FIG. 3 is a diagram illustrating a switch logic table of SW16. FIG. 4 is a timing chart of the control circuit according to the first embodiment. FIG. 5 is a circuit configuration diagram of a circuit that generates a one-pulse waveform signal in the control circuit. FIG. 6 is a circuit configuration diagram of a circuit that controls the switch using the one-pulse waveform signal in the control circuit. FIG. 7 is a timing chart of signals input to the control circuit according to the first embodiment and generated signals. FIG. 8 is a flowchart of the operation of the control circuit. FIG. 9 is a circuit configuration diagram illustrating an outline of the mobile phone evaluation apparatus according to the second embodiment. FIG. 10 is a diagram illustrating a switch logic table of SW19 and SW20. FIG. 11 is a timing chart of the control circuit according to the second embodiment.

  Hereinafter, embodiments of an evaluation apparatus and an evaluation method disclosed in the present application will be described in detail based on the drawings. In addition, the evaluation apparatus and evaluation method which this application discloses are not limited by the following examples. In the following embodiments, a mobile phone evaluation device will be described as an example of an evaluation device. However, this may be an evaluation device for another wireless communication terminal, for example, an evaluation device for a PDA.

  FIG. 1 is an overall view of an evaluation system for evaluating mobile phones. Here, the overall operation of the mobile phone evaluation system will be briefly described with reference to FIG. As shown in FIG. 1, the evaluation system includes a mobile phone evaluation device 1 and a pseudo base station 2.

  The mobile phone evaluation device 1 and the pseudo base station 2 are connected by, for example, a coaxial cable 3. Specifically, the coaxial cable 3 is connected to the antenna end 4 of the mobile phone evaluation device 1. The mobile phone evaluation device 1 and the pseudo base station 2 perform pseudo wireless communication with each other via the coaxial cable 3.

  A mobile phone evaluation apparatus 1 according to the present embodiment includes an antenna end 4, a control circuit 10, a DBB-LSI 11, and an RF-LSI 12.

  The RF-LSI 12 receives input of signals such as data and control commands from the pseudo base station 2 by pseudo wireless communication via the coaxial cable 3. The RF-LSI 12 converts the received signal into a digital baseband signal. Then, the RF-LSI 12 outputs a baseband signal to the DBB-LSI 11.

  Further, the RF-LSI 12 receives input of transmission data from the DBB-LSI 11. The RF-LSI 12 converts the received transmission data into an analog radio signal and transmits the analog radio signal to the pseudo base station 2 via the coaxial cable 3 as a pseudo radio signal.

  Further, the RF-LSI 12 receives an input of a command for transmitting a control command or the like from the DBB-LSI 11. Then, the RF-LSI 12 executes processing according to the input command. Here, the RF-LSI 12 transmits a signal to the pseudo base station 2 if necessary in the processing according to the input command. The RF-LSI 12 is an example of an “RF unit”.

  The DBB-LSI 11 receives a baseband signal input from the RF-LSI 12. Then, the DBB-LSI 11 performs processing such as data demodulation on the received baseband signal.

  Further, the DBB-LSI 11 outputs a command to the RF-LSI 12 as necessary. For example, when the DBB-LSI 11 receives a retransmission instruction from the RF-LSI 12, the DBB-LSI 11 retransmits the command.

  Furthermore, the DBB-LSI 11 may store a history of operations of the RF-LSI 12, for example. The worker who is evaluating the operation of the mobile phone can grasp whether or not the RF-LSI 12 is operating normally by referring to this history. The RF-LSI 12 is an example of a “baseband processing unit”.

  The control circuit 10 inverts the logic of the designated bit among the bits included in the signal output from the DBB-LSI 11 to the RF-LSI 12. The configuration and operation of the control circuit 10 will be described in detail later. The control circuit 10 is an example of a “control unit”.

  The pseudo base station 2 transmits signals such as data and control commands to the mobile phone evaluation device 1 using pseudo wireless communication via the coaxial cable 3. Then, the pseudo base station 2 receives a response to the control command transmitted by itself from the RF-LSI 12 via the coaxial cable 3. For example, the pseudo base station 2 determines whether or not the operations of the DBB-LSI 11 and the RF-LSI 12 arranged in the mobile phone evaluation device 1 are normally performed from the response received from the mobile phone evaluation device 1. .

  The storage of the history of the operation of the RF-LSI 12 by the DBB-LSI 11 and the determination of the operation of the RF-LSI 12 by the pseudo base station 2 are examples of “acquisition of behavior information of the RF-LSI”. For example, the DBB-LSI 11 and the pseudo base station 2 are examples of the “information acquisition unit”.

  Next, an outline of the configuration and operation of the mobile phone evaluation apparatus 1 according to the present embodiment will be described with reference to FIG. FIG. 2 is a circuit configuration diagram illustrating an outline of the mobile phone evaluation apparatus according to the first embodiment.

  The DBB-LSI 11 has an LVDS transmission circuit 13. The DBB-LSI 11 has an output terminal 14.

  The LVDS transmission circuit 13 has a positive signal output terminal 301 and a negative signal output terminal 302. The positive side signal output terminal 301 outputs a positive side differential output signal. Hereinafter, the positive differential output signal is referred to as Output-P (Positive). The negative signal output terminal 302 outputs a negative differential output signal. Hereinafter, the negative differential output signal is referred to as Output-N (Negative). This positive differential input signal corresponds to the “first signal”. The negative differential input signal is an example of the second signal.

  When SW (Switch) 16 to be described later is switched to a transmission path connecting the positive signal output terminal 301 and the positive signal input terminal 501, Output-P is the positive signal input terminal as the positive differential input signal. 501 is input.

  Output-P is branched from the transmission path and input to the positive input terminal 101 of the control circuit 10.

  Output-N is input to the negative-side signal input terminal 502 as a negative-side differential input signal. Output-N is branched from the transmission path and input to the negative input terminal 102 of the control circuit 10.

  The output terminal 14 is a general-purpose port that outputs a control command or the like. The DBB-LSI 11 outputs a trigger signal from the output terminal 14 toward the control circuit 10. When SW 17 described later is ON, the trigger signal output from the output terminal 14 is input to the control signal input terminal 103 of the control circuit 10. The DBB-LSI 11 has previously received input of command information to be tested. When the DBB-LSI 11 outputs a command other than the test target command as a trigger signal, the DBB-LSI 11 outputs an L logic signal from the output terminal 14, and outputs the test target command from the output terminal 14. Output logic signals.

  The RF-LSI 12 has an LVDS receiving circuit 15.

  The LVDS receiver circuit 15 has a positive signal input terminal 501 and a negative signal input terminal 502. The positive side signal input terminal 501 receives an input of a positive side differential input signal. Hereinafter, the positive differential input signal may be referred to as Input-P (Positive). The positive-side signal input terminal 501 receives Output-P as Input-P when SW16 described later is switched to a transmission path connecting the positive-side signal output terminal 301 and the positive-side signal input terminal 501. Further, when the SW 16 is switched to the Vdd (Drain Voltage) side, the positive side signal input terminal 501 receives a signal having a power source voltage as Input-P. Further, when the SW 16 is switched to the GND (Ground: reference voltage) side, the positive side signal input terminal 501 receives a signal having a reference voltage as Input-P.

  The negative signal input terminal 502 receives a negative differential input signal. Hereinafter, the negative differential input signal may be referred to as Input-N (Negative). Input-N matches Output-N.

  The LVDS receiving circuit 15 calculates the difference between the potential of the signal input to the positive signal input terminal 501 and the potential of the signal input to the negative signal input terminal 502. The LVDS receiving circuit 15 determines that the logic of the corresponding bit is H when the difference is positive, and sets the logic of the corresponding bit as L when the difference is negative. Then, the LVDS reception circuit 15 acquires a command composed of bits having the determined logic as a command output from the DBB-LSI 11.

  The control circuit 10 includes a positive input terminal 101, a negative input terminal 102, a control signal input terminal 103, a first control signal output terminal 104, a second control signal output terminal 105, a selection logic input terminal 106, and an inverted bit input terminal. 107. Hereinafter, a signal input to the positive input terminal 101 may be represented as “InP”. In addition, a signal input to the negative input terminal 102 may be represented as “InN”. In addition, a signal input to the control signal input terminal 103 may be represented as “Cnt_En”. In addition, a signal output from the first control signal output terminal 104 may be represented as “Cnt1”. In addition, a signal output from the second control signal output terminal 105 may be represented as “Cnt2”. In addition, a signal input to the selection logic input terminal 106 may be expressed as “Cnt_sel”.

  The positive input terminal 101 receives the output of Output-P from the positive signal output terminal 301. This signal corresponds to InP.

  The negative side input terminal 102 receives the output of Output-N from the negative side signal output terminal 302. This signal corresponds to InN.

  The control signal input terminal 103 receives an input of a trigger signal from the output terminal 14 when the SW 17 is closed. This signal corresponds to Cnt_sel. For example, the control signal input terminal 103 receives an L logic signal when the DBB-LSI 11 outputs a command other than the test target. On the other hand, the control signal input terminal 103 receives an input of an H logic signal when the DBB-LSI 11 outputs a command to be tested.

  The inverted bit input terminal 107 has n input terminals B1 to Bn. Here, n is a positive integer and matches the number of bits of the command to be tested. For example, when testing an 8-bit command, n = 8. The inversion bit input terminal 107 receives a signal specifying a bit to be inverted. Here, an example of a signal that is input when the third bit of the command is inverted will be described. In this case, H logic is input to the input terminals B1, B2, and B4 to Bn. Then, L logic is input to the input terminal B3.

  The selection logic input terminal 106 receives an instruction for selecting which of the H logic and the L logic is selected as the logic generated by bit inversion. Hereinafter, a logic generated by inverting a bit out of H logic or L logic is referred to as “selection logic”. The selection logic being H logic means that the L logic is inverted and changed to H logic. The fact that the selection logic is L logic indicates that the H logic is inverted and changed to L logic.

  The control circuit 10 acquires Output-P, Output-N, and a trigger signal input to the positive input terminal 101, the negative input terminal 102, and the control signal input terminal 103. In addition, the control circuit 10 acquires signals specifying the selection logic and the bit to be inverted, which are input to the selection logic input terminal 106 and the inverted bit input terminal 107. Then, the control circuit 10 uses the acquired signal to generate a one-pulse waveform signal that is a signal for switching the SW 16 at a position corresponding to the bit designated as the bit to be inverted in Output-P. The specific generation of the one-pulse waveform signal by the control circuit 10 using Output-P, Output-N, a trigger signal, and a signal designating a bit to be inverted will be described in detail later.

  When the H logic is selected as the logic generated by bit inversion, the first control signal output terminal 104 outputs a one-pulse waveform signal corresponding to the designated bit to be inverted to the SW 16.

  When the L logic is selected as the logic generated by bit inversion, the second control signal output terminal 105 outputs a one-pulse waveform signal corresponding to the bit to be inverted to SW6.

  The DBB-LSI 11 and an RF-LSI 12 to be described later are connected by a transmission path for transmitting a positive differential input signal and a transmission path for transmitting a negative differential input signal. The transmission path for transmitting the positive differential input signal and the transmission path for transmitting the negative differential input signal are connected by a terminating resistor 18.

  The SW 16 is a switch for switching each signal path connecting the positive signal output terminal 301, Vdd or GND and the positive signal input terminal 501. When there is no input of a one-pulse waveform signal from either the first control signal output terminal 104 or the second control signal output terminal 105, the SW 16 is a signal path connecting the positive signal output terminal 301 and the positive signal input terminal 501. Switch.

  Further, when the SW16 receives a one-pulse waveform signal from the first control signal output terminal 104, the SW16 is a signal that connects Vdd and the positive-side signal input terminal 501 while a pulse is generated in the one-pulse waveform signal. Switch to the path. As a result, when Output-P passes, SW 16 sends a signal from Vdd to positive-side signal input terminal 501 during a bit that matches the pulse of the one-pulse waveform signal among the bits included in Output-P. That is, the voltage of the designated bit of Output-P rises to the power supply voltage.

  Further, when the SW16 receives the input of the one-pulse waveform signal from the second control signal output terminal 105, the signal connecting the GND and the positive signal input terminal 501 while the pulse is generated in the one-pulse waveform signal. Switch to the path. As a result, when Output-P passes, SW 16 sends the signal from GND to positive-side signal input terminal 501 during the bit that matches the pulse of the one-pulse waveform signal among the bits included in Output-P. That is, the voltage of the designated bit of Output-P falls to the reference signal.

  That is, by switching SW16, Output-P in which the voltage at the designated bit position is changed to the power supply voltage or the reference voltage is input to the positive signal input terminal 501 as Input-P.

  Here, with reference to FIG. 3, the switching of the signal path of the SW 16 will be described together. FIG. 3 is a diagram illustrating a switch logic table of SW16. The SW 16 performs switching according to the logic represented by the switch logic table 200 of FIG. The column of Cnt1 in the switch logic table 200 represents a signal output from the first control signal output terminal 104. When the column of Cnt1 is 0, an L logic signal is input from the first control signal output terminal 104 to the SW16, and when it is 1, an H logic signal is input from the first control signal output terminal 104 to the SW16. It is expressed that. The column of Cnt2 in the switch logic table 200 represents a signal output from the second control signal output terminal 105. When the column of Cnt2 is 0, an L logic signal is input from the second control signal output terminal 105 to the SW16, and when it is 1, an H logic signal is input from the second control signal output terminal 105 to the SW16. It is expressed that. As shown in the switch logic table 200, when an L logic signal is input from both the first control signal output terminal 104 and the second control signal output terminal 105, the SW 16 is connected to the positive signal output terminal 301. The transmission line is switched to a transmission path for transmitting the signal to the positive signal input terminal 501. When an H logic signal is input only from the first control signal output terminal 104, the SW 16 switches to a signal path connecting Vdd and the positive signal input terminal 501. When an H logic signal is input only from the second control signal output terminal 105, the SW 16 switches to a signal path connecting the GND and the positive signal input terminal 501.

  The SW 17 is a switch for switching ON / OFF of a signal path connecting the output terminal 14 and the control signal input terminal 103. The SW 17 receives in advance an ON / OFF instruction from a worker for a signal path connecting the output terminal 14 and the control signal input terminal 103. When receiving an ON instruction, the SW 17 closes the switch. When receiving an OFF instruction, the SW 17 opens the switch.

  Here, with reference to FIG. 4, the correspondence between the signals in this embodiment and the correspondence between the logic of the transmission command output from the DBB-LSI and the logic of the reception command acquired by the RF-LSI will be described. FIG. 4 is a timing chart of the control circuit according to the first embodiment. FIG. 4 shows the passage of time toward the right toward the page.

  The positive-side signal output terminal 301 outputs a signal having the voltage represented by the graph 201 as Output-P. Further, as Output-N, the negative signal output terminal 302 outputs a signal having a voltage represented by the graph 202. A potential represented by a dotted line 203 represents a high potential in the LVDS of this embodiment, and is 1.1 V in this embodiment. Further, the potential represented by the dotted line 204 represents a low potential in the LVDS of this embodiment, and is 0.7 V in this embodiment. The bit of the part where the graph 201 is at a higher potential than the graph 202 is H logic, and the bit of the part where the graph 202 is at a higher potential than the graph 201 represents L logic. That is, FIG. 4 shows that L logic and H logic are alternately output. The BDD-LIS output logic at the upper stage toward the page of Table 211 represents the logic of the command (hereinafter referred to as “transmission command”) that is the basis of Output-P and Output-N. Here, the logic at the left end in the table 211 indicates the logic of the 0th bit.

  Here, it is assumed that the first bit and the fourth bit are designated as bits to be inverted. The first bit of the transmission command is L as shown in Table 211. Therefore, in order to invert the first bit, the potential of the bit of Output-P is set higher than 1.1V. That is, the potential of the first bit of Output-P is set to the power supply voltage. The fourth bit of the transmission command is H as shown in Table 211. Therefore, in order to invert the fourth bit, the potential of the bit of Output-P is made lower than 0.7V. That is, the potential of the first bit of Output-P is set to the reference voltage. In this case, an instruction to invert the first bit and the fifth bit is input to the inverted bit input terminal 107 of the control circuit 10. That is, L logic is input to the input terminal B1 and the input terminal B4 of the inverting bit input terminal 107. Further, the selection logic input terminal 106 of the control circuit 10 receives the selection of the H logic as the selection logic of the first bit, and the selection of the L logic as the selection logic of the fourth bit.

  The first control signal output terminal 104 outputs a one-pulse waveform signal (Cnt1) in which a pulse is generated at the position of the first bit as shown in the graph 205. The second control signal output terminal 105 outputs a one-pulse waveform signal (Cnt2) that generates a pulse at the position of the fourth bit as shown in the graph 206.

  When the one-pulse waveform signal of the graph 205 is input from the first control signal output terminal 104, the SW 16 is switched to the Vdd side during the first bit in which a pulse is generated. Then, when the one-pulse waveform signal of the graph 206 is input from the second control signal output terminal 105, the SW 16 is switched to the GND side during the fourth bit in which the pulse is generated.

  As a result, the signal input to the positive signal input terminal 501 as Input-P becomes a signal having a voltage represented by the graph 207. Here, the voltage represented by the dotted line 209 is a power supply voltage, and the voltage represented by the dotted line 210 is a reference voltage (GND). As described above, in Input-P in this case, the voltage of the first bit is the power supply voltage (Vdd), and the power supply voltage of the fourth bit is the reference voltage.

  On the other hand, Output-N is directly input to the negative-side signal input terminal 502 as Input-N, and therefore has a voltage in which a high potential and a low potential are repeated as in the graph 208 as in the graph 208.

  The voltage of the first bit of the graph 207 is higher than the voltage of the first bit of the graph 208. Therefore, the first bit of the command acquired by the RF-LSI 12 (hereinafter referred to as a received command) is H logic. The voltage of the fourth bit in the graph 207 is lower than the voltage of the fourth bit in the graph 208. Therefore, the fourth bit of the received command is L logic. In addition, the logic of bits other than the first and fourth bits of the received command matches the logic of the bit of the corresponding transmission command. That is, the logic of each bit of the received command is the lower RF-LSI input logic toward the page of Table 211. As can be seen from Table 2, at the positions of the column 212 representing the first bit and the column 213 representing the fourth bit, the logic of the reception command is inverted with respect to the logic of the transmission command.

  Next, the circuit configuration of the control circuit 10 will be described with reference to FIGS. FIG. 5 is a circuit configuration diagram of a circuit that generates a one-pulse waveform signal in the control circuit. FIG. 6 is a circuit configuration diagram of a circuit that controls the switch using the one-pulse waveform signal in the control circuit. First, a circuit for generating a one-pulse waveform signal will be described with reference to FIG.

  The control circuit 10 has a circuit as shown in FIG. A CDR (Clock Data Recovery) 120 is connected to a positive input terminal 101 and a negative input terminal 102. The CDR 120 acquires Output-P input to the positive input terminal 101 and Output_N input to the negative input terminal 102. Then, the CDR 120 acquires the clock superimposed on the Output-P and the Output-N from the Output-P and the Output-N. The CDR 120 is not particularly limited as long as it is a circuit that acquires a clock superimposed on data, such as a phase synchronization method or a phase interpolation method. Then, the CDR 120 outputs the acquired clock to D-FF (Flip Flop) 121 (1) to 121 (n).

  Then, D-FFs 121 (1) to 121 (n) are arranged in series at the subsequent stage of the CDR 120 as shown in FIG. n is a positive integer and matches the number of bits of the command to be tested. That is, if the command to be tested is 8 bits, n = 8. The outputs of the D-FFs 121 (1) to 121 (n) are initialized to a low potential. That is, the D-FFs 121 (1) to 121 (n) output L logic unless an H logic signal is input. The D-FFs 121 (1) to 121 (n) receive clock input from the CDR 120. The D-FFs 121 (1) to 121 (n) output signals at the rising timing of the input clock.

  A case where the first clock is input from the CDR 120 will be described. The D-FF 121 (1) receives a signal having a power supply voltage (Vdd) from the line 122. Since the D-FF 121 (1) receives a signal having a power supply voltage, it outputs an H logic signal. At this time, since the D-FF 121 (2) to D-FF 121 (n) do not receive any signal input, they output an L logic signal that is an initial value.

  Therefore, in the first clock, the XOR circuit 123 (1) receives an input of an H logic signal from the D-FF 121 (1) and receives an input of an L logic signal from the D-FF 121 (2). Therefore, the XOR circuit 123 (1) outputs an H logic signal by taking an exclusive OR. In the first clock, each of the XOR circuits 123 (2) to 123 (n) receives two L logic signals. Therefore, the XOR circuits 123 (2) to 123 (n) output an L logic signal at the rising timing of the clock by taking an exclusive OR.

  Next, the case where the second clock is input from the CDR 120 will be described. The D-FF 121 (1) receives a signal having a power supply voltage from the line 122 and outputs an H logic signal. Since the D-FF 121 (2) receives the input of the H logic signal from the D-FF 121 (1), the D-FF 121 (2) outputs the H logic signal. At this time, since the D-FF 121 (3) to D-FF 121 (n) do not receive any signal input, they output an L logic signal that is an initial value.

  Therefore, in the second clock, the XOR circuit 123 (1) receives an input of an H logic signal from the D-FF 121 (1) and receives an input of an H logic signal from the D-FF 121 (2). Therefore, the XOR circuit 123 (1) outputs an L logic signal by taking an exclusive OR. The XOR circuit 123 (2) receives an input of an H logic signal from the D-FF 121 (2) and receives an input of an L logic signal from the D-FF 121 (3). Therefore, the XOR circuit 123 (2) outputs an H logic signal by taking an exclusive OR. In the second clock, the XOR circuits 123 (3) to 123 (n) all receive two L logic signals. Therefore, the XOR circuits 123 (3) to 123 (n) output an L logic signal at the rising timing of the clock by taking an exclusive OR.

  Next, the case where the third clock is input from the CDR 120 will be described. The D-FF 121 (1) receives a signal having a power supply voltage from the line 122 and outputs an H logic signal. Since the D-FF 121 (2) receives the input of the H logic signal from the D-FF 121 (1), the D-FF 121 (2) outputs the H logic signal. Further, since the D-FF 121 (3) receives the input of the H logic signal from the D-FF 121 (2), the D-FF 121 (3) outputs the H logic signal. At this time, since the D-FF 121 (4) to D-FF 121 (n) do not receive the input of the signal, the D-FF 121 (4) to D-FF 121 (n) outputs an L logic signal which is an initial value.

  Therefore, in the third clock, the XOR circuit 123 (1) receives an input of an H logic signal from the D-FF 121 (1) and receives an input of an H logic signal from the D-FF 121 (2). Therefore, the XOR circuit 123 (1) outputs an L logic signal by taking an exclusive OR. The XOR circuit 123 (2) receives an input of an H logic signal from the D-FF 121 (2) and receives an input of an H logic signal from the D-FF 121 (3). Therefore, the XOR circuit 123 (1) outputs an L logic signal by taking an exclusive OR. The XOR circuit 123 (3) receives an input of an H logic signal from the D-FF 121 (3) and receives an input of an L logic signal from the D-FF 121 (4). Therefore, the XOR circuit 123 (2) outputs an H logic signal by taking an exclusive OR. In the third clock, the XOR circuits 123 (4) to 123 (n) all receive two L logic signals. Therefore, the XOR circuits 123 (4) to 123 (n) output an L logic signal at the rising edge of the clock by calculating an exclusive OR.

  In this manner, the XOR circuits 123 (1) to 123 (n) repeat the output of logic signals until the nth clock is input from the CDR 120. Each XOR circuit 123 (j) (an integer satisfying 1 ≦ j ≦ n) outputs a signal that is H logic only when the j-th clock is input. That is, the XOR circuit 123 (j) outputs a one-pulse waveform signal in which a pulse is generated at the j-th bit. In other words, the one-pulse waveform signal in which a pulse is generated in the j-th bit is a signal in which the j-th bit is H logic and the other bits are L logic. Here, a one-pulse waveform signal in which a pulse is generated in the first bit output from the XOR circuit 123 (1) is defined as a signal (a). A one-pulse waveform signal in which a pulse is generated in the second bit output from the XOR circuit 123 (2) is referred to as a signal (b). A one-pulse waveform signal in which a pulse is generated in the third bit output from the XOR circuit 123 (3) is referred to as a signal (c). Further, a one-pulse waveform signal in which a pulse is generated in the nth bit output from the XOR circuit 123 (n) is referred to as a signal (n).

  Next, the control of the SW 16 by the control circuit 10 using the one-pulse waveform signal will be described with reference to FIG. Here, a case where the third bit of the transmission command is inverted will be described. That is, an L logic signal is input to the input terminal B3, and an H logic signal is input to the input terminals B1, B2, and B4 to Bn.

  The OR circuit 131 (j) receives the signal output from the XOR circuit 123 (j). For example, the OR circuit 131 (1) receives the signal (a) from the XOR circuit 123 (1). The OR circuit 131 (2) receives the signal (b) from the XOR circuit 123 (2). The OR circuit 131 (3) receives the signal (c) from the XOR circuit 123 (3). Further, the OR circuit 131 (n) receives the signal (n) from the XOR circuit 123 (n).

  Further, the OR circuit 131 (j) receives a signal input to the input terminal Bj. That is, the OR circuit 131 (3) receives an L logic signal input to the input terminal B3. Each of the OR circuits 131 (1), 131 (2) and 131 (4) to 131 (n) receives an H logic signal.

  Then, the OR circuit 131 (j) outputs a logical sum of the input signals. That is, the OR circuit 131 (3) receives the input of the L logic signal from the input terminal B3, and receives the input of the signal (c) in which the third bit is H, so that the third bit is The signal (c) which is H is output.

  On the other hand, the OR circuits 131 (1), 131 (2) and 131 (4) to 131 (n) receive the input of the H logic signal from the input terminals B1, B2 and B4 to Bn, respectively. , Always output an H logic signal. Thus, the one-pulse waveform signal is output only from any one of the OR circuits 131 (1) to 131 (n).

  The AND circuit 132 receives an input of the signal (c) which is a one-pulse waveform signal from the OR circuit 131 (3). The AND circuit 132 receives an input of an H logic signal from the OR circuits 131 (1), 131 (2) and 131 (4) to 131 (n). The AND circuit 132 takes a logical product and generates a signal. Here, when the bit of the signal (c) is L logic, all the other inputs are H logic, so the AND circuit 132 outputs an L logic signal. Further, when the bit of the signal (c) is H logic, all the other inputs are H, so that the AND circuit 132 outputs a signal of H logic. That is, the AND circuit 132 outputs the same one-pulse waveform signal as the signal in which the third bit is H logic and the other bits are L logic, that is, the signal (c). Thus, the AND circuit 132 receives the input of the one-pulse waveform signal from any one of the OR circuits 131 (1) to 131 (n), and outputs the same signal as the input one-pulse waveform signal.

  The AND circuit 133 receives the input one-pulse waveform signal from the AND circuit 132. Here, the AND circuit 133 receives from the AND circuit 132 an input of a one-pulse waveform signal in which a pulse is generated in the third bit. Further, the AND circuit 133 receives the trigger signal (Cont_En) input to the control signal input terminal 103 of the control circuit 10. Here, the AND circuit 133 receives an input of an H logic signal when a designated command is output as a trigger signal, and receives an input of an L logic signal otherwise. The AND circuit 133 outputs the same signal as the one-pulse waveform signal input from the AND circuit 132 when an H logic signal is input to the control signal input terminal 103. When an L logic signal is input to the control signal input terminal 103, the AND circuit 133 outputs an L logic signal. Further, the trigger signal (Cnt_En) input to the control signal input terminal 103 is suspended by Vdd and is subjected to a weak pull-up. That is, in the state where the trigger signal is not input to the control signal input terminal 103, an H logic signal is input to the AND circuit 133.

  The switch 134 is a switch that switches the signal path of the output of the AND circuit 133 to either the first control signal output terminal 104 or the second control signal output terminal 105. The switch 134 receives in advance an input of a selection logic for changing the L logic of the designated bit to the H logic or the H logic to the L logic. When the switch 134 receives an input of a selection logic for changing the L logic to the H logic, the switch 134 switches the signal path of the output of the AND circuit 133 to the first control signal output terminal 104 side. Further, the switch 134 switches the signal path of the output of the AND circuit 133 to the second control signal output terminal 105 side when receiving the input of the selection logic for changing the H logic to the L logic. A weak pull-down is applied to any signal from the switch 134 toward the first control signal output terminal 104 and the second control signal output terminal 105. That is, outputs from the unused side of the first control signal output terminal 104 and the second control signal output terminal 105 are set to L logic.

  For example, a case where a logic for changing the L logic to the H logic is designated as the selection logic of the third bit will be described. In this case, the switch 134 is switched to the first control signal output terminal 104 side. Then, a one-pulse waveform signal in which a pulse is generated in the third bit output from the AND circuit 133 is output from the first control signal output terminal 104.

  Accordingly, the SW 16 receives from the first control signal output terminal 104 an input of a one-pulse waveform signal in which a pulse is generated in the third bit. In this case, since the L logic is input in a portion other than the pulse of the one-pulse waveform signal, Cnt1 in the switch logic table 200 in FIG. Since the H logic is input at the portion where the pulse of the one-pulse waveform signal is generated, Cnt1 in the switch logic table 200 is 1 during that period. On the other hand, the SW 16 receives an L logic signal from the second control signal output terminal 104. That is, the column of Cnt2 in the switch logic table 200 is always in the 0 state. Therefore, except for the third bit of Output-P, Cnt1 in the switch logic table 200 is 0 and Cnt2 is 0, so that SW16 is connected to the transmission line. In the third bit of Output-P, since Cnt1 of the switch logic table 200 is 1 and Cnt2 is 0, SW16 is switched to the Vdd side. As a result, the third bit of Output-P is changed to a signal having the power supply voltage.

  Here, the correspondence of each signal in the control circuit will be described with reference to FIG. FIG. 7 is a timing chart of signals input to the control circuit according to the first embodiment and generated signals. FIG. 7 shows the passage of time toward the right toward the page. Here, a case where the command to be tested is n bits and the third bit of the command is changed from L logic to H logic will be described. FIG. 7 shows a case where the test target command is a transmission command.

  First, the positive input terminal 101 receives an input of a signal having a voltage represented by the graph 220 from the positive signal output terminal 301 as Output-P. Further, the negative input terminal 102 receives an input of a signal having a voltage represented by the graph 221 from the negative signal output terminal 302 as Output-N.

  Then, the CDR 120 creates a clock (CLK) represented by the graph 222 from Output-P represented by the graph 220 and Output-N represented by the graph 221.

  The XOR circuit 123 (1) is output using outputs from the D-FFs 121 (1) to 121 (n) when a signal having a clock and a power supply voltage input from the line 122 are received. ) To 123 (n) generate a one-pulse waveform signal. Here, the XOR circuit 123 (1) generates a signal (a) in which only the first bit represented by the graph 223 is H logic. Further, the XOR circuit 123 (2) generates a signal (b) in which only the second bit represented by the graph 224 is H logic. In addition, the XOR circuit 123 (3) generates a signal (c) in which only the third bit represented by the graph 225 is H logic. Further, the XOR circuit 123 (n) generates a signal (n) in which only the nth bit represented by the graph 226 is H logic.

  Further, an H logic signal indicated by a graph 227 is input to the input terminal B1. Here, in the graph 227, the upper line of the two lines toward the paper surface represents the high potential of LVDS, and the lower line represents the low potential of LVDS. The solid line in the graph 227 represents the voltage of the signal input to the input terminal B1. (The graphs 228, 229, 230, 232, and 234 described below also represent signals in the same manner as the graph 227.) Similarly, the input terminals B2 and B4 to Bn include the graph 228 and the graph 230, respectively. An H logic signal represented by the above is input. An L logic signal represented by the graph 229 is input to the input terminal B3.

  One-pulse waveform signals represented by graphs 223 to 226 are input to OR circuits 131 (1) to 131 (n), respectively. In addition, signals represented by graphs 227 to 230 are input to the OR circuits 131 (1) to 131 (n), respectively. As a result, the OR circuit 131 (3) outputs the signal (c) represented by the graph 225. The OR circuits 131 (1), 131 (2) and 131 (4) to 131 (n) output H logic signals. Then, the AND circuit 132 receives the signals output from the OR circuits 131 (1) to (n). Then, the AND circuit 132 outputs a signal (c) represented by the graph 225. Further, the control signal input terminal 103 receives an input of a signal (Cnt_En) that becomes H logic from the rising edge of the first clock as shown in the graph 231. The AND circuit 133 receives the signal indicated by the graph 231 and outputs the signal (c) indicated by the graph 225.

  The switch 134 receives a signal specifying the selection logic represented by the graph 232. In the graph 232, since an H logic signal that is a signal for changing the L logic to the H logic is input, the switch 134 switches the path to the first control signal output terminal 104 side. The switch 134 receives the input of the signal (c) represented by the graph 225 from the AND circuit 133. Then, the switch 134 outputs the signal (c) represented by the graph 225 from the first control signal output terminal 104. As a result, the signal output from the first control signal output terminal 104 becomes the signal Cnt1 represented by the graph 233. The graph 233 has the same waveform as the graph 225, and the third bit is H logic. Further, an L logic signal as represented by a graph 234 is output from the second control signal output terminal 105.

  The SW 16 receives the signals represented by the graph 233 and the graph 234, and switches the path to Vdd by the third bit of Output-P. As a result, the signal input to the positive signal input terminal 501 is Input-P represented by the graph 235. In Input-P, as shown by the graph 235, the voltage of the third bit is the power supply voltage.

  The signal input to the negative side signal input terminal 502 is Input-N represented by the graph 236. The signal Input-N represented by the graph 236 matches the signal Output-N represented by the graph 221.

  As represented by the graph 235 and the graph 236, the third bit Input-P has a higher potential than the third bit Input-N. For this reason, the LVDS reception circuit 15 acquires a command obtained by inverting the third bit of the transmission command as a reception command.

  Next, the operation of the control circuit 10 will be further described with reference to FIG. FIG. 8 is a flowchart of the operation of the control circuit.

  Output-P and Output-N are input to the CDR 120 (step S101).

  Next, the CDR 120 generates a synchronous clock from Output-P and Output-N (step S102).

  The D-FF 121 (1) to D-FF 121 (n) and the XOR circuit 123 (1) to XOR circuit 123 (n) use n synchronous clocks generated by the CDR 120 and n pulses whose pulses are shifted bit by bit. A one-pulse waveform signal is generated (step S103).

  Next, the OR circuits 131 (1) to 131 (n) and the AND circuit 132 extract a one-pulse waveform signal having a pulse at the designated bit (step S104).

  The AND circuit 133 determines whether or not the SW 17 is ON based on whether or not a signal is input to the control signal input terminal 103 (step S105). When SW17 is OFF (No at Step S105), an AND logic 133 signal is output from the AND circuit 133, and the control of SW15 by the control circuit 10 ends.

  On the other hand, when SW17 is ON (Yes at step S105), the AND circuit 133 determines whether or not the command is a specified command depending on whether or not the signal Cnt_En input from the control signal input terminal 103 is H logic. (Step S106). If Cnt_En = H and the command is not designated (No at Step S106), the process proceeds to Step S109.

  On the other hand, if Cnt_En = H and the command is specified (Yes at Step S106), the AND circuit 133 outputs a one-pulse waveform signal having a pulse at the specified bit to the switch 134. Then, the switch 134 outputs a one-pulse waveform signal having a pulse at the designated bit from the designated signal path of either the first control signal output terminal 104 or the second control signal output terminal 105 (step S107).

  Then, the SW 16 receives inputs from the first control signal output terminal 104 and the second control signal output terminal 105, switches the signal path, and applies the voltage of the bit corresponding to the pulse position of the Output-P one-pulse waveform signal. Change (step S108). Then, the positive side input terminal 101 of the LVDS receiving circuit 15 receives Input-P input, which is a signal in which the voltage of the designated bit among the Output-P bits is changed.

  Then, the control circuit 10 determines whether all the commands output from the DBB-LSI 11 have been completed (step S109). If a command remains (No at Step S109), Steps S101 to S108 are repeated. On the other hand, if no command remains (Yes at step S109), the control circuit 10 ends the control of the SW16.

  As described above, the evaluation apparatus according to the present embodiment can invert a predetermined bit of a predetermined command transmitted by the DBB-LSI and input it to the RF-LSI. Thereby, it is possible to easily evaluate the behavior of the wireless communication terminal apparatus when the signal undergoes bit inversion.

  Here, in this embodiment, the case where the voltage of the designated bit of the positive differential signal is changed has been described, but this is to change the voltage of the designated bit of the negative differential signal. May be.

  FIG. 9 is a circuit configuration diagram illustrating an outline of the mobile phone evaluation apparatus according to the second embodiment. The mobile phone evaluation apparatus 1 according to the present embodiment performs the inversion of the logic of the designated bit by lowering the voltage of the designated bit of the positive differential input signal or the negative differential input signal. This is different from Example 1. 9, parts having the same reference numerals as those in FIG. 2 have the same functions unless otherwise specified.

  In the mobile phone evaluation apparatus according to the present embodiment, as shown in FIG. 9, the SW 19 is arranged on the transmission path for the positive differential input signal, and the SW 20 is arranged on the transmission path for the negative differential input signal.

  Also in this embodiment, the operation of the control circuit 10 is the same as that of the first embodiment. When the selection logic is H logic, that is, when L logic is changed to H logic, the control circuit 10 outputs a one-pulse waveform signal in which a pulse exists at the designated bit position from the first control signal output terminal 104. To do. When the selection logic is L logic, that is, when H logic is changed to L logic, the control circuit 10 outputs from the second control signal output terminal 105 a one-pulse waveform signal in which a pulse is present at the designated bit position. To do.

  The SW 19 is a switch that switches between a signal path for inputting Output-P output from the positive signal output terminal 301 to the positive signal input terminal 501 and a signal path for inputting a signal having a reference voltage to the positive signal input terminal 501. It is. The SW 19 receives the one-pulse waveform signal output from the second control signal output terminal 105. Then, the SW 19 switches to a signal path for inputting a signal having a reference voltage to the positive signal input terminal 501 while the pulse is generated. As a result, the voltage of the designated bit of Output-P drops to the reference voltage. If the designated bit in Output-P is at a high potential, the LVDS receiving circuit 15 determines that the logic of the bit is H logic if it is as it is. However, since the potential of Output-P is lower than Output-N when the voltage of the bit drops to the reference voltage, the LVDS reception circuit 15 determines that the logic of the bit is L logic.

  SW 20 is a switch for switching between a signal path for inputting Output-N output from negative-side signal output terminal 302 to negative-side signal input terminal 502 and a signal path for inputting a signal having a reference voltage to negative-side signal input terminal 502. It is. The SW 20 receives the one-pulse waveform signal output from the first control signal output terminal 104. Then, the SW 20 switches to a signal path for inputting a signal having a reference voltage to the negative side signal input terminal 502 while the pulse is generated. As a result, the voltage of the designated bit of Output-N drops to the reference voltage. If the designated bit in Output-N is at a high potential, the LVDS reception circuit 15 determines that the logic of the bit is L logic if it is as it is. However, since the potential of Output-N is lower than Output-P because the voltage of the bit drops to the reference voltage, the LVDS reception circuit 15 determines that the logic of the bit is H logic.

  Here, with reference to FIG. 10, the switching of the signal paths of SW19 and SW20 will be described together. FIG. 10 is a diagram illustrating a switch logic table of SW19 and SW20. The SW 19 performs switching according to the logic represented by the column Cnt2 in the switch logic table 600 of FIG. The column of Cnt1 in the switch logic table 600 represents a signal output from the first control signal output terminal 104. When the column of Cnt1 is 0, an L logic signal is input from the first control signal output terminal 104 to the SW20, and when it is 1, an H logic signal is input from the first control signal output terminal 104 to the SW20. It is expressed that. The Cnt2 row of the switch logic table 600 represents a signal output from the second control signal output terminal 105. When the Cnt2 column is 0, an L logic signal is input to the SW 19 from the second control signal output terminal 105, and when it is 1, an H logic signal is input to the SW 19 from the second control signal output terminal 105. It is expressed that. As shown in the switch logic table 600, when an L logic signal is input from the first control signal output terminal 104, the SW 20 transmits a signal from the negative signal output terminal 302 to the negative signal input terminal 502. Switch to signal path. When an H logic signal is input from the first control signal output terminal 104, the SW 20 is switched to GND. When a signal is input only from the first control signal output terminal 104, the SW 20 is switched to GND. Also, as shown in the switch logic table 600, when an L logic signal is input from the second control signal output terminal 105, the SW 19 sends the signal from the positive signal output terminal 301 to the positive signal input terminal 501. Switch to the transmission signal path. When an L logic signal is input from the first control signal output terminal 104, the SW 19 is switched to GND.

  Here, with reference to FIG. 11, the correspondence between each signal and the correspondence between the logic of the transmission command output from the DBB-LSI and the logic of the reception command acquired by the RF-LSI will be described. FIG. 11 is a timing chart of the control circuit according to the second embodiment. FIG. 11 shows the passage of time toward the right toward the page.

  As Output-P, the positive signal output terminal 301 outputs a signal having the voltage represented by the graph 241. Further, as Output-N, the negative signal output terminal 302 outputs a signal having a voltage represented by the graph 242. A potential represented by a dotted line 243 represents a high potential in the LVDS of this embodiment, and is 1.1 V in this embodiment. Further, the potential represented by the dotted line 244 represents a low potential in the LVDS of this embodiment, and is 0.7 V in this embodiment. A bit in a portion where the graph 241 has a higher potential than the graph 242 is H logic, and a bit in a portion where the graph 242 has a higher potential than the graph 241 represents L logic. That is, FIG. 11 shows that L logic and H logic are alternately output. The logic of the transmission command that is the basis of Output-P and Output-N is the same as the BDD-LSI output logic at the top of the table 250. Here, the logic at the left end of the table 250 indicates the logic of the 0th bit.

  Here, it is assumed that the first bit and the fourth bit are designated as bits to be inverted. The first bit of the transmission command is L as shown in Table 250. Therefore, in order to invert the first bit, the potential of the bit of Output-N is made lower than 0.7V. That is, the potential of the first bit of Output-N is set to the reference voltage (GND). The fourth bit of the transmission command is H as shown in Table 250. Therefore, in order to invert the fourth bit, the potential of the bit of Output-P is made lower than 0.7V. That is, the potential of the fourth bit of Output-P is set to the reference voltage. In this case, an instruction to invert the first bit and the fourth bit is input to the inverted bit input terminal 107 of the control circuit 10. That is, L logic is input to the input terminal B1 and the input terminal B4 of the inverting bit input terminal 107. Further, the selection logic input terminal 106 of the control circuit 10 receives the selection of the H logic as the selection logic of the first bit, and the selection of the L logic as the selection logic of the fourth bit.

  The first control signal output terminal 104 outputs a one-pulse waveform signal (Cnt1) that generates a pulse at the position of the first bit as shown in the graph 245. The second control signal output terminal 105 outputs a one-pulse waveform signal (Cnt2) that generates a pulse at the position of the fourth bit as shown in the graph 246.

  In response to the input of the one-pulse waveform signal of the graph 245 from the first control signal output terminal 104, the SW 20 switches to the GND side during the first bit in which the pulse is generated. Then, the input of the one-pulse waveform signal of the graph 246 is received from the second control signal output terminal 105, and the SW 20 switches to the GND side during the fourth bit in which the pulse is generated.

  As a result, the signal input to the positive-side signal input terminal 501 as Input-P becomes a signal having a voltage represented by the graph 247. In addition, a signal input to the negative side signal input terminal 502 as Input-N is a signal having a voltage represented by the graph 248. Here, the voltage represented by the dotted line 249 is a reference voltage (GND).

  In Input-P, the voltage of the first bit is the reference voltage. On the other hand, the first bit of Output-N is directly input to the negative side signal input terminal 502 as Input-N.

  In addition, the voltage of the fourth bit is the reference voltage for Input-N. On the other hand, the fourth bit of Output-P is directly input to the negative side signal input terminal 502 as Input-P.

  The voltage of the first bit of the graph 247 is lower than the voltage of the first bit of the graph 248. Therefore, the first bit of the received command acquired by the RF-LSI 12 is H logic. The voltage of the fourth bit in the graph 248 is higher than the voltage of the fourth bit in the graph 247. Therefore, the fourth bit of the received command is L logic. In addition, the logic of bits other than the first and fourth bits of the received command matches the logic of the bit of the corresponding transmission command. That is, the logic of each bit of the received command is the RF-LIS input logic shown at the bottom of the table 250. As can be seen from the table 250, the logic of the received command is inverted with respect to the logic of the transmitted command at the position of the column 251 representing the first bit and the column 252 representing the fourth bit.

  In the above description, SW19 and SW20 are switched to GND and the reference voltage is supplied. However, SW19 and SW20 may be switched to Vdd and the power supply voltage may be supplied. In that case, Cnt1 is input to SW19, and Cnt2 is input to SW20. Then, the L logic of the designated bit is changed to H logic by switching SW1, and the H logic of the designated bit is changed to L logic by switching SW2.

  As described above, the evaluation apparatus according to the present embodiment reduces the predetermined bit logic of the transmission command from the H logic to the L logic by dropping the voltage of the predetermined bit of the positive differential input signal to the reference voltage. The command converted into is a received command. In addition, by reducing the voltage of a predetermined bit of the positive side differential input signal to the reference voltage, a signal obtained by converting the logic of a predetermined bit of the transmission command from H logic to L logic is set as a reception command. That is, as in the first embodiment, a signal obtained by inverting a predetermined bit of a predetermined command transmitted by the DBB-LSI can be input to the RF-LSI as a received command. Thereby, it is possible to easily evaluate the behavior of the wireless communication terminal apparatus when the signal undergoes bit inversion. Further, since the same switch is inserted on both the positive side and the negative side, more accurate signal transmission can be performed as LVDS.

  Furthermore, in the above description, the inversion of specific bits has been described. However, the inversion test of all bits may be performed by sequentially switching the bits to be inverted and repeating the test. Further, the command to be specified may be automatically specified in accordance with the bit to be inverted so that the inversion of the predetermined bit of the predetermined command can be tested.

DESCRIPTION OF SYMBOLS 1 Mobile phone evaluation apparatus 2 Pseudo base station 3 Coaxial cable 4 Antenna end 10 Control circuit 11 DBB-LSI
12 RF-LSI
13 LVDS transmission circuit 14 Output terminal 15 LVDS reception circuit 16 SW
17 SW
18 Terminating resistor 19 SW
20 SW
101 Positive input terminal 102 Negative input terminal 103 Control signal input terminal 104 First control signal output terminal 105 Second control signal output terminal 106 Selection logic input terminal 107 Inverted bit input terminal 120 CDR
121 (1) to 121 (n) D-FF
123 (1) to 123 (n) XOR circuit 131 (1) to 131 (n) OR circuit 132 AND circuit 133 AND circuit 134 switch

Claims (6)

A baseband processing unit that outputs a first signal representing the logic of each bit included in the communication data by a potential;
An RF unit that determines the logic of each bit based on the potential of the input signal and acquires data having the logic;
A signal transmission path for inputting the first signal output from the baseband processing section to the RF section, and a predetermined voltage input path for inputting a signal having a predetermined voltage to the RF section instead of the first signal. A first switch for switching;
In response to designation of a predetermined bit included in the communication data, the potential of a portion where the predetermined bit of the first signal input to the RF unit is located by switching the first switch to the predetermined voltage input path Data obtained by inverting the logic of the predetermined bit of the communication data by receiving the input of the first signal in which the potential of the portion where the predetermined bit is located and the potential of the portion where the predetermined bit is changed is changed to a predetermined value Information acquisition unit for acquiring the behavior information of the RF unit,
An evaluation apparatus comprising: The controller is
A clock generation unit that generates a clock corresponding to the first signal from the first signal output from the baseband processing unit;
A one-pulse waveform generation unit that generates a one-pulse waveform having one pulse at a position corresponding to a specific bit included in the communication data using the clock generated by the clock generation unit, corresponding to each bit;
An extraction unit for extracting a one-pulse waveform corresponding to the predetermined bit from the one-pulse waveform generated by the one-pulse waveform generation unit;
The evaluation apparatus according to claim 1, further comprising: a switch switching unit that switches the first switch to the predetermined voltage input path while the pulse of the one-pulse waveform extracted by the extraction unit is generated. . The first switch has a path for inputting a ground voltage and a path for inputting a power supply voltage as a predetermined voltage input path,
The control unit switches the first switch to a path for inputting a ground voltage, thereby lowering a potential of a portion where the predetermined bit of the first signal is located, and setting the first switch to a path for inputting a power supply voltage. 3. The evaluation apparatus according to claim 1, wherein the potential of a portion where the predetermined bit of the first signal is located is increased by switching. The baseband processing unit has a transmission-side differential interface, and transmits a second signal representing the logic of each bit of the communication data according to a potential difference with the first signal,
The RF unit has a reception-side differential interface, receives the first signal and the second signal output from the baseband processing unit, and performs communication based on a potential difference between the first signal and the second signal. The evaluation device according to any one of claims 1 to 3, wherein each bit logic included in the data is determined. A signal transmission path for inputting the second signal output from the baseband processing section to the RF section, and a predetermined voltage input path for inputting a signal having a predetermined voltage to the RF section instead of the second signal. A second switch for switching,
The control unit receives the designation of a predetermined bit included in the communication data, and switches the first switch or the second switch to the predetermined voltage input path, whereby the first signal or the second signal is changed. Change the potential of the part where the predetermined bit is located to a predetermined value,
The information acquisition unit includes the first signal in which the potential of the portion where the predetermined bit is located is changed to a predetermined value or the second signal in which the potential of the portion where the predetermined bit is located is changed to a predetermined value. Obtaining the behavior information of the RF unit when obtaining data in which the logic of the predetermined bit of the communication data is inverted by receiving an input;
The evaluation apparatus according to claim 4. A first signal representing the logic of each bit included in the communication data by a potential is output from the DBB-LSI,
A signal transmission path for inputting the first signal to the RF-LSI in response to designation of a predetermined bit included in the communication data, and a predetermined voltage input for inputting a predetermined voltage to the RF-LSI instead of the first signal By switching the path, the potential of the portion where the predetermined bit of the first signal is located is changed to a predetermined value,
The first signal in which the potential of the portion where the predetermined bit is located is changed to a predetermined value is input to the RF-LSI,
Let the RF-LSI determine the logic of each bit included in the communication data based on the potential of the input first signal, and acquire data obtained by inverting the logic of the predetermined bit in the communication data. ,
The behavior information of the RF-LSI is obtained when data in which the logic of the predetermined bit of the communication data is inverted is obtained.

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