JP2012199610A - Crystal oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit in which a reverse voltage VTH, negative resistance -RL, and an oscillation frequency f0 are not influenced by a power source VDD, eliminates the need of adding a constant voltage circuit, has a low operating voltage, and can reduce a current flowing through a crystal oscillator.SOLUTION: In a crystal oscillation circuit 1, an NMOS inverter IVn, a feedback resistor Rf, and a crystal oscillator Qz are connected in parallel to one another, a capacitor CG is connected between an input of the NMOS inverter IVn and a power source VSS, and a capacitor CD is connected between an output of the NMOS inverter IVn and the power source VSS. The NMOS inverter IVn includes a constant current circuit In connected to a power source VDD and an n-type MOS transistor Tn connected between the constant current circuit In and the power source VSS.

Description

  The present invention relates to a crystal oscillation circuit, and in particular, an inverter, a feedback resistor connected in parallel to the inverter, a crystal resonator connected in parallel to the inverter, and one end of the crystal resonator and a power source. And a second capacitor connected between the other end of the quartz crystal resonator and a power source.

Conventionally, as the above-described crystal oscillation circuit, for example, the one shown in FIG. 6 has been proposed. As shown in FIG. 6A, the crystal oscillation circuit 1 includes a crystal resonator Qz and an oscillation circuit 2. The oscillation circuit 2, the CMOS inverter IVc as an inverter, a feedback resistor Rf, and a capacitor C _G and C _D of the first capacitor and the second capacitor, and a. The crystal resonator Qz, the CMOS inverter IVc, and the feedback resistor Rf are connected in parallel to each other. Then, the capacitor C _G has a CMOS inverter IVc input and power - are provided between the power supply VSS is a side. Capacitor C _D is provided between the output and the power supply VSS of the CMOS inverter IVc. Incidentally, capacitors C _G and C _D may be provided between the power supply VDD is a CMOS inverter IVc and power supply plus.

As shown in FIG. 6B, the CMOS inverter IVc is connected between the p-type MOS transistor Tp ₂ connected to the power supply VDD that is the positive side of the power supply, and between the MOS transistor Tp ₂ and the power supply VSS. N-type MOS transistor Tn ₂ . The MOS transistors Tp ₂ and Tn ₂ are connected in series between the power supply VDD and the power supply VSS. In the CMOS inverter IVc, when the input voltage Vin exceeds the inversion potential VTH, the MOS transistor Tp ₂ is turned off and the MOS transistor Tn ₂ is turned on so that the output voltage Vout becomes equal to the power supply VSS. On the other hand, when the input voltage Vin falls below the inversion potential VTH, the MOS transistor Tp ₂ is turned on, the MOS transistor Tn ₂ is turned off, and the output voltage Vout becomes equal to the power supply VDD.

The above-described CMOS inverter IVc is configured as shown in FIG. The MOS transistors Tp ₂ and Tn ₂ described above include a p-type silicon substrate Sp and an n-type silicon substrate Sn formed by ion implantation into the p-type silicon substrate Sp. The MOS transistor Tp ₂ includes p + regions Apd and Aps formed by ion-implanting high-concentration impurities into an n-type silicon substrate Sn, a gate oxide film f formed on the n-type silicon substrate Sn, and p + regions Apd, A drain electrode Mpd and a source electrode Mps provided on Aps, and a gate electrode Mpg provided on the gate oxide film f are provided. The p + regions Apd and Aps are provided to be spaced from each other in the length direction. The gate electrode Mpg is provided on the gate oxide film f between the p + regions Apd and Aps.

The n-type MOS transistor tn ₂ includes n + regions And and Ans formed by ion-implanting high-concentration impurities into a p-type silicon substrate Sp, a gate oxide film f formed on the p-type silicon substrate Sp, A drain electrode Mnd and a source electrode Mns provided on the n + regions And and Ans, and a gate electrode Mng provided on the gate oxide film f are provided. The n + regions And and Ads are provided to be spaced from each other in the length direction. The gate electrode Mng is provided on the gate oxide film f between the n + regions And and Ads.

The crystal resonator Qz and the oscillation circuit 2 configured as described above can be represented by an equivalent circuit as shown in FIG. That is, the crystal resonator Qz can be equivalent to a resistor R1, a capacitor C1, and an inductance L1 connected in series to each other, and a capacitor C0 connected in parallel to the resistor R1, the capacitor C1, and the inductance L1. The oscillation circuit 2 can be equivalent to a load resistor −RL and a capacitor CL connected in series with each other. The negative resistance -RL is represented by the following formula (1).
^{-RL = -gm / (ω 2 ·} C G · C D) ... (1)
gm is the mutual conductance of the MOS transistors Tp ₂ and Tn ₂ , which will be described later. ω is the oscillation angular frequency.

The crystal resonator Qz vibrates at a frequency determined by the inductance L1 and the capacitors C1 and C0. The minute vibration of the quartz resonator Qz generated by heat or the like is attenuated by the resistor R1 as it is. However, the micro vibration is amplified by the CMOS inverter IVc and supplied to the crystal resonator Qz again, whereby the oscillation of the crystal resonator Qz is maintained. That is, the resistor R1 is a resistor that attenuates vibration energy, whereas the negative resistance -RL of the oscillation circuit 2 is considered to be a resistor that supplements vibration energy. Therefore, as shown in the following formula (2), if the negative resistance -RL is larger than the resistance R1, the oscillation of the crystal unit Qz is continued.
| R1 | <| -RL | (2)

なお、Ｌ：ＭＯＳトランジスタのゲート長（図７）、Ｗ：ＭＯＳトランジスタのゲート幅（図７）、εox：ゲート酸化膜ｆの誘電率、ｔox：ゲート酸化膜ｆの膜厚、μ：チャネル中キャリア移動度、Ｖgs：ゲート−ソース間電圧、Ｖds：ドレイン−ソース間電圧、Ｖth：しきい値電圧（ドレイン−ソース間が導通し始める電圧）である。 However, the crystal oscillation circuit 1 using the above-described conventional CMOS inverter IVc has the following problems. First, there is a problem that the inverted voltage VTH of the CMOS inverter IVc varies depending on the power supply VDD. The inversion voltage VTH is obtained and viewed. The current Ids flowing between the drain and source of a general MOS transistor can be expressed by the following formulas (3) and (4).

L: gate length of MOS transistor (FIG. 7), W: gate width of MOS transistor (FIG. 7), εox: dielectric constant of gate oxide film f, tox: film thickness of gate oxide film f, μ: in channel Carrier mobility, Vgs: gate-source voltage, Vds: drain-source voltage, Vth: threshold voltage (voltage at which drain-source begins to conduct).

When the output of the CMOS inverter IVc is inverted, the currents Idsp and Idsn flowing in the MOS transistors Tp ₂ and Tn ₂ become equal as shown in the following equation (5).
Idsp = −Idsn (5)

なお、Ｌｐ：ＭＯＳトランジスタＴｐ₂のゲート長（図７）、Ｗｐ：ＭＯＳトランジスタＴｐ₂のゲート幅（図７）、Ｌｎ：ＭＯＳトランジスタＴｎ₂のゲート長（図７）、Ｗｎ：ＭＯＳトランジスタＴｎ₂のゲート幅（図７）、μｐ：ＭＯＳトランジスタＴｐ₂のチャンネル中キャリア移動度、μｎ：ＭＯＳトランジスタＴｎ₂のチャンネル中キャリア移動度、Ｖthp：ＭＯＳトランジスタＴｐ₂のしきい値電圧、Ｖthn：ＭＯＳトランジスタＴｎ₂のしきい値電圧である。 At this time, since the output Vout of the CMOS inverter IVc is in the range of Vin−Vthn ≦ Vout ≦ Vin− | Vthp |, the currents Idsp and Idsn at the time of inversion are expressed by the following equation (6) using the above equation (4). ), (7).

Lp: gate length of MOS transistor Tp ₂ (FIG. 7), Wp: gate width of MOS transistor Tp ₂ (FIG. 7), Ln: gate length of MOS transistor Tn ₂ (FIG. 7), Wn: MOS transistor Tn ₂ , Μp: carrier mobility in the channel of MOS transistor Tp ₂ , μn: carrier mobility in the channel of MOS transistor Tn ₂ , Vthp: threshold voltage of MOS transistor Tp ₂ , Vthn: MOS transistor it is a threshold voltage of Tn _2.

式（８）から明らかなように、電源ＶＤＤが変動すると反転電圧ＶＴＨも変動してしまう。 The input voltage Vin when the above equations (6) and (7) are substituted into the above equation (5) becomes the inverted voltage VTH. Therefore, the inversion voltage VTH can be expressed by the following formula (8).

As is clear from the equation (8), when the power supply VDD varies, the inversion voltage VTH also varies.

In addition, the crystal oscillation circuit 1 using the conventional CMOS inverter IVc has a problem that the negative resistance -RL varies depending on the power supply VDD. This negative resistance -RL is proportional to gm as shown in the above equation (1). Look for this gm. gm can be expressed by the following equation (9) using the mutual conductance gmp of the MOS transistor Tp _{2 and} the mutual conductance gmn of the MOS transistor Tn ₂ .

式（９）〜（１１）から明らかなように、上記負性抵抗−ＲＬも電源ＶＤＤに依存して変動してしまう。このため、電源ＶＤＤの変動によっては式（２）に示す発振条件を満たすことができずに発振が停止したり、発振異常が生じる恐れがあった。 The gmp and gmn can be expressed by the following formulas (10) and (11).

As is clear from the equations (9) to (11), the negative resistance -RL also varies depending on the power supply VDD. For this reason, depending on the fluctuation of the power supply VDD, the oscillation condition shown in the equation (2) cannot be satisfied, and the oscillation may stop or an oscillation abnormality may occur.

Furthermore, there is a problem that the oscillation frequency f0 of the crystal oscillation circuit 1 also varies depending on the power source. The oscillation frequency f0 can be expressed by the following equation (12).

The CMOS inverter IVc is provided with an ESD protection circuit using a diode (not shown). Therefore, as shown in FIG. 6, parasitic diodes D _G and D _C attached by the diode used in the ESD protection circuit are generated in parallel with the capacitors C _G and C _D. When the parasitic diodes D _G and D _C are non-potential, a potential failure occurs at the junction surface, and the failure increases when a reverse voltage is applied. This failure appears as a capacitance to the outside, and the capacitances of the parasitic diodes D _G and D _C are added to the series capacitance CL of the equivalent circuit. Since the capacitances of the parasitic diodes D _G and D _C change depending on the inversion potential VTH, that is, the power supply VDD, the oscillation frequency f0 also changes.

  In order to solve the above problem, for example, a constant voltage circuit is added so that the power supply VDD does not fluctuate. However, since it is necessary to add a constant voltage circuit, there has been a problem of increasing the size and cost.

  Further, the CMOS inverter IVc requires at least two MOS transistors. When the constant voltage circuit is used as a MOS transistor, there is a problem that three MOS transistors need to be connected in series, and a high operating voltage is required. Furthermore, since the output voltage Vout of the CMOS inverter IVc greatly varies between the power supply VDD and the power supply VSS, there is a problem that the current flowing through the crystal resonator QZ increases.

JP 2004-187004 A

  Therefore, in the present invention, the inversion voltage VTH, the negative resistance -RL, and the oscillation frequency f0 are not affected by the power supply VDD, and it is not necessary to add a constant voltage circuit. It is an object of the present invention to provide an oscillation circuit capable of reducing the current flowing through a child.

  The invention according to claim 1, which has been made to solve the above-described problem, includes an inverter, a feedback resistor connected in parallel to the inverter, a crystal resonator connected in parallel to the inverter, and an input of the inverter. In a crystal oscillation circuit having a first capacitor connected between a power source and a second capacitor connected between an output of the inverter and a power source, the inverter is connected to the + side of the power source The crystal oscillation circuit includes a constant current circuit and an n-type MOS transistor connected between the constant current circuit and the negative side of the power supply.

  According to a second aspect of the present invention, there is provided an inverter, a feedback resistor connected in parallel to the inverter, a crystal resonator connected in parallel to the inverter, and a first connected between an input of the inverter and a power source. A crystal oscillation circuit having a capacitor and a second capacitor connected between the output of the inverter and a power supply, wherein the inverter is connected to a negative side of the power supply, and the constant current circuit; The crystal oscillation circuit is characterized by comprising a p-type MOS transistor connected between the positive side of the power supply.

  A third aspect of the present invention resides in the crystal oscillation circuit according to the first or second aspect, wherein the gate length of the MOS transistor is 0.8 μm or less.

  According to a fourth aspect of the present invention, there is provided the crystal oscillation circuit according to the first or second aspect, wherein the gate length of the MOS transistor is 0.5 μm or less.

  The invention according to claim 5 is characterized in that the first capacitor is connected to one of the positive side and the negative side of the power source, and the second capacitor is connected to the other of the positive side and the negative side of the power source. It exists in the crystal oscillation circuit of any one of Claims 1-4.

  As described above, according to the first aspect of the present invention, the inverter is composed of the constant current circuit and the n-type MOS transistor, so that the inversion voltage VTH and the negative resistance -RL are affected by the fluctuation of the power supply VDD. I do not receive it. In addition, in an inverter configured by connecting a constant current circuit and an n-type MOS transistor in series, the inverted voltage VTH is determined by the constant current value and the n-type MOS transistor, so that the value of the parasitic diode varies. As a result, since the oscillation frequency f0 is not affected by the power supply VDD, it is not necessary to provide a constant voltage circuit as in the prior art. In addition, only one MOS transistor may be included in the inverter. Even if a MOS transistor is used in the constant current circuit, two MOS transistors may be connected in series between the power supplies, and the number of MOS transistors connected in series between the power supplies can be reduced to reduce the operating voltage of the MOS transistors. In addition, since a constant current from the constant current circuit flows through the crystal resonator, the crystal current can be reduced and the electromagnetic wave emitted from the crystal oscillation can be reduced by setting the constant current.

  According to the second aspect of the present invention, since the inverter is composed of a constant current circuit and a p-type MOS transistor, the inversion voltage VTH and the negative resistance -RL are determined based on the power supply VDD. Unaffected by fluctuations. In addition, in an inverter configured by connecting a p-type MOS transistor and a constant current circuit in series, the inverted voltage VTH is determined by the constant current value and the p-type MOS transistor, so that the value of the parasitic diode varies. As a result, the oscillation frequency f0 is not affected by the power supply VDD, and there is no need to provide a constant voltage circuit. In addition, since it is composed of at least one MOS transistor, the operating voltage of the MOS transistor can be lowered. In addition, since a constant current from the constant current circuit flows through the crystal resonator, the crystal current can be reduced and the electromagnetic wave emitted from the crystal oscillation can be reduced by setting the constant current.

  According to the invention described in claim 3, the size of one IC chip including a CMOS inverter, a feedback resistor, a first capacitor and a second capacitor is 0.8 mm × 0.8 mm, and the gate length of the CMOS inverter is 1 μm or less. The same characteristics (that is, equivalent drain-source current, gm) can be obtained with the same size as the conventional product (= 0.8 mm × 0.8 mm).

  According to the fourth aspect of the present invention, the size of one IC chip incorporating a CMOS inverter, feedback resistor, first capacitor and second capacitor is 0.8 mm × 0.8 mm, and the gate length of the CMOS inverter is 1 μm or less. The size of the IC chip can be suppressed to 0.72 mm × 0.72 mm with the same characteristics as the conventional product (that is, equivalent drain-source current, negative resistance-RL).

  According to the fifth aspect of the present invention, even if the operation of the constant current circuit is delayed immediately after the power is turned on, the input and output of the inverter can be inverted, and the oscillation immediately after the power is turned on can be stabilized.

It is a circuit diagram which shows the crystal oscillation circuit of this invention in 1st Embodiment. FIG. 2 is a circuit diagram showing an example of an NMOS inverter shown in FIG. 1. It is a circuit diagram which shows the crystal oscillation circuit of this invention in 2nd Embodiment. 2A is a cross-sectional view of a package including the crystal resonator and the oscillation circuit shown in FIG. 1, and FIG. 2B is a top view of the package. It is a circuit diagram which shows the crystal oscillation circuit of this invention in 3rd Embodiment. (A) is a circuit diagram which shows an example of the conventional crystal oscillation circuit, (B) is a circuit diagram which shows the CMOS inverter shown to (A). It is a perspective view which shows the structure of the CMOS inverter shown to FIG. 6 (B). It is an equivalent circuit of the crystal oscillation circuit of FIG.1 and FIG.6.

First Embodiment Next, a crystal oscillation circuit according to a first embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, the crystal oscillation circuit 1 includes a crystal resonator Qz, an oscillation circuit 2, and an amplification circuit 3. The oscillation circuit 2, the NMOS inverter IVn as an inverter, a feedback resistor Rf, and a capacitor C _G and C _D of the first capacitor and the second capacitor, and a. The crystal resonator Qz, NMOS inverter IVn, and feedback resistor Rf are connected in parallel to each other. Then, the capacitor C _G is the NMOS inverter IVn input and power supply V - is provided between the power supply VSS is a side. Capacitor C _D is provided between the output and the power supply VSS of the NMOS inverter IVn.

  The NMOS inverter IVn includes an n-type MOS connected between the constant current circuit In connected to the power supply VDD on the positive side of the power supply V and the power supply VSS on the negative side of the power supply V with the constant current circuit In. Transistor Tn. The MOS transistor Tn has a drain connected to the power supply VDD side and a source connected to the power supply VSS side. The constant current circuit In and the MOS transistor Tn are connected in series, the gate of the MOS transistor Tn serves as the input of the NMOS inverter IVn, and the connection point between the constant current circuit In and the drain of the MOS transistor Tn serves as the output of the NMOS inverter IVn. .

  As the constant current circuit In, for example, a current mirror circuit 21 as shown in FIG. 2A, a resistance R2 as shown in FIG. As shown in C), known ones such as those composed of transistors T are used.

  In the NMOS inverter IVn, when the input voltage Vin exceeds the threshold voltage Vthn of the MOS transistor Tn, the MOS transistor Tn is turned on and the output voltage Vout becomes equal to the power supply VSS (Lo level). On the other hand, when the input voltage Vin falls below the threshold voltage Vthn, the MOS transistor Tn is turned off and the output voltage Vout becomes equal to the power supply VDD (Hi level).

The amplifier circuit 3 includes an operational amplifier 31 to which the output of the NMOS inverter IVn and the reference voltage Vref are supplied. The reference voltage Vref is the voltage at the connection point between the MOS transistors Tn ₁ of the constant current circuit I1 and n-type connected in series to each other between the power supply V. The constant current circuit I1 is provided with the same configuration as the constant current circuit In. The MOS transistor Tn ₁ is provided with the same configuration as the MOS transistor Tn, and the gate is connected to the power supply VDD. Therefore, the reference voltage Vref becomes equal to the output of the inversion potential VTH of the NMOS inverter IVn. The operational amplifier 31 amplifies the output of the NMOS inverter IVn by amplifying and outputting the difference between the output of the NMOS inverter IVn and the reference voltage Vref.

なお、Ｌｎ：ＭＯＳトランジスタＴｎのゲート長、Ｗｎ：ＭＯＳトランジスタＴｎのゲート幅、μｎ：ＭＯＳトランジスタＴｎのチャンネル中キャリア移動度、Ｖthn：ＭＯＳトランジスタＴｎのしきい値電圧である。 Next, the inversion voltage VTH of the crystal oscillation circuit 1 having the above-described configuration is obtained and viewed. The constant current from the constant current circuit In is defined as Ic. As shown in the background art, when the output of the NMOS inverter IVn is inverted, the current Idsn flowing between the drain and the source of the MOS transistor Tn can be expressed by the following equation (13).

Ln: gate length of the MOS transistor Tn, Wn: gate width of the MOS transistor Tn, μn: carrier mobility in the channel of the MOS transistor Tn, Vthn: threshold voltage of the MOS transistor Tn.

式（１５）から明らかなように、反転電圧ＶＴＨは電源ＶＤＤに依存する値ではない。 When the NMOS inverter IVn is inverted, the current Idsn and the constant current Ic become equal as shown in the following formula (14).
Idsn = Ic (14)
The input voltage Vin when the above equation (14) is substituted into the above equation (13) becomes the inverted voltage VTH. Therefore, the inversion voltage VTH can be expressed by the following equation (15).

As apparent from the equation (15), the inversion voltage VTH is not a value depending on the power supply VDD.

上記式（１６）からも明らかなように、ｇｍ（＝ｇｍｎ）は電源ＶＤＤに依存する値とならない。 Next, the negative resistance -RL of the crystal oscillation circuit 1 is obtained and viewed. The negative resistance -RL is proportional to gm as described in the background art. In the crystal oscillation circuit 1 of the first embodiment, gm is equal to the mutual conductance gmn of the MOS transistor Tn, and is a value depending on the current Idsn as shown in the following equation (16).

As is clear from the above equation (16), gm (= gmn) does not depend on the power supply VDD.

Therefore, according to the crystal oscillation circuit 1, by configuring the NMOS inverter IVn with the constant current circuit In and the n-type MOS transistor Tn, the inversion voltage VTH and the negative resistance -RL are affected by the fluctuation of the power supply VDD. I do not receive it. Further, since the voltage applied to the parasitic diodes D _G and D _D (see FIG. 6) (VSS side) does not fluctuate, the capacitance does not fluctuate. As a result, the oscillation frequency f0 is not affected by the power supply VDD. Thus, there is no need to provide a constant voltage circuit.

  In addition, the NMOS inverter IVn needs only one MOS transistor Tn. Even if the constant current circuit In is used as a MOS transistor, two MOS transistors may be connected in series between the power supplies V, and the number of MOS transistors connected in series between the power supplies is reduced to reduce the operating voltage of the MOS transistors. Can do. In addition, since the constant current Ic from the constant current circuit In flows through the crystal resonator Qz, the setting of the constant current Ic can reduce the power consumption of the crystal and reduce the electromagnetic wave generated from the crystal oscillation.

Second Embodiment Next, a second embodiment will be described with reference to FIG. In the figure, the same parts as those already described in the first embodiment with respect to FIG. 1 described above are denoted by the same reference numerals, and detailed description thereof is omitted. A significant difference between the first embodiment and the second embodiment is the configuration of the inverter. In the second embodiment, a PMOS inverter IVp is used instead of the NMOS inverter IVn.

  The PMOS inverter IVp is a constant current circuit connected between a p-type MOS transistor Tp connected to the power supply VDD which is the positive side of the power supply V and a power supply VSS which is the negative side of the MOS transistor Tp and the power supply V. Ip. The MOS transistor Tp has a drain connected to the power supply VDD side and a source connected to the power supply VSS side. The constant current circuit Ip and the MOS transistor Tp are connected in series, the gate of the MOS transistor Tp serves as the input of the PMOS inverter IVp, and the connection point between the constant current circuit Ip and the drain of the MOS transistor Tp serves as the output of the PMOS inverter IVp. .

  In the PMOS inverter IVp, when the input voltage Vin falls below the threshold voltage Vthp of the MOS transistor Tp, the MOS transistor Tp is turned on and the output voltage Vout becomes equal to the power supply VDD (Hi level). On the other hand, when the input voltage Vin exceeds the threshold voltage Vthp, the MOS transistor Tp is turned off and the output voltage Vout becomes equal to the power supply VSS (Lo level).

The operational amplifier 31 is supplied with a reference voltage ref which is a voltage at a connection point between the p-type MOS transistor Tp ₁ and the constant current circuit I 2 connected in series between the power sources V. The MOS transistor Tp ₁ is provided with the same configuration as the MOS transistor Tp, and the gate is connected to the power supply VSS. The constant current circuit I2 is provided with the same configuration as the constant current circuit Ip. Therefore, the reference voltage Vref becomes equal to the output of the inversion potential VTH of the PMOS inverter IVp. The operational amplifier 31 amplifies the output of the PMOS inverter IVp by amplifying and outputting the difference between the output of the PMOS inverter IVp and the reference voltage Vref.

なお、Ｌｐ：ＭＯＳトランジスタＴｐのゲート長、Ｗｐ：ＭＯＳトランジスタＴｐのゲート幅、μｐ：ＭＯＳトランジスタＴｐのチャンネル中キャリア移動度、Ｖthp：ＭＯＳトランジスタＴｐのしきい値電圧である。 Next, the inversion voltage VTH of the crystal oscillation circuit 1 having the above-described configuration is obtained and viewed. The constant current from the constant current circuit Ip is defined as Ic. As shown in the background art, when the PMOS inverter IVp is inverted, the current Idnp flowing between the drain and the source of the MOS transistor Tp can be expressed by the following equation (17).

Lp: gate length of the MOS transistor Tp, Wp: gate width of the MOS transistor Tp, μp: carrier mobility in the channel of the MOS transistor Tp, Vthp: threshold voltage of the MOS transistor Tp.

式（１９）から明らかなように、反転電圧ＶＴＨは電源ＶＤＤとの差分に依存する値となる。即ち、反転電位ＶＴＨは電源ＶＤＤを基準として決定される値となる。 When the PMOS inverter IVp is inverted, the current Idsp and the constant current Ic are equal as shown in the following formula (18).
Idsp = Ic (18)
The input voltage Vin when the above equation (18) is substituted into the above equation (17) becomes the inverted voltage VTH. Therefore, the inversion voltage VTH can be expressed by the following equation (19).

As is clear from Equation (19), the inversion voltage VTH is a value that depends on the difference from the power supply VDD. That is, the inversion potential VTH is a value determined with reference to the power supply VDD.

上記式（２０）からも明らかなように、ｇｍ（＝ｇｍｐ）は電源ＶＤＤとの差分に依存する値となる。即ち、ｇｍは電源ＶＤＤを基準として決定される値となる。 Next, the negative resistance -RL of the crystal oscillation circuit 1 is obtained and viewed. The negative resistance -RL is proportional to gm as described in the background art. In the crystal oscillation circuit 1 of the second embodiment, gm is equal to the mutual conductance gmp of the MOS transistor Tp, and is a value depending on the current Idsp as shown in the following equation (20).

As is clear from the above equation (20), gm (= gmp) is a value depending on the difference from the power supply VDD. That is, gm is a value determined based on the power supply VDD.

  Therefore, according to the crystal oscillation circuit 1, the inversion voltage VTH and the negative resistance -RL are determined based on the power supply VDD by configuring the PMOS inverter IVp with the constant current circuit Ip and the p-type MOS transistor Tp. Therefore, it is not affected by fluctuations in the power supply VDD. In addition, a PMOS inverter IVp configured by connecting a constant current circuit Ip and a p-type MOS transistor Tp in series has a p-type semiconductor and an n-type semiconductor coexisting on a single substrate like the conventional CMO inverter IVc. Not. For this reason, the voltage applied to the parasitic diode (VDD side) does not fluctuate, and the capacitance does not fluctuate. As a result, the oscillation frequency f0 is not affected by the power supply VDD. Therefore, it is necessary to provide a constant voltage circuit as in the prior art. Absent.

  In addition, the PMOS inverter IVp needs only one MOS transistor Tp. Even if a MOS transistor is used for the constant current circuit Ip, two MOS transistors may be connected in series between the power supplies V, and the number of MOS transistors connected in series between the power supplies is reduced to reduce the operating voltage of the MOS transistors. Can do. In addition, since the constant current Ic from the constant current circuit Ip flows through the crystal resonator Qz, the setting of the constant current Ic can reduce the crystal current and reduce the electromagnetic wave emitted from the crystal oscillation.

  By the way, in the first and second embodiments, as shown in FIG. 4, the above-described oscillation circuit 2 is resin-sealed in one IC chip 5, and this IC chip 5 is cased together with the crystal resonator Qz. One package 7 is accommodated in 6. When the size of the package 7 becomes smaller than A × B = 3.2 mm × 2.5 mm, the power consumed by the crystal resonator Qz is limited by the miniaturization of the crystal resonator Qz, and the package 7 is mounted. The size of the IC chip 5 is also limited.

When the size of the package 7 is A × B = 3.2 mm × 2.5 mm, the size of the IC chip 5 needs to be C × D = 0.8 mm × 0.8 mm or less. In the conventional product using the conventional CMOS inverter IVc shown in FIG. 6, the gate lengths Ln and Lp of the MOS transistors Tp ₂ and Tn ₂ when the size of the IC chip 5 is C × D = 0.8 mm × 0.8 mm. Is designed to have a characteristic (values of Ids and gm) such that is 1 μm or less.

In the conventional product using a CMOS inverter IVc, gm becomes a combination of the gmn of the MOS transistor Tp ₂ of gmp and n-type p-type MOS transistor Tp _2. The gm of the NMOS inverter IVn described in the first embodiment is equal to the gmn of the n-type MOS transistor Tn. Further, the gm of the NMOS inverter IVn described in the second embodiment is equal to the gmp of the p-type MOS transistor Tp. Therefore, in order to obtain the same size and equivalent characteristics as the conventional IC chip 5 in the first and second embodiments, it is necessary to reduce the gate lengths Ln and Lp. In consideration of including the MOS transistors used in the constant current circuits In and Ip in the IC chip 5, in order to design the same characteristics without changing the size of the IC chip 5, the first embodiment In the embodiment and the second embodiment, the gate lengths Ln and Lp of the MOS transistors Tn and Tp are set to 0.8 μm or less.

  Therefore, by setting the gate lengths Ln and Lp to 0.8 μm or less, they have the same size (C × D = 0.8 mm × 0.8 mm or less) and the same characteristics (ie, equivalent Ids, gm). Can be.

  In addition, if the gate lengths Ln and Lp of the MOS transistors Tn and Tp are 0.5 μm or less in the first and second embodiments, the size of the IC chip 5 can be set to C × D = It can be within 0.72 mm × 0.72 mm. The IC chip 5 having C × D = 0.72 mm × 0.72 mm can be incorporated in the package 7 having A × B = 2.5 mm × 2.0 mm.

Third Embodiment Next, a third embodiment will be described. In the figure, the same parts as those already described in the first embodiment with respect to FIG. 1 described above are denoted by the same reference numerals, and detailed description thereof is omitted. The first embodiment greatly different in the third embodiment, a connection of the capacitors C _D, C _G. In the first embodiment, the capacitors C _D and _CG are both connected to the power source VSS. In contrast, in the third embodiment, the capacitor C _D is connected to the power supply VSS, the capacitor C _G is connected to the power supply VDD.

  Since the constant current circuit In does not start operation immediately after the power supply V is turned on, in the first embodiment, the input and output of the NMOS inverter IVn are both the power supply VSS, and the oscillation is not stable. On the other hand, in the third embodiment, even if the operation of the constant current circuit In is delayed immediately after the power supply V is turned on, the input of the N inverter IVn is set to the power supply VSS and the output is set to the power supply VDD to invert the input and the output. The oscillation immediately after the power supply V is turned on can be stabilized.

In the third embodiment, the capacitor and C _D is connected to the power supply VSS, and had connected a capacitor C _G to power source VDD, and the present invention is not limited thereto. Conversely, to connect the capacitor C _D to the power supply VDD, and may be connected to the capacitor C _G to the power supply VDD.

Also, connect the capacitor C _D of the second embodiment shown in FIG. 3 described above supply VSS, one of the power supply VDD, and may be connected to the capacitor C _G power VSS, the other power supply VDD.

  Further, the above-described embodiments are merely representative forms of the present invention, and the present invention is not limited to the embodiments. That is, various modifications can be made without departing from the scope of the present invention.

1 Crystal oscillator circuit _CG capacitor (first capacitor)
_CD capacitor (second capacitor)
In constant current circuit Ip constant current circuit Tn MOS transistor Tp MOS transistor IVn NMOS inverter (inverter)
IVp PMOS inverter (inverter)
Qz Crystal resonator Rf Feedback resistance V Power supply

Claims (5)

An inverter, a feedback resistor connected in parallel to the inverter, a crystal resonator connected in parallel to the inverter, a first capacitor connected between an input of the inverter and a power source, and an output of the inverter A crystal oscillation circuit having a second capacitor connected to a power source;
The inverter includes a constant current circuit connected to the + side of a power supply, and an n-type MOS transistor connected between the constant current circuit and the − side of the power supply. Crystal oscillator circuit. An inverter, a feedback resistor connected in parallel to the inverter, a crystal resonator connected in parallel to the inverter, a first capacitor connected between an input of the inverter and a power source, and an output of the inverter A crystal oscillation circuit having a second capacitor connected to a power source;
The inverter includes a constant current circuit connected to a negative side of a power supply, and a p-type MOS transistor connected between the constant current circuit and the positive side of the power supply. Crystal oscillator circuit. The crystal oscillation circuit according to claim 1, wherein a gate length of the MOS transistor is 0.8 μm or less. The crystal oscillation circuit according to claim 1, wherein a gate length of the MOS transistor is 0.5 μm or less. Connecting the first capacitor to one of a + side and a-side of a power source;
The crystal oscillation circuit according to any one of claims 1 to 4, wherein the second capacitor is connected to the other of the + side and the-side of the power source.

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