JP2012199363A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means for inhibiting occurrence of unbalance in a signal transmission characteristic in a stacked semiconductor device in which an external terminal and a semiconductor chip are connected through a wire.SOLUTION: In an antenna switch module and the like in which first and second semiconductor chips 2a and 2b are laminated such that first and second high frequency signal bonding pads 8a and 8b having corresponding functions are adjacent to each other and the second semiconductor chip faces upward, among external terminals 5, a high frequency signal metal terminal 5a that is most adjacent to the first high frequency signal bonding pad is mutually connected with the second high frequency signal bonding pad 8b by a first bonding wire 6x and the first high frequency signal bonding pad 8a is mutually connected with the other high frequency signal metal terminal 5b by a second bonding wire 6y.

Description

  The present invention relates to a technique effective when applied to a package structure in a semiconductor device (or a semiconductor integrated circuit device).

  In Japanese Unexamined Patent Publication No. 2002-222913 (Patent Document 1) or US Patent Publication No. 2002-96755 (Patent Document 2) corresponding thereto, semiconductor chips of the same size are mainly stacked and mounted in a package. In this case, after wire bonding of the lower layer chip is completed, a technique for realizing a laminated die bond that ensures flatness of the chip by pressing an upper layer chip having a die bonding adhesive layer on the lower surface from above is disclosed. .

  In Japanese Patent Laid-Open No. 2001-308262 (Patent Document 3) or US Pat. No. 6,545,365 (Patent Document 4) corresponding to this, in the case where a semiconductor chip is stacked in a package and mounted, A technique is disclosed in which, after completion of wire bonding, a sufficient amount of die bond resin is applied to the upper surface of the lower layer chip so that there is no short circuit between the bonding wire and the chip, and the upper layer chip is laminated on the upper layer.

  In Japanese Patent Laid-Open No. 2006-128169 (Patent Document 5), when semiconductor chips of the same size are mainly stacked and mounted in a package, after wire bonding of a lower layer chip is completed, a die bond is applied from above to the lower surface. A technique for effectively preventing a short circuit between a wire and an upper layer chip and a short circuit between wires by pressing an upper layer chip having an adhesive layer for use is disclosed. That is, the die bonding adhesive layer is composed of an upper half layer in which the wire is difficult to enter and a lower half layer in which the wire is likely to enter.

JP 2002-222913 A US Patent Publication No. 2002-96755 JP 2001-308262 A US Pat. No. 6,545,365 JP 2006-128169 A

  In general, in order to reduce the size of a semiconductor device, a structure in which another semiconductor chip is stacked on a semiconductor chip is effective. The inventor of the present application has examined the configuration in which electrodes (leads) serving as external terminals and respective semiconductor chips are electrically connected to each other through wires in such a stacked semiconductor device. I found In other words, the length of the wire electrically connected to the semiconductor chip arranged on the upper stage side is electrically different from that of the semiconductor chip arranged on the lower stage side by the thickness of the semiconductor chip arranged on the lower stage side. It becomes longer than the length of the wire to be connected. As a result, the speed of signal processing (input / output) performed on the upper semiconductor chip is slower than the speed of signal processing (input / output) performed on the lower semiconductor chip.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a highly reliable stacked semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, the first high-frequency signal bonding pad and the second high-frequency signal bonding pad having functions corresponding to the first semiconductor chip and the second semiconductor chip are close to each other, and In a semiconductor device, such as an antenna switch module, laminated so that the second semiconductor chip is on top, among the external terminals, the high-frequency signal metal terminal closest to the first high-frequency signal bonding pad and the first Two high frequency signal bonding pads are interconnected by a first bonding wire, and the first high frequency signal bonding pad and other high frequency signal metal terminals are interconnected by a second bonding wire.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the first high-frequency signal bonding pad and the second high-frequency signal bonding pad having functions corresponding to the first semiconductor chip and the second semiconductor chip are close to each other, and the second semiconductor chip is located above. In the semiconductor device such as the antenna switch module laminated so as to become, among the external terminals, the metal terminal for the high frequency signal closest to the first high frequency signal bonding pad and the second high frequency signal bonding pad Are interconnected by a first bonding wire, and the first high-frequency signal bonding pad and the other high-frequency signal metal terminals are interconnected by a second bonding wire. Since the wire length is uniform between terminals, impedance between both paths There is a merit that the balance can be maintained.

1 is a circuit configuration diagram of a mobile phone terminal for explaining an outline of a circuit configuration of a mobile phone terminal or the like that is a main application example of a semiconductor device of each embodiment of the present application. It is a schematic circuit block diagram of the lower semiconductor chip which comprises the antenna switch module which is an example of the semiconductor device (basic form) of one embodiment of this application. It is a schematic circuit block diagram of the upper semiconductor chip which comprises the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. The top view of the antenna switch module which shows the connection relation between each bonding pad of the lower semiconductor chip in the antenna switch module which is an example of the semiconductor device of one embodiment of this application, and the external terminal of an antenna switch module ( The top chip etc. has been removed for easy viewing). The top view of the antenna switch module which shows the connection relation between each bonding pad of the upper semiconductor chip mainly in the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application, and the external terminal of an antenna switch module (The upper sealing resin or the like is removed for easy viewing). It is a package top view of the antenna switch module of FIG. It is a package bottom view of the antenna switch module of FIG. It is typical sectional drawing corresponding to the X-X 'cross section of the antenna switch module of FIG. FIG. 9 is an enlarged cross-sectional view of the wedge bonding peripheral cutout portion R1 of FIG. FIG. 9 is an enlarged cross-sectional view of the wedge bonding peripheral cutout portion R2 of FIG. FIG. 9 is an enlarged cross-sectional view of a ball bonding peripheral cutout portion R3 of FIG. It is a process block flowchart for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is wafer sectional drawing (wafer preparation process) in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is wafer sectional drawing (back grinding process) in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is wafer sectional drawing (DAF bonding process) in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is a perspective view (wafer dicing process) of the wafer etc. in the middle of a manufacturing process for explaining a manufacturing method of an antenna switch module which is an example of a semiconductor device of the one embodiment of the present application. FIG. 17 is a wafer cross-sectional view (wafer dicing process) in the middle of the manufacturing process corresponding to FIG. 16 for describing the method of manufacturing the antenna switch module which is an example of the semiconductor device in the embodiment of the present application; It is sectional drawing (die bonding process of a lower semiconductor chip), such as a semiconductor chip in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is sectional drawing (wire bonding process of a lower semiconductor chip), such as a semiconductor chip in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. FIG. 20 is an enlarged cross-sectional view of the wedge bonding peripheral cutout portion R4 of FIG. FIG. 20 is an enlarged cross-sectional view of the ball bonding peripheral cutout portion R5 of FIG. It is sectional drawing (die bonding process of an upper semiconductor chip), such as a semiconductor chip in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is sectional drawing (wire bonding process of an upper semiconductor chip), such as a semiconductor chip in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is sectional drawing (resin sealing process) of the semiconductor chip etc. in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is sectional drawing (metal base sheet peeling process) of the resin sealing body etc. in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is sectional drawing (package dicing process) of the resin sealing body etc. in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one Embodiment of this application. It is a circuit block diagram of the mobile telephone terminal for demonstrating the modification (lamination | stacking of the same chip size) of the antenna switch module structure which is an example of the semiconductor device of the said one Embodiment of this application. It is a schematic circuit block diagram of the upper semiconductor chip which comprises the said modification (FIG. 27) of the antenna switch module structure which is an example of the semiconductor device of the said one Embodiment of this application. The connection relation between each bonding pad of the lower semiconductor chip and the external terminal of the antenna switch module in the modified example (FIG. 27) of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application is shown. It is a top view of the antenna switch module (the upper chip and the like are removed for easy viewing). In the modified example (FIG. 27) of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application, the connection relationship between each bonding pad of the upper semiconductor chip and the external terminal of the antenna switch module. FIG. 6 is a top view of the antenna switch module (with the upper sealing resin removed for easy viewing). FIG. 28 is a schematic cross-sectional view (corresponding to FIG. 8 in the basic mode) of the whole antenna switch module corresponding to the modified example (FIG. 27) of the antenna switch module which is an example of the semiconductor device of the embodiment of the present application. FIG. 32 is an enlarged cross-sectional view of a wedge bonding peripheral cutout portion R2 of FIG. 31. FIG. 31 is an enlarged top view of the antenna switch module local cutout region R6 of FIG. 30. Model corresponding to FIG. 8 of a basic form showing a modification 1 (when the upper chip does not overlap the wire of the lower chip) of the chip arrangement in the antenna switch module which is an example of the semiconductor device of the embodiment of the present application. FIG. FIG. 8 of a basic form showing a modification 2 (when the upper chip overlaps part of the bonding pad of the lower chip) of the chip arrangement in the antenna switch module which is an example of the semiconductor device of the embodiment of the present application. It is a typical sectional view corresponding to.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a first semiconductor chip having a first front side main surface and a first back side main surface and having a rectangular shape;
(B) a second semiconductor chip mounted on the first front main surface of the first semiconductor chip and having a second front main surface and a second back main surface and having a rectangular shape;
(C) a first high-frequency signal bonding pad provided on the first front main surface of the first semiconductor chip;
(D) a second high-frequency signal bonding pad provided on the second front main surface of the second semiconductor chip so as to be close to the first high-frequency signal bonding pad;
(E) The first side of the first semiconductor chip outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface. A first high-frequency signal external terminal provided along the line;
(F) a second external terminal for high frequency signals provided outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface;
Here, the first high-frequency signal external terminal is closer to the first high-frequency signal bonding pad than the second high-frequency signal external terminal, and the semiconductor device further includes: including:
(G) a first bonding wire that interconnects the second high-frequency signal bonding pad and the first high-frequency signal external terminal;
(H) A second bonding wire for interconnecting the first high-frequency signal bonding pad and the second high-frequency signal external terminal.

  2. 2. The semiconductor device according to the item 1, wherein the second semiconductor chip is on the first semiconductor chip and is planarly formed inside the first front main surface with the first adhesive layer interposed therebetween. Mounted and a portion of the second bonding wire is in the first adhesive layer.

3. The semiconductor device according to item 1 or 2 further includes the following:
(I) a first high-frequency signal bonding pad group including the first high-frequency signal bonding pad provided on the first front main surface along the first side;
(J) A second layer provided on the second front main surface along the second side of the second semiconductor chip along the first side and including the second high-frequency signal bonding pad. 2 High frequency signal bonding pads.

  4). In the semiconductor device of the item 3, the second semiconductor chip is mounted eccentrically so that the second side is close to the first side.

5. The semiconductor device according to any one of 1 to 4 further includes the following:
(K) a first grounding bonding pad provided on the first front main surface in the vicinity of one side of the first semiconductor chip;
(L) A second ground bonding pad provided on the second front main surface in the vicinity of the other one side of the second semiconductor chip along the one side.

  6). 6. In the semiconductor device according to any one of items 1 to 5, the second high-frequency signal bonding pad and the first bonding wire, and the first high-frequency signal bonding pad and the second bonding wire are: , Each connected via a stud bump.

  7). 7. In the semiconductor device according to any one of items 2 to 6, the thickness of the first adhesive layer is larger than the sum of the height of the stud bump and the wire diameter.

  8). 8. The semiconductor device according to 6 or 7, wherein the height of the stud bump, the diameter of the second bonding wire, and the second backside main surface of the second semiconductor chip and the second bonding wire The distances from the tops of the side surfaces are almost the same.

9. The semiconductor device according to any one of 1 to 8 further includes the following:
(M) the first semiconductor chip, the second semiconductor chip, the first high-frequency signal external terminal, the second high-frequency signal external terminal, the first bonding wire, and the second bonding A sealing resin body for integrally sealing the wire;
(N) a second adhesive layer covering the first back main surface of the first semiconductor chip;
Here, the lower surface of the second adhesive layer is exposed from the lower surface of the sealing resin body.

  10. 10. In the semiconductor device as described above in any one of 1 to 9, the first bonding wire and the second bonding wire are each bonded by a reverse bonding method.

  11. 11. In the semiconductor device as described above in any one of 1 to 10, each of the first semiconductor chip and the second semiconductor chip includes an antenna switch.

  12 12. In the semiconductor device as described above in any one of 1 to 11, each of the high-frequency signal bonding pads constituting the first high-frequency signal bonding pad group and the second high-frequency signal bonding pad group is a high-frequency signal via an antenna. It is a bonding pad.

  13. 12. The semiconductor device according to the item 12, wherein the first high-frequency signal bonding pad and the second high-frequency signal bonding pad are antenna high-frequency signal bonding pads in the same frequency band.

  14 14. The semiconductor device as described above in any one of 9 to 13, wherein the first adhesive layer and the second adhesive layer are each a DAF member.

  15. 15. In the semiconductor device as described above in any one of 9 to 14, the package format of the semiconductor device is a PLP method.

  16. 16. In the semiconductor device as described above in any one of 1 and 5 to 15, the first semiconductor chip and the second semiconductor chip are mounted so as to have substantially the same size and their sides substantially coincide with each other. Yes.

  17. 16. The semiconductor device according to item 16, wherein the first bonding wire is bonded to a side of the first high-frequency signal external terminal close to the second high-frequency signal bonding pad, and the second bonding wire. Are bonded to a side of the second high frequency signal external terminal close to the first high frequency signal bonding pad.

  18. 18. In the semiconductor device as described above in any one of 5 to 17, the one side and the other one side are sides different from the first side and the second side, respectively.

  19. 19. In the semiconductor device as described above in any one of 1 to 18, the first high frequency signal external terminal has a function of either an input terminal or an output terminal, and the second high frequency signal external terminal is , Having the same function as the one of the functions.

  20. 20. The semiconductor device according to any one of 9 to 19, wherein the first adhesive layer is thicker than the second adhesive layer.

21. Semiconductor devices including:
(A) a first semiconductor chip having a first front side main surface and a first back side main surface and having a rectangular shape;
(B) a second semiconductor chip mounted on the first front main surface of the first semiconductor chip and having a second front main surface and a second back main surface and having a rectangular shape;
(C) a first high-frequency signal bonding pad provided on the first front main surface of the first semiconductor chip;
(D) a second high-frequency signal bonding pad provided on the second front main surface of the second semiconductor chip;
(E) The first side of the first semiconductor chip outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface. A first high-frequency signal external terminal provided along the line;
(F) a second external terminal for high frequency signals provided outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface;
Here, the first high-frequency signal external terminal is closer to the first high-frequency signal bonding pad than the second high-frequency signal external terminal, and the semiconductor device further includes: including:
(G) a first bonding wire that interconnects the second high-frequency signal bonding pad and the first high-frequency signal external terminal;
(H) A second bonding wire for interconnecting the first high-frequency signal bonding pad and the second high-frequency signal external terminal.

  Next, an outline of another embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a first semiconductor chip having a first front side main surface and a first back side main surface and having a rectangular shape;
(B) a second semiconductor chip mounted on the first front main surface of the first semiconductor chip and having a second front main surface and a second back main surface and having a rectangular shape;
(C) A first high-frequency signal bonding pad group including a first high-frequency signal bonding pad provided on the first front main surface of the first semiconductor chip along the first side. ;
(D) on the second front main surface of the second semiconductor chip along the second side of the second semiconductor chip along the first side; A second high-frequency signal bonding pad group including a second high-frequency signal bonding pad provided so as to be close to the bonding pads;
(E) provided outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface along the first side; A group of external terminals for high-frequency signals including a first external terminal for high-frequency signals and a second external terminal for high-frequency signals;
Here, the first high frequency signal external terminal is closest to the first high frequency signal bonding pad in the high frequency signal external terminal group, and the semiconductor device further includes:
(F) a first bonding wire for interconnecting the second high-frequency signal bonding pad and the first high-frequency signal external terminal;
(G) A second bonding wire for interconnecting the first high-frequency signal bonding pad and the second high-frequency signal external terminal.

    2. 2. The semiconductor device according to the item 1, wherein the second semiconductor chip is on the first semiconductor chip and is planarly formed inside the first front main surface with the first adhesive layer interposed therebetween. Mounted and a portion of the second bonding wire is in the first adhesive layer.

  3. In the semiconductor device according to 1 or 2, the second semiconductor chip is mounted eccentrically so that the second side is close to the first side.

  4). In the semiconductor device of the item 1, the first semiconductor chip and the second semiconductor chip are mounted so as to have substantially the same size and their sides substantially coincide with each other.

  5). 5. The semiconductor device according to item 4, wherein the first bonding wire is bonded to a side of the first high-frequency signal external terminal close to the second high-frequency signal bonding pad, and the second bonding wire. Are bonded to a side of the second high frequency signal external terminal close to the first high frequency signal bonding pad.

6). The semiconductor device according to any one of 1 to 5 further includes the following:
(H) a first grounding bonding pad provided on one side of the first front surface and in the vicinity of one side of the first semiconductor chip;
(I) A second ground bonding pad provided on the second main surface in the vicinity of the other side of the second semiconductor chip along the one side.

  7). In the semiconductor device according to any one of 1 to 6, the second high-frequency signal bonding pad and the first bonding wire, and the first high-frequency signal bonding pad and the second bonding wire are: , Each connected via a stud bump.

  8). In the semiconductor device according to any one of 2 to 7, the thickness of the first adhesive layer is larger than the sum of the height of the stud bump and the wire diameter.

  9. 9. The semiconductor device according to 7 or 8, wherein the height of the stud bump, the diameter of the second bonding wire, and the second backside main surface of the second semiconductor chip and the second bonding wire The distances from the tops of the side surfaces are almost the same.

10. The semiconductor device according to any one of 1 to 9 further includes the following:
(J) The first semiconductor chip, the second semiconductor chip, the first high-frequency signal external terminal, the second high-frequency signal external terminal, the first bonding wire, and the second bonding A sealing resin body for integrally sealing the wire;
(K) a second adhesive layer covering the first back main surface of the first semiconductor chip;
Here, the lower surface of the second adhesive layer is exposed from the lower surface of the sealing resin body.

  11. In the semiconductor device according to any one of 1 to 10, the first bonding wire and the second bonding wire are bonded by a reverse bonding method.

  12 12. In the semiconductor device as described above in any one of 1 to 11, the first semiconductor chip and the second semiconductor chip each incorporate an antenna switch.

  13. 13. In the semiconductor device as described above in any one of 1 to 12, each high frequency signal bonding pad constituting the first high frequency signal bonding pad group and the second high frequency signal bonding pad group is a high frequency signal via an antenna. It is a bonding pad.

  14 14. The semiconductor device according to item 13, wherein the first high-frequency signal bonding pad and the second high-frequency signal bonding pad are high-frequency signal via-antenna bonding pads in the same frequency band.

  15. 15. The semiconductor device as described above in any one of 10 to 14, wherein each of the first adhesive layer and the second adhesive layer is a DAF member.

  16. 16. In the semiconductor device as described above in any one of 10 to 15, the package format of the semiconductor device is a PLP method.

  17. 17. In the semiconductor device as described above in any one of 6 to 16, the one side and the other one side are sides different from the first side and the second side, respectively.

  18. 18. In the semiconductor device as described above in any one of 1 to 17, the first high-frequency signal external terminal has a function of either an input terminal or an output terminal, and the second high-frequency signal external terminal is , Having the same function as the one of the functions.

  19. 19. In the semiconductor device as described above in any one of 10 to 18, the first adhesive layer is thicker than the second adhesive layer.

  Next, an outline of still another embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a first semiconductor chip having a first front side main surface and a first back side main surface and having a rectangular shape;
(B) a second semiconductor chip mounted on the first front main surface of the first semiconductor chip and having a second front main surface and a second back main surface and having a rectangular shape;
(C) a first signal bonding pad provided on the first front main surface of the first semiconductor chip;
(D) a second signal bonding pad provided on the second front main surface of the second semiconductor chip so as to be close to the first signal bonding pad;
(E) The first side of the first semiconductor chip outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface. A first signal external terminal provided along the line;
(F) a second signal external terminal provided outside the first semiconductor chip and the second semiconductor chip and on the first back main surface side with respect to the first front main surface;
The first signal external terminal is closer to the first signal bonding pad than the second signal external terminal, and the semiconductor device further includes:
(G) a first bonding wire for interconnecting the second signal bonding pad and the first signal external terminal;
(H) a second bonding wire for interconnecting the first signal bonding pad and the second signal external terminal;

  2. 2. The semiconductor device according to the item 1, wherein the second semiconductor chip is on the first semiconductor chip and is planarly formed inside the first front main surface with the first adhesive layer interposed therebetween. Mounted and a portion of the second bonding wire is in the first adhesive layer.

3. The semiconductor device according to item 1 or 2 further includes the following:
(I) a first signal bonding pad group including the first signal bonding pads provided on the first front main surface along the first side;
(J) A second layer provided on the second front main surface along the second side of the second semiconductor chip along the first side and including the second signal bonding pad. Signal bonding pad group.

  4). In the semiconductor device of the item 3, the second semiconductor chip is mounted eccentrically so that the second side is close to the first side.

5. The semiconductor device according to any one of 1 to 4 further includes the following:
(K) a first grounding bonding pad provided on the first front main surface in the vicinity of one side of the first semiconductor chip;
(L) A second ground bonding pad provided on the second front main surface in the vicinity of the other one side of the second semiconductor chip along the one side.

  6). In the semiconductor device according to any one of items 1 to 5, the second signal bonding pad and the first bonding wire, and the first signal bonding pad and the second bonding wire are respectively They are connected via stud bumps.

  7). 7. In the semiconductor device according to any one of items 2 to 6, the thickness of the first adhesive layer is larger than the sum of the height of the stud bump and the wire diameter.

  8). 8. The semiconductor device according to 6 or 7, wherein the height of the stud bump, the diameter of the second bonding wire, and the second backside main surface of the second semiconductor chip and the second bonding wire The distances from the tops of the side surfaces are almost the same.

9. The semiconductor device according to any one of 1 to 8 further includes the following:
(M) The first semiconductor chip, the second semiconductor chip, the first signal external terminal, the second signal external terminal, the first bonding wire, and the second bonding wire. Sealing resin body for sealing together;
(N) a second adhesive layer covering the first back main surface of the first semiconductor chip;
Here, the lower surface of the second adhesive layer is exposed from the lower surface of the sealing resin body.

  10. 10. In the semiconductor device as described above in any one of 1 to 9, the first bonding wire and the second bonding wire are each bonded by a reverse bonding method.

  11. 11. In the semiconductor device as described above in any one of 1 to 10, each of the first semiconductor chip and the second semiconductor chip includes an antenna switch.

  12 12. In the semiconductor device as described above in any one of 1 to 11, each signal bonding pad constituting the first signal bonding pad group and the second signal bonding pad group is a signal bonding pad via an antenna. is there.

  13. 12. The semiconductor device according to the item 12, wherein the first signal bonding pad and the second signal bonding pad are antenna signal passing signal bonding pads in the same frequency band.

  14 14. The semiconductor device as described above in any one of 9 to 13, wherein the first adhesive layer and the second adhesive layer are each a DAF member.

  15. 15. In the semiconductor device as described above in any one of 9 to 14, the package format of the semiconductor device is a PLP method.

  16. 16. In the semiconductor device as described above in any one of 1 and 5 to 15, the first semiconductor chip and the second semiconductor chip are mounted so as to have substantially the same size and their sides substantially coincide with each other. Yes.

  17. 16. The semiconductor device according to Item 16, wherein the first bonding wire is bonded to a side of the first signal external terminal close to the second signal bonding pad, and the second bonding wire is Bonding is performed on the side of the second signal external terminal close to the first signal bonding pad.

  18. 18. In the semiconductor device as described above in any one of 5 to 17, the one side and the other one side are sides different from the first side and the second side, respectively.

  19. The semiconductor device according to any one of 1 to 18, wherein the first signal external terminal has a function of either an input terminal or an output terminal, and the second signal external terminal is It has the same function as one of the functions.

  20. 20. The semiconductor device according to any one of 9 to 19, wherein the first adhesive layer is thicker than the second adhesive layer.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly includes a single chip and a plurality of chips, and the semiconductor chip is a substrate (lead frame, metal plate). Mounted on a metal substrate, insulating film, resin substrate, ceramic substrate, or the like, or a semiconductor chip or the like by a holding member (sealing resin body, ceramic housing, resin housing, metal housing, etc.) The one held in Needless to say, it includes WLP (Wafer Level Package), SIP (System In Package), a multi-chip module, and the like. Here, the semiconductor chip refers to various transistors (active elements) alone, and those in which resistors, capacitors, etc. are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate) (a plurality of semiconductor chips or the like). Including modules integrated in a package). A typical example of various transistors in a silicon-based semiconductor chip is a MISFET (Metal Insulator Semiconductor Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor). At this time, a typical integrated circuit configuration is a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit in which an N-channel MISFET and a P-channel MISFET are combined. Can be illustrated.

  Further, representative examples of various transistors mainly in compound semiconductor chips include MESFET (Metal-Semiconductor Field Effect Transistor), HEMT (High Electron Mobility Transistor), and the like.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  The terms “semiconductor chip”, “integrated circuit chip”, “chip” and the like refer to a single unit or an integrated circuit formed on a semiconductor substrate or an insulating substrate. Currently used semiconductor chips are classified into “silicon-based semiconductor chips” and “compound-based semiconductor chips”. Typical examples of the semiconductor corresponding to the “compound semiconductor chip” are GaAs, GaN, AlGaAs, SiC, InSb, InP, etc. (including these composite substrates). On the other hand, a typical example of a semiconductor corresponding to a silicon-based semiconductor chip is one formed on a single crystal silicon substrate, an epitaxial silicon substrate, or the like. In this application, since SiGe-based devices (which are strictly compound semiconductors) are often integrated on a silicon substrate, for convenience, those integrated on a single SiGe-based device and a silicon-based semiconductor substrate are used. Are classified as “silicon-based”.

  6). The package form mainly handled in the embodiment of the present application is generally called a PLP (Platining Lead Package) system.

  Further, the compound semiconductor chip exemplified in the embodiment of the present application is a high-frequency antenna switch used for, for example, a mobile phone, and the silicon-based semiconductor chip has, for example, a control chip (control function of the high-frequency antenna switch) Chip).

  In addition, in the present application, the term “upper surface” or “front surface”, “lower surface” or “rear surface” for a chip, package, lead, external terminal and its portion, unless otherwise specified, The surface on the side where the chip is located is referred to as “upper surface” or “front surface” regardless of the direction of the space, and the surface on the opposite side is referred to as “lower surface” or “back surface”.

  The wire bonding is usually performed by a thermosonic method in which heating, bonding pressure, and ultrasonic vibration are applied almost simultaneously using a bonding tool such as a capillary. When bonding between leads, the first bonding point on the chip side and the second bonding point on the connection lead side is called “forward bonding”, and the opposite is called “reverse bonding”. When bonding between two chips, the first bonding point on the chip A side and the second bonding point on the chip B side is referred to as “forward bonding with respect to chip A”, and vice versa. This is called “reverse bonding”.

  In reverse bonding, generally, at the first bonding point, the wire direction immediately above the ball is substantially vertical (that is, the angle formed by the wire and the water surface is close to 90 degrees), and at the second bonding point, The direction of the wire is close to the horizontal plane or has a relatively shallow inclination (that is, the angle formed between the wire and the water surface is smaller than 90 degrees).

  Here, in the present application, description will be made mainly on the example of reverse bonding, but forward bonding may be used in whole or in part. Reverse bonding has the merit of lowering the wire height, but when connecting chips, either one is forward bonding. In such a case, if the reverse bonding is performed on the upper chip, it is possible to enjoy the merit that the wire height is reduced.

  In the present application, placing (mounting) a semiconductor chip on a die pad is called “indirect die bonding”, and bonding outside the die pad is called “direct die bonding”.

  In the present application, an example in which DAF (Die Attach Film) is used as an adhesive layer interposed on the back surface of the chip will be mainly described. Here, the DAF is an adhesive layer that has already been applied before die bonding, and is usually applied at the wafer stage, and is divided into individual chips together with the wafer during dicing. Of course, die bonding without using DAF is possible, but using DAF has advantages such as a simplified process.

  7). In this application, the term "for high frequency signal" in bonding pads, external terminals, etc., is the lower frequency of the reception or oscillation frequency of a mobile phone (generally mobile communication) or more than that. It shall refer to the high frequency region.

  8). “Dicing” is also called “pelletizing” by dividing the wafer into chips. It includes not only a blade but also a laser (including a thermal fusing method and a layer that forms a deteriorated layer by two-photon absorption).

  9. "MAP (Mold Array Process)" means wiring board (printed circuit board such as glass / epoxy wiring board, flexible wiring board, etc.) and tape backup lead frame with lead frame affixed on polyimide adhesive tape etc. Semiconductor chip (s) are fixed to each of a large number of unit device regions on the main surface such as a metal plate and the like, and the large number of unit device regions are collectively sealed with a resin and then dicing. The package system is divided into individual unit device regions (semiconductor elements). When using a printed circuit board, the wiring board is divided. In the case of a tape backup lead frame, the tape is peeled off after sealing, the adhesive is removed, and after necessary lead plating or the like, it is divided. In the case of a metal plate, the metal plate is peeled off after sealing and then divided.

  10. “Electroforming package” means that lead electrodes, tab electrodes (island parts or die pad parts) are formed on a metal plate by electroforming (a kind of electroplating), chip bonding, wire bonding, resin sealing It is a package manufactured by separating a device part (single or a plurality of unit device regions) and a metal plate after stopping. In the following embodiments, a MAP type electroformed package mainly using a metal plate will be described. One advantage of the electroformed package is that it can increase the height by not using a wiring board or the like. The electroformed package method forms a lead (external terminal) by electroplating, and is also called a PLP (Platining Lead Package) method.

  In the “MAP type electroformed package process”, a lead electrode or the like is formed on a metal plate by electroforming, and chip bonding, wire bonding, resin sealing, etc. are performed, so that a semiconductor chip, a bonding wire, and a lead electrode are formed. After manufacturing a “metal plate resin encapsulant composite” (intermediate product) including a “resin encapsulant” and a metal plate sealed with a resin, the resin separated by peeling off the metal plate A sealing body is obtained. Here, the “metal plate” is usually an almost solid metal plate (including those with a necessary surface treatment), but an organic resin tape (including coating) is applied to the main surface opposite to the plated surface. A reinforcing treatment such as

  One advantage of the MAP type electroformed package process is that since the leads and the like are not formed integrally with the tie bar or the like, dicing is easy (the resin and the metal need not be cut simultaneously). Unlike the tape backup lead frame method, since the adhesive tape is not used, it is not necessary to remove the contamination of the adhesive after peeling. In addition, since the substrate (metal plate) that is the lower surface of the sealing process is not a resin with low rigidity but a metal plate with high rigidity, resin burrs are not easily generated, and the effect of ultrasonic waves in wire bonding is not impaired. There are benefits. Further, it is possible to avoid a decrease in flatness of the lower surface of the package due to the deflection of the resin sheet.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Outline description of a circuit configuration of a mobile phone terminal or the like which is a main application example of the semiconductor device of each embodiment of the present application (mainly FIG. 1)
Here, a mobile phone terminal which is a main application example of the semiconductor device of each embodiment of the present application will be specifically described as an example, but the application field is not limited to this, and general mobile communication, other, Needless to say, the present invention can be applied to electronic devices that handle high frequencies.

  FIG. 1 is a circuit configuration diagram of a mobile phone terminal for explaining an outline of a circuit configuration of a mobile phone terminal or the like, which is a main application example of the semiconductor device of each embodiment of the present application. Based on this, an outline of a circuit configuration of a mobile phone terminal or the like, which is a main application example of the semiconductor device of each embodiment of the present application, will be described.

  As shown in FIG. 1, a mobile phone terminal includes a single or multiple antennas ANT, an antenna switch module SWM that switches between transmission and reception, a frequency band, and the like, a high-frequency signal processing chip RFIC that mainly performs analog processing of a high-frequency signal, and a baseband Are composed of a baseband circuit BB that performs communication signal processing, a speaker SP, a liquid crystal display & input key LCD, a microphone MP, and an interface circuit IF for these. Among these, the high-frequency signal processing chip RFIC is usually composed of a silicon-based semiconductor integrated circuit chip, while the first semiconductor chip 2a and the second semiconductor chip 2b constituting the antenna switch module SWM are usually , GaAs or AlGaAs compound semiconductor integrated circuit chip (compound semiconductor chip). Generally, the antenna switch module SWM and the high-frequency signal processing chip RFIC constitute a single high-frequency module RFM, and the semiconductor device according to each embodiment of the present invention mainly includes the antenna switch module SWM. It is targeted.

  Specifically, for example, the first semiconductor chip 2a includes a DCS (Digital Cellular System) and PCN in a low frequency band such as 800 MHz to 1 GHz and a high frequency band such as 1.7 GHz to 2.2 GHz. The second semiconductor chip 2b covers mobile communication protocols such as GSM (Global System for Mobile Communications) such as a low frequency band such as 800 MHz to 1 GHz. Covering.

2. Description of antenna switch module structure and the like as an example of a semiconductor device according to an embodiment of the present application (mainly FIGS. 2 to 11)
Here, an embodiment of the present invention will be described by taking an antenna switch module as an example. However, the present invention is not limited thereto, and it is necessary to align the lengths of wires when involving semiconductor chips. Needless to say, it can be widely applied to a certain technical field.

  The package shape mainly described in the present application is a QFN (Quad Flat Non-Leaded Package), but it goes without saying that it can be applied to other package shapes.

  FIG. 2 is a schematic circuit configuration diagram of a lower semiconductor chip constituting an antenna switch module which is an example of a semiconductor device (basic form) according to an embodiment of the present application. FIG. 3 is a schematic circuit configuration diagram of an upper semiconductor chip constituting the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 4 is an antenna switch module showing a connection relationship between each bonding pad of a lower semiconductor chip and an external terminal of the antenna switch module in the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. It is a top view (the upper chip etc. are removed for easy viewing). FIG. 5 is an antenna switch module showing a connection relationship between each bonding pad of the upper semiconductor chip and an external terminal of the antenna switch module in the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 6 is a top view of the above (the upper sealing resin and the like are removed for easy viewing). FIG. 6 is a top view of the package of the antenna switch module of FIG. FIG. 7 is a bottom view of the package of the antenna switch module of FIG. FIG. 8 is a schematic cross-sectional view corresponding to the X-X ′ cross section of the antenna switch module of FIG. 6. FIG. 9 is an enlarged cross-sectional view of the wedge bonding peripheral cutout portion R1 of FIG. 10 is an enlarged cross-sectional view of the wedge bonding peripheral cutout portion R2 of FIG. FIG. 11 is an enlarged cross-sectional view of the ball bonding peripheral cutout portion R3 of FIG. Based on these drawings, an antenna switch module structure, which is an example of a semiconductor device according to an embodiment of the present application, will be described.

  First, the schematic structure of the antenna switch module SWM, that is, the semiconductor package 10 as an example of the semiconductor device according to the embodiment of the present application will be described with reference to FIGS. 6, 7, and 8 to 11. As can be seen from FIGS. 6, 7 and 8, the semiconductor package 10 has a relatively thin rectangular parallelepiped structure (for example, about 1.5 mm square and a thickness of about 0.5 mm). A rectangular shape (substantially square or rectangular) close to the target square.

  As shown in FIG. 6 or FIG. 7, nothing is particularly exposed on the upper surface 9 a of the resin sealing body 9, whereas the center portion of the lower surface 9 b of the resin sealing body 9 has a normal thickness. Die attach film (die attach film) 3a, that is, second adhesive layer of back side main surface 2ab (first back side main surface) of lower semiconductor chip 2a (first semiconductor chip) 3a (FIG. 8) is exposed. A plurality of metal terminals 5 are exposed around the die attach film 3a. In addition, as a material of the die attach film 3a, for example, an epoxy-based adhesive containing a colorant such as carborundum whose material is relatively similar to that of the sealing resin is desirable.

  Next, FIG. 8 schematically shows the X-X ′ cross section of FIG. 6. As shown in FIG. 8, the lower surface 9b of the resin sealing body 9 has a die attach film 3a and a plurality of metal terminals 5. On the die attach film 3a, a lower semiconductor chip 2a (first semiconductor chip 2a) (Semiconductor chip) (for example, a GaAs-based compound semiconductor chip having dimensions of, for example, 0.8 mm square and thickness of about 0.1 mm). On the front main surface 2aa (first front main surface) of the lower semiconductor chip 2a, the upper semiconductor chip 2b (second semiconductor) is interposed via the thick film die attach film 3b (first adhesive layer). Chip) is mounted such that the back side main surface 2bb (second back side main surface) is in contact with the die attach film 3b. Upper surface main surface 2ba (second front surface main surface) of upper semiconductor chip 2b (for example, a GaAs-based compound semiconductor chip having dimensions of, for example, 0.4 mm square and thickness of about 0.1 mm) Is provided with a plurality of bonding pads 8 (FIG. 9) such as gold bonding pads, and these bonding pads 8 are bonded to the metal terminals 5 via gold stud bumps 7 and the like. 6 (for example, a gold bonding wire having a diameter of about 20 micrometers) is bonded in the reverse direction. That is, as shown in FIGS. 9 to 11, the metal terminal 5 side is a ball bonding portion 6b (first bonding portion), and the bonding pad 8 side is a wedge bonding portion 6w (second bonding portion). Yes.

  Similarly, a plurality of bonding pads 8 (FIG. 10) such as gold bonding pads are provided on the front main surface 2aa of the lower semiconductor chip 2a, and these bonding pads 8 are composed of gold stud bumps 7 and the like. The metal wire 5 is reversely bonded to the metal terminal 5 by a bonding wire 6 (for example, a gold bonding wire having a diameter WD of about 20 micrometers). Here, exemplifying a typical distance between the upper and lower spaces of the bonding wire 6 in FIG. 10, the horizontal wire lower surface height WH (stud bump height) is about 20 micrometers, for example, and the side surface of the lower chip wire. The distance WC between the upper end and the lower surface of the upper chip is about 20 micrometers. Further, the DAF thickness T2 (the space between the upper and lower chips or the thickness of the first adhesive layer) of the upper semiconductor chip is, for example, about 60 micrometers. On the other hand, the normal thickness of the die attach film 3a (second adhesive layer) shown in FIG. 8, that is, the thickness T1 of the second adhesive layer is, for example, about 30 micrometers. Here, the DAF thickness T2 (the space between the upper and lower chips or the thickness of the first adhesive layer) of the upper semiconductor chip may be the same as the thickness T1 of the second adhesive layer. By making it thicker than the thickness T1 of the adhesive layer 2, the front main surface 2ba (second front main surface) of the upper semiconductor chip 2b (second semiconductor chip) can be kept horizontal, There is an advantage that the wire bonding of the semiconductor chip 2b can be executed smoothly. The suitable thickness range of the DAF thickness T2 is determined by the diameter of the stud bump and the wire, and the lower limit is approximately 40 micrometers, and the upper limit is determined by the life of the blade in dicing or the like, and is approximately 100 micrometers. is there.

  Next, the role of each semiconductor chip constituting the antenna switch module RFM described in FIG. 1 will be described. FIG. 2 shows a schematic internal structure of the first semiconductor chip 2a and the role of external pads (bonding pads). As shown in FIG. 2, the antenna switch SW1 is provided in the semiconductor chip 2a, and the connection with the antenna terminal Aa is connected to the low band input terminal Ia1, the low band output terminal Oa1, the high band input terminal Ia2, and the high band. The structure is selected from any one of the output terminals Oa2, and the drive is performed via the antenna switch control terminal Vac. In addition to these, there are a power supply terminal Vad and a ground terminal Ga.

  Here, the antenna terminal Aa, the low-band input terminal Ia1, the low-band output terminal Oa1, the high-band input terminal Ia2, the high-band output terminal Oa, etc. are different from other terminals in the nature of the signals handled. Terminals or “high-frequency signal bonding pads” (or simply “signal terminals” or “signal bonding pads”). In addition, when particularly indicating that the signal is via an antenna, “terminal for high-frequency signal via antenna” or “bonding pad for high-frequency signal via antenna” (or simply “terminal for signal via antenna” or “signal via antenna” Bonding pad for use ") (the same applies to the terminals of the corresponding antenna switch module SWM below).

  Similarly, as shown in FIG. 3, an antenna switch SW2 is provided in the semiconductor chip 2b, and the connection to the antenna terminal Ab is selected from either the low-band input terminal Ib1 or the low-band output terminal Ob1. It has a structure and its driving is performed via the antenna switch control terminal Vbc. In addition to these, there are a power supply terminal Vbd and a ground terminal Gb.

  Here, as described above, the antenna terminal Ab, the low-band input terminal Ib1, the low-band output terminal Ob1, and the like have different signal characteristics from the other terminals, so that the “high-frequency signal terminal” or “high-frequency signal terminal” Signal bonding pad "(or simply" signal terminal "or" signal bonding pad "). In addition, when particularly indicating that the signal is via an antenna, “terminal for high-frequency signal via antenna” or “bonding pad for high-frequency signal via antenna” (or simply “terminal for signal via antenna” or “signal via antenna” Bonding pad for use ") (the same applies to the terminals of the corresponding antenna switch module SWM below).

  Next, the bonding wire connection relation between the planar bonding pad and the external terminal will be described with reference to FIGS. As shown in FIG. 4, the plurality of external terminals 5 corresponding to the terminals of FIGS. 2 and 3 include an antenna terminal Aa, an antenna terminal Ab, a low-band input terminal Ia1, a low-band input terminal Ib1, a low-band output terminal Oa1, High-frequency signal metal terminal 5 (signal metal terminal or metal terminal for high-frequency signal via antenna) such as low-band output terminal Ob1, high-band input terminal Ia2, and high-band output terminal Oa2, antenna switch control terminal Vac, and antenna switch control The terminal Vbc, the power terminal Vad, the power terminal Vbd, the ground terminal Ga, and the other metal terminals 5 such as the ground terminal Gb are configured. Here, for example, when attention is paid to the first high-frequency signal bonding pad group 14 provided along the first side 11 of the lower semiconductor chip 2a (first semiconductor chip), the first high-frequency signal bond The bonding pad 8a is not connected to the first high-frequency signal metal terminal 5a closest to the bonding pad 8a, but is connected to the second high-frequency signal metal terminal 5b farther away by the second bonding wire 6y.

  On the other hand, as shown in FIG. 5, the upper side semiconductor chip 2b (second semiconductor chip) has a second side 12 whose first side 11 is lower semiconductor chip 2a (first semiconductor chip). Of the second high frequency signal bonding pad group 15 provided along the second side 12 on the upper semiconductor chip 2b. Focusing on the signal bonding pad 8b, the second high-frequency signal bonding pad 8b is interconnected by the first bonding wire 6x and the first high-frequency signal metal terminal 5a closest to the pad. Here, the suitable wire length of these wires is about 0.6 millimeters in this example, for example.

  That is, as shown in FIG. 8 (see FIG. 4 and FIG. 5), the metal terminal 5 (external terminal) has a lower semiconductor chip 2a as shown by an arrow LS indicating the height range of the upper surface of the metal terminal. Since the front side main surface 2aa (first front side main surface) of the (first semiconductor chip) or a plane including this is disposed on the back side main surface 2ab (first back side main surface) side, The upper surface of the metal terminal 5 (external terminal) is positioned lower than the front main surface 2aa of the lower semiconductor chip 2a. This is because the thickness of the semiconductor chip 2 a is larger than the thickness of the metal terminal 5. Further, since the semiconductor chip 2a is arranged on the die attach film (adhesive layer) 3a, the front main surface 2aa (first surface) of the semiconductor chip 2a from the lower surface (the lower surface in FIG. 8) of the die attach film 3a. The distance (overall height) to 1 (front side main surface) is greater than the distance (overall height) from the lower surface (lower surface in FIG. 8) to the upper surface (upper surface in FIG. 8) of the metal terminal 5. It is. Since the front main surface 2ba (second front main surface) of the upper semiconductor chip 2b (second semiconductor chip) is higher than the front main surface 2aa of the lower semiconductor chip 2a, the same Considering the connection with the metal terminal 5 in a planar position, the wire length tends to be longer in the interconnection with the upper semiconductor chip 2b. Therefore, as shown in FIG. 4, as far as the high-frequency signal bonding pad is concerned, the lower semiconductor chip 2a dares to avoid the closest metal terminal 5 and establish an interconnection, and the upper semiconductor chip 2b. As for the interconnection with the metal terminal 5, the closest metal terminal 5 is connected as much as possible.

  In the present embodiment, as shown in FIG. 5, among the plurality of bonding pads formed on the front main surface 2ba of the upper semiconductor chip 2b, the high-frequency signal bonding pad is on the second side 12 side. It is arranged only in. That is, no high frequency signal bonding pad is disposed on the side opposite to the second side. Therefore, bonding wires that are electrically connected to the upper semiconductor chip 2b are not connected to several (here, two) of the plurality of metal terminals 5 arranged on the right side in FIG. Therefore, among the plurality of high frequency signal bonding pads formed on the front main surface 2aa of the lower semiconductor chip 2a, the high frequency disposed on the right side (the right side in FIG. 5) of the semiconductor chip 2a. The signal bonding pad can be electrically connected to the metal terminal 5 closest to the bonding pad via a bonding wire. However, in this case, the length of the formed bonding wire is the shortest. In other words, it becomes shorter than the length of the bonding wire 6x electrically connected to the high frequency signal bonding pad of the upper semiconductor chip 2b. In the present embodiment, the frequency band handled by the high-frequency signal bonding pad arranged on the right side of the semiconductor chip 2a (the right side in FIG. 5) is the high-frequency signal bonding of the upper semiconductor chip 2b. The wire length is not adjusted because it is greatly different from the frequency band handled by the pad, but it may be preferable to maintain the impedance balance when the frequency band handled by each bonding pad is close. Therefore, as a modification of the present embodiment, of the plurality of high frequency signal bonding pads formed on the front main surface 2aa of the lower semiconductor chip 2a, the right side of the semiconductor chip 2a (as shown in FIG. 5). The high-frequency signal bonding pad arranged on the right side) is closest to the bonding pad like the high-frequency signal bonding wire located on the left side in FIG. 5 of the lower semiconductor chip 2a. You may electrically connect with the metal terminal 5 located farther than the metal terminal 5.

3. Description of a manufacturing method of an antenna switch module which is an example of the semiconductor device according to the embodiment of the present application (mainly FIGS.
In this section, an example of a manufacturing method related to the antenna switch module described in Section 2 will be schematically described. This example can be applied to the various modifications described in section 4 or 5 almost as it is, and therefore, redundant description will be omitted in principle.

  FIG. 12 is a process block flow diagram for explaining a method of manufacturing an antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 13 is a wafer cross-sectional view (wafer preparation process) in the middle of the manufacturing process for explaining a method of manufacturing the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 14 is a wafer cross-sectional view (back grinding process) in the middle of the manufacturing process for explaining a method of manufacturing the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 15 is a wafer cross-sectional view (DAF pasting step) in the middle of the manufacturing process for explaining the manufacturing method of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 16 is a perspective view (wafer dicing process) of a wafer or the like during the manufacturing process for explaining a method of manufacturing the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 17 is a wafer cross-sectional view (wafer dicing process) in the middle of the manufacturing process corresponding to FIG. 16 for describing the manufacturing method of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 18 is a cross-sectional view of a semiconductor chip or the like (die bonding process of the lower semiconductor chip) in the middle of the manufacturing process for explaining the manufacturing method of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. . FIG. 19 is a cross-sectional view of a semiconductor chip or the like in the middle of a manufacturing process (wire bonding process of the lower semiconductor chip) for explaining a method of manufacturing the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. . 20 is an enlarged cross-sectional view of the wedge bonding peripheral cutout portion R4 of FIG. FIG. 21 is an enlarged cross-sectional view of the ball bonding peripheral cutout portion R5 of FIG. FIG. 22 is a cross-sectional view (die bonding process of an upper semiconductor chip) of a semiconductor chip and the like in the middle of the manufacturing process for explaining a method of manufacturing the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 23 is a sectional view (wire bonding process of the upper semiconductor chip) of a semiconductor chip and the like in the middle of the manufacturing process for explaining a manufacturing method of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 24 is a cross-sectional view (resin sealing step) of a semiconductor chip or the like in the middle of a manufacturing process for explaining a method of manufacturing an antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. It is sectional drawing (metal base sheet peeling process) of the resin sealing body etc. in the middle of a manufacturing process for demonstrating the manufacturing method of the antenna switch module which is an example of the semiconductor device of the said one embodiment. FIG. 26 is a cross-sectional view (package dicing process) of a resin sealing body and the like in the middle of a manufacturing process for explaining a manufacturing method of an antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. Based on these, the manufacturing method of the antenna switch module which is an example of the semiconductor device of the one embodiment of the present application will be described.

  First, as shown in FIG. 13, a GaAs wafer 1 or the like that has almost completed the wafer process is prepared. On the surface opposite to the front-side main surface 1a (first main surface), that is, the back-side main surface 1b (second main surface) of the wafer 1, a device such as an antenna switch is formed. Normally, the lower semiconductor chip 2a and the upper semiconductor chip 2b are obtained from different wafers (upper chip wafer 1y and lower chip wafer 1x), so logically two wafers are obtained. It is necessary to prepare. However, for example, when the same size semiconductor chip or the like is manufactured on the same wafer, only a single wafer may be prepared.

  Next, as shown in FIG. 14, the back grinding steps 51a and 51b are performed in a state where the BG (Back Grinding) tape 33 is attached to the front main surface 1a of the wafer 1 (1x, 1y).

  Next, as shown in FIG. 15, a die attach film 3a (second adhesive layer) having a normal thickness (for example, about 30 micrometers) is formed on the back surface 1b of the lower chip wafer 1x and the upper chip wafer 1y. Then, a die attach film 3b (first adhesive layer) of a thick film (for example, about 60 micrometers) is pasted (normal DAF pasting step 52a, thick film DAF pasting step 52b in FIG. 12).

  Next, as shown in FIGS. 16 and 17, the back surface 1b of the lower chip wafer 1x and the upper chip wafer 1y are fixed to the dicing frame 31 via the dicing tape 32, respectively. Subsequently, in this state, a dicing groove 34 (dicing line) is formed in the XY directions (directions orthogonal to each other) by a rotating blade or the like, so that the lower chip wafer 1x and the upper chip wafer 1y are individually separated from each other. The semiconductor chip 2a (first semiconductor chip) and the upper semiconductor chip 2b (second semiconductor chip) are separated (wafer dicing steps 53a and 53b in FIG. 12).

  Next, as shown in FIG. 18, for example, a plurality of metal terminals 5 (external) are formed on a metal base sheet 4 (for example, about 0.15 mm thick) made of a thin plate such as stainless steel by electroplating or the like. Terminal). That is, a resist film of about 50 micrometers, for example, is attached to the upper surface of the cleaned stainless steel plate 4, and an opening pattern corresponding to the external terminal is formed by a photolithography technique. Subsequently, a gold plating layer of about 0.3 micrometers is formed in this opening by electroplating (in addition, there are tin, solder, palladium, etc.). As the gold plating solution, a non-cyanide gold plating solution containing, for example, gold sulfite is preferable from the environmental viewpoint, but a cyan gold plating solution may also be used. Further, a nickel layer of about 60 micrometers is formed thereon by electroplating. As the nickel plating solution, a nickel sulfamate-based one is suitable for the electroforming process, but other conventional nickel plating solutions may be used. Finally, a silver layer of, for example, about 5 micrometers is formed by electroplating (a gold layer may be used, but it is slightly noble). Examples of the silver plating solution include a cyan silver plating solution. Thereafter, the resist film is removed to obtain a structure having the metal terminals 5. The gold plating layer (mounting metal film) and the silver plating layer (wire bonding metal film) are not essential.

  Subsequently, the individually separated lower semiconductor chips 2a on the dicing tape 32 are picked up, and the front-side main surface 2aa (first front-side main surface) is placed on the metal base sheet 4 via the die attach film 3a. Then, die bonding is performed so that the upper side faces upward (die bonding step 54a corresponding to the lower semiconductor chip in FIG. 12). The die bonding temperature is, for example, about 80 degrees Celsius.

  Subsequently, a baking process (for example, about 160 degrees Celsius) for proceeding the curing of the die attach film 3a is executed (post-die bonding baking process 55a corresponding to the lower semiconductor chip in FIG. 12).

  Next, as shown in FIG. 19, the bonding pad 8 (FIG. 20) on the front main surface 2aa of the lower semiconductor chip 2a and the metal terminal 5 are reverse-bonded using a bonding wire 6 such as a gold wire. The wire bonding step (wire bonding step 56a corresponding to the lower semiconductor chip in FIG. 12) is executed by this method. That is, as shown in FIG. 20, the bonding pad 8 side is the wedge bonding portion 6w (second bonding portion of the bonding wire), and as shown in FIG. 21, the metal terminal 5 side is the ball bonding portion 6b (bonding wire). 1st bonding part).

  Next, as shown in FIG. 22, the individually separated upper semiconductor chips 2b on the dicing tape 32 (FIG. 16 or FIG. 17) are picked up and placed on the front main surface 2aa of the lower semiconductor chip 2a. Through the die attach film 3b, die bonding is performed such that the front main surface 2ba (second front main surface) faces upward (die bonding step 54b corresponding to the upper semiconductor chip in FIG. 12). The die bonding temperature is, for example, about 80 degrees Celsius.

  Subsequently, a baking process (for example, about 160 degrees Celsius) for proceeding the curing of the die attach film 3b is performed (post-die bonding baking process 55b corresponding to the upper semiconductor chip in FIG. 12).

  Next, as shown in FIG. 23, a reverse bonding method is performed using a bonding wire 6 such as a gold wire between the bonding pad 8 (FIG. 9) on the front main surface 2ba of the upper semiconductor chip 2b and the metal terminal 5. Then, a wire bonding step (wire bonding step 56b corresponding to the lower semiconductor chip in FIG. 12) is executed. That is, as shown in FIG. 20, the bonding pad 8 side is the wedge bonding part 6w (second bonding part of the bonding wire), and as shown in FIG. 21, the metal terminal 5 side is the ball bonding part 6b (bonding wire). 1st bonding part).

  Next, as shown in FIG. 24, a chip-terminal assembly composed of semiconductor chips 2a, 2b, metal terminals 5, wires 6 and the like integrated on a metal base sheet 4 (stainless steel sheet) is formed into a mold mold cavity or the like. The upper surface portion of the metal base sheet 4 is sealed by using, for example, an epoxy resin or the like, for example, by transfer molding (or compression molding may be used) to form the resin sealing body 9 (FIG. 12). Molding step 57).

  Subsequently, a post mold bake 58 (FIG. 12) for final curing of the sealing resin member is executed by, for example, a batch process. As suitable baking conditions, about several hours (for example, about 5 hours) can be illustrated in the range of 170 to 180 degrees Celsius (for example, 175 degrees).

  Next, as shown in FIG. 25, the metal base sheet 4 on the back surface 9b of the resin sealing body 9 is peeled off (metal plate peeling step in FIG. 12).

  Next, as shown in FIG. 26, the resin sealing body 9 is separated into individual packages 10 by forming the dicing grooves 34 using, for example, a rotating blade (package dicing step 60 in FIG. 12).

4). Description of Modification Example (Stacking of Same Chip Size) of Antenna Switch Module Structure which is an Example of Semiconductor Device of One Embodiment of the Present Application (Mainly FIGS. 27 to 33)
The example described in this section is a modification of the antenna switch module described in sections 1 and 2. Here, only parts different from sections 1 and 2 will be described.

  FIG. 27 is a circuit configuration diagram of a mobile phone terminal for explaining a modified example (lamination of the same chip size) of the antenna switch module structure which is an example of the semiconductor device according to the embodiment of the present application. FIG. 28 is a schematic circuit diagram of an upper semiconductor chip constituting the modified example (FIG. 27) of the antenna switch module structure which is an example of the semiconductor device according to the embodiment of the present application. FIG. 29 is a connection between each bonding pad of the lower semiconductor chip and the external terminal of the antenna switch module in the modified example (FIG. 27) of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. It is a top view of the antenna switch module showing the relationship (the upper chip and the like are removed for easy viewing). FIG. 30 is a diagram mainly showing a position between each bonding pad of the upper semiconductor chip and an external terminal of the antenna switch module in the modification (FIG. 27) of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application. FIG. 6 is a top view of the antenna switch module showing the connection relationship (the upper sealing resin is removed for easy viewing). FIG. 31 is a schematic cross-sectional view of the entire antenna switch module corresponding to the modified example (FIG. 27) of the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application (corresponding to FIG. 8 in the basic mode). It is. FIG. 32 is an enlarged cross-sectional view of the wedge bonding peripheral cutout portion R2 of FIG. FIG. 33 is an enlarged top view of the antenna switch module local cutout region R6 of FIG. Based on these, a modified example (lamination of the same chip size) of the antenna switch module structure which is an example of the semiconductor device according to the embodiment of the present application will be described.

  As shown in FIG. 27, the difference from the antenna switch module described in sections 1 and 2 is that the upper semiconductor chip 2b (second semiconductor chip) covers not only a single frequency band but also a plurality of frequency bands. This is the point. Therefore, the role of each bonding pad of the different upper semiconductor chip 2b will be described based on FIG. 28 (corresponding to FIG. 3).

  Specifically, for example, the first semiconductor chip 2a includes a DCS (Digital Cellular System) and PCN in a low frequency band such as 800 MHz to 1 GHz and a high frequency band such as 1.7 GHz to 2.2 GHz. Mobile communication protocols such as (Personal Communication Services) are covered, and the second semiconductor chip 2b is a GSM having a low frequency band such as 800 MHz to 1 GHz and a high frequency band such as 1.7 GHz to 2.2 GHz. Covers mobile communication protocols such as (Global System for Mobile Communication).

  As shown in FIG. 28, an antenna switch SW2 is provided in a semiconductor chip 2b (for example, a GaAs-based compound semiconductor chip having dimensions of, for example, 0.8 millimeter square and about 0.1 millimeter thick). The connection to the antenna terminal Ab is selected from any one of the low-band input terminal Ib1, the low-band output terminal Ob1, the high-band input terminal Ib2, and the high-band output terminal Ob2, and is driven by the antenna. This is done via the switch control terminal Vbc. In addition to these, there are a power supply terminal Vbd and a ground terminal Gb.

  Here, as described above, the antenna terminal Ab, the low-band input terminal Ib1, the low-band output terminal Ob1, the high-band input terminal Ib2, the high-band output terminal Ob2, and the like have characteristics of signals handled by other terminals. Since they are different, they are referred to as “high-frequency signal terminals” or “high-frequency signal bonding pads” (or simply “signal terminals” or “signal bonding pads”). In addition, when particularly indicating that the signal is via an antenna, “terminal for high-frequency signal via antenna” or “bonding pad for high-frequency signal via antenna” (or simply “terminal for signal via antenna” or “signal via antenna” Bonding pad for use ") (the same applies to the terminals of the corresponding antenna switch module SWM below).

  Next, a bonding wire connection relationship between a planar bonding pad and external terminals will be described with reference to FIGS. As shown in FIG. 29, the plurality of external terminals 5 corresponding to the terminals of FIGS. 2 and 28 include an antenna terminal Aa, an antenna terminal Ab, a low-band input terminal Ia1, a low-band input terminal Ib1, a low-band output terminal Oa1, High-frequency signal metal terminals 5 (a metal terminal for signals or a metal terminal for high-frequency signals via an antenna, such as a low-band output terminal Ob1, a high-band input terminal Ia2, a high-band output terminal Oa2, a high-band input terminal Ib2, a high-band output terminal Ob2) ) And other metal terminals 5 such as an antenna switch control terminal Vac, an antenna switch control terminal Vbc, a power supply terminal Vad, a power supply terminal Vbd, a ground terminal Ga, and a ground terminal Gb. Here, for example, when attention is paid to the first high-frequency signal bonding pad group 14 provided along the first side 11 of the lower semiconductor chip 2a (first semiconductor chip), the first high-frequency signal bond The bonding pad 8a is not connected to the first high-frequency signal metal terminal 5a closest to the bonding pad 8a, but is connected to the second high-frequency signal metal terminal 5b farther away by the second bonding wire 6y.

  On the other hand, as shown in FIG. 30, the upper semiconductor chip 2b (second semiconductor chip) has a second side 12 that is substantially the same size as the lower semiconductor chip 2a (first semiconductor chip). And have substantially the same planar shape, are mounted so as to substantially coincide with the first side 11 of the semiconductor chip 2a, and are provided along the second side 12 on the upper semiconductor chip 2b. When attention is paid to the second high-frequency signal bonding pad 8b in the second high-frequency signal bonding pad group 15, the second high-frequency signal bonding pad 8b is the first high-frequency signal bonding pad 8b closest to the pad. The signal metal terminals 5a and the first bonding wires 6x are interconnected. Here, the suitable wire length of these wires is about 0.6 millimeters in this example, for example.

  That is, as shown in FIG. 31 (see FIG. 29 and FIG. 30), the metal terminal 5 (external terminal) has a lower semiconductor chip 2a as shown by an arrow LS indicating the height range of the upper surface of the metal terminal. Since the front side main surface 2aa (first front side main surface) of the (first semiconductor chip) or a plane including this is disposed on the back side main surface 2ab (first back side main surface) side, the metal The upper surface of the terminal 5 (external terminal) is lower than the front main surface 2aa of the lower semiconductor chip 2a. Since the front main surface 2ba (second front main surface) of the upper semiconductor chip 2b (second semiconductor chip) is higher than the front main surface 2aa of the lower semiconductor chip 2a, the same Considering the connection with the metal terminal 5 in a planar position, the wire length tends to be longer in the interconnection with the upper semiconductor chip 2b. Therefore, as shown in FIG. 29, as far as the high-frequency signal bonding pad is concerned, the lower semiconductor chip 2a dares to avoid the closest metal terminal 5 and establish an interconnection so that the upper semiconductor chip 2b. As for the interconnection with the metal terminal 5, the closest metal terminal 5 is connected as much as possible.

  32, as in FIGS. 9 to 11, the wires 6 are interconnected between the bonding pads 8 and the metal terminals 5 (external terminals) by the reverse bonding method. In this case, inevitably, one of the bonding wires 6 connecting the front side main surface 2aa (first front side main surface) of the lower semiconductor chip 2a (first semiconductor chip) and the metal terminal 5 (external terminal). The part is embedded in the die attach film 3b (first adhesive layer).

  In addition, when the upper and lower semiconductor chips are mounted so that the upper and lower semiconductor chips are substantially congruent and both sides coincide with each other as in this example, the two wires are sufficiently connected due to the chip thickness. There are cases where the lengths cannot be aligned. That is, when the connection is normal, the first bonding wire 6x is too long. In such a case, as shown in FIG. 33, the upper surface of each metal terminal 5 (external terminal) is an intersection line between the plane perpendicular to the extending direction of the wire 6 connected thereto and the upper surface of the metal terminal 5. With C1 and C2 (pad center lines orthogonal to the wire) as a boundary, the first bonding wire 6x is divided into two parts, the side closer to the bonding pad 8 and the side far from the interconnecting pad 8b, and the side closer to the bonding pad 8b. Bonding is performed, and the second bonding wire 6y may be bonded to the side far from the first high-frequency signal bonding pad 8a.

5. Description of modification of chip arrangement in antenna switch module which is an example of semiconductor device of one embodiment of the present application (mainly FIG. 34 and FIG. 35)
The modification described in this section corresponds to FIG. 8 in section 2, and is a bonding pad 8 (or a stud bump 7 thereon) on the front main surface 2aa of the upper semiconductor chip 2b and the lower semiconductor chip 2a. That is, it relates to the mutual relationship with the wedge bonding portion 6w of the bonding wire (second bonding portion of the bonding wire). In each of the following drawings, the connection relationship between the bonding pad and the external terminal is substantially the same except for the relationship between the center of the upper and lower chips, and the description thereof will not be repeated here.

  In addition, as shown in the following figures, the functionally corresponding high frequency signal bonding pads of the upper and lower chips are basically spatially close to each other. However, it is not essential to be close to each other.

  FIG. 34 is a basic form of FIG. 8 showing Modification Example 1 of the chip arrangement in the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application (when the upper chip does not overlap the wire of the lower chip). It is a corresponding typical sectional view. FIG. 35 is a basic configuration showing a second modification of the chip arrangement in the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application (when the upper chip overlaps a part of the bonding pad of the lower chip). FIG. 9 is a schematic cross-sectional view corresponding to FIG. 8. Based on these, a modification of the chip arrangement in the antenna switch module which is an example of the semiconductor device according to the embodiment of the present application will be described.

  In the example of FIG. 8, the upper semiconductor chip 2b is arranged eccentrically, and a part of the bonding pads 8 on the front main surface 2aa of the lower semiconductor chip 2a is attached to the die attach film 3b (first The adhesive layer) is almost completely covered. In other words, the upper semiconductor chip 2b in plan view overlaps with a part of the bonding pads 8 on the front main surface 2aa of the lower semiconductor chip 2a.

  On the other hand, in the example of FIG. 34, the upper semiconductor chip 2b is not decentered (may be decentered), and is flat with any bonding pad 8 on the front main surface 2aa of the lower semiconductor chip 2a. Does not overlap. In the present modification, the central portion of the front side main surface 2ba (or back side main surface 2bb) of the upper semiconductor chip 2b is the front side main surface 2aa (or back side main surface) of the lower semiconductor chip 2a. The upper semiconductor chip 2b is arranged (mounted or stacked) on the lower semiconductor chip 2a so as to overlap with the central portion of the surface 2ab).

  On the other hand, in the example of FIG. 35, the upper semiconductor chip 2b is not decentered (may be decentered), but it is planar with at least some of the bonding pads 8 on the front main surface 2aa of the lower semiconductor chip 2a. It overlaps. In the examples of FIGS. 34 and 35, the bonding method applied in FIGS. 4, 5, 29, 30, and 33 can be applied.

6). Considerations and Supplementary Explanations for the Embodiments, etc. In this section, general considerations and supplementary explanations relating to the present invention, the above-described embodiments, modifications, and the like are given.

  In each of the embodiments and modifications, corresponding to the improvement in the arrangement of the wire bonding pads to be aligned with each other on the plurality of chips arranged in the vertical direction close to each other and the arrangement of the external terminals corresponding thereto. Yes. In other words, the positional relationship of the external terminals to be connected to the wire bonding pads of the upper chip is preferentially arranged closest to each other, and the positional relationship of the external terminals to be connected to the wire bonding pads of the lower chip to be paired therewith is determined. By deliberately separating them, both wire lengths are made substantially the same.

  This is because, for example, in an antenna switch module in a mobile terminal such as a mobile phone, the wavelength of a signal to be handled is about the same as the wire length, so that, for example, the same function (for example, output) This is because a pair of wire bonding pads having a terminal needs to have substantially the same wire length.

  Needless to say, the need to align such wire lengths between certain bonding pad groups is not limited to the above example, and may be necessary for various reasons.

7). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the present invention has been specifically described mainly using a non-lead type package as an example. However, the present invention is not limited to this and can be applied to other packages.

  In the above-described embodiment, the present invention has been specifically described mainly using a high-frequency antenna module (multichip module) as an example. However, the present invention is not limited to this, and other applications such as a multichip module, etc. Needless to say, it can also be applied. Furthermore, the combination of mounted chips is not limited to a combination of a silicon-based semiconductor chip and a GaAs (or AlGaAs) -based semiconductor chip (compound-based semiconductor chip). A combination with a chip may be used.

  In the above-described embodiment, the manufacturing process of the present invention has been specifically described by taking a MAP (Mold Array Package) process as an example. However, the present invention is not limited thereto, and an individual sealing type packaging process. Needless to say, it can also be applied.

1 Wafer (GaAs wafer)
1a Front side main surface of wafer (first main surface)
1b Wafer back main surface (second main surface)
1x Lower chip wafer 1y Upper chip wafer 2 Semiconductor chip or chip area (GaAs chip)
2a Lower semiconductor chip (first semiconductor chip)
2aa Front side main surface of the lower semiconductor chip (first front side main surface)
2ab Back side main surface of the lower semiconductor chip (first back side main surface)
2b Upper semiconductor chip (second semiconductor chip)
2ba Front main surface of the upper semiconductor chip (second front main surface)
2bb Back side main surface of upper semiconductor chip (second back side main surface)
3 Adhesive layer or die attach film (DAF)
3a Normal thickness die attach film 3a (second adhesive layer)
3b Thick film die attach film (first adhesive layer)
4 Metal base sheet (stainless steel sheet)
5 Metal terminal (external terminal)
5a First high-frequency signal metal terminal 5b Second high-frequency signal metal terminal 6 Bonding wire 6b Ball bonding portion of bonding wire (first bonding portion of bonding wire)
6w Wedge bonding part of bonding wire (second bonding part of bonding wire)
6x 1st bonding wire 6y 2nd bonding wire 7 Stud bump 8 Bonding pad (gold bonding pad)
8a First high frequency signal bonding pad 8b Second high frequency signal bonding pad 9 Resin sealing body or sealing resin member 9a Resin sealing body or top surface of semiconductor package 9b Resin sealing body or bottom surface of semiconductor package 10 Semiconductor Package 11 First side 12 Second side 14 First high frequency signal bonding pad group 15 Second high frequency signal bonding pad group 31 Dicing frame 32 Dicing tape 33 BG tape 34 Dicing groove (dicing line)
51a Wafer backside grinding process corresponding to lower semiconductor chip 51b Wafer backside grinding process corresponding to upper semiconductor chip 52a Normal DAF adhering process corresponding to lower semiconductor chip 52b Thickness corresponding to upper semiconductor chip Film DAF pasting process 53a Wafer dicing process corresponding to lower semiconductor chip 53b Wafer dicing process corresponding to upper semiconductor chip 54a Die bonding process corresponding to lower semiconductor chip 54b Die bonding corresponding to upper semiconductor chip Step 55a Post-die bonding baking step corresponding to the lower semiconductor chip 55b Post-die bonding baking step corresponding to the upper semiconductor chip 56a Wire bonding step corresponding to the lower semiconductor chip 56b Corresponding to the upper semiconductor chip Ear bonding step 57 molding step 58 post mold bake step 59 the metal plate peeling step 60 package dicing step Aa lower side of the semiconductor chip antenna terminal (or the corresponding bonding pads)
Ab Antenna terminal of upper semiconductor chip (or corresponding bonding pad)
ANT antenna BB Baseband circuit C1, C2 Pad center line orthogonal to wire Ia1 Low-band input terminal (or corresponding bonding pad) of lower semiconductor chip
Ia2 High-band input terminal (or corresponding bonding pad) of lower semiconductor chip
Low-band input terminal (or corresponding bonding pad) of Ib1 upper semiconductor chip
Ib2 High band input terminal (or corresponding bonding pad) of upper semiconductor chip
IF interface circuit Ga Ground terminal of the lower semiconductor chip (or corresponding bonding pad)
Gb Ground terminal of upper semiconductor chip (or corresponding bonding pad)
MP Microphone LCD Liquid crystal display & input keys, etc. LS Arrow indicating the height range of the upper surface of the metal terminal Oa1 Low band output terminal (or corresponding bonding pad) of the lower semiconductor chip
Oa2 High-band output terminal (or corresponding bonding pad) of lower semiconductor chip
Ob1 Low band output terminal of the upper semiconductor chip (or corresponding bonding pad)
Ob2 High band output terminal of upper semiconductor chip (or corresponding bonding pad)
R1 Wedge bonding peripheral cutout portion R2 Wedge bonding peripheral cutout portion R3 Ball bonding peripheral cutout portion R4 Wedge bonding peripheral cutout portion R5 Ball bonding peripheral cutout portion R6 Antenna switch module local cutout region RFIC High frequency signal processing chip RFM High frequency module SP Speaker or earphone SW1 Antenna switch SW2 in the lower semiconductor chip Antenna switch SWM in the upper semiconductor chip SWM Antenna switch module T1 DAF thickness of the lower semiconductor chip (thickness of the second adhesive layer)
T2 DAF thickness of upper semiconductor chip (distance between upper and lower chips or thickness of first adhesive layer)
Vac lower semiconductor chip antenna switch control terminal (or corresponding bonding pad)
Vad Power supply terminal of lower semiconductor chip (or corresponding bonding pad)
Vbc Antenna switch control terminal (or corresponding bonding pad) of upper semiconductor chip
Vbd Power supply terminal (or corresponding bonding pad) of upper semiconductor chip
WC Distance between the upper edge of the side of the wire of the lower chip and the lower surface of the upper chip WD Wire diameter WH Horizontal part wire lower surface height (Stud bump height)

Claims (20)

Semiconductor devices including:
(A) a first semiconductor chip having a first front side main surface and a first back side main surface and having a rectangular shape;
(B) a second semiconductor chip mounted on the first front main surface of the first semiconductor chip and having a second front main surface and a second back main surface and having a rectangular shape;
(C) a first high-frequency signal bonding pad provided on the first front main surface of the first semiconductor chip;
(D) a second high-frequency signal bonding pad provided on the second front main surface of the second semiconductor chip so as to be close to the first high-frequency signal bonding pad;
(E) The first side of the first semiconductor chip outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface. A first high-frequency signal external terminal provided along the line;
(F) a second external terminal for high frequency signals provided outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface;
Here, the first high-frequency signal external terminal is closer to the first high-frequency signal bonding pad than the second high-frequency signal external terminal, and the semiconductor device further includes: including:
(G) a first bonding wire that interconnects the second high-frequency signal bonding pad and the first high-frequency signal external terminal;
(H) A second bonding wire for interconnecting the first high-frequency signal bonding pad and the second high-frequency signal external terminal.     2. The semiconductor device according to the item 1, wherein the second semiconductor chip is on the first semiconductor chip and is planarly formed inside the first front main surface with the first adhesive layer interposed therebetween. Mounted and a portion of the second bonding wire is in the first adhesive layer. The semiconductor device according to the item 2, further includes:
(I) a first high-frequency signal bonding pad group including the first high-frequency signal bonding pad provided on the first front main surface along the first side;
(J) A second layer provided on the second front main surface along the second side of the second semiconductor chip along the first side and including the second high-frequency signal bonding pad. 2 High frequency signal bonding pads.     In the semiconductor device of the item 3, the second semiconductor chip is mounted eccentrically so that the second side is close to the first side. The semiconductor device according to the item 4, further includes:
(K) a first grounding bonding pad provided on the first front main surface in the vicinity of one side of the first semiconductor chip;
(L) A second ground bonding pad provided on the second front main surface in the vicinity of the other one side of the second semiconductor chip along the one side.     5. In the semiconductor device according to the item 5, the second high-frequency signal bonding pad and the first bonding wire, and the first high-frequency signal bonding pad and the second bonding wire are respectively connected via stud bumps. Connected.     In the semiconductor device according to Item 6, the thickness of the first adhesive layer is larger than the sum of the height of the stud bump and the wire diameter.     8. The semiconductor device according to 7 above, wherein the height of the stud bump, the diameter of the second bonding wire, and the upper end of the side surface of the second backside main surface and the second bonding wire of the second semiconductor chip. Are approximately equal to each other. The semiconductor device of item 8, further includes:
(M) the first semiconductor chip, the second semiconductor chip, the first high-frequency signal external terminal, the second high-frequency signal external terminal, the first bonding wire, and the second bonding A sealing resin body for integrally sealing the wire;
(N) a second adhesive layer covering the first back main surface of the first semiconductor chip;
Here, the lower surface of the second adhesive layer is exposed from the lower surface of the sealing resin body.     In the semiconductor device according to the item 9, the first bonding wire and the second bonding wire are bonded by a reverse bonding method.     In the semiconductor device according to the item 10, each of the first semiconductor chip and the second semiconductor chip includes an antenna switch.     12. In the semiconductor device of the item 11, each high frequency signal bonding pad constituting the first high frequency signal bonding pad group and the second high frequency signal bonding pad group is a high frequency signal bonding pad via an antenna.     12. The semiconductor device according to the item 12, wherein the first high-frequency signal bonding pad and the second high-frequency signal bonding pad are antenna high-frequency signal bonding pads in the same frequency band.     14. The semiconductor device according to item 13, wherein each of the first adhesive layer and the second adhesive layer is a DAF member.     14. The semiconductor device according to item 14, wherein the package format of the semiconductor device is a PLP method.     In the semiconductor device of the item 1, the first semiconductor chip and the second semiconductor chip are mounted so as to have substantially the same size and their sides substantially coincide with each other.     16. The semiconductor device according to item 16, wherein the first bonding wire is bonded to a side of the first high-frequency signal external terminal close to the second high-frequency signal bonding pad, and the second bonding wire. Are bonded to a side of the second high frequency signal external terminal close to the first high frequency signal bonding pad.     In the semiconductor device according to the item 5, the one side and the other side are different from the first side and the second side, respectively.     In the semiconductor device of the item 1, the first high-frequency signal external terminal has a function of either an input terminal or an output terminal, and the second high-frequency signal external terminal has the one function. Has the same function. Semiconductor devices including:
(A) a first semiconductor chip having a first front side main surface and a first back side main surface and having a rectangular shape;
(B) a second semiconductor chip mounted on the first front main surface of the first semiconductor chip and having a second front main surface and a second back main surface and having a rectangular shape;
(C) a first high-frequency signal bonding pad provided on the first front main surface of the first semiconductor chip;
(D) a second high-frequency signal bonding pad provided on the second front main surface of the second semiconductor chip;
(E) The first side of the first semiconductor chip outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface. A first high-frequency signal external terminal provided along the line;
(F) a second external terminal for high frequency signals provided outside the first semiconductor chip and the second semiconductor chip and on the first back side main surface side with respect to the first front side main surface;
Here, the first high-frequency signal external terminal is closer to the first high-frequency signal bonding pad than the second high-frequency signal external terminal, and the semiconductor device further includes: including:
(G) a first bonding wire that interconnects the second high-frequency signal bonding pad and the first high-frequency signal external terminal;
(H) A second bonding wire for interconnecting the first high-frequency signal bonding pad and the second high-frequency signal external terminal.

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