JP2012195665A - Reception apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the decoding accuracy of Viterbi decoding circuits.SOLUTION: A reception apparatus for receiving a radio signal includes: a plurality of reception sections each having at least a Viterbi decoder for Viterbi-decoding convolution-encoded data and a trace-back length control section for controlling a trace-back length to be used in Viterbi-decoding the convolution-encoded data; a parallel path memory shared to save survivor paths when the plurality of reception sections Viterbi-decode the convolution-encoded data; and a memory control section for controlling a parallel path memory usage to be used by each reception section according to a trace-back length to be controlled by the plurality of reception sections.

Description

  The present invention relates to a receiving apparatus.

  In Viterbi decoding, which is maximum likelihood decoding of a convolutional code, which is one of error correction codes used in digital wireless communication and the like, it is known that the decoding error decreases when the traceback length is increased. Therefore, a method is known that reduces the processing time and power consumption of the circuit when the traceback length is shortened by dynamically changing the traceback length for each received frame to shorten the decoding performance.

  In addition, a method for increasing the decoding speed by dividing a memory used in the Viterbi decoding circuit and performing a traceback process in parallel is already known.

  Furthermore, in recent years, further reduction in power consumption of circuits has been demanded from the viewpoint of mounting digital wireless communication functions on mobile devices and environmental considerations.

  In addition, it is also required that one mobile device can communicate with a plurality of communication methods.

  In an apparatus that changes the traceback length, the power consumption is merely reduced by shortening the processing time by shortening the traceback length. That is, by shortening the traceback length, a memory that does not need to be used for the decoding process is generated among the divided memories to be used in the Viterbi decoding circuit. However, since this unnecessary memory continues to operate during the decoding process, power is wasted.

  A single device may be equipped with a plurality of decoding circuits. Each decoding circuit corresponds to a different communication method and performs Viterbi decoding processing together. In this case, since a plurality of decoding circuits manage the memories separately, the memory capacity increases.

  Furthermore, generally speaking, if the number of divided memories used for Viterbi decoding is increased, the accuracy of Viterbi decoding is further improved. However, in practice, the accuracy of the decoding process cannot be increased by increasing the number of divided memories used for Viterbi decoding due to severe restrictions on increasing the memory and circuit capacity.

  In order to improve the error rate characteristics of the maximum likelihood decoder, the traceback length is increased by decoding the header of the received data based on the wireless LAN (IEEE (The Institute of Electrical and Electronics Engineers) 802.11a) frame format. It is known to improve the reliability of received frames by controlling (see, for example, Patent Document 1). By controlling the traceback length using the header of the received data, it is possible to improve throughput and reduce retransmission requests. As a result, the power consumption of the transceiver can be reduced.

  However, since a memory that does not need to be used for the Viterbi decoding process continues to operate during the process, power is wasted.

  In addition, a plurality of Viterbi decoding circuits do not share a memory, and when a plurality of receivers are combined, the traceback length cannot be collectively controlled.

  Therefore, the present invention has been made in view of at least one of the above-described problems, and an object thereof is to improve decoding accuracy in a Viterbi decoding circuit.

This receiving device
A receiving device for receiving a radio signal,
A plurality having at least a Viterbi decoder that performs Viterbi decoding on convolutionally encoded data, and a traceback length control unit that controls a traceback length to be used in Viterbi decoding the convolutionally encoded data The receiver of
A parallel path memory shared to store a survivor path when the convolutionally encoded data is Viterbi-decoded by the plurality of receivers;
And a memory control unit that controls the parallel path memory usage to be used by each receiving unit based on a traceback length to be controlled by the plurality of receiving units.

  According to the disclosed embodiment, the decoding accuracy in the Viterbi decoding circuit can be improved.

It is a figure which shows an example of a convolutional encoder. It is a figure which shows an example of the trellis produced in the case of Viterbi decoding. It is a figure which shows an example of a data frame structure. It is a functional block diagram which shows one Example of a receiver. It is a functional block diagram which shows one Example of the receiving part of a receiver. It is a flowchart which shows one Example of a process of a receiver. It is a figure which shows one Example of a parallel traceback process. It is a figure which shows one Example of a parallel traceback process. It is a functional block diagram which shows one Example of a receiver. It is a functional block diagram which shows one Example of the receiving part of a receiver. It is a flowchart which shows one Example of a process of a receiver. It is a figure which shows one Example of a parallel traceback process. It is a functional block diagram which shows one Example of a receiver. It is a flowchart which shows one Example of a process of a receiver. It is a functional block diagram which shows one Example of a receiver. It is a flowchart which shows one Example of a process of a receiver. It is a flowchart which shows one Example of a process of a receiver. It is a flowchart which shows one Example of a process of a receiver. It is a flowchart which shows one Example of a process of a receiver.

Next, the form for implementing this invention is demonstrated, referring drawings based on the following Examples.
In all the drawings for explaining the embodiments, the same reference numerals are used for those having the same function, and repeated explanation is omitted.

<Example>
<Receiving device>
The receiving apparatus according to the present embodiment receives convolutionally encoded data.

  The receiving apparatus has a plurality of receiving units. That is, it has a plurality of receiving systems. After receiving the data, the receiving apparatus performs maximum likelihood decoding by Viterbi decoding. The maximum likelihood decoding is performed in parallel by using memories connected in parallel (hereinafter referred to as “parallel path memory”). The reception apparatus shares and manages a parallel path memory used for Viterbi decoding when performing reception processing in a plurality of reception systems. By sharing and managing the parallel path memory used for Viterbi decoding, the power consumption in the receiving circuit can be reduced. Also, the reception accuracy in the Viterbi decoder can be improved.

  For example, a case where two Viterbi decoding circuits are provided will be described. When one Viterbi decoding circuit is not used, the traceback length in the other Viterbi decoding circuit is increased. By increasing the traceback length in the other Viterbi decoding circuit, the usage amount of the parallel path memory can be increased, so that the decoding accuracy of the Viterbi decoding circuit can be improved.

  Specifically, in the Viterbi decoding circuit in one receiving unit, the receiving apparatus uses the information included in the header of the received data to control the traceback length. When the path memory is shared and used by a plurality of Viterbi decoding circuits, the receiving apparatus determines a method of using the parallel path memory based on the traceback length to be controlled by each receiving unit.

  By controlling the parallel path memories that are shared and used collectively, the decoding accuracy in Viterbi decoding can be improved when the traceback length is long and there is something that increases the parallel memory to be used. .

<Convolution encoder>
FIG. 1 shows an example of a convolutional encoder.

  The convolutional encoder shown in FIG. 1 has a shift register D1 and a shift register D2. The convolutional encoder outputs codewords OUT1 and OUT2 by exclusive OR of the values of the 1-bit input IN and the shift registers D1 and D2.

  In the convolutional encoder shown in FIG. 1, the constraint length is 3, the states represented by the shift register D1 and the shift register D2 are {00, 01, 10, 11}, and the total number of states is 4.

  Note that convolutional codes are often adopted in communication standards. For example, it is adopted in IEEE (The Institute of Electrical and Electronics Engineers, Inc.) 802.11 adopted in wireless LAN (Local Area Network), satellite communication, terrestrial digital broadcasting, and the like.

  FIG. 2 shows an example of a part of a trellis created during Viterbi decoding.

  FIG. 2 shows a part of a trellis created when Viterbi decoding a codeword created by the convolutional encoder shown in FIG. A trellis represents a temporal transition of a state. In FIG. 2, a solid line is a path when 0 is input from each state, and a broken line is a path when 1 is input.

  In Viterbi decoding, when decoding is performed from a received codeword, the most likely path is selected from all possible paths on the trellis, and traceback is performed to perform decoding.

  Consider decoding a codeword created by the convolutional encoder shown in FIG.

  The received data is truncated to a certain length. In other words, the received data is divided into a certain length. After truncation, it is divided into 2-bit received words, and the distance from possible codewords is calculated. This distance is called a branch distance.

  After calculating distances for all received words, surviving paths are selected in the order of received words, and after selecting surviving paths for all transitions, traceback is performed on the surviving paths.

  After the traceback is performed, a result corresponding to the input of the surviving path is set as a decoding result. However, at this time, all the surviving paths are not decrypted but a part thereof is discarded. Here, the number of state transitions on the trellis that is only tracebacked and not the decoding result is traceback length and traceback to obtain the decoding result (this process is called decoding). The number of state transitions on the trellis is the decode length.

<Data frame>
FIG. 3 shows a configuration example of the data frame.

  FIG. 3 shows a configuration example of a data frame defined by the standard “Multiband OFDM Physical Layer Specification Approved Draft 1.2” defined by WiMedia Alliance, Inc. The standard is a physical layer standard adopted in a wireless USB (Universal Serial Bus) standard that employs an ultra wide band (UWB) wireless communication system.

  In FIG. 3, the arrow indicates the time direction. The frame structure is temporally followed by preamble, header, and PSDU (Physical layer convergence protocol Service Data Unit).

  The preamble is required for packet detection, gain control, phase shift correction, and the like. The preamble is a value determined in advance by the standard.

  In the header, the PSDU data rate (RATE) following the header, the length of the PSDU data rate (LENGTH), and the like are described according to a format defined by the standard. The data rate of the header is constant.

  The PSDU includes data to be originally transferred and error detection codewords for data to be originally transferred called FCS (Frame Check Sequence). The PSDU data rate varies depending on the data encoding method. The standard defines eight types of 53.3 [Mbps], 80 [Mbps], 106.7 [Mbps], 160 [Mbps], 200 [Mbps], 320 [Mbps], 400 [Mbps], and 480 [Mbps].

  At the time of reception, data describing the received signal quality is added to the end of the data frame shown in FIG.

<Receiving device>
FIG. 4 shows an embodiment of the receiving device 100.

The receiving apparatus 100 has a plurality of receiving systems. The plurality of receiving systems are represented by a receiving unit 102 _n (n is an integer satisfying n> 1). In the present embodiment, as an example, a case will be described in which the receiving apparatus 100 has two receiving systems, and each of the two receiving systems has a receiving unit 102 ₁ and a receiving unit 102 ₂ . Three or more reception systems may be provided, and each of the three or more reception systems may have a respective reception unit.

The receiving unit 102 _n includes a Viterbi decoder 1020 _n and a traceback length control unit 1100 _n that controls the traceback length used in Viterbi decoding.

The Viterbi decoder 1020 _n shares a parallel path memory (shared parallel path memory) 1300 to be used for decoding. The Viterbi decoder 1020 _n performs decoding using the parallel path memory 1300.

The receiving apparatus 100 includes an all trace back length control unit 1400. The total traceback length control unit 1400 uses the traceback lengths to be set in the traceback length control units 1100 ₁ and 1100 ₂ in the receiving units 102 ₁ and 102 ₂ , and uses a plurality of Viterbi decoders 1020 ₁ , controlling the parallel path memory shared parallel paths in the memory to be used by 1020 _2.

<Details of the receiver>
FIG. 5 shows details of the receiving unit 102 _n .

Among the parallel path memories included in the shared parallel path memory 1300 shown in FIG. 4, the parallel path memory used by the Viterbi decoder 1020 _n for Viterbi decoding is a first memory 1300 ₁ and a second memory 1300 _2. A case will be described in which there are six of the third memory 1300 ₃ , the fourth memory 1300 ₄ , the fifth memory 1300 ₅ , and the sixth memory 1300 ₆ .

Further, in the receiving unit 102 _n shown in FIG. 5, the convolutional encoder constraint length is 7, the convolutional code total number is 64, the Viterbi decoding traceback length is 60, and the Viterbi decoding decoding length is 30. explain.

The receiving unit 102 _n includes a Viterbi decoder 1020 _n . The Viterbi decoder 1020 _n decodes the convolutionally encoded data.

The receiving unit 102 _n includes a traceback length control unit 1100 _n . The traceback length control unit 1100 _n controls the traceback length of parameters used in the Viterbi decoder 1020 _n from the data described in the header of the received data frame.

The receiving unit 102 _n includes a header analyzing unit 1200 _n . The header analysis unit 1200 _n uses the header of the decoded data to read information in the header.

The Viterbi decoder 1020 _n has a branch distance calculation unit 1021 _n . The branch distance calculation unit 1021 _n calculates the distance between the received data frame and the convolutional codeword. The Viterbi decoder 1020 _n inputs the calculation result of the distance between the received data frame and the convolutional codeword to the comparison / selection unit 1022 _n .

The Viterbi decoder 1020 _n includes a comparison / selection unit 1022 _n . The comparison / selection unit 1022 _n selects a surviving path using the calculation result of the distance between the received data frame and the convolutional codeword to be input by the branch distance calculation unit 1021 _n . The comparison / selection unit 1022 _n inputs the survivor path information to the survivor path storage unit 1023 _n . Information of the surviving path is stored in the survivor path storage unit 1023 _n.

The shared parallel path memory 1300 includes a first memory 1300 ₁ , a second memory 1300 ₂ , a third memory 1300 ₃ , a fourth memory 1300 ₄ , a fifth memory 1300 ₅ , and a sixth memory 1300 _6. included. For example, the capacity of each memory may be 1920 (= 30 * 64) bit RAM (Random Access Memory).

The Viterbi decoder 1020 _n includes a write destination memory selection unit 1024 _n . The write destination memory selection unit 1024 _n includes a first memory 1300 ₁ , a second memory 1300 ₂ , a third memory 1300 ₃ , a fourth memory 1300 ₄ , a fifth memory 1300 ₅ , and a sixth memory 1300. ₆ to select one, to the selected memory, it writes the survivor path.

The Viterbi decoder 1020 _n has a read source memory selection unit 1025 _n . The reading source memory selection unit 1025 _n includes a first memory 1300 ₁ , a second memory 1300 ₂ , a third memory 1300 ₃ , a fourth memory 1300 ₄ , a fifth memory 1300 ₅ , and a sixth memory 1300. Select one from ₆ and read the survivor path.

The Viterbi decoder 1020 _n has a traceback unit 1026 _n . The traceback unit 1026 _n reads the surviving path written in the shared parallel path memory 1300 to perform traceback and decoding.

The traceback unit 1026 _n includes a parallel traceback selection unit 1027 _n . The parallel traceback selection unit 1027 _n selects any one of the first parallel traceback unit 10281 _n , the second parallel traceback unit 10282 _n , and the third parallel traceback unit 10283 _n. Causes a traceback to be performed.

The traceback unit 1026 _n includes a plurality of parallel traceback units 10281 _{n to} 10283 _n . The parallel traceback units 10281 _{n to} 10283 _n perform traceback. FIG. 5 shows three parallel traceback units 10281 _{n to} 10283 _n as an example, but may be two or four or more. The parallel traceback units 10281 _{n to} 10283 _n input the decoded data to be obtained by the traceback process to one of a first LIFO (Last In First Out) memory 10291 _n and a second LIFO 10292 _n .

The traceback unit 1026 _n has a plurality of LIFOs. 5 shows, as an example, the first LIFO10291 _n, the second LIFO10292 _n shown. Three or more LIFOs may be prepared. First LIFO10291 _n, among the second LIFO10292 _n, from one of the parallel trace-back unit 10281 _n -10283 _n, LIFO decoded data is input, stores the the decoded data. A LIFO to which no decoded data is input outputs the decoded data.

<Operation of this receiver>
FIG. 6 is a flowchart showing the operation of the receiving apparatus 100.

In the flowchart shown in FIG. 6, the Viterbi decoding process is performed using a part of the parallel path memory included in the shared parallel path memory 1300 using the header information obtained from the header analysis unit 1200 _n . Of the parallel path memories included in the shared parallel path memory 1300, parallel path memories other than the parallel path memory used are not used.

Similar processing is performed in both the receiving unit 102 ₁ and the receiving unit 102 ₂ shown in FIG.

  In the example shown in FIG. 6, the case where one data frame is received is shown.

All six parallel path memories included in the shared parallel path memory 1300 stored by the surviving path storage unit 1023 _n and all three parallel traceback units included in the traceback unit 1026 _n are made available for use. .

The receiving apparatus 100 initializes the traceback length to 60 (step S602). In other words, the traceback length control unit 1100 _n initializes the traceback length to 60.

The receiving apparatus 100 performs data frame reception processing in the order of preamble, header, and PSDU. Since the preamble is not convolutionally encoded, the Viterbi decoder 1020 _n performs Viterbi decoding on the header of the received data frame (step S604).

The receiving apparatus 100 analyzes the content of the decrypted header (step S606). That is, the header analysis unit 1200 _n analyzes the content of the decrypted header.

The receiving apparatus 100 determines whether the data rate is less than 200 Mbps based on the result of analyzing the information included in the header (step S608). In other words, the traceback length control unit 1100 _n determines whether the data rate is less than 200 Mbps. The 200 Mbps is an example and can be changed as appropriate.

If it is determined that the data rate is less than 200 Mbps (step S608: YES), the traceback length is set to 30 (step S610). In other words, the traceback length control unit 1100 _n, when the data rate is determined to be less than 200 Mbps, sets the traceback length 30.

The receiving apparatus 100 sets the two memories, for example, the fifth memory 1300 ₅ and the sixth memory 1300 ₆ to be unused and stationary (step S612). That is, the write destination memory selection unit 1024 _n, the read source memory selection unit 1025 _n, the fifth memory 1300 ₅ included in the shared parallel path memory 1300, a memory 1300 ₆ sixth to be unused, still Set to be.

The receiving apparatus 100 does not use the third parallel traceback unit 10283 _n (step S614). That is, the parallel traceback selection unit 1027 _n sets, for example, the third parallel traceback unit 10283 _n not to be used.

  If it is not determined in step S614 that the data rate is less than 200 Mbps (step S608: NO), the receiving apparatus 100 performs Viterbi decoding of PSDU (step S616). That is, PSDU is Viterbi-decoded according to the set traceback length.

  In the receiving apparatus 100, when a data frame is received, the traceback length is set using information to be included in the header. The receiving apparatus 100 controls the parallel path memory used in the Viterbi decoding process based on the traceback length set based on the information to be included in the header. By controlling the parallel path memory used in the Viterbi decoding process, other than the required parallel path memory is not used, so that power consumption can be reduced.

  The data rate is used as an index to be used when changing the traceback length. This is because the coding rate of the convolutional code and the error correction capability of the codeword differ depending on the data rate, and the optimum traceback length in Viterbi decoding varies depending on the data rate. Further, information other than the data frame included in the header may be used.

<Traceback processing (part 1)>
FIG. 7 is a diagram illustrating an example of the traceback process. FIG. 7 shows a parallel traceback process when the traceback length is 60 and the decode length is 30 as an example. That is, in step S608 of the flowchart shown in FIG. 6, parallel traceback processing is shown when the data rate is not determined to be less than 200 Mbps, that is, when the data rate is determined to be 200 Mbps or higher.

In FIG. 7, as an example, a case where the parallel traceback units 10281 _{n to} 10283 _n perform traceback and decoding once each is shown.

(1) writing of the write destination memory selection unit 1024 _n by the survivor path, (2) first parallel traceback unit 10281 _n traceback and decoding processing by, (3) traceback by second parallel traceback unit 10282 _n The description will be divided into (4) trace back and decode processing by the third parallel trace back unit 10283 _n .

(1) Writing of surviving path A surviving path is written to the _first memory 1300 ₁ to the sixth memory 1300 ₆ (WR). The order of the write destination memories is the order of the first memory 1300 ₁ , the second memory 1300 ₂ ,..., The sixth memory 1300 ₆ , the first memory 1300 ₁ ,. It takes 30 hours to write to one memory. Each memory is written next after decoding is completed.

(2) First Parallel Viterbi Decoding Process The surviving paths written in the third memory 1300 ₃ and the second memory 1300 ₂ are traced back by the first parallel traceback unit 10281 _n (TB1). Let T be the start time of traceback processing.

After the trace back is performed, the decoding process is started from the time T + 60 using the surviving path written in the _first memory 13001 (DC1). Simultaneously with the decoding process, the decoding result is stored in the first LIFO 10291 _n (IN1).

For the first memory 1300 _1, it is not used in a parallel Viterbi decoding process subsequent to or state write the survivor path.

Also, the decoding result written in the first LIFO 10291 _n is output from time T + 90 (OT1).

(3) Second Parallel Viterbi Decoding Process The surviving paths written in the fourth memory 1300 ₄ and the third memory 1300 ₃ are traced back by the second parallel traceback unit 10282 _n (TB2). The start time of the traceback process is T + 30.

After the trace back is performed, the decoding process is started from the time T + 90 using the surviving path written in the _first memory 13001 (DC2). Simultaneously with the decoding process, the decoding result is stored in the second LIFO 10292 _n (IN2).

For the second memory 1300 ₂ does not use a parallel Viterbi decoding process subsequent to or state write the survivor path.

Further, the decoded result written to the second LIFO10292 _n, outputs from the time T + 120 (OT2).

(4) Third parallel Viterbi decoding process The third parallel traceback unit 10283 _n traces back the surviving paths written in the fifth memory 1300 ₅ and the fourth memory 1300 ₄ (TB3). The start time of the traceback process is T + 60.

After the trace back is performed, the decoding process is started from the time T + 120 using the surviving path written in the _first memory 13001 (DC3). Simultaneously with the decoding process, the decoding result is stored in the first LIFO 10291 _n (IN3).

For the third memory 1300 ₃ does not use a parallel Viterbi decoding process subsequent to or state write the survivor path.

Also, the decoding result written in the first LIFO LIFO 10291 _n is output from time T + 150 (OT3).

  As described above, three parallel traceback units sequentially read the surviving paths from the six memories in which the surviving paths are written, and perform Viterbi decoding in parallel, thereby performing high-speed processing.

<Traceback processing (part 2)>
FIG. 8 is a diagram illustrating an example of the traceback process. FIG. 8 shows a parallel traceback process when the traceback length is 30 and the decode length is 30 as an example. That is, parallel traceback processing is shown in the case where it is determined in step S608 in the flowchart shown in FIG. 6 that the data rate is less than 200 Mbps.

Unlike the parallel traceback process described with reference to FIG. 7, the traceback process of the first parallel traceback unit 10281 _n is performed from the time T to the third memory 1300 by changing the traceback length from 60 to 30. performed only for ₃ content, performs a decoding process for the second memory 1300 ₂ content than subsequent time T + 30.

Similarly, the traceback process according to the second parallel traceback unit 10282 _n, performed from the time T + 30 respectively traceback, from the time T + 60 decodes the data.

Further, by making the traceback length is 30, and the third parallel trace-back portion of the 10283 _n, a memory 1300 ₅ of the fifth, there is no need to use a memory 1300 ₆ sixth.

As described above, when reducing the traceback length from 60 to 30, reducing the memory 1300 ₅ fifth, and a memory 1300 ₆ sixth stationary, by the standby mode, the power consumption of the receiving device can do.

A receiving unit 102 _1, both in the receiving portion 102 _2, the same processing is performed.

<Modification (Part 1)>
<Receiving device>
FIG. 9 shows a modification of the receiving device.

The receiving apparatus 100 shown in FIG. 9 includes the header analyzing unit 1200 _n as a specific means for determining the traceback length in the receiving apparatus described with reference to FIG.

As long as you have multiple receiver shown in FIG. 4, of the twelve parallel path memory to be included in the shared parallel path memory 1300, the reception unit 102 ₁ using 6, the receiving unit 102 Viterbi decoding can be performed by using the remaining 6 of ₂ . In this case, the number of parallel path memories used by one receiving unit cannot be larger than six.

Therefore, in the receiving apparatus 100, all traceback length control unit 1400, and traceback length in the receiving unit 102 _1, based on the traceback length in the receiving unit 102 _2, to be used by a single Viterbi decoder Control the number of path memories. By controlling the number of path memories to be used by one Viterbi decoder based on the traceback length in both receivers, the number of path memories to be used by one Viterbi decoder is a number greater than 6. Can be increased.

In this embodiment, the case where the receiving unit 102 ₁ is eight path memory, the receiving unit 102 ₂ is controlled to use four path memory.

<Details of the receiver>
FIG. 10 shows details of the receiving unit 102 _n .

The receiving unit 102 _n shown in FIG. 10 has four parallel traceback units in the receiving unit described with reference to FIG.

<Operation of this receiver>
FIG. 11 is a flowchart showing the operation of the receiving apparatus 100.

In the flowchart shown in FIG. 11, the Viterbi decoding process is performed using a part of the parallel path memory included in the shared parallel path memory 1300 using the header information obtained from the header analysis unit 1200 _n . Of the parallel path memories included in the shared parallel path memory 1300, parallel path memories other than the parallel path memory used are not used.

  The operation of the receiving apparatus 100 is substantially the same as the operation described with reference to FIG. 6 when it is determined that the data rate is less than 200 Mbps. That is, steps S1102-S1114 and S1122 shown in FIG. 11 are the same as steps S602-S616 shown in FIG.

If it is determined in step S1108 that the data rate is 200 Mbps or higher (step S1108: NO), the traceback length is set to 90 (step S1116). That is, the traceback length control unit 1100 _n sets the traceback length to 90 when it is determined that the data rate is 200 Mbps or higher.

The receiving apparatus 100 sets to use the first memory 1300 _{1 to} the eighth memory 1300 ₈ (step S1118). In other words, the setting is made so that the first memory 8300 _{1 to} the eighth memory 1300 ₈ included in the shared parallel path memory 1300 are used by the write destination memory selection unit 1024 _n and the read source memory selection unit 1025 _n .

The receiving apparatus 100 uses the first parallel traceback unit 10281 _n -the fourth parallel traceback unit 10284 _n (step S1120). In other words, the parallel traceback selection unit 1027 _{n is set} to use, for example, the first parallel traceback unit 10281 _n -the fourth parallel traceback unit 10284 _n .

After the processing in step S1114 or the processing in step S1120 is performed, the receiving apparatus 100 performs Viterbi decoding of the PSDU (step S1122). That is, PSDU is Viterbi-decoded according to the set traceback length. <Traceback processing (part 1)>
FIG. 12 is a diagram illustrating an example of the traceback process. FIG. 12 shows a parallel traceback process when the traceback length is 90 and the decode length is 30 as an example. That is, in step S1108 of the flowchart shown in FIG. 11, the parallel traceback process is shown when the data rate is not determined to be less than 200 Mbps, that is, when the data rate is determined to be 200 Mbps or more.

FIG. 12 shows, as an example, a case where the first parallel traceback unit 10281 _n -the fourth parallel traceback unit 10284 _n perform traceback and decoding once each.

(1) writing of the write destination memory selection unit 1024 _n by the survivor path, (2) first parallel traceback unit 10281 _n traceback and decoding processing by, (3) traceback by second parallel traceback unit 10282 _n The description will be divided into: (4) trace back and decode processing by the third parallel trace back unit 10283 _n , and (5) trace back and decode processing by the fourth parallel trace back unit 10284 _n .

(1) the memory 1300 ₈ writing surviving path first memory 1300 ₁ to 8 writes the survivor path (WR). The order of the write destination memories is the order of the first memory 1300 ₁ , the second memory 1300 ₂ ,..., The eighth memory 1300 ₈ , the first memory 1300 ₁ ,. It takes 30 hours to write to one memory. Each memory is written next after decoding is completed.

(2) First Parallel Viterbi Decoding Process The surviving paths written in the third memory 1300 ₃ and the second memory 1300 ₂ are traced back by the first parallel traceback unit 10281 _n (TB1). Let T + 90 be the start time of traceback processing.

After the traceback is performed, the decoding process is started from the time T + 150 using the surviving path written in the _first memory 13001 (DC1). Simultaneously with the decoding process, the decoding result is stored in the first LIFO 10291 _n .

For the first memory 1300 _1, it is not used in a parallel Viterbi decoding process subsequent to or state write the survivor path.

Further, the decoding result written in the first LIFO 10291 _n is output from time T + 180 (OT1).

(3) Second Parallel Viterbi Decoding Process The surviving paths written in the fifth memory 1300 ₅ and the fourth memory 1300 ₄ are traced back by the second parallel traceback unit 10282 _n (TB2). The start time of the traceback process is T + 90.

After the trace back is performed, the decoding process is started from the time T + 180 using the surviving path written in the _second memory 13002 (DC2). Simultaneously with the decoding process, the decoding result is stored in the second LIFO 10292 _n (IN2).

For the second memory 1300 ₂ does not use a parallel Viterbi decoding process subsequent to or state write the survivor path.

In addition, the decoding result written in the second LIFO 10292 _n is output from time T + 210.

(4) Third parallel Viterbi decoding process The third parallel traceback unit 10283 _n traces back the surviving paths written in the fifth memory 1300 ₅ and the fourth memory 1300 ₄ (TB3). The start time of the traceback process is T + 150.

After the trace back is performed, the decoding process is started from the time T + 210 using the surviving path written in the _third memory 13003 (DC3). Simultaneously with the decoding process, the decoding result is stored in the first LIFO 10291 _n .

For the third memory 1300 ₃ does not use a parallel Viterbi decoding process subsequent to or state write the survivor path.

Also, the decoding result written in the first LIFO LIFO 10291 _n is output from time T + 240 (OT3).

(5) Fourth Parallel Viterbi Decoding Process The surviving paths written in the seventh memory 1300 ₇ and the sixth memory 1300 ₆ are traced back by the fourth parallel traceback unit 10284 _n (TB4). The start time of the traceback process is T + 150.

After the trace back is performed, the decoding process is started from the time T + 240 using the surviving path written in the _fourth memory 13004 (DC4). Simultaneously with the decoding process, the decoding result is stored in the second LIFO 10292 _n .

For the fourth memory 1300 _4, it is not used in a parallel Viterbi decoding process subsequent to or state write the survivor path.

Also, the decoding result written in the second LIFO LIFO 10292 _n is output from time T + 270 (OT3).

  As described above, four parallel traceback units sequentially read the surviving paths from the eight memories in which the surviving paths are written, and perform Viterbi decoding in parallel, thereby enabling high-speed processing.

<Modification (Part 2)>
<Receiving device>
FIG. 13 shows an embodiment of a receiving apparatus.

  The receiving apparatus 100 illustrated in FIG. 13 includes a receiving unit selecting unit 1500 as a specific means for causing the receiving unit described with reference to FIG. 4 to select a receiving unit that should preferentially use the shared parallel path memory. It is what you have.

<Details of the receiver>
The receiving unit 102 _n of this receiving apparatus is the same as the receiving unit described with reference to FIG. The receiving unit described with reference to FIG. 10 may be applied.

<Operation of this receiver>
FIG. 14 is a flowchart showing the operation of the receiving apparatus 100.

In the flowchart shown in FIG. 14, as the reception unit should be used in preference, it is described a case where the receiving unit 102 ₂ is set.

Receiver 100, a receiving unit to be used in preference, sets the reception unit 102 ₂ (step S1402). That is, the receiving unit selecting unit 1500, a receiving unit to be used in preference, sets the reception unit 102 _2.

The receiving apparatus 100 sets a traceback length (step S1404). That is, the traceback length control unit 1100 ₁ sets the traceback length. By setting the traceback length, the number of path memories to be used can be grasped.

The receiving apparatus 100 sets a traceback length (step S1406). In other words, the trace-back length controller 1100 ₂ sets the traceback length. By setting the traceback length, the number of path memories to be used can be grasped.

The receiving apparatus 100 grasps the traceback length set by each receiving unit (step S1408). A full traceback length control unit 1400 obtains the traceback length set by the traceback length control unit 1100 _1, the traceback length set by the traceback length controller 1100 _2.

The receiving apparatus 100 determines whether or not the total number of path memories to be used is 12 or less (step S1410). A full traceback length controller 1400, based on the traceback length set by the traceback length control unit 1100 _1, the traceback length and set by the traceback length controller 1100 _2, parallel to be used It is determined whether or not the number of path memories is 12 or less.

  If it is determined that the number of parallel path memories to be used is greater than 12 (step S1410: NO), the receiving apparatus 100 reduces the traceback length of the receiving unit 1022 (step S1412).

  When it is determined that the number of path memories to be used is 12 or less (step S1410: YES), or after the process of step S1412 is performed, the receiving apparatus 100 performs a reception process (step S1414).

  According to this modification, it is possible to preferentially use the parallel path memory for the receiver that is set to use the parallel path memory preferentially.

For example, when the trace back length to be controlled by the receiving unit 102 ₁ is 90 and the trace back length to be controlled by the receiving unit 102 ₂ is 60, the number of parallel path memories required in the receiving unit 102 ₁ is is 8, the number of parallel path memory required in the receiving unit 102 ₂ is six. Therefore, the total number of parallel path memories required exceeds 12. If the number of parallel paths memory required exceeds 12, to reduce the traceback length 60 to the reception unit 102 _1, is the path memory required six. By doing so, the total number of parallel path memories to be used is 12 or less. Thereafter, reception processing is performed.

<Modification (Part 3)>
<Receiving device>
FIG. 15 shows a modification of the receiving device.

The receiving apparatus 100 shown in FIG. 15 includes the received data frame number counting unit 1600 _n , the invalid frame determining unit 1700 _n, and the invalid frame number counting unit 1800 _n in the receiving apparatus described with reference to FIG. .

The received data frame number counting unit 1600 _n counts the total number of received frames. Received data frame number counting section 1600 _n inputs the total number of received frames to all traceback length control section 1400.

Invalid frame determination unit 1700 _n determines whether invalid frame using the FCS or the like contained in the received frame.

The invalid frame number counting unit 1800 _n counts and records the number of invalid frames determined to be invalid frames by the invalid frame determination unit 1700 _n . The invalid frame number counting unit 1800 _n inputs the number of invalid frames to the all traceback length control unit 1400.

The total traceback length control unit 1400 is based on the total number of received frames to be input by the received data frame number counting unit 1600 _n and the number of invalid frames to be input by the invalid frame number counting unit 1800 _n. , The receiving unit 102 ₁ and the receiving unit 102 ₂ switch the receiving unit that should use the shared path memory preferentially. For example, switching may be performed when the number of invalid frames increases based on the reception state.

Further, the traceback length controller 1100 _n of the receiving unit 102 _n, when the traceback length is controlled, the received data frame number counting unit 1600 _n, invalid frame determination unit 1700 _n, invalid frame number counting unit 1800 _n The data to be output by may be used.

<Details of the receiver>
The receiving unit 102 _n of this receiving apparatus is the same as the receiving unit described with reference to FIG. The receiving unit described with reference to FIG. 10 may be applied.

<Operation of this receiver>
FIG. 16 is a flowchart showing the operation of the receiving apparatus 100.

  The receiving apparatus 100 performs an initialization process (step S1602).

  The receiving apparatus 100 performs a reception process by executing a reception loop (step S1604).

  FIG. 17 is a flowchart showing the initialization process in the flowchart shown in FIG.

The receiving device 100 gives priority to _one of the receiving unit 102 ₁ and the receiving unit 102 ₂ and sets the receiving unit to which the parallel path memory is allocated (step S1702). Here, in favor of the reception unit 102 _2, the case of setting the receiver to allocate a parallel path memory.

Receiver 100, the number of invalid frames _{C n} in the receiving unit 102 ₂ about invalid frame counting section 1800 ₂ to 0 (step S1704).

Receiver 100 to 0 received total frame number _{S n} in the received data frame number counting unit 1600 ₂ relating to the reception unit 102 ₂ (step S1706).

  FIG. 18 is a flowchart showing a reception loop in the flowchart shown in FIG.

  The receiving apparatus 100 executes a reception loop for each received frame (step S1802).

Receiver 100, the received total number of frames _{S n,} is added 1 (step S1804).

Receiving apparatus 100 determines whether _{S n} is smaller than 10001 (step S1806). Here, 10001 is an example and can be changed as appropriate.

If S _n is not less than 10001 (step S1806: NO), it performs initialization processing. After the initialization process, the process returns to step S1804.

If S _n is smaller than 10001 (step S1806: YES), the receiving apparatus 100 performs a normal reception (step S1810).

  The receiving apparatus 100 determines whether the frame received in step S1810 is an invalid frame. For example, when determining whether the frame is an invalid frame, it is determined by using an error detection codeword for data to be originally transferred, called FCS, which should be included in the received frame.

If it is determined to be invalid frame (step S1812: YES), the number of invalid frames _{C n,} 1 is added to (step S1814).

If it is not determined in step S1812 that the frame is an invalid frame, or after the processing in step S1814, the receiving apparatus 100 determines whether C _n is less than 1000 (step S1816). Here, 1000 is an example and can be changed as appropriate.

If C _n is not less than 1000 (Step S1816: NO), the reception unit 102 ₂ switches the receiver to allocate a parallel path memory with priority (step S1818). By setting the receiver to allocate a parallel path memory receiving unit 102 ₂ in preference, since it either possible to ensure the reception accuracy of the reception unit 102 _2, it is possible to improve the reception quality.

When C _n is less than 1000 (step S1816: YES), or after the process of step S1818 is completed, the process returns to step S1804.

  FIG. 19 is a flowchart showing normal reception processing in the flowchart shown in FIG.

The receiving apparatus 100 sets a traceback length (step S1902). That is, the traceback length control unit 1100 ₁ sets the traceback length. By setting the traceback length, the number of path memories to be used can be grasped.

The receiving apparatus 100 sets a traceback length (step S1904). In other words, the trace-back length controller 1100 ₂ sets the traceback length. By setting the traceback length, the number of path memories to be used can be grasped.

The receiving apparatus 100 grasps the traceback length set by each receiving unit (step S1906). A full traceback length control unit 1400 obtains the traceback length set by the traceback length control unit 1100 _1, the traceback length set by the traceback length controller 1100 _2.

The receiving apparatus 100 determines whether or not the total number of path memories to be used is 12 or less (step S1908). A full traceback length controller 1400, based on the traceback length set by the traceback length control unit 1100 _1, the traceback length and set by the traceback length controller 1100 _2, parallel to be used It is determined whether or not the number of path memories is 12 or less.

  If it is determined that the number of parallel path memories to be used is greater than 12 (step S1908: NO), the receiving apparatus 100 reduces the traceback length of the receiving unit to which no parallel path memory is preferentially allocated (step S1908). S1910).

  When it is determined that the number of path memories to be used is 12 or less (step S1908: YES), or after the processing according to step S1910 is performed, the receiving apparatus 100 performs a reception process (step S1912).

  The following items are further disclosed regarding the embodiment including the above examples.

(1) A receiving device for receiving a radio signal,
A plurality having at least a Viterbi decoder that performs Viterbi decoding on convolutionally encoded data, and a traceback length control unit that controls a traceback length to be used in Viterbi decoding the convolutionally encoded data The receiver of
A parallel path memory as a shared parallel path memory shared to store a survivor path when the convolutionally encoded data by the plurality of receivers is Viterbi-decoded;
And a memory control unit as a total traceback length control unit for controlling the parallel path memory usage to be used by each receiving unit based on the traceback length to be controlled by the plurality of receiving units.

(2) In the receiving device according to (1),
It has a header analysis unit that analyzes the header of the received signal,
The traceback length control unit controls the traceback length based on information included in the header analyzed by the header analysis unit.

(3) In the receiving device according to (1) or (2),
The parallel path memory has a plurality of path memories,
The memory control unit controls the number of path memories as the parallel path memory usage to be used by each receiving unit.

(4) In the receiver according to any one of (1) to (3),
When the parallel path memory usage is controlled by the memory control unit, a reception unit setting unit is provided as a reception unit selection unit that sets a reception unit to which the parallel path memory usage is preferentially allocated.

(5) In the receiving device according to (4),
If the memory usage to be set based on the traceback length to be controlled by the plurality of receiving units by the memory control unit exceeds the capacity of the parallel path memory, the receiving unit setting unit has priority. A trace back length control unit as a total trace back length control unit for reducing a trace back length corresponding to a receiving unit other than the receiving unit set as the receiving unit to which the parallel path memory usage is allocated;

(6) In the receiving device according to (4),
An invalid frame determination unit that determines whether the data frame received by the receiving device is invalid;
An invalid frame number counting unit that counts the number of data frames determined to be invalid by the invalid frame determining unit;
When the number of data frames determined to be invalid to be counted by the invalid frame number counting unit is equal to or greater than a predetermined threshold, the receiving unit setting unit preferentially allocates the parallel path memory usage. The amount of memory used for receiving units other than the receiving unit set as a unit is reduced.

  Although the present invention has been described with reference to particular embodiments, each embodiment is merely illustrative, and those skilled in the art will appreciate various variations, modifications, alternatives, substitutions, and the like. . For convenience of explanation, an apparatus according to an embodiment of the present invention has been described using a functional block diagram, but such an apparatus may be implemented in hardware, software, or a combination thereof. The present invention is not limited to the above-described embodiments, and various variations, modifications, alternatives, substitutions, and the like are included without departing from the spirit of the present invention.

100 Receiver 102 _n (n is an integer of n> 0) Receiver 1020 _n (n is an integer of n> 0) Viterbi decoder 1021 _n (n is an integer of n> 0) Branch distance calculation unit 1022 _n (N is an integer of n> 0) Comparison selection unit 1023 _n (n is an integer of n> 0) Surviving path storage unit 1024 _n (n is an integer of n> 0) Write destination memory selection unit 1025 _n (n Is an integer of n> 0) Source memory selection unit 1026 _n (n is an integer of n> 0) Traceback unit 1027 _n (n is an integer of n> 0) Parallel traceback selection unit 10281 _n (n is , n> 0 integer) first parallel traceback unit 10282 _n (n is, n> 0 is an integer) second parallel traceback unit 10283 _{n (n, n>} 0 integer ) The third parallel trace-back unit 10284 _{n (n} a, n> 0 integer) fourth parallel trace-back unit 10291 _n (n a, n> 0 integer) first LIFO
10292 _n (n is an integer of n> 0) Second LIFO
1100 _n (n is an integer of n> 0) Traceback length control unit 1200 _n (n is an integer of n> 0) Header analysis unit 1300 Shared parallel path memory 1300m (m is m = 1-12) m 1400 _n (n is an integer n> 0) Received data frame count unit 1700 _n (n is an integer n> 0) Invalid frame determination unit 1800 _n (N is an integer where n> 0) Invalid frame count section

JP 2006-173903 A

Claims (6)

A receiving device for receiving a radio signal,
A plurality having at least a Viterbi decoder that performs Viterbi decoding on convolutionally encoded data, and a traceback length control unit that controls a traceback length to be used in Viterbi decoding the convolutionally encoded data The receiver of
A parallel path memory shared to store a survivor path when the convolutionally encoded data is Viterbi-decoded by the plurality of receivers;
And a memory control unit that controls the parallel path memory usage to be used by each receiving unit based on a traceback length to be controlled by the plurality of receiving units. The receiving device according to claim 1,
It has a header analysis unit that analyzes the header of the received signal,
The receiving apparatus, wherein the traceback length control unit controls a traceback length based on information included in a header analyzed by the header analysis unit. The receiving apparatus according to claim 1 or 2,
The parallel path memory has a plurality of path memories,
The said memory control part is a receiver which controls the number of path memories as said parallel path memory usage which should be used by each said receiving part. The receiving apparatus according to any one of claims 1 to 3,
A receiving device, comprising: a receiving unit setting unit configured to set a receiving unit to which the parallel path memory usage is preferentially allocated when the parallel path memory usage is controlled by the memory control unit. The receiving device according to claim 4,
If the memory usage to be set based on the traceback length to be controlled by the plurality of receiving units by the memory control unit exceeds the capacity of the parallel path memory, the receiving unit setting unit has priority. A receiving apparatus, comprising: a traceback length control unit that reduces a traceback length corresponding to a receiving unit other than the receiving unit set as a receiving unit to which the parallel path memory usage is allocated. The receiving device according to claim 4,
An invalid frame determination unit that determines whether the data frame received by the receiving device is invalid;
An invalid frame number counting unit that counts the number of data frames determined to be invalid by the invalid frame determining unit;
When the number of data frames determined to be invalid to be counted by the invalid frame number counting unit is equal to or greater than a predetermined threshold, the receiving unit setting unit preferentially allocates the parallel path memory usage. A receiving device that reduces the amount of memory used for a receiving unit other than the receiving unit set as a unit.

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