JP2011035568A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver which reduces power consumption. <P>SOLUTION: The receiver 50 is configured with a Viterbi decoder 1 which decodes convolutional encoded data, a traceback length control means 6 for controlling the traceback length of parameters used in the Viterbi decoder based on data described in the header of received data frames, and a header analysis means 7 for reading information of decoding data using the header. The receiver 50 receives convolutional encoded data, and controls, when the Viterbi decoder which has a plurality of memories and performs parallel processing performs maximum likelihood decoding, the traceback length using header information of the received data. Then, the receiver 50 sets whether a plurality of parallel memories are used or not, and if there is a parallel memory not to be used, the receiver 50 stops it and sets standby mode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a receiving apparatus, and more particularly to a memory operation control technique for further reducing power consumption of a Viterbi decoding circuit in the receiving apparatus.

In Viterbi decoding, which is maximum likelihood decoding of a convolutional code that is one of error correction codes used in digital wireless communication and the like, it is known that the decoding error decreases when the traceback length is increased. Therefore, a method for reducing the processing time and the power consumption of the circuit when the traceback length is shortened by dynamically changing the traceback length for each received data frame and shortening the traceback length is already known. In addition, a method for increasing the decoding speed by dividing the memory used in the Viterbi decoding circuit and performing the traceback processing in parallel is already known.
In recent years, further reduction in power consumption of circuits has been demanded from the viewpoint of mounting digital wireless communication on mobile devices and environmental considerations. The header of the received data frame of digital wireless communication includes information necessary for reception processing, such as information representing decoding error correction capability, and is effective in determining the optimum traceback length.

However, in the conventional apparatus for changing the traceback length, the processing time is shortened by reducing the traceback length, and the power consumption is merely reduced. That is, by shortening the traceback length, among the divided memories used in the Viterbi decoding circuit, there is a memory that does not need to be used for the decoding process, but since this memory continues to operate during the decoding process, There was a problem that power was wasted. Further, since the information in the header in the received data frame effective for changing the traceback length is not used, there is a problem that complicated processing is required to determine the optimum traceback length.
Therefore, in Patent Document 1, in order to improve the error rate characteristics of the maximum likelihood decoder, the header of the received data based on the data frame format of the wireless LAN (IEEE802.11a) is decoded, thereby controlling the traceback length. Thus, a method is disclosed in which the reliability of the received data frame is improved, the throughput is improved, and the number of retransmission requests is reduced, resulting in a reduction in power consumption of the transceiver.

However, the prior art disclosed in Patent Document 1 is similar to the present invention in that the traceback length is controlled using the header of the received data frame, but it is not necessary to use it for the Viterbi decoding process. Since the memory continues to operate during processing, the problem that power is wasted cannot be solved.
The present invention has been made in view of such a problem, and receives convolutionally encoded data, and thereafter, when maximum likelihood decoding is performed by a Viterbi decoder capable of parallel processing including a plurality of memories, Controls the traceback length using information in the header of the received data, sets whether multiple parallel memories are used or not used, and if there are unused parallel memories, freezes them and puts them into standby An object of the present invention is to provide a receiving apparatus that reduces power consumption by setting the mode.

In order to solve this problem, the present invention provides at least a parallel traceback means for decoding convolutionally encoded data at a high speed and a parallel path memory for storing a survivor path, wherein the convolutional code is provided. A Viterbi decoder for decoding the converted data, a header analysis means for analyzing information described in the header of the data frame, and a parameter used in the Viterbi decoder by the header information obtained by the header analysis means Traceback length control means for controlling the traceback length, and the Viterbi decoder controls the operation and stop of the parallel path memory according to the traceback length controlled by the traceback length control means. Features.
According to a second aspect of the present invention, there is provided preamble analysis means for estimating a quality of a received signal using a preamble value in the data frame.
The traceback length control means controls the traceback length when the header is Viterbi-decoded based on the signal quality estimated by the preamble obtained by the preamble analysis means. .
According to a fourth aspect of the present invention, the information in the header is analyzed by the header analyzing unit based on the signal quality estimated by the preamble obtained by the preamble analyzing unit, and the traceback length control unit is controlled by the analyzed information. Header analysis control means for analyzing whether or not to control is provided.
According to a fifth aspect of the present invention, there is provided an invalid frame determination unit for determining whether or not a received data frame is invalid, and an invalid frame number for counting the number of invalid data frames when the invalid frame determination unit determines that the data frame is invalid. It is characterized by comprising counting means and received data frame number counting means for counting the number of received data frames.
According to a sixth aspect of the present invention, the traceback length control means controls the traceback length based on the results obtained by the invalid frame number counting means and the received data frame number counting means.

  According to the present invention, for information in the header of received data, for example, when the data rate is low, the coding rate of the convolutional code is low, so the traceback length in Viterbi decoding can be shortened. The power consumption in the receiving apparatus can be further reduced because the stand-by mode, i.e., the standby mode, can be set without using the signal.

It is a figure which shows an example of a convolutional encoder. It is a figure which shows a part of trellis produced when carrying out Viterbi decoding of the codeword produced by the encoder of FIG. It is a figure explaining the structure of a reception data frame. It is a figure explaining the structure of the receiver which concerns on the 1st Embodiment of this invention. It is a figure which shows the specific processing flow of the receiver which concerns on the 1st Embodiment of this invention. It is a figure which shows the mode of the parallel traceback process by the traceback length 60 and the decoding length 30. FIG. It is a figure which shows the mode of the parallel traceback process by the traceback length 30 and the decoding length 30. FIG. It is a figure explaining the structure of the receiver which concerns on the 2nd Embodiment of this invention. It is a figure which shows the specific processing flow of the receiver which concerns on the 2nd Embodiment of this invention. It is a figure explaining the structure of the receiver which concerns on the 3rd Embodiment of this invention. It is a figure which shows the specific processing flow of the receiver which concerns on the 3rd Embodiment of this invention. It is a figure explaining the structure of the receiver which concerns on the 4th Embodiment of this invention. It is a figure which shows the specific processing flow of the receiver which concerns on the 4th Embodiment of this invention.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
The present invention receives convolutionally encoded data, and then uses information in the header of the received data when maximum likelihood decoding is performed by a Viterbi decoder capable of parallel processing including a plurality of memories. Controls traceback length, sets whether multiple parallel memories are used or not used, and if there are unused parallel memories, freezes them and puts them into standby mode to reduce power consumption in the receiver It is characterized by being able to. The features of the present invention described above will be described in detail with reference to the following drawings.
FIG. 1 is a diagram illustrating an example of a convolutional encoder. The encoder of FIG. 1 has two shift registers D1 and D2, and outputs codewords OUT1 and OUT2 by exclusive OR of the values of 1-bit input IN and shift registers D1 and D2. In the encoder of FIG. 1, the constraint length is 3, the states represented by D1 and D2 are {00, 01, 10, 11}, and the total number of states is 4.

FIG. 2 is a diagram showing a part of a trellis created when Viterbi decoding a codeword created by the encoder of FIG. A trellis represents a temporal transition of a state. In the figure, a solid line is a path when “0” is input from each state, and a broken line is a path when “1” is input. In Viterbi decoding, when decoding is performed from a received codeword, the most likely path is selected from all possible paths on the trellis, traceback is performed, and decoding is performed.
Consider decoding a codeword produced by the convolutional encoder of FIG. First, the received data is cut off to a certain length. After truncation, the received word is divided into 2 bits, and the distance from the possible code word is calculated. This distance is called a branch distance. After calculating distances for all received words, surviving paths are selected in the order of received words, and after selecting surviving paths for all transitions, traceback is performed on the surviving paths. After the traceback is performed, a result corresponding to the input of the surviving path is set as a decoding result. However, at this time, all the surviving paths are not decrypted but a part is discarded. Here, the number of state transitions on the trellis that is only tracebacked and not the decoding result is the traceback length, and the traceback is the decoding result (this process is called decoding). The number of state transitions on the trellis is the decoding length. And

FIG. 3 is a diagram for explaining the configuration of the received data frame. That is, WiMedia Alliance, Inc. This is a data frame configuration defined by the standard “Multiband OFDM Physical Layer Specification Approved Draft 1.2” defined by the standard. The above standard is a physical layer standard adopted in a wireless USB (Universal Serial Bus) standard that employs an ultra wide band (UWB) wireless communication system. The direction of the arrow a in FIG. 3 indicates the time direction, and the frame configuration continues in time with a preamble b, a header c, and a PSDU (Physical layer convergence protocol Service Data Unit) d.
The preamble is necessary for packet detection, gain control, phase shift correction, and the like, and is a value determined in advance by the standard. In the header, the data rate (RATE) of the PSDU following the header, the length (LENGTH), and the like are described according to a format defined by the standard. The data rate of the header is constant. The PSDU includes data to be originally transferred, error detection codewords for data to be originally transferred, called FCS (Frame Check Sequence), and the like. The data rate of PSDU differs depending on the data encoding method, etc. In the above standard, 53.3 [Mbps], 80 [Mbps], 106.7 [Mbps], 160 [Mbps], 200 [Mbps], 320 [Mbps] , 400 [Mbps], and 480 [Mbps] are defined. At the time of reception, data describing received signal quality is added to the end of the data frame shown in FIG.

FIG. 4 is a diagram for explaining the configuration of the receiving apparatus according to the first embodiment of the present invention. In FIG. 4, the constraint length of the convolutional encoder is 7, the total number of states of the convolutional code is 64, the traceback length of Viterbi decoding is 60, and the decoding length of Viterbi decoding is 30. The receiving apparatus 50 includes a Viterbi decoder 1 that decodes convolutionally encoded data, and a traceback that controls the traceback length of parameters used in the Viterbi decoder from data described in the header of the received data frame. The length control means 6 and the header analysis means 7 for reading the information therein using the header of the decoded data.
Reference numeral 2 denotes a branch distance calculation unit for calculating the distance between the received data frame and the convolutional codeword. A survivor path is selected by the comparison calculation unit shown in 3 using the distance, and the survivor path information is set to 5. Save to Survival Path Storage Unit. 5c is the first memory, 5d is the second memory, 5e is the third memory, 5f is the fourth memory, 5g is the fifth memory, and 5h is the sixth memory. Consider adopting a RAM (Random Access Memory) with a capacity of 30 * 64 = 1920 bits.

5a is a write destination memory selection unit for selecting one of the six memories 5c, 5d, 5e, 5f, 5g, and 5h and writing a surviving path. This is a read source memory selection unit that selects one from the memory and reads the survival path.
Reference numeral 4 denotes a traceback unit that reads the surviving path written in the memory and performs traceback and decoding. 4a is a parallel traceback selection unit that selects one of the first parallel traceback unit 4b, the second parallel traceback unit 4c, and the third parallel traceback unit 4d to perform the traceback. It is. The decoded data obtained by the three traceback means is stored in one of the first LIFO (Last In First Out Memory) 4e and the second LIFO 4f, and is decoded from the other LIFO not used for storage. Is output.

FIG. 5 is a diagram showing a specific processing flow of the receiving apparatus according to the first embodiment of the present invention. In the receiving apparatus 50 in FIG. 4, consider a state in which one data frame is received for the sake of simplicity. Further, the traceback length control means 6 initializes the traceback length to 60 so that all six memories in the surviving path storage unit 5 and all three parallel traceback means in the traceback unit 4 can be used. (Step SA1).
The received data frame is received and processed in the order of preamble, header, and PSDU. Since the preamble is not convolutionally encoded, the Viterbi decoder 1 performs Viterbi decoding on the header of the received data frame (step SA2). The contents of the decrypted header are analyzed by the header analysis means 7 (step SA3). In response to the result of analyzing the information described in the header, if, for example, the data rate (RATE) is less than 200 Mbps in the traceback length control means 6 (step SA4), the traceback length is set to 30 (step SA5). In the write destination memory selection unit 5a and the read source memory selection unit 5b, for example, the fifth memory 5g and the sixth memory 5h in the surviving path storage unit 5 are set to be unused and stationary (step SA6). ).

In the parallel traceback selection means 4a, for example, the third parallel traceback means 2A0d is not used (step SA7). Since the traceback length when the PSDU is Viterbi-decoded is set as described above, the PSDU is finally Viterbi-decoded (Step SA8).
When a data frame is received as described above, the traceback length is set using the information included in the header, and the memory used in the parallel Viterbi decoding process is controlled by the traceback length. Can be further reduced. The reason for using the data rate as an index to change the traceback length is that the convolutional code coding rate and codeword error correction capability differ depending on the data rate, and the optimum traceback length in Viterbi decoding varies depending on the data rate. Because. Information other than the data frame included in the header can also be used.

  FIG. 6 is a diagram showing a state of parallel traceback processing with the traceback length 60 and the decode length 30. In FIG. In order to make the explanation easy to understand, the parallel traceback units 1 to 3 perform traceback and decoding once each time, and will be described below. Also, the explanation is as follows: (1) writing of surviving path by the write destination memory selection unit 5a, (2) traceback and decoding processing by the first parallel traceback means 4b, and (3) trace by the second parallel traceback means 4c. It is divided into back and decode processing, and (4) trace back and decode processing by the third parallel trace back means 4d.

(1) Writing of surviving path A surviving path is written to the first to sixth memories (WR). .., 6, 1, 2,..., And the time required for writing to one memory is 30. Each memory is written next after decoding.
(2) First Parallel Viterbi Decoding Process The surviving path written in the third memory and the second memory is traced back by the first parallel traceback means (TB1). The start time of the traceback process is T.
After the traceback is performed, the decoding process is started using the surviving path written in the first memory from time T + 60 (DC1), and the decoding result is simultaneously stored in the first LIFO 4e (IN1). Since the first memory is not used in the subsequent parallel Viterbi decoding process, the survivor path can be written. Also, the decoding result written in the first LIFO is output from time T + 90 (OT1).

(3) Second Parallel Viterbi Decoding Process The surviving path written in the fourth memory and the third memory is traced back by the second parallel traceback means (TB2). The start time of the traceback process is T + 30. After the traceback is performed, the decoding process is started using the surviving path written in the first memory from time T + 90 (DC2), and at the same time, the decoding result is stored in the second LIFO 4f (IN2). Since the second memory is not used in the subsequent parallel Viterbi decoding process, the surviving path can be written. The decoding result written in the second LIFO is output from time T + 120 (OT2).
(4) Third Parallel Viterbi Decoding Process The surviving path written in the fifth memory and the fourth memory is traced back by the third parallel traceback means 4d (TB3). The start time of the traceback process is T + 60. After the trace back is performed, the decoding process is started using the surviving path written in the first memory from time T + 120 (DC3), and at the same time, the decoding result is stored in the first LIFO (IN3). Since the third memory is not used in the subsequent parallel Viterbi decoding process, the surviving path can be written. Also, the decoding result written in the first LIFO is output from time T + 150 (OT3).
As described above, the three parallel traceback units sequentially read the surviving paths from the six memories in which the surviving paths are written, and perform Viterbi decoding in parallel, whereby high-speed processing can be performed.

FIG. 7 is a diagram showing a state of parallel traceback processing with the traceback length 30 and the decode length 30. In FIG. Unlike the parallel traceback process in FIG. 2.3 by changing the traceback length from 60 to 30, the traceback process of the first parallel traceback means 4b is performed only for the contents of the third memory from the time T, Thereafter, the contents of the second memory are decoded from time T + 30.
Similarly, the traceback processing by the second parallel traceback means 4c is traced back from time T + 30 and decoded from time T + 60, respectively.
Further, since the traceback length is set to 30, it is not necessary to use the third parallel traceback means 4d, the fifth memory 5g, and the sixth memory 5h.
As described above, when the traceback length is reduced from 60 to 30, the power consumption of the receiving apparatus can be reduced by setting the fifth memory and the sixth memory to the static and standby modes.

FIG. 8 is a diagram for explaining the configuration of a receiving apparatus according to the second embodiment of the present invention. The same components are denoted by the same reference numerals as in FIG. This receiving device 51 includes a preamble analyzing unit 12 that estimates signal quality using a preamble value in a data frame, and a trace when the header is subjected to Viterbi decoding after estimating the signal quality of the received signal by the preamble analyzing unit 12. Trace back length control means 11 for controlling the back length is further provided.
The traceback length control means 11 has a function of controlling the traceback length based on the signal quality estimated by the preamble. With the receiving apparatus 51 configured as described above, it is possible to reduce power consumption when Viterbi decoding the header, as compared with the receiving apparatus 50 in FIG.

FIG. 9 is a diagram showing a specific processing flow of the receiving apparatus according to the second embodiment of the present invention. However, steps having the same meaning and function in FIG. 5 are given the same symbols. 5 is different from the processing in FIG. 5 in that the preamble analysis means 12 and the traceback length control means 11 for controlling the traceback length from the signal quality estimated by the analysis means are performed.
As in FIG. 5, first, the traceback length is set to 60 (step SB1).
Next, the preamble is analyzed. For example, for the preamble data 128 points, R (n) (n = 1,..., 128), the average power P is obtained as follows. However, the symbol * means taking a complex conjugate. R (n) is a complex number.

In digital wireless communication, AGC (Automatic Gain Control) processing is performed using a normal preamble. In AGC processing, gain control is performed using RSSI (Received Signal Strength Indicator) calculated by the above average power P or RF (Radio Frequency, radio frequency) circuit, and the input level of the received signal during this AGC processing. Can be estimated. As the signal quality, the input level of the received signal obtained in the AGC process may be used, or a correlation calculation value obtained in the packet detection process may be used (step SB2). It is determined whether the signal quality is good (step SB3), and if step SB3 is established, the traceback length is set to 30 (step SB4). Further, the fifth and sixth memories are not used and set to be stationary (step SB5). Then, the third parallel traceback means is not used (step SB6). Viterbi decoding of the header is performed with the traceback length set as described above (step SB7).
Since there is a possibility that the traceback length has been changed in the Viterbi decoding of the header, the traceback length is set to 60 (step SB8). The subsequent steps are the same as those after step SA3 in FIG.
As described above, by performing Viterbi decoding of the header with the traceback length set after analyzing the preamble, the power consumption when decoding the header Viterbi compared to the receiving apparatus shown in FIG. Can be reduced.

  FIG. 10 is a diagram for explaining the configuration of a receiving apparatus according to the third embodiment of the present invention. The same components are denoted by the same reference numerals as in FIG. The receiving device 52 estimates the signal quality using the preamble value in the data frame, estimates the signal quality of the received signal by the preamble analyzing means 6, and then performs “header analysis” depending on whether the signal quality is good or bad. The header analysis control means 13 is further provided for controlling whether or not to perform the process of analyzing the information in the header using the means and controlling the traceback length based on the information. The receiving device 52 configured as described above can estimate the signal quality using the preamble of the received data frame, and for example, when the signal quality is poor, the header analysis process and the traceback length control can be prevented. As a result, power consumption can be reduced compared to the receiving device 50 in FIG.

デジタル無線通信においては、通常プリアンブルを用いてＡＧＣ（Automatic Gain Control）処理を行う。ＡＧＣ処理では、上記平均パワーＰやＲＦ（Radio Frequency、無線周波数）回路で算出されたＲＳＳＩ（Received Signal Strength Indicator）などを使用してゲインコントロールを行うが、このＡＧＣ処理過程で受信信号の入力レベルを推定することができる。 FIG. 11 is a diagram showing a specific processing flow of the receiving apparatus according to the third embodiment of the present invention. However, steps having the same meaning and function in FIG. 5 are given the same reference numerals. Similar to the processing of FIG. 5, first, the traceback length is set to 60 (step SC1). Next, the preamble is analyzed. Specifically, for example, the average P of the power is obtained as follows for 128 points of preamble data, R (n) (n = 1,..., 128). However, the symbol * means taking a complex conjugate. R (n) is a complex number.

In digital wireless communication, AGC (Automatic Gain Control) processing is performed using a normal preamble. In AGC processing, gain control is performed using RSSI (Received Signal Strength Indicator) calculated by the above average power P or RF (Radio Frequency, radio frequency) circuit. Can be estimated.

As the signal quality, the input level of the received signal obtained in the AGC process may be used, or the correlation calculation value obtained in the packet detection process may be used (step SC2). It is determined whether or not the signal quality is good (step SC3), and if step SC3 is established, the processing similar to the processing up to step SA8 is performed after step SA2 in FIG. If step SC3 is not established, the header analysis means is not required (step SC4), the traceback length control is not required (step SC5), and the Viterbi decoding of the header is performed with the traceback length 60 (step SC6). Finally, the PSDU is Viterbi-decoded (step SA8) and the process ends.
As described above, the signal quality is estimated by preamble analysis. For example, when the signal quality is very poor, the traceback length is not controlled for Viterbi decoding of PSDU. As a result, it becomes possible to reduce power consumption compared with the receiving apparatus shown in FIG.

FIG. 12 is a diagram for explaining the configuration of a receiving apparatus according to the fourth embodiment of the present invention. The same components are denoted by the same reference numerals as in FIG. This receiving device 53 uses invalid frame determination means 15 for determining whether or not the received data frame is an invalid frame (in order to determine whether or not the received data frame is an invalid frame, FCS included in the PSDU of the received data frame may be used. And an invalid frame number counting unit 16 that counts the number of received data frames when the received data frame is determined to be an invalid frame, and a received data frame number counting unit 14 that counts the number of received data frames. .
When receiving a number of data frames, the receiving apparatus 50 shown in FIG. 4 uses information in the header of the received data frame. In addition, when the number of invalid data frames increases, the PSDU of the next data frame is used. By increasing the traceback length when Viterbi decoding is performed, the traceback length can be controlled with higher accuracy. In addition, by counting the number of received data frames, for example, the traceback length can be set periodically to be longer and the traceback length can be controlled with higher accuracy.

FIG. 13 is a diagram showing a specific processing flow of the receiving apparatus according to the fourth embodiment of the present invention. However, steps having the same meaning and function in FIG. 5 are given the same symbols. In the embodiment of FIG. 13, as in the process of FIG. 5, the data rate (RATE) included in the header of the received data frame is adopted as a criterion for controlling the traceback length. For example, the invalid frame count is sufficient. The threshold value of the judgment criterion is changed when it becomes larger. In addition, when the number of received data frames becomes sufficiently large, the threshold value of the criterion is returned to the initial setting value.
First, the value for counting the number of invalid frames is Cn (Cn is a positive integer), and 0 is substituted for Cn (step SD1). Further, the threshold of the data rate, which is a criterion for controlling the traceback length, is Rth [Mbps] (Rth is a positive real number), and 200 is substituted for Rth (step SD2). Then, the number of received data frames is Sn (Sn is a positive integer), and 0 is substituted for Sn (step SD3). When one received data frame is received, Sn is increased by 1 (step SD4). It is determined whether the expression “Sn <10001” is satisfied (step SD5). If the expression is not satisfied in step SD5, the process returns to immediately before step SD1 to reset Cn, Rth, and Sn to initial values. When the formula is established in step SD5, the following processing is performed.

Steps SA1 to SA4 are the same as those in FIG. After analyzing the header and obtaining the value of RATE, it is determined whether or not the value is less than Rth (step SD6). If RATE is less than Rth, steps SA5 to SA8 similar to those in FIG. 2.2 are executed. If RATE is equal to or greater than Rth, step SA8 is executed. After the Viterbi decoding of the PSDU is completed, it is determined whether or not the received data frame is an invalid frame using the FCS included in the PSDU of the received data frame (step SD7). If the received data frame is an invalid frame (step SD8), Cn is incremented by 1 (step SD9). Since the determination criterion of the traceback length control is changed with reference to the number of invalid frames, it is determined whether the expression “Cn <1000” is satisfied (step SD10). If the expression in step SD10 is satisfied, Rth is set. The next received frame is processed without change. If the expression in step SD10 does not hold, Rth is changed to 80, for example (step SD11), and the next received frame is processed.
When the number of invalid frames increases as a result of determining whether or not the received data frame is invalid as a result of controlling the traceback length, instead of controlling the traceback length only with the information in the header of the received frame. Therefore, the traceback length can be increased, and the traceback length can be controlled with higher accuracy. In addition, when the number of received data frames becomes large, it is possible to control the traceback length with higher accuracy by resetting Rth.

  1 Viterbi decoder, 2 branch distance calculation unit, 3 comparison / selection unit, 4 traceback unit, 5 surviving path storage unit, 6, 11 traceback length control means, 7 header analysis means, 8 received data, 9 decoded data, 12 Preamble analysis means, 13 header analysis control means, 14 received data frame count counting means, 15 invalid frame determination means, 16 invalid frame count counting means, 50, 51, 52, 53 receiver

JP 2006-173903 A

Claims (6)

A Viterbi decoder for decoding the convolutionally encoded data, comprising at least parallel traceback means for decoding the convolutionally encoded data at a high speed and a parallel path memory for storing a survivor path;
Header analysis means for analyzing information described in the header of the data frame;
Traceback length control means for controlling the traceback length of a parameter used in the Viterbi decoder according to the header information obtained by the header analysis means,
The Viterbi decoder controls the operation and stop of the parallel path memory according to the traceback length controlled by the traceback length control means.   2. The receiving apparatus according to claim 1, further comprising preamble analyzing means for estimating a quality of a received signal using a preamble value in the data frame.   The traceback length control means controls the traceback length when Viterbi decoding the header based on the signal quality estimated by the preamble obtained by the preamble analysis means. The receiving device described in 1.   Whether the header analysis unit analyzes the information in the header based on the signal quality estimated by the preamble obtained by the preamble analysis unit, and determines whether or not the traceback length control unit is controlled by the analyzed information. 4. The receiving apparatus according to claim 1, further comprising header analysis control means for analyzing. Invalid frame determination means for determining whether or not the received data frame is invalid;
Invalid frame number counting means for counting the number of invalid data frames when the invalid frame determining means determines that the data frame is invalid;
5. The receiving apparatus according to claim 1, further comprising: a received data frame number counting unit that counts the number of the received data frames.   6. The traceback length control unit controls the traceback length based on the results obtained by the invalid frame number counting unit and the received data frame number counting unit. Receiver.

Images