JP2012194693A - Interface circuit and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To verify validity of an encoder regardless of an external storage medium.SOLUTION: An interface circuit comprises a test circuit 170 which has: a mode selection unit 171 for setting an encoder 153 in a test mode; a DMA controller control unit 174 for controlling operation of a DMA controller 152 in the test mode; an encoder control unit 173 for controlling operation of the encoder 153 in the test mode. The test circuit 170 causes the encoder 153 to execute test for encoding and decoding, by performing switching control of a transfer direction of the DMA controller 152 via the encoder 153 in the test mode so that a memory reads/writes test data from/in an SRAM 151 and vice versa.

Description

  The present invention relates to an interface circuit including an DMA (Direct Memory Access) controller and an image forming apparatus.

  Usually, the reading (reading) direction or the writing (writing) direction is exclusively performed on the external storage medium. Due to this characteristic, in order to reduce the circuit scale, the read / write direction of one DMA controller is switched and used.

  Here, since the external storage medium can be easily removed, it tends to be a security problem. For this reason, a method has been proposed in which encryption is performed using an encryption device when recording on an external storage medium (see, for example, Patent Document 1).

  In an LSI having an encryption device, in order to ensure the validity of the encryption device, an operation check test of the encryption device must be performed at startup. In this case, a method is used in which an encryption device is used to output the data once to an external storage medium, read it back into the memory, and compare whether or not it matches the prepared expected value. Some external storage media need to wait until the drive system operates stably, and some external storage media need to be initialized before operation. It is a well-known fact that these processes take a relatively long time. Therefore, if this process is performed at the time of activation, the time until the user uses the device (activation time) is significantly increased, and the convenience for the user is significantly impaired.

  The present invention has been made in view of the above, and an object of the present invention is to provide an interface circuit and an image forming apparatus capable of confirming the validity of an encryptor regardless of the state of an external storage medium.

  In order to solve the above-described problems and achieve the object, the present invention provides a read / write DMA controller for directly performing a read or write operation on a memory, and an encryptor for encrypting or decrypting data. An SRAM for temporarily storing transfer data from the memory or transfer data from an external storage medium, a memory control module for transferring data between the encryptor and the SRAM, and the external storage medium An interface control module for transferring data between the SRAM and the SRAM, a mode selection unit for setting a test mode for the encryptor, a DMA controller control unit for controlling the operation of the DMA controller during the test mode, An encryption controller for controlling the operation of the encryption device in the test mode, Performs tests related to encryption and decryption of the encryptor by switching the transfer direction of the DMA controller so as to read and write test data between the memory and the SRAM through the encryptor during the mode. And a test circuit.

  According to another aspect of the present invention, there is provided the interface circuit according to any one of the above-mentioned inventions, including the DMA controller, to which an external storage medium is connected, a CPU for controlling operation of the apparatus according to software, and various data. And a memory that can be accessed from the CPU or the DMA controller, a scanner that reads a document image, and a plotter that prints out the image according to image data.

  According to the present invention, it is possible to provide an interface circuit and an image forming apparatus that can confirm the validity of an encryption device regardless of the state of an external storage medium.

FIG. 1 is a schematic block diagram illustrating a configuration example of an image forming apparatus according to the present embodiment. FIG. 2 is a schematic block diagram illustrating a configuration example of the external media IF 15. FIG. 3 is a schematic block diagram illustrating a configuration example of the IF control unit. FIG. 4 is a schematic flowchart showing control of software executed by the CPU. FIG. 5 is a schematic flowchart showing an example of operation control when the test circuit tests the encryption function of the encryption device. FIG. 6 is a schematic flowchart showing an example of operation control when the test circuit tests the decryption function of the encryptor. FIG. 7 is a schematic block diagram showing a configuration example of Modification 1 of the present embodiment. FIG. 8 is a schematic flowchart showing an example of operation control when the test circuit tests the encryption function of the encryption device in the second modification. FIG. 9 is a schematic flowchart showing an example of operation control when testing the decryption function of the encryptor in the second modification. FIG. 10 is a schematic flowchart showing control of software executed by the CPU in the second modification.

  Embodiments of an interface circuit and an image forming apparatus according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

  FIG. 1 is a schematic block diagram illustrating a configuration example of an image forming apparatus according to the present embodiment. The image forming apparatus according to the present embodiment includes a CPU 1 that performs operation control so as to control the entire image forming apparatus according to software. In addition to a memory 2 that can be accessed from the CPU 1 and a DMA controller (to be described later) and stores various data, a plurality of image processing algorithm modules such as a scanner 3, a plotter 4, an external storage medium 5, a FAX 6, and a network 7 are provided. The scanner 3 is a device that reads a document image. The plotter 4 is a device that prints out image data. The FAX 6 is a device for performing facsimile communication according to a connected facsimile line network. The network 7 is a communication network such as a LAN (Local Area Network) for exchanging data with a device such as a personal computer.

  The CPU 1 is connected to a data bus 19 via a CPU I / F (interface) 11 that performs access control. Similarly, a memory 2, a scanner 3, a plotter 4, an external storage medium 5, a FAX 6, and a network 7 are respectively a memory I / F 12 that performs access control, a scanner input unit 13, a plotter output unit 14, an external medium IF 15, and a FAX I. / F16 and the network I / F17 are connected to the data bus 19. These access control units such as the CPU I / F 11 have an ASIC (Application Specific IC) 10 configuration. The ASIC 10 also includes a rotator 18 that rotates the direction of the image data.

  FIG. 2 is a schematic block diagram illustrating a configuration example of the external media IF 15. The external media IF 15 controls access to the external storage medium 5 such as a USB memory, and constitutes an interface circuit of the present embodiment. The external media IF 15 of the present embodiment includes an SRAM (Static RAM) 151, a read / write DMA controller 152, an encryptor 153, and an IF control unit 160. The SRAM 151 is a memory that is used as a temporary buffer when reading from the memory 2 and transferring to the external storage medium 5. This is because data transfer to the external storage medium 5 generally requires a certain amount of data to be sent continuously. The DMA controller 152 is for directly performing data read or data write to the memory 2 without going through the CPU 1. Normally, the external storage medium 5 performs exclusive read and write operations. Therefore, in order to reduce the circuit scale, a DMA controller 152 that is also used as a read / write is usually used. The encryptor 153 encrypts data read by the DMA controller 152, or decrypts encrypted data read from the external storage medium 5 and passes the data to the DMA controller 152. Part. The IF control unit 160 is a block that controls an interface for accessing the external storage medium 5.

  FIG. 3 is a schematic block diagram illustrating a configuration example of the IF control unit 160. The IF control unit 160 of the present embodiment is configured to include a test circuit 170 in addition to the memory control module 161 and the IF control module 162. The memory control module 161 is a functional unit that interfaces with the encryptor 153. That is, the memory control module 161 controls the encryptor 153 to acquire data from the DMA controller 152 and stores it in the SRAM 151, or acquires data from the SRAM 151 and controls the encryptor 153 to store data in the DMA controller 152. It has the function to do. The IF control module 162 is a functional unit that interfaces with the external storage medium 5. In other words, the IF control module 162 has a function of acquiring data from the SRAM 151 and transferring it to the external storage medium 5 or acquiring data from the external storage medium 5 and storing it in the SRAM 151.

  The test circuit 170 includes a mode selection unit 171, an IF operation control unit 172, an encoder control unit 173, a DMA controller control unit 174, a read address holding unit 175, a write address holding unit 176, a test data size holding unit 177, and a data counter 178. And a completion notification unit 179. The mode selection unit 171 serves as a switch for selecting whether or not to perform an encryption test. As a mode, a “normal transfer” mode and an “encryptor test” mode can be selected. The “normal transfer” mode is a mode in which normal transfer is performed without performing a test. The “encryptor test” mode is a mode selected when confirming the operation of the encryptor 153. The IF operation control unit 172 functions to stop the IF control module 162 and operate the memory control module 161 according to a control flow described later when the “encryptor test” mode is selected by the mode selection. The encryption device control unit 173 is a functional unit that selects the operation mode of the encryption device 153. The encryptor 153 has three operation modes of “encryption”, “decryption”, and “through”. The encryption device control unit 173 controls these modes according to a control flow described later. The DMA controller control unit 174 is a functional unit that controls the transfer direction of the DMA controller 152 that also serves as a read / write. The completion notification unit 179 is a functional unit that notifies the software that the operation of the test circuit 170 has been completed.

  The read address holding unit 175 holds an address set by software and having test data. The write address holding unit 176 holds an address to which a test result is set, which is set from software. The test data size holding unit 177 is set from software and holds the size of the test data. The write data counter 178 holds the number of data that has been written. When the count value of the write data counter 178 and the held value of the test data size are the same, the write end condition is set.

  FIG. 4 is a schematic flowchart showing control of software executed by the CPU 1. First, the software prepares test input data and expected value data (encryption result) in the memory 2 (steps S1 and S2). Further, an output destination memory area for placing output data is secured (step S3). Further, the operation mode of the test circuit 170 is set to the “encryptor test” mode (step S4). Then, the first address of the test input data prepared on the memory 2 is set in the read address holding unit 175 (step S5). Similarly, the first address of the output destination of the output data secured on the memory 2 is set in the write address holding unit 176 (step S6). Further, the data size of the test input data prepared on the memory 2 is set in the test data size holding unit 177 (step S7). After completing these settings, the test circuit 170 is activated (step S8). Thereafter, when a test completion notification is received from the test circuit 170 (step S9), the output data and the expected value data are compared (step S10). If they do not match (step S11: Yes), predetermined error processing is performed. If the output data matches the expected value data (step S11: No), it can be determined that the encryptor 153 is operating normally, and the test is terminated.

  FIG. 5 is a schematic flowchart showing an example of operation control when the test circuit 170 tests the encryption function of the encryptor 153. When activated, the test circuit 170 determines whether the mode is the “encryption test” mode (step S101). If it is not in the “encryption test” mode (step S101: No), the process is terminated without performing the encryption confirmation test. When the “encryption test” mode is set (step S101: Yes), an encryption test is executed.

  The encryption test is executed according to the following procedure. First, input data is read, encrypted, and stored in the SRAM 151. The DMA controller control unit 174 sets memory read in the DMA controller 152 (step S103), and sets the transfer size in the DMA controller 152 so that the data size that can be held in the SRAM 151 is transferred (step S104). At the same time, the DMA controller 152 is notified of the address held in the read address holding unit 175 as the read start address. Next, the encryptor control unit 173 sets the encryptor 153 to the “encryption” mode (step 105). Further, the IF operation control unit 172 stops the operation so that the IF control module 162 does not read data from the SRAM 151 (step S106), and the memory control module 161 is set to perform the memory read operation (step S107). . Next, the DMA controller control unit 174 activates the DMA controller 152 (step S108).

  The DMA controller 152 reads data for the set data size from the set read start address from the memory 2 and transfers it to the encryptor 153 (steps S109 and S110). The encryptor 153 encrypts the received data and transfers it to the memory control module 161 (step S111). The memory control module 161 writes the encrypted data transferred from the encryptor 153 to the SRAM 151 (step S112). When the transfer is completed, the test circuit 170 adds the address corresponding to the transferred data size to the read address (step S113).

  Next, the encrypted data written in the SRAM 151 is written back to the memory 2. First, the DMA controller control unit 174 sets the DMA controller 152 to memory write (step S121), and sets the transfer size so that data stored in the SRAM 151 is transferred (step S122). At the same time, the DMA controller 152 is notified of the address held in the write address holding unit 176 as the write start address. Further, the encryption device controller 173 sets the encryption device 153 to the “through” mode (step S123). Further, the IF operation control unit 172 stops the operation so that the IF control module 162 does not write data to the SRAM 151 (step S124) and sets the memory control module 161 to perform the memory write operation (step S125). . Then, the DMA controller 152 is activated by the DMA controller control unit 174 (step S126).

  First, the memory control module 161 reads data from the SRAM 151 and transfers it to the encryptor 153 (steps S127 and S128). The encryptor 153 transfers (through) the received data to the DMA controller 152 as it is (step S129). The DMA controller 152 writes the data for the set data from the set write start address to the memory 2 (step S130). When the transfer is completed, the data counter 178 adds only the write data size (step S131), and the test circuit 170 also adds the address corresponding to the transferred data size for the write address (step S132).

  The reading from the memory 2 and the writing operation to the memory 2 as described above are repeated until the value held in the test data size holding unit 177 is the same as the value of the data counter 178 (step S102). When all the data transfer is completed, the test circuit 170 notifies the software to the completion by the completion notification unit 179 (step S133).

  FIG. 6 is a schematic flowchart showing an example of operation control when the test circuit 170 tests the decryption function of the encryptor 153. Except that the input data is replaced with the encrypted data and the expected value data is replaced with the decryption result, this is the same as the case of the flowchart shown in FIG.

  First, when activated, the test circuit 170 determines whether or not the mode is the “decoding test” mode (step S151). If it is not in the “decryption test” mode (step S151: No), the process is terminated without performing the decryption confirmation test. When the “decryption test” mode is set (step S151: Yes), the decryption test is executed.

  The decryption test is executed according to the following procedure. First, the encrypted input data is read, and the encrypted data is stored in the SRAM 151 as it is. The DMA controller control unit 174 sets memory read in the DMA controller 152 (step S153), and sets the transfer size in the DMA controller 152 so that the data size that can be held in the SRAM 151 is transferred (step S154). At the same time, the DMA controller 152 is notified of the address held in the read address holding unit 175 as the read start address. Next, the encryptor control unit 173 sets the encryptor 153 to the “through” mode (step 155). Further, the IF operation control unit 172 stops the operation so that the IF control module 162 does not read data from the SRAM 151 (step S156) and sets the memory control module 161 to perform a memory read operation (step S157). . Next, the DMA controller control unit 174 activates the DMA controller 152 (step S158).

  The DMA controller 152 reads data for the set data size from the set read start address from the memory 2 and transfers the data to the encryptor 153 (steps S159 and S160). The encryptor 153 passes the received data and transfers it to the memory control module 161 as it is (step S161). The memory control module 161 writes the encrypted data transferred as it is from the encryptor 153 to the SRAM 151 (step S162). When the transfer is completed, the test circuit 170 adds the address corresponding to the transferred data size to the read address (step S113).

  Next, the encrypted data written in the SRAM 151 is decrypted and written back to the memory 2. First, the DMA controller control unit 174 sets the DMA controller 152 to memory write (step S171), and sets the transfer size so that the data stored in the SRAM 151 is transferred (step S172). At the same time, the DMA controller 152 is notified of the address held in the write address holding unit 176 as the write start address. Further, the encryptor control unit 173 sets the encryptor 153 to the “decryption” mode (step S173). Further, the IF operation control unit 172 stops the operation so that the IF control module 162 does not write data to the SRAM 151 (step S174) and sets the memory control module 161 to perform the memory write operation (step S175). . Then, the DMA controller 152 is activated by the DMA controller control unit 174 (step S176).

  First, the memory control module 161 reads encrypted data from the SRAM 151 and transfers it to the encryptor 153 (steps S177 and S178). The encryptor 153 decrypts the received encrypted data and transfers it to the DMA controller 152 (step S179). The DMA controller 152 writes the data for the set data from the set write start address to the memory 2 (step S180). When the transfer is completed, the data counter 178 adds only the write data size (step S181), and the test circuit 170 also adds the address corresponding to the transferred data size for the write address (step S182).

  The reading from the memory 2 and the writing operation to the memory 2 as described above are repeated until the value held in the test data size holding unit 177 is the same as the value of the data counter 178 (step S152). When all the data transfer is completed, the test circuit 170 notifies the software to the completion by the completion notification unit 179 (step S183).

  By generating the completion notification as an interrupt, the software can easily perform other processing after the test circuit 170 is activated until a test completion interrupt occurs. The completion notification may be notified by a register. In this case, the completion notification register is initialized simultaneously with the test circuit activation.

  As described above, according to the present embodiment, in the test mode, the transfer direction of the DMA controller 152 is switched and controlled so that the test data is read and written between the memory 2 and the SRAM 151 through the encryptor 153 in a reciprocal manner. Since the test circuit 170 for performing a test relating to encryption and decryption of the encryptor 153 is provided, the test data is transferred back and forth between the memory 2 and the SRAM 151 while automatically switching the transfer direction of the DMA controller 152. Since the external storage medium 5 is not used, the authenticity of the encryptor 153 can be confirmed regardless of the state of the external storage medium 5.

(Modification 1)
FIG. 7 is a schematic block diagram showing a configuration example of Modification 1 of the present embodiment. The test circuit 180 of this modification is a combination of a read address holding unit 175 and a write address holding unit 176 in one address holding unit 181. Since the data size does not normally change with the encryption by the encryption device 153, the software setting can be reduced by adding the following conditions. The first method is a calculation method in which the output destination address is address hold + data size hold on condition that the software continuously secures the input data and the output destination area. That is, the output data may be output to a position where the address has advanced by the test data size from the position of the input data on the memory 2. The second is a method of designating the place where the input data was found as the output destination because the output of the result is always delayed with respect to the reading of the input data. That is, the output data may be overwritten on the input data on the memory 2. By doing so, it is possible to reduce the memory area secured in the output destination.

(Modification 2)
In the second modification of the present embodiment, an output completion notification is performed for each memory read / write. FIG. 8 is a schematic flowchart showing an example of operation control when the test circuit 170 tests the encryption function of the encryptor 153 in the second modification, and FIG. 9 tests the decryption function of the encryptor 153 in the second modification. FIG. 10 is a schematic flowchart showing control of software executed by the CPU 1 in the second modification.

  First, the encryption function test is basically the same as in the case of FIG. 5, but after the memory read and memory write are performed, the output completion notification is sent to the software (step S141). Thereafter, when a transfer continuation notice is received from the software (step S142), the transfer is resumed. At this time, the output destination address is not changed. The decryption function test is basically the same as in the case of FIG. 6, but after the memory read and memory write are performed, the output completion notification is sent to the software (step S191). Thereafter, when a transfer continuation notice is received from the software (step S192), the transfer is resumed. At this time, the output destination address is not changed. By doing so, it is sufficient to secure the memory reservation amount of the output destination not the test data size but the size of the SRAM 151, and the test can be executed with a small memory area.

  As control on the software side, as shown in FIG. 10, when the output completion notification is confirmed from the hardware side (step S22), the output data is compared with the expected value data (step S23), and it is determined whether or not there is a mismatch. (Step S24). If they do not match (step S24: Yes), predetermined error processing is performed (step S25). On the other hand, if they match (step S24: No), the transfer is continued to the hardware (step S26). Such operation control is repeated until the transfer is completed (step S21: Yes).

1 CPU
2 Memory 3 Scanner 4 Plotter 15 External media IF
151 SRAM
152 Read / write DMA controller 153 Encoder 170, 180 Test circuit 171 Mode selection unit 173 Encryptor control unit 174 DMA controller control unit 175 Read address holding unit 176 Write address holding unit 177 Test data size holding unit 178 Data counter 179 Completion Notification unit 181 Address holding unit

JP 2007-215028 A

Claims (10)

A DMA controller that also serves as a read / write for directly performing a read or write operation to a memory;
An encryptor for encrypting or decrypting data;
SRAM for temporarily storing transfer data from the memory or transfer data from an external storage medium;
A memory control module for transferring data between the encryptor and the SRAM;
An interface control module for exchanging data between the external storage medium and the SRAM;
A mode selection unit for setting a test mode for the encryptor, a DMA controller control unit for controlling the operation of the DMA controller during the test mode, and an encryptor control unit for controlling the operation of the encryptor during the test mode. And encrypting and decrypting the encryptor by switching the transfer direction of the DMA controller so as to read and write test data between the memory and the SRAM through the encryptor in the test mode in a reciprocating manner. A test circuit for performing a test on
An interface circuit comprising:   The encryption unit controller encrypts test data read from the memory and writes it to the SRAM during an encryption test in a test mode, and passes the encrypted test data read from the SRAM through the memory. The interface circuit according to claim 1, wherein the encryptor is controlled so as to be written back.   The encryption controller controls the encrypted test data read from the memory to be written to the SRAM during the decryption test in the test mode, and decrypts the encrypted test data read from the SRAM. The interface circuit according to claim 1, wherein the encryptor is controlled to write back to the memory. The test circuit includes:
A read address holding unit for holding a data read address in the test mode;
A write address holding unit for holding a data write address in the test mode;
A test data size holding unit for setting the data size to be transferred in the test mode;
A write data counter that holds the size of the write back to the memory during test mode;
A completion notification unit that notifies the software of completion when the write counter becomes the same as the test data size in the test mode;
The interface circuit according to claim 1, further comprising:   The interface circuit according to claim 4, wherein the completion notification unit generates a completion notification by interruption.   The interface circuit according to claim 4, wherein the completion notification unit notifies the completion notification using a register.   5. The interface circuit according to claim 4, wherein the read address holding unit and the write address holding unit are configured by one address holding unit, and the output data is overwritten on the input data on the memory.   The read address holding unit and the write address holding unit are configured as a single address holding unit, and output data is output to a position where the address is advanced by the test data size from the position of the input data on the memory. The interface circuit according to claim 4.   5. The interface circuit according to claim 4, wherein the completion notification unit performs an operation control so as to perform an output completion notification for each read / write operation and temporarily suspend data transfer. The interface circuit according to any one of claims 1 to 9, comprising the DMA controller and connected to an external storage medium;
A CPU for controlling the operation of the apparatus according to software,
A memory for storing various data and accessible from the CPU or the DMA controller;
A scanner that reads the original image;
A plotter that prints out according to the image data;
An image forming apparatus comprising:

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