JPS5890849A - Encryption test equipment - Google Patents

Abstract

PURPOSE:To make the self-test possible, by switching the transmission and reception state of an encryption device for semi-duplex communication in time division, storing a test signal from a transmission circuit to a memory at transmission, reading out it at the reception state and giving it to a reception circuit. CONSTITUTION:A self-test circuit 10 is connected to a transmission circuit 11 and a reception circuit 12 of an encryption device, and when the encryption device is at transmission state, a test signal of a prescribed length is generated from a test signal generating circuit 1, the test signal is inputted to the transmission circuit 11 for encryption and the test signal is sequentially stored in a memory 3. In switching this device to the reception state, the test signal of the memory 3 is read out and inputted to the reception circuit 12, where the interpretation of encryption is processed and the restored test signal is inputted to a comparison discrimination circuit 5. The circuit 5 compares the restored test signal from the reception circuit 12 with that from the circuit 1 bit by bit for the discrimination of propriety and the result is shown on a display section 4.

Description

[Detailed description of the invention] The present invention relates to testing of cryptographic devices that perform half-duplex communication.

Generally, when transmitting data such as digital signals and facsimile signals, the data is encrypted and transmitted in order to prevent it from being received by a third party, and then the receiving side decodes and receives the encrypted data. In this case, there are a full-duplex communication method that performs transmission and reception at the same time, and a half-duplex communication method that performs breathtalk-type transmission and reception.

The test equipment that tests the transmission and reception of such cryptographic equipment is
Since the operation of the device is half-duplex, and the transmitting state and receiving state cannot occur at the same time, it is not possible to use the loop-back test method used in full-duplex communication cryptographic devices. Therefore, these transmitter/receiver circuits either do not have a self-test function, or even if they do have a self-test function, when performing a self-test, it is recommended to perform a test on the transmitter side and a test on the receiver side separately. It was getting worse.

In this case, the self-test is set in the cryptographic device in advance, a test signal is given to the transmitting circuit or the receiving circuit, and a judgment signal corresponding to the output signal from the transmitting circuit or the receiving circuit and the test signal in the self-test circuit prepared in advance is sent. The quality of the test was determined by comparing the results. The reason why the key is used for self-testing is that even if a certain test signal is given to the transmitting circuit or the receiving circuit, if the key changes, the output signal of the transmitting circuit or the receiving circuit will not correspond to the key. Judgment 4 corresponds to the test signals for the number of key types.
This is because preparing Fj1 in advance requires a huge amount of memory circuitry. Therefore, during self-examination,
This method has disadvantages in that it takes time and effort to perform tests separately on the sending and receiving sides, and it is not possible to test arbitrary keys.

An object of the present invention is to provide a cryptographic testing device that can automatically perform a self-test on an arbitrary key by time-divisionally switching between the transmission state and receipt of a cryptographic device that performs half-duplex communication. Our goal is to provide the following.

The 4-% test device of the present invention encodes the digital signal.
A cryptographic testing device for testing a device including a cryptographic circuit that encodes a digital signal and a decoding circuit that decodes the encoded signal, the cryptographic test device comprising: a test signal generation circuit that generates a digital test signal of a predetermined length in accordance with a predetermined start signal; a storage circuit that stores an encrypted digital test signal and supplies it to the decoding circuit after a predetermined time; a comparison and determination circuit that compares the output of the decoding circuit with the test signal of the test signal circuit and outputs the comparison result; The start signal is formed from each synchronization signal of the encryption circuit and the decryption circuit, and is provided with means for supplying it to the test signal generation circuit.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram containing an embodiment of the invention. In the figure, the area inside the dotted line is the self-test circuit [10], and the input and output are connected to the transmitting circuit 11 and receiving circuit 12 of the cryptographic device to be tested, and the transmitting circuit 11 performs the encryption process. , Reception times j! ! At step 12, restoration processing is performed. In the self-test state of the device, the transmitting state and receiving state of the device are switched in a time-sharing manner.

First, in the transmitting state, the test signal generation circuit! A test signal having a predetermined length (for example, 32 bits) is generated, and the test signal is input to the transmitting circuit 11. The test signal encrypted by the transmitting circuit 11 is stored in the memory 3.
are stored sequentially. Next, when this device switches from the transmitting state to the receiving state, the test signal stored in the memory 3 is read out and input to the receiving circuit 12. The test signal restored by decryption processing in the reception circuit 12 is input to the comparison/judgment circuit 5. Since the comparison/judgment circuit 5 receives the restored test signal inputted from the reception circuit 12 and the test signal from the test signal generation circuit 1 at the same time, the comparison/judgment circuit 5 compares these two signals to obtain a self-test result. Each bit is examined to determine whether it is good or bad, and the results are shown on the display section 4.

Note that in order to compare the two test years, it is necessary to match the starting positions of the two test signals. At the time of this round transmission, the pulse at the end of the synchronization signal sent at the beginning of the message is sent to the OR circuit. By using the signal as a start signal for the test signal generation circuit 1 through the signal, the start positions of the two test signals at the time of comparison are aligned.

As explained above, during a self-test of a cryptographic device that performs half-duplex communication, the present invention switches the transmitting state and receiving state of the device in a time-sharing manner, and stores test signals output from a transmitting circuit during transmission in a memory. By accumulating this signal in the receiving state and applying it to the receiving circuit, it is possible to automatically perform a self-test on any key.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a schematic diagram of an embodiment of the present invention. In the figure, 1... test signal generation circuit, 2... old OR circuit, 3... memory, 4... display section, 5
. . . Comparison/determination circuit, 10 . . . Self-test circuit, 11 . . . Transmission circuit, 12 .

Claims (1)

[Claims] A test signal generation circuit that generates a digital test signal of a predetermined length in accordance with a predetermined start signal in a cryptographic testing device that tests a device including a cryptographic circuit that encrypts a digital signal and a decoding circuit that decodes the encoded signal; A storage circuit that stores the digital test signal encrypted by the encryption circuit and supplies it to the decoding circuit after a predetermined time, compares the output of the decoding circuit with the test signal of the test signal generation circuit, and outputs the comparison result. A cryptographic testing device comprising: a comparison/judgment circuit; and means for forming the start signal from each synchronizing signal of the encrypting circuit and the decoding circuit and supplying it to the test signal generating circuit.