JP2012191578A - Driving method of 4 line ccd unit, image reading method, image reader and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily suppress excessive voltage generated when a mode is switched from a color to a monochrome or from the monochrome to the color without complicating control in a driving method of a 4 line CCD unit.SOLUTION: In a driving method of a 4 line CCD unit 103 having separately a color drive clock input terminal and a monochrome drive clock input terminal, a color drive clock (shift pulse SP1 and transfer clocks TC1 and TC2) and a monochrome drive clock (shift pulse SP2 and transfer clocks TC1' and TC2') are inputted from the corresponding input terminals to the 4 line CCD unit 103 when the 4 line CCD unit 103 is operated at the color mode or at the monochrome mode.

Description

  The present invention relates to a driving method for a 4-line CCD unit having separate color driving clock input terminals and monochrome driving clock input terminals, and an image for reading an original image using the 4-line CCD unit driven by this driving method. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reading method, an image reading apparatus including a 4-line CCD unit, and an image forming apparatus including the image reading apparatus as an image reading unit.

Conventionally, a line image sensor CCD (Charge
Coupled Device) is widely used.
This CCD generally comprises a light receiving unit in which photodiodes as photoelectric conversion elements are arranged for the number of pixels, and a transfer register that temporarily accumulates charges received from the light receiving unit and sequentially transfers them toward the output unit. A transfer unit and an output unit that converts the charge accumulated and transferred in the transfer register at the final stage of the transfer unit into an analog voltage and outputs the analog voltage are provided.

In such a CCD, when a color image is read by one original scan, a three-line CCD having R (red), G (green) and B (blue) light receiving portions is usually used.
On the other hand, when reading a monochrome image, a one-line CCD having a K (monochrome) light receiving unit is used.
A 4-line CCD unit is also known in which these color 3-line CCD and monochrome 1-line CCD are unitized so as to be compatible with both color and monochrome images.

  For example, in Patent Document 1, as an example of a configuration of a four-line CCD unit, a drive clock input terminal for driving a color transfer register among transfer registers that transfer charges accumulated in a light receiving unit of a CCD is provided. A configuration is disclosed in which a drive clock input terminal for driving a monochrome transfer register is provided, and the color and monochrome transfer registers are driven separately.

Here, conventional driving methods for driving the above-described CCD and 4-line CCD unit will be described with reference to FIGS. FIG. 7 is a timing chart of the driving clock input to the CCD, and FIG. 8 is a timing chart of the conventional driving clock input to the 4-line CCD unit in the monochrome mode.
As shown in FIG. 7, the main drive clocks for driving the CCD include a first transfer clock, a second transfer clock, a reset pulse, a clamp pulse, and the like. Depending on the rise or fall of these drive clocks. CCD drive control is performed. In the figure, an analog output signal from the CCD is also shown.

Of these drive clocks, the first transfer clock is a clock that is input to sequentially transfer the charges accumulated in the transfer register of the CCD to the transfer register on the output unit side in the subsequent stage. The second transfer clock is an inverted signal of the first transfer clock.
The reset pulse is a pulse that is input to reset the analog voltage and discard it to GND. The clamp pulse is a pulse that is input to clamp the reset potential to a predetermined reference potential.

When the CCD is driven at such timing, it is stored in the final stage transfer register in proportion to the intensity of reflected light from the original at the timing of the fall of the first transfer clock (rise of the second transfer clock). The analog voltage corresponding to the generated charge is added to the reference DC offset potential and appears in the analog output signal.
This analog voltage is then reset by the input of a reset pulse, and reset noise is superimposed. The reset noise is clamped to a predetermined reference potential by inputting a clamp pulse, and stabilized to a reference DC offset potential.

More specifically, the charges accumulated in the transfer register of the CCD are sequentially transferred to the subsequent stage on the transfer register arranged for the number of pixels by the input of the first and second transfer clocks of the two-phase drive. . The charge accumulated in the charge transfer register at the final stage is converted into an analog voltage at the falling timing of the first transfer clock.
Thereafter, the analog voltage is reset by the reset pulse and discarded to GND before the next falling timing of the first transfer clock comes, and the potential after the reset is clamped to the DC offset potential by the clamp pulse. Such an operation is performed every time before the charge accumulated in the transfer register before the final stage is transferred to the transfer register at the final stage, so that an appropriate analog voltage value is taken out.
Note that the number of first and second transfer clocks to be input is the same number of clocks as the number of photodiodes arranged in the number of pixels, and charges on one line are transferred.

  On the other hand, the conventional monochrome mode driving method of the 4-line CCD unit, as shown in FIG. 8, is a color / monochrome switching signal, monochrome shift pulse, first monochrome transfer clock, second, as the main drive clock. A monochrome transfer clock, a reset pulse, a clamp pulse, a color shift pulse, a first color transfer clock, a second color transfer clock, and the like are input.

  Note that this 4-line CCD unit is a 4-line CCD unit provided with a color shift pulse input terminal and transfer clock input terminal and a monochrome shift pulse input terminal and transfer clock input terminal separately. Of these drive clocks, the description of the reset pulse and the clamp pulse is as described above, and the description thereof is omitted. Moreover, the wavy line in the figure indicates that clocks or pulses are continuously input.

First, the color / monochrome switching signal is for switching modes by changing the signal from H to L or from L to H by fixing the H level fixed to monochrome and the L level fixing to color. In the state shown in the figure, the monochrome mode is set with the H level fixed.
The monochrome shift pulse is a pulse that is input to shift the charges accumulated in the photodiodes of the light receiving unit in the monochrome one-line CCD to the transfer register. With this shift pulse input, all charges are shifted to the transfer register from the photodiodes arranged in one line for the number of pixels.
The first monochrome transfer clock is a clock input to transfer the charge shifted to the transfer register side to the transfer register at the subsequent stage. The second monochrome transfer clock is an inverted signal of the first monochrome transfer clock.

The color shift pulse is a pulse that is input to shift the charges accumulated in the photodiodes of the light receiving unit in the color 3-line CCD to the transfer register side. With this shift pulse input, all charges are shifted from the photodiodes arranged in the number of pixels on three lines to the transfer register side.
The first and second color transfer clocks are the same as the monochrome transfer clocks, and are simultaneously input to all three lines during color reading.

  In such a 4-line CCD unit, in the monochrome mode, as shown in the figure, first, the charges accumulated in all the photodiodes in the monochrome 1-line CCD by the input of the monochrome shift pulse are transferred to the transfer register side. After that, the first and second monochrome transfer clocks are continuously input, and the charges for each pixel are converted into analog voltages and output one after another. This process is repeated until all the charges on one line are output. When all the charges have been output, the next shift pulse is input and the same processing as described above is repeated to read a monochrome original image.

On the other hand, in the monochrome mode, since it is not necessary to drive the color 3-line CCD, the color shift pulse and the first and second color transfer clocks are fixed to the H or L level as shown. . As described above, the operation of the color 3-line CCD that is not used is stopped by not inputting a pulse or clock, thereby reducing power consumption and suppressing unnecessary radiation (Electromagnetic Interference: EMI). Is generally done.
When a color image is read, the color / monochrome switching signal changes from H to L to switch to the color mode, and the monochrome shift pulse and monochrome transfer clock, and the color shift pulse and color transfer clock respectively. It will be replaced.

  By the way, in the latter stage of the CCD described above, generally, an analog front end (analog processing (analog image signal) obtained from the output is subjected to various analog processing and converted into a digital image signal ( Hereinafter, an IC integrated with each circuit for analog processing called “AFE” is connected, and an AC coupling capacitor for AC coupling is inserted in series between the AFE and the CCD. Yes.

For this reason, only the change (AC component) of the analog image signal output from the CCD is transmitted to the AFE. In other words, this means that output fluctuations, which are changes in the analog image signal output from the CCD, are always transmitted to the AFE. For this reason, for example, when the CCD temporarily generates an excessive voltage exceeding the rating of the AFE, it is transmitted to the AFE as it is, and there is a possibility that the characteristic deterioration of the AFE and the worst device destruction are caused. This occurs in the same manner even when a 4-line CCD unit is used.
For this reason, the problem of excessive input voltage to the AFE is known, and several methods for suppressing the excessive voltage have been proposed.

  For example, in Japanese Patent Laid-Open No. 2004-260, AC is used for the purpose of suppressing an excessive voltage that is generated because unnecessary charges accumulated when the CCD power source is turned off are discharged to the AFE at once immediately after the CCD power source is turned on. Clamping means for fixing the reference potential of the analog image signal to an arbitrary potential by charging / discharging the coupling capacitor. As a sequence corresponding to an excessive voltage, before turning on the CCD power supply from OFF to ON, the clamping process is performed in one line in advance. It is proposed that the CCD power supply is turned from OFF to ON after a sufficient time has passed through the entire period, and even after turning ON, the transition to the normal clamping operation is made after the time until the influence of the excessive voltage becomes sufficiently small. ing.

  However, in the above-mentioned 4-line CCD unit, even if the power supply to the unit is continued in the ON state, it has not been used until the mode switching from color to monochrome or monochrome to color. Unnecessary charges accumulated in the CCD (for example, a monochrome 1-line CCD if the color mode was used, or a color 3-line CCD if the monochrome mode was used) are discharged at once after the mode switching. There was a problem that excessive voltage was generated.

This problem will be described with reference to FIG. FIG. 9 is a diagram for explaining an excessive voltage generated when the monochrome mode is switched to the color mode in the 4-line CCD unit according to the conventional driving method.
Note that the monochrome or color pulses and clocks shown in the figure are the same as those described in FIG. In this figure, an analog output signal is also shown. The analog output signals are OS1, OS2, and OS3, which correspond to the output signals output from the CCDs of the RGB lines in the order of RGB, and any one of them can be used as a monochrome output signal. It is also used. In this example, OS1 is also used, and monochrome analog output signals and R analog output signals of colors are output to OS1. Further, the 4-line CCD unit used here is provided with a color shift pulse input terminal and transfer clock input terminal and a monochrome shift pulse input terminal and transfer clock input terminal separately as in FIG. Shall.

  In the monochrome mode, since the first and second color transfer clocks are stopped, unnecessary charges are accumulated in the photodiodes arranged in the number of pixels for each line in the 3-line CCD, and the color mode. Immediately after switching to, as shown in the figure, an excessive voltage is generated. This excessive voltage is also generated immediately after switching from the color mode to the monochrome mode.

In this regard, the technique of Patent Document 1 does not describe means for solving this problem.
On the other hand, when the technique of Patent Document 2 is used, it is necessary to separately perform an excessive voltage handling sequence other than mode switching, and a control signal for executing this sequence is also required, which complicates control in mode switching. There is a problem that switching takes time.

  The present invention solves such a problem, and in the driving method of the 4-line CCD unit, an excessive voltage generated at the time of mode switching from color to monochrome or monochrome to color is easily suppressed without complicating the control. For the purpose.

  In order to achieve the above object, the present invention provides a driving method for a 4-line CCD unit having a color driving clock input terminal and a monochrome driving clock input terminal separately. Both the color driving clock and the monochrome driving clock are input to the 4-line CCD unit from the corresponding input terminals, both in the case of operating in the mode and in the monochrome mode. is there.

  In the driving method for the 4-line CCD unit, the color and monochrome driving clocks include at least a shift pulse and a transfer clock. When the 4-line CCD unit is operated in the color mode, When at least one signal period of the monochrome driving clock is longer than the signal period of the monochrome driving clock when the monochrome driving clock is operated, and the 4-line CCD unit is operated in the monochrome mode. In this case, it is preferable that at least one signal period of the color driving clock is longer than the signal period of the color driving clock when the color driving clock is operated.

Further, in the driving method of the 4-line CCD unit, an operation of inputting both the color driving clock and the monochrome driving clock to the 4-line CCD unit, and the 4-line CCD unit from the color mode. It may be performed only during a predetermined period immediately before switching to the monochrome mode and during a predetermined period immediately before switching the 4-line CCD unit from the monochrome mode to the color mode.
The predetermined period is the period of the monochrome shift pulse in the monochrome mode when switching from the color mode to the monochrome mode, and the color for the color mode in switching from the monochrome mode to the color mode. The period of each of the shift pulses may be one unit, and the period may be a natural number multiple thereof.

The image reading method according to the present invention is an image reading method in which an image reading apparatus provided with a 4-line CCD unit reads an image of a document with the 4-line CCD unit, and the driving means of the image reading apparatus includes the above-mentioned 4 The line CCD unit is driven by any one of the four-line CCD unit driving methods described above.
An image reading apparatus according to the present invention is an image reading apparatus including a 4-line CCD unit, and includes a driving means for driving the 4-line CCD unit by any one of the 4-line CCD unit driving methods. It is.
An image forming apparatus according to the present invention includes the image reading device as an image reading unit.

  According to the driving method of the 4-line CCD unit of the present invention as described above, it is possible to easily suppress the excessive voltage generated when the mode is switched from color to monochrome or from monochrome to color without complicating the control. .

1 is a block diagram illustrating a hardware configuration of an image reading apparatus according to an embodiment of the present invention. It is a schematic diagram of the 4-line CCD unit shown in FIG. It is a detailed circuit diagram between the 4-line CCD unit and AFE in FIG. It is the figure which showed the timing chart of the drive clock input into the 4-line CCD unit in the monochrome mode. FIG. 6 is a timing chart of drive clocks input to a 4-line CCD unit when switching from the monochrome mode to the color mode. It is the figure which showed another timing chart of the drive clock input into the 4-line CCD unit in monochrome mode. It is the figure which showed the timing chart of the drive clock input into CCD. It is the figure which showed the timing chart of the conventional drive clock input into a 4-line CCD unit in monochrome mode. It is a figure for demonstrating the excessive voltage which arises when switching from a monochrome mode to a color mode in the 4-line CCD unit by the conventional drive method.

Hereinafter, embodiments for carrying out the present invention will be specifically described with reference to the drawings.
FIG. 1 is a block diagram showing a hardware configuration of an image reading apparatus 100 according to an embodiment of the present invention.
As shown in FIG. 1, the image reading apparatus 100 includes an illumination light source 101, a light source lighting device 102, a 4-line CCD unit 103, an emitter follower 104, an AC coupling capacitor 105, an AFE 106, a data processing unit 107, a control unit 109, and A storage unit 114 is provided. The writing unit 108 is provided in an image forming apparatus (not shown), and is digital image data directly transmitted from the data processing unit 107 or digital image data stored in the storage unit 114 and transmitted via the control unit 109. Is written on a manuscript.

Among these, the illumination light source 101 is a light source that irradiates light on a document that is a target for image reading. The light source lighting device 102 is an inverter circuit for converting a direct current voltage input from the light source drive control unit 110 into an alternating current voltage and supplying it to the illumination light source 101 for lighting.
The 4-line CCD unit 103 is a line image sensor capable of reading monochrome and color originals, and accumulates charges according to the intensity of reflected light from the originals, and converts the charges into analog voltages for output. belongs to. The configuration of the 4-line CCD unit 103 will be described later with reference to FIG.
The emitter follower 104 is for performing impedance matching between the 4-line CCD unit 103 and the AFE 106.
The AC coupling capacitor 105 is for removing the DC (direct current) component and inputting only the AC (alternating current) component of the analog voltage (analog image signal) output from the 4-line CCD unit 103 to the subsequent AFE 106. It is. The emitter follower 104 and the AC coupling capacitor 105 will be described later with reference to FIG.

The AFE 106 is an IC in which circuits such as an A / D conversion circuit, a clamp circuit, an S / H circuit, and a variable gain circuit that performs gain adjustment are integrated. The AFE 106 converts an analog image signal input to the AFE 106 into a digital image signal by an A / D conversion circuit, and also clamps the level of the analog image signal input by the clamp circuit to a desired constant voltage level. An automatic gain control (AGC) function that adjusts the peak level of the converted digital image signal to a desired level and a black offset adjustment function that sets the black level that is the reference of the digital image signal to a desired output I have.
The data processing unit 107 is for performing various data processing such as shading correction and gamma correction on the digital image signal output from the AFE 106. The processed digital image data is transmitted directly to the writing unit 108 or temporarily stored in the storage unit 114 via the control unit 109 and then transmitted again to the writing unit 108 via the control unit 109.

The control unit 109 controls the entire image reading apparatus 100, and includes a light source drive control unit 110, a CCD drive control unit 111, an AFE drive control unit 112, and a data processing control unit 113.
Among these, the light source drive control part 110 is for controlling the emitted light quantity of the illumination light source 101 by controlling the drive of the light source lighting device 102. Specifically, a direct-current voltage is input (applied) to the light source lighting device 102, or the amount of light emitted from the illumination light source 101 is controlled by inputting a pulse width modulation (PWM) signal.

The CCD drive control unit 111 controls driving of the 4-line CCD unit 103. Specifically, it is selected from the monochrome or color reading modes of the 4-line CCD unit 103 to select the reading mode of the original to be read by the 4-line CCD unit 103, and this is selected as the 4-line CCD unit 103. Or instruct. It also controls the input timing of clocks and pulses to the 4-line CCD unit 103.
The AFE drive control unit 112 is for controlling the drive of the AFE 106, and the data processing control unit 113 is for controlling the drive of the data processing unit 107.
The storage unit 114 stores various drive setting data and digital image data processed by the data processing unit 107. For example, the storage unit 114 is assumed to be a storage medium such as a ROM, RAM, or HDD. Here, the various drive setting data are drive setting data of the light source lighting device 102, drive setting data of the 4-line CCD unit 103, drive setting data of the AFE 106, data processing setting data of the data processing unit 107, and the like.

In such an image reading apparatus 100, when reading a document image, the light source drive control unit 110 first controls the light source lighting device 102 based on the drive setting data stored in the storage unit 114, and the illumination light source 101. Irradiate light. The illumination light is applied to the document, and the reflected light is input to the 4-line CCD unit 103 via a plurality of mirrors (not shown).
Then, the CCD drive control unit 111 controls the 4-line CCD unit based on the drive setting data stored in the storage unit 114, and outputs an analog image signal corresponding to the input light quantity. The output analog image signal is input to the AC coupling capacitor 105 via the emitter follower 104.

  Here, the analog image signal at the stage output from the 4-line CCD unit 103 is based on a certain DC offset voltage, but this offset voltage exceeds the input rated voltage of the AFE 106, and if input to the AFE 106 as it is, Although the DC offset voltage can be removed by the AC coupling capacitor 105, the analog image signal based on the DC offset voltage may be transmitted to the subsequent stage and an AC component exceeding the input rated voltage may be transmitted. For this reason, the AC coupling capacitor 105 is used to shift the DC offset voltage serving as the reference of the analog image signal so that the input rated voltage of the AFE 106 is not exceeded, and then the analog image signal is input to the AFE 106. Yes. This point will be described later.

Next, the analog image signal that has passed through the emitter follower 104 and the AC coupling capacitor 105 is input to the AFE 106. Then, the AFE drive control unit 112 controls the AFE 106 based on the drive setting data stored in the storage unit 114, thereby converting an analog image signal into a digital image signal and performing gain adjustment and the like. Thereafter, the digital image signal is subjected to shading correction, gamma correction, and the like in the data processing unit 107 controlled by the data processing control unit 113 to become digital image data.
As described above, various control units included in the control unit 109 read the document image and generate digital image data by appropriately controlling the illumination light source 101, the 4-line CCD unit 103, the AFE 106, and the like in the image reading apparatus 100. Can do.

Next, the configuration of the 4-line CCD unit 103 will be described with reference to FIG. FIG. 2 is a schematic diagram of the 4-line CCD unit 103 shown in FIG.
As shown in the figure, the 4-line CCD unit 103 includes a red (R) 1-line CCD 103R, a green (G) 1-line CCD 103G, a blue (B) 1-line CCD 103B, and a monochrome (K) 1-line CCD 103K. I have. The one-line CCD 103R for red, the one-line CCD 103G for green, and the one-line CCD 103B for blue constitute a three-line CCD for color.

  As shown in FIG. 2, the 4-line CCD unit 103 has an input terminal for inputting color transfer clocks (TC1 and TC2) and an input terminal for inputting a color shift pulse (Shift Pulse) SP1. (Hereinafter, these input terminals are collectively referred to as “color drive clock input terminals”), input terminals for inputting monochrome transfer clocks TC1 ′ and TC2 ′, and input terminals for inputting monochrome shift pulse SP2 ( Hereinafter, these input terminals are collectively referred to as a “monochrome driving clock input terminal”), which is a 4-line CCD unit.

  Although not shown in this figure, the 4-line CCD unit 103 has an input terminal for inputting a reset pulse and an input terminal for inputting a clamp pulse, in each line CCD. In both color and monochrome modes, the reset pulse and the clamp pulse are collectively input to the corresponding input terminals at a predetermined timing. That is, the reset pulse and the clamp pulse are used in common in the monochrome mode and the color mode.

In such a four-line CCD unit 103, the red one-line CCD 103R includes a red photodiode array R1, a red shift gate R2, a red transfer register R3, and a red output amplifier R4.
Among them, the red photodiode array R1 is provided with a red color filter (not shown) on the light receiving surface, and photodiodes for storing charges corresponding to the intensity of reflected light are arranged for the number of pixels. The received light receiving part.
The red shift gate R2 becomes a path for charges when the charges accumulated in the respective photodiodes of the red photodiode array R1 are collectively shifted to the red transfer register R3 by the input of the shift pulse SP1. It is a gate.

The red transfer register R3 is a transfer unit for temporarily storing the shifted charge and for sequentially transferring the stored charge to a subsequent register in response to the input of the transfer clocks TC1 and TC2.
The red output amplifier R4 is an output unit that converts the charges accumulated in the final stage register of the red transfer register R3 into an analog voltage and outputs the analog voltage. The analog voltage output from the red output amplifier R4 appears in OS1 as an output signal.

  The configurations of the green one-line CCD 103G and the blue one-line CCD 103B are different from the red one-line CCD 103R only in that green and blue color filters (not shown) are provided in the respective photodiode arrays, and thus description thereof is omitted. .

The monochrome one-line CCD 103K includes a monochrome photodiode array K1, monochrome shift gates K2 and K2 ', monochrome transfer registers K3 and K3', and monochrome output amplifiers K4 and K4 '.
Among them, the monochrome photodiode array K1 is not provided with a color filter on the light receiving surface, and has a light receiving portion in which photodiodes for storing charges corresponding to the intensity of reflected light are arranged for the number of pixels. It is.

  The monochrome shift gates K2, K2 ', monochrome transfer registers K3, K3', and monochrome output amplifiers K4, K4 'have the same configuration as the red shift gate R2, transfer register R3, and output amplifier R4, respectively. In monochrome use, these shift gates K2, K2 ', transfer registers K3, K3', and output amplifiers K4, K4 'are arranged symmetrically with a monochrome photodiode array K1 in between, forming a dual channel line CCD. ing.

  In this dual channel type line CCD, among the charges accumulated in the monochrome photodiode array K1, the charges accumulated in the photodiodes corresponding to the odd pixels (ODD) are shifted by the shift pulse SP2. Shifted to transfer register K3 'via K2'. On the other hand, the charge accumulated in the photodiode corresponding to the even pixel (EVEN) is shifted to the transfer register K3 via the shift gate K2 by the input of the shift pulse SP2.

  The charges corresponding to the odd-numbered pixels and even-numbered pixels shifted to the transfer registers K3 and K3 ′ are sequentially transferred to the subsequent stage by the inputs of the transfer clocks TC1 ′ and TC2 ′, and are output via the output amplifiers K4 and K4 ′. Are converted into analog voltages and appear in output signals OS1 and OS2, respectively. Note that an analog voltage corresponding to an odd pixel appears in OS1, and an analog voltage corresponding to an even pixel appears in OS2. As described above, the dual channel type can output analog voltages for two channels at the same time, so that a monochrome image can be read at a higher speed than a three-line CCD for color.

  In such a 4-line CCD unit 103, when the monochrome or color mode is switched, each software in the 4-line CCD unit is operated by a switching signal (Change Signal) CS from the CCD drive control unit 111. An analog voltage output from a color 3-line CCD or a monochrome 1-line CCD is selected and output to the outside of the 4-line CCD unit 103. As shown in the figure, the switching signal CS from the CCD drive control unit 111 is input to the output stage of the 4-line CCD unit 103 via the inverters 201 and 202, and the switching signal CS is input. A monochrome or color switch (SW) is opened and closed by switching H or L of the signal, and an analog voltage from either one is selectively output.

  When the 4-line CCD unit 103 operates in the color mode, the CCD drive control unit 111 controls the input timings of the transfer clocks TC1 and TC2 and the shift pulse SP1 that are input to the color drive clock input terminals, for a total of 3 channels. Outputs analog voltage for minutes.

On the other hand, when operating in the monochrome mode, the CCD drive control unit 111 controls the input timing of the transfer clocks TC1 'and TC2' and the shift pulse SP2 input to the monochrome drive clock input terminal, and the analog voltage for a total of 2ch. Is output.
In the color mode or monochrome mode described above, the CCD drive control unit 111 inputs the reset pulse (not shown) that is input to reset the analog voltage and discard it to GND, and the potential of the output stage after the reset. Assume that the input timing of a clamp pulse (not shown) that is input to clamp the signal to a predetermined reference potential is also controlled.

  The configuration of the 4-line CCD unit 103 shown in FIG. 2 is merely a schematic diagram, and the physical configuration of each line CCD is not limited to this. For example, the monochrome one-line CCD 103K does not have to be a dual channel type, and may have the same configuration as the color one-line CCD and output an analog voltage for one channel. Further, the red photodiode array R1 may be provided in another stage so as to be staggered to increase the resolution.

  Next, a mechanism for preventing the analog voltage from the above-described 4-line CCD unit 103 from exceeding the input rated voltage of the AFE 106 will be described with reference to FIG. FIG. 3 is a detailed circuit diagram between the 4-line CCD unit 103 and the AFE 106 in FIG.

  In this figure, it is assumed that the power supply voltage supplied to the 4-line CCD unit 103 and the emitter follower 104 is 10 to 12V, and the power supply voltage supplied to the AFE 106 is 3.3V. The input rated voltage of the AFE 106 is 0 to 2V. In addition, an output signal A in the figure shows a state in which a negative pulse analog voltage outputted from the 4-line CCD unit 103 is superimposed on the basis of a DC offset voltage of 5 V, and the output signal B is A state in which an analog voltage of a minus pulse at the stage of input to the AFE 106 is superimposed on the basis of the offset voltage of 2V is shown.

  As shown in the figure, the emitter follower 104 is configured using an NPN-type bipolar transistor. Since the emitter follower 104 has a high input impedance and a low output impedance, it is inserted between the 4-line CCD unit 103 and the AFE 106 to match the low impedance in the input stage of the AFE 106. Note that a PNP transistor may be used as the transistor for the emitter follower 104.

Further, the offset voltage on the input side of the AFE 106 is clamped to 2 V by the AC coupling capacitor 105 by a clamp circuit (not shown) of the AFE 106, and the AC voltage
The coupling capacitor 105 inputs an analog voltage superimposed with 2V as a reference to the AFE 106 at the subsequent stage. In other words, the offset voltage reference is level-shifted from 5V to 2V so that the input analog voltage falls within the range of the input rated voltage of the AFE 106, and thus the input rated voltage of the AFE 106 is reduced. An analog voltage not exceeding can be input to the AFE 106.
The power supply voltage value and the offset voltage value described above are examples, and other values may be used in accordance with the device characteristics of the 4-line CCD unit 103 and the AFE 106.

  Here, if the amplitude value (absolute value) of the analog voltage at the stage of output from the 4-line CCD unit 103 is originally 2V or more, the amplitude value is lower than GND even when the offset voltage is 2V. Therefore, it exceeds the lower limit 0 V of the input rated voltage of the AFE 106 and adversely affects the AFE 106. In the worst case, the device is destroyed. Therefore, the analog voltage amplitude value is generally used within a range that falls within the input rated voltage of the AFE 106.

However, in a transient state such as during the state transition of the 4-line CCD unit 103, an excessive voltage exceeding the input rated voltage range may occur. For example, when the power of the 4-line CCD unit 103 is shifted from OFF to ON, an excessive voltage is generated because unnecessary charges accumulated when the power is turned off are discharged all at once immediately after the power is turned on. This is as described in the background section.
Further, in the 4-line CCD unit 103, even when the CCD power is turned on, when the mode is switched between the color mode and the monochrome mode, the unnecessary charge accumulated in the sensor that has not been used until then changes the mode. Immediately after switching, it is discharged at once and an excessive voltage is generated. This is also as described in the background section.

In order to cope with this problem, a characteristic point in the above-described image reading apparatus 100 is a driving method of the 4-line CCD unit 103. Therefore, in connection with this point, a driving method performed by the CCD drive control unit 111 for the 4-line CCD unit 103 will be described with reference to FIGS.
FIG. 4 is a timing chart of drive clocks input to the 4-line CCD unit 103 in the monochrome mode. The description of the various clocks and pulses shown in this figure is the same as described in the background art section, and the description thereof is omitted.

First, in order to read a monochrome image, the CCD drive control unit 111 inputs the shift pulse SP2 to the monochrome shift pulse input terminal among the monochrome drive clock input terminals, and is stored in the monochrome photodiode array K1. The charges are transferred to the monochrome transfer registers K3 and K3 ′, respectively. After that, the monochrome transfer clocks TC1 'and TC2' are input to the monochrome transfer clock input terminal to sequentially transfer charges, and the reset pulse and clamp pulse are input between the transfers to reset the analog voltage. Then, the reset potential is returned to a predetermined reference potential.
As described above, the CCD drive control unit 111 inputs the monochrome shift pulse SP2 and the transfer clocks TC1 'and TC2' to the monochrome drive clock input terminal at the timing shown in FIG. The CCD 103K is driven to read a normal monochrome image.

On the other hand, the CCD drive control unit 111 inputs the color shift pulse SP1 and the transfer clocks TC1 and TC2 to the color 3-line CCDs 103R, G, and B, as in the case of monochrome. The color three-line CCDs 103R, G, and B are input to the terminals and driven.
This makes it possible to always transfer and reset unnecessary charges accumulated in the photodiode arrays of the color 3-line CCDs 103R, G, and B that are not used, and switch from monochrome to color mode. The excessive voltage immediately after can be suppressed. Conversely, even in the color mode, if the monochrome one-line CCD 103K is driven, an excessive voltage immediately after switching from the color to the monochrome mode can be suppressed.

  This means that, when operating in either the color mode or the monochrome mode, both the color drive clock and the monochrome drive clock are input to the corresponding input terminals, respectively, and the color 3-line CCD 103R is input. , G and B and monochrome one-line CCD 103K are driven. Since the color and monochrome drive clocks (shift pulse and transfer clock) are input at the same timing, the drive clocks for the monochrome mode and the color mode can be made common. The configuration of the drive circuit can be simplified.

  In addition, in either the color mode or the monochrome mode, it is only necessary to input drive clocks having the same timing, so that an excessive voltage immediately after the mode switching can be easily suppressed without particularly complicating the control. FIG. 4 shows a timing chart in the monochrome mode. In the color mode, the timing is the same as that shown in the figure except that the switching signal CS is fixed to L for color.

  Next, another drive method performed by the CCD drive control unit 111 for the 4-line CCD unit 103 will be described with reference to FIG. FIG. 5 is a timing chart of drive clocks input to the 4-line CCD unit when switching from the monochrome mode to the color mode. In FIG. 5, analog output signals OS1, OS2, and OS3 are also shown. In the monochrome mode, an analog voltage corresponding to an odd pixel is output to OS1, and an analog voltage corresponding to an even pixel is output to OS2. Yes.

In the timing chart of FIG. 5, the difference from FIG. 4 is that the color three-line CCDs 103R, G, and B are not always driven in the monochrome mode, but the CCD drive control unit 111 immediately before switching to color. In the line period, the three-color CCDs 103R, G, and B for color are driven as in FIG. This makes it possible to reset all unnecessary charges stored in the photodiode arrays of the 3-line CCDs 103R, G, and B immediately before switching to the color mode, thereby suppressing an excessive voltage immediately after the color mode switching. be able to.
Also in the color mode, if the CCD drive control unit 111 drives the monochrome one-line CCD 103K only for the period of one line immediately before switching to the monochrome mode, the same effect as described above can be obtained.

Further, since the color and monochrome shift pulses and the transfer clock are stopped except immediately before the mode is switched, the power consumption of the driving circuit is reduced and unnecessary radiation is further suppressed.
In FIG. 5, the driving is performed only for the period of the immediately preceding one line, but this may be a period of a plurality of lines. In addition, the period of one line here refers to the period of the color shift pulse SP1 in the color mode when switching from the monochrome mode to the color mode, and for monochrome in the monochrome mode when switching from the color mode to the monochrome mode. The period of the shift pulse SP2 is one period when each unit is defined as one unit, and the period of a plurality of lines means a period that is a natural number multiple thereof.

[Modification: FIG. 6]
Although the description of the embodiment has been completed, the configuration of the image reading apparatus 100 and the input timing of various clocks or pulses input to the 4-line CCD unit 103 by the CCD drive control unit 111 are described in the above-described embodiment. Of course, it is not limited to what was done.

  For example, in the image reading apparatus 100 according to the above-described embodiment, a reset pulse input terminal and a clamp pulse input terminal (not shown) included in each line CCD are collectively displayed regardless of whether the reset pulse and the clamp pulse are in the monochrome mode or the color mode. However, the reset pulse and the clamp pulse may be input separately in the monochrome mode and the color mode.

  In the mode in which the reset pulse and the clamp pulse are separately input in the monochrome mode and the color mode, for example, another drive method performed by the CCD drive control unit 111 for the 4-line CCD unit 103 is shown in FIG. A timing chart according to such a modification can be considered. FIG. 6 is a diagram showing another timing chart of the drive clock input to the 4-line CCD unit in the monochrome mode. In this figure, as shown in the figure, the CCD drive control unit 111 separately inputs monochrome and color reset pulses and clamp pulses.

First, on the monochrome side, the CCD drive control unit 111 inputs the monochrome shift pulse SP2, the transfer clocks TC1 'and TC2', the reset pulse and the clamp pulse at the same timing as in FIG. The one-line CCD 103K is driven.
On the other hand, on the color side, the CCD drive control unit 111 inputs the color shift pulse SP1, the transfer clocks TC1 and TC2, the reset pulse and the clamp pulse, and drives the color three-line CCDs 103R, G and B. At this time, the CCD drive control unit 111 sets at least one of the input color shift pulse SP1, the transfer clocks TC1 and TC2, the reset pulse and the clamp pulse, or the period of all the pulses and clocks in the normal color mode. I try to make it longer.

Here, when extending the period, the CCD drive control unit 111 transfers and outputs all charges accumulated in the photodiode arrays of the color 3-line CCDs 103R, G, and B during one period of the shift pulse SP1. Thus, the number of input transfer clocks TC1 and TC2 is set to be equal to or greater than the number of transfer registers corresponding to each photodiode array.
As described above, by setting at least one period out of the period of the driving clock for driving the color 3-line CCDs 103R, G, and B in the monochrome mode to be longer than the period in the normal color mode, In addition to suppressing an excessive voltage immediately after switching to, the power consumption of the drive circuit can be reduced and unnecessary radiation can be suppressed.

In the color mode, although not shown, when the color / monochrome switching signal CS is switched to the L-fixed color mode, a monochrome shift pulse SP2, transfer clocks TC1 'and TC2', a reset pulse and a clamp pulse, The color shift pulse SP1, the transfer clocks TC1 and TC2, the reset pulse, and the clamp pulse are interchanged. As a result, at least one of the driving clock cycles for driving the monochrome one-line CCD 103K in the color mode can be made longer than the cycle in the normal color mode. An effect is obtained.
In FIG. 6, in the monochrome mode, the color reset pulse and the clamp pulse are input with a longer cycle than in the normal color mode, but the reset or clamp may be always applied with the H level or L level fixed.

In the image reading apparatus 100 including the 4-line CCD unit 103, when reading a document image, the CCD drive control unit 111 drives the 4-line CCD unit 103 by any one of the driving methods described above to read the document image. Good.
Further, the image reading apparatus 100 including the 4-line CCD unit 103 may be provided as an image reading unit in an image forming apparatus such as a digital copying machine, a facsimile machine, or a complex machine combining these functions.
In addition, the embodiments and modifications described above can be combined as appropriate within a consistent range.

As described above, according to the driving method of the 4-line CCD unit of the present invention, the excessive voltage generated when the mode is switched from color to monochrome or from monochrome to color can be easily suppressed without complicating the control. be able to.
Therefore, by applying the present invention, it is possible to provide a highly safe 4-line CCD unit that does not adversely affect the circuit block at the subsequent stage.

100: Image reading device, 101: Illumination light source, 102: Light source lighting device, 103: 4-line CCD unit, 103R: 1-line CCD for red, 103G: 1-line CCD for green, 103B: 1-line CCD for blue, 103K: 1 line CCD for monochrome, 104: emitter follower, 105: AC coupling capacitor, 106: AFE, 107: data processing unit, 108: writing unit, 109: control unit, 110: light source drive control unit, 111: CCD drive control Unit: 112: AFE drive control unit, 113: data processing control unit, 114: storage unit

JP 2003-348296 A JP 2006-314039 A

Claims (7)

A driving method of a 4-line CCD unit having a driving clock input terminal for color and a driving clock input terminal for monochrome separately.
Whether the 4-line CCD unit is operated in the color mode or the monochrome mode, both the color driving clock and the monochrome driving clock are supplied from the corresponding input terminals to the 4-line CCD unit. A driving method for a 4-line CCD unit, characterized by inputting. A driving method of a 4-line CCD unit according to claim 1,
The color and monochrome drive clocks each include at least a shift pulse and a transfer clock,
When the four-line CCD unit is operated in the color mode, at least one signal period of the monochrome driving clock is set longer than the signal period of the monochrome driving clock when operating in the monochrome mode. When the 4-line CCD unit is operated in the monochrome mode, at least one signal period of the color driving clock is longer than the signal period of the color driving clock when operating in the color mode. A method for driving a four-line CCD unit. A method for driving a 4-line CCD unit according to claim 1 or 2,
An operation of inputting both the color driving clock and the monochrome driving clock to the 4-line CCD unit, a predetermined period immediately before switching the 4-line CCD unit from the color mode to the monochrome mode, and A method for driving a 4-line CCD unit, which is performed only during a predetermined period immediately before the 4-line CCD unit is switched from the monochrome mode to the color mode. A method for driving a 4-line CCD unit according to claim 3,
The predetermined period is a period of a monochrome shift pulse in the monochrome mode when switching from the color mode to the monochrome mode, and a color shift in the color mode when switching from the monochrome mode to the color mode. A driving method of a 4-line CCD unit, characterized in that each pulse period is one unit and the period is a natural number multiple thereof. An image reading apparatus comprising a 4-line CCD unit is an image reading method for reading an image of a document with the 4-line CCD unit,
5. The image reading method according to claim 1, wherein the driving unit of the image reading apparatus drives the 4-line CCD unit by the driving method of the 4-line CCD unit according to claim 1. An image reading apparatus having a 4-line CCD unit,
An image reading apparatus comprising: a driving unit that drives the 4-line CCD unit by the driving method of the 4-line CCD unit according to any one of claims 1 to 4.   An image forming apparatus comprising the image reading apparatus according to claim 6 as image reading means.

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