JP2012190853A - Power semiconductor device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device that can suppress heat generation during switching operation and contribute to the size and cost reduction of a switching power supply device.SOLUTION: A power semiconductor device is sectioned into an element region and an outer peripheral region surrounding the element region. The power semiconductor device includes a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type formed on a surface of the first semiconductor layer, a third semiconductor layer having the first conductivity type formed on a surface of the second semiconductor layer in the element region, a first trench formed in the element region, a second trench formed in the outer peripheral region, and a metal layer electrically connected to surfaces of the second semiconductor layer and the third semiconductor layer in the element region and to the surface of the second semiconductor layer in the outer peripheral region.

Description

The present invention relates to a trench type power semiconductor device used in a switching power supply device and a manufacturing method thereof.

2. Description of the Related Art A switching power supply device that switches input power (on / off) and converts it into desired DC or AC power is known. As a power semiconductor device applied as a switching element of a switching power supply device, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated)
Gate Bipolar Transistor). In recent years, switching power supply devices are required to have high efficiency from the viewpoint of ecology and energy saving, and thus power semiconductor devices are required to have low power consumption and small size.

As a means for reducing power consumption of a power semiconductor device such as a MOSFET, a power semiconductor device having a trench structure in which a trench is formed in a semiconductor layer and a gate electrode is embedded in the trench is disclosed in Patent Document 1. Patent Document 1 discloses a power semiconductor device and a manufacturing method thereof for providing a small MOSFET having a high driving capability.

FIG. 6 is a process cross-sectional view illustrating a conventional method for manufacturing a power semiconductor device described in Patent Document 1. In FIG. First, a semiconductor substrate including an n + type semiconductor region (drain region) 101 and an n − type semiconductor region (drift region) 102 is prepared, boron (B) is implanted into the surface of the drift region 102, and then heat treatment is performed. Thus, a p-type semiconductor region (body region) 103 is formed (FIG. 6A).

Next, a trench 105 that reaches the drift region 102 from the surface of the body region 103 is formed, and then a gate insulating film 106 is formed on the side wall and bottom surface of the trench 105. Further, polycrystalline silicon (polysilicon) 107 containing impurities is buried in the trench 105, and etching back is performed so that the polysilicon 107 remains only in the trench 105 (FIG. 6B).

Next, arsenic (As) is implanted into the surface of the body region 103 and then heat-treated, thereby forming an n + -type semiconductor region (source region) 104. Further, an interlayer insulating film is deposited, and then etched back so that the interlayer insulating film remains only in the trench 105, thereby exposing the body region 103 and the source region 104 (FIG. 6C).

Next, a metal film (source electrode) 100S is formed on a flat surface formed by the body region 103 and the source region 104 to form an ohmic contact. Further, a metal film (drain electrode) 100D is formed on the surface of the drain region 101 to form an ohmic contact (FIG. 6D).

Since the conventional power semiconductor device does not require a layout margin such as misalignment between the body region 103 and the source region 104 and the source electrode 100S as described above, the trench type power semiconductor device can be miniaturized.

JP 2004-31547 A

However, when a conventional power semiconductor device is applied to a switching power supply device and a switching operation is performed, there is a concern that the chip generates a large amount of heat due to the current flowing through the power semiconductor device, leading to smoke and fire. In addition, if a large radiating fin is provided in order to suppress the heat generation of the power semiconductor device, the switching power supply device is prevented from being reduced in size and cost.

An object of the present invention is to provide a power semiconductor device that can suppress heat generation during a switching operation and contribute to downsizing and cost reduction of a switching power supply device.

According to one aspect of the present invention, there is provided a power semiconductor device that is divided into an element region in which a trench-type semiconductor element is formed and an outer peripheral region surrounding the element region, the element region and the outer peripheral region A first semiconductor layer having a first conductivity type provided over the second region and a second semiconductor layer having a second conductivity type formed on the surface of the first semiconductor layer in the element region and the outer peripheral region. A semiconductor layer; a third semiconductor layer having a first conductivity type formed on a surface of the second semiconductor layer in the element region; and the second semiconductor layer and the third semiconductor layer in the element region. A first trench that reaches the first semiconductor layer through the first semiconductor layer, a second trench that reaches the first semiconductor layer through the second semiconductor layer in the outer peripheral region, and the element Said second in the region Provided is a power semiconductor device comprising: a semiconductor layer; and a metal layer electrically connected to a surface of the third semiconductor layer and a surface of the second semiconductor layer in the outer peripheral region. Is done.
According to another aspect of the present invention, there is provided a method for manufacturing a power semiconductor device divided into an element region in which a trench type semiconductor element is formed and an outer peripheral region surrounding the element region. Forming a second semiconductor layer having a second conductivity type on a surface of the first semiconductor layer having a conductivity type; and penetrating the second semiconductor layer in the element region to form the first semiconductor layer Forming a first trench that reaches the first semiconductor layer, and forming a second trench that penetrates the second semiconductor layer and reaches the first semiconductor layer in the outer peripheral region; and Forming a third semiconductor layer having a first conductivity type on a surface of the second semiconductor layer; and the second semiconductor layer and the third semiconductor layer in the element region and the outer region. With the second semiconductor layer Method of manufacturing a power semiconductor device, characterized in that it comprises a step of forming a metal film on the surface is provided.

According to the present invention, it is possible to provide a power semiconductor device that can suppress heat generation during a switching operation and contribute to downsizing and cost reduction of a switching power supply device.

It is sectional drawing which shows the structure of the power semiconductor device which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the power semiconductor device which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the power semiconductor device which concerns on embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the power semiconductor device which concerns on embodiment of this invention. It is a top view which shows the structure of the outer periphery area | region of the conventional power semiconductor device, and the outer periphery area | region of the power semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the conventional power semiconductor device.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, and arrangement of component parts. Etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

FIG. 1 is a cross-sectional view showing the structure of a power semiconductor device 10 according to an embodiment of the present invention. The power semiconductor device 10 according to the embodiment of the present invention includes a first semiconductor layer 2, a second semiconductor layer 3, a third semiconductor layer 4, a first trench 5a, a second trench 5b, and a metal layer 10S. Is provided.

The power semiconductor device 10 according to the present embodiment is formed on a drift layer (first semiconductor layer) 2 having n − type (first conductivity type) and the surface of the drift layer 2 (upper surface in FIG. 1). In addition, a body layer (second semiconductor layer) 3 having p-type (second conductivity type) and an n + -type source layer (third semiconductor layer) formed in an island shape in the surface region of the body layer 3 4 is provided. The semiconductor substrate constituting the power semiconductor device 10 according to the present embodiment is made of, for example, silicon (Si) or silicon carbide (SiC), and includes a drain layer (fourth semiconductor layer) 1 having an n + type. The drain layer 1 can also be omitted. Further, the semiconductor substrate is formed in the vicinity of the outer edge of the semiconductor chip so as to surround the element region in plan view and the element region in which at least one power semiconductor element is formed with a broken line as shown in FIG. And an outer peripheral region. As shown in FIG. 1, in the power semiconductor device 10 according to the present embodiment, the drain layer 1, the drift layer 2, and the body layer 3 are formed from the element region to the outer peripheral region, and the source layer 4 is formed in the element region. Only formed.

In the power semiconductor device 10 according to the present embodiment, at least one first trench 5a penetrating the source layer 4 and the body layer 3 from the surface of the semiconductor substrate is formed in the element region. The outer bottom surface of the first trench 5 a reaches at least the inside of the drift layer 2, and the outer surface of the first trench 5 a is adjacent to the drift layer 2, the body layer 3, and the source layer 4.

The power semiconductor device 10 includes a gate insulating film (first insulating film) 6a formed so as to cover the inner bottom surface and the inner side surface of the first trench 5a in the element region. The gate insulating film 6a may be formed of, for example, a silicon oxide film (SiOx film) or an insulator such as a silicon nitride film (SiN film). A gate electrode (first conductive layer) 7a (10G) is formed so as to fill the inside of the first trench 5a via the gate insulating film 6a. The lower part of the gate electrode 7a is formed so as to face the drift layer 2, and the upper part of the gate electrode 7a is formed so as to face the source layer 4 and is not exposed to the surface of the semiconductor substrate. The gate electrode 7a is made of polysilicon having n-type (polycrystalline Si). Further, the interlayer insulating film 8 is formed on the gate electrode 7a inside the first trench 5a. The interlayer insulating film 8 is made of a silicon oxide film similarly to the gate insulating film 6a, and electrically insulates the gate electrode 7a from a source electrode described later.

In the power semiconductor device 10 according to the present embodiment, at least one second trench 5b penetrating the body layer 3 from the surface of the semiconductor substrate is formed in the outer peripheral region. The outer bottom surface of the second trench 5 b reaches at least the inside of the drift layer 2, and the outer surface of the second trench 5 b is adjacent to the drift layer 2 and the body layer 3.

The power semiconductor device 10 includes an insulating film (second insulating film) 6b formed so as to cover the inner bottom surface and the inner side surface of the second trench 5b in the outer peripheral region. The insulating film 6b may be formed of a silicon oxide film similarly to the gate insulating film 6a, or may be formed of a different insulator. A dummy electrode (second conductive layer) 7b is formed so as to fill the inside of the second trench 5b via the insulating film 6b. The lower part of the dummy electrode 7b is formed so as to face the drift layer 2, and the upper part of the dummy electrode 7b is formed so as to face the body layer 3 and is not exposed to the surface of the semiconductor substrate. The dummy electrode 7b is made of polysilicon having n-type similarly to the gate electrode 7a. Further, an interlayer insulating film 8 made of a silicon oxide film is formed on the dummy electrode 7b inside the second trench 5b.

The power semiconductor device 10 includes a drain electrode 10D and a source electrode 10S formed from the element region to the outer peripheral region on the front surface (upper surface in FIG. 1) and the rear surface (lower surface in FIG. 1) of the semiconductor substrate. The drain electrode 10D is ohmically connected to the drift layer 2 via the drain layer 1, and the source electrode 10S is ohmically connected to the body layer 3 and the source layer 4 that form a flat surface in the element region, and in the outer peripheral region. An ohmic connection is made to the body layer 3 having a flat surface. The drain electrode 10D is formed of, for example, a laminated structure of titanium (Ti) and nickel (Ni) or a Ni layer, and the source electrode is formed of aluminum (Al), an Al—Si alloy, or the like.

As described above, the power semiconductor device 10 according to the present embodiment includes a trench MOSFET (Metal-Oxide-Semiconductor).
Field-Effect Transistor), and has a trench type MOSFET as a semiconductor element in the element region. The second trench 5b and the dummy electrode 6b formed in the outer peripheral region are not formed between the source electrode 10S and the drain electrode 10D like the first trench 5a and the gate electrode 6a because the source layer 4 is not formed. The flowing current cannot be controlled. The source electrode 10S in the outer peripheral region functions as an anode electrode of a parasitic pn diode (regenerative diode) formed by the drift layer 2 and the body layer 3, and the drain electrode 10D in the outer peripheral region functions as a cathode electrode of the parasitic pn diode. To do.

In the power semiconductor device 10 according to this embodiment, the second trench 5b, the dummy electrode 6b, and the interlayer insulating film 8 are formed in the outer peripheral region of the semiconductor chip, and the source electrode 10S is the body layer 3 in the outer peripheral region. It differs from a conventional power semiconductor device in that it is adjacent to a flat surface.

2 to 4 are process cross-sectional views illustrating a method for manufacturing the power semiconductor device 10 according to the embodiment of the present invention. 2 to 4, the manufacturing process of the element region is shown on the left side, and the manufacturing process of the outer peripheral region is shown on the right side.

(Process for forming a mask)
First, an n + type substrate that can be used as the drain layer 1 is prepared, and an n − type semiconductor layer is epitaxially grown on the surface of the drain layer 1 to form the drift layer 2. Further, boron (B) is implanted into the surface of the drift layer 2 and then heat treated to diffuse B into the drift layer 2 to form the p-type body layer 3. The body layer 3 can be formed by injecting B into the entire surface of the drift layer 2 so as to form a linear junction interface with the drift layer 2 as shown in the outer peripheral region of FIG. The body layer 3 may be formed so that B is implanted into a part of the drift layer 2 to form a junction interface including the drift layer 2 and the curved portion.

After the body layer 3 is formed on the surface of the drift layer 2, a mask 21 made of a silicon oxide film having predetermined openings 22 and 23 is formed on the surface of the body layer 3 (FIG. 2A). ). The predetermined openings 22 and 23 are formed by subjecting the silicon oxide film to a well-known photolithography process and a patterning process to form a position where the first trench 5a is formed in the element region and a second trench 5b in the outer peripheral region. And a position to be formed.

(Process of forming trench)
Next, dry etching such as RIE (Reactive Ion Etching) is performed on the semiconductor substrate on which the mask 21 is formed, and the first trench 5a and the first trench 5a that reach the drift layer 2 through the body layer 3 from the surface of the semiconductor substrate. 2 trenches 5b are formed (FIG. 2B). The dry etching process may be rephrased as a trench etching process. The first trench 5a and the second trench 5b are formed in a stripe shape, a ring shape, a circular shape, or a square dot shape in a plan view. The second trench 5b is preferably formed with the same size and interval as the first trench 5a. In addition, after forming the first trench 5a and the second trench 5b, a step of forming a sacrificial oxide film for removing damage (defects) caused by dry etching and a step of removing the sacrificial oxide film by etching are performed. preferable.

(Process for depositing a polysilicon layer)
Next, the semiconductor substrate on which the first trench 5a and the second trench 5b are formed is subjected to thermal oxidation, CVD (Chemical Vapor Deposition), or the like, and extended along the surface of the body layer 3 and the inner wall of the trench. A gate insulating film 6a and an insulating film 6b are formed. In the method for manufacturing the power semiconductor device according to the present embodiment, the gate insulating film 6a and the insulating film 6b are formed by a single process, but are formed by individual processes in order to meet different required characteristics for the element region and the outer peripheral region. You may do it. Further, the inside of the first trench 5a and the second trench 5b by LP-CVD (Low-Pressure CVD) and the surface of the semiconductor substrate (body layer 3) are interposed via the gate insulating film 6a and the insulating film 6b. Then, an n-type polysilicon layer 24 is deposited (FIG. 3A). It is also possible to form the n-type polysilicon layer 24 by depositing polysilicon containing no impurities, implanting P, and thermally diffusing P.

(Process of etching the polysilicon layer)
Next, the polysilicon layer deposited on the surface of the semiconductor substrate is removed by etching, and subsequently, a part of the polysilicon layer embedded in the first trench 5a and the second trench 5b is etched. Remove. The etching process may be rephrased as an etch-back process, and is performed until the upper surface portion of the n-type polysilicon layer 24 becomes deeper than the surface of the body layer 3. By etching the polysilicon layer 24, the gate electrode 7a is formed inside the first trench 5a in the element region, and the dummy electrode 7b is formed inside the second trench 5b in the outer peripheral region (FIG. 3 ( b)).

(Process of etching the polysilicon layer)
Next, a mask 25 made of a known photoresist material having a predetermined opening 26 is formed on the surfaces of the gate insulating film 6a, the insulating film 6b, and the dummy electrode 7b. The predetermined opening 26 is formed in the peripheral portion of the gate electrode 6a and the first trench 5a of the gate insulating film 6a through a known photolithography process and patterning process. In the outer peripheral region, it is preferable that at least the surface of the insulating film 6b is entirely covered with the mask 25, and the mask 25 is also formed on the upper surface of the dummy electrode 7b.

(Step of forming source layer)
Next, as indicated by arrows in the drawing, arsenic (As) is ion-implanted from the upper surface of the semiconductor substrate on which the mask 25 is formed (ion implantation step). Since As ions are implanted so as to reach the inside of the body layer 3 through the opening 26 of the mask 25, As diffuses into the body layer 3 adjacent to the first trench 5a, and the source layer 4 is formed. (FIG. 4A).

(Process for forming interlayer insulating film)
Next, the mask 25 is removed, and an insulating film made of a silicon oxide film is formed on the surfaces of the gate insulating film 6a, the insulating film 6b, the gate electrode 7a, and the dummy electrode 7b by CVD or SOG (Spin On Glass). . Subsequently, an etching (etch back) process is performed on the insulating film, the gate insulating film 6a, the insulating film 6b, and the mask 21. By the etch back process, the surfaces of the body layer 3 and the source layer 4 are exposed, and the interlayer insulating film 8 is formed inside the first trench 5a and the second trench 5b (FIG. 4B). . The upper surface of the interlayer insulating film 8 is preferably flush with or lower than the surface of the semiconductor substrate (the body layer 3 and the source layer 4).

(Process for forming electrodes)
Next, after a metal film is formed on the flat surface formed by the body layer 3 and the source layer 4 by a sputtering process, the metal film is formed on the surface of the drain layer 1, and the source electrode 10S and the drain electrode 10D are formed. It is formed. Further, a step of drawing out the gate electrode 5a (10G) in the element region is performed, and the power semiconductor device 10 shown in FIG. 1 is formed.

In the method for manufacturing the power semiconductor device 10 according to the present embodiment, the step of forming the second trench 5b, the step of forming the dummy electrode 6b, and the step of forming the interlayer insulating film 8 in the outer peripheral region of the semiconductor chip. And a method of manufacturing a power semiconductor device in that the source electrode 10S is formed on the flat surface of the body layer 3 in the outer peripheral region.

The power semiconductor device 10 and the manufacturing method thereof according to the present embodiment have the following operational effects.
(1) The power semiconductor device 10 includes a second trench 5b penetrating the body layer 3 and a source electrode 10S electrically connected to the body layer 3 in the outer peripheral region. By forming the second trench 5b, the mask 21 is reliably removed in the outer peripheral region as will be described later, so that the contact area between the body layer 3 and the source electrode 10S increases. Therefore, the pn diode built in the power semiconductor device 10 can flow a large current during the switching operation, and can suppress the heat generation of the power semiconductor device 10.
(2) Since the second trench 5b is formed at the same time as the first trench 5a, the power semiconductor device 10 can be manufactured at low cost by a simple manufacturing process.
(3) The power semiconductor device 10 includes the second trench 5b on which the insulating film 6b and the dummy electrode 7b are deposited. By embedding the inside of the second trench 5b, the surface of the semiconductor substrate is flattened, and the coverage of the metal layer is improved in the sputtering process for forming the source electrode 10S. Therefore, the thickness variation of the metal layer constituting the source electrode 10S is reduced, the characteristics of the power semiconductor device 10 are stabilized, and the manufacturing yield is improved.
(4) The method for manufacturing the power semiconductor device 10 includes a step (trench etching step) of forming the second trench 5b in the outer peripheral region. When only the first trench 5b is formed in the trench etching process, the silicon oxide film (for example, the mask 21) formed in the outer peripheral region is not removed in the process of forming the interlayer insulating film (etch back process). (FIG. 5 (a)). When the contact area between the body layer 3 and the source electrode 10S is reduced by the silicon oxide film remaining on the surface of the body layer 3, the area of the pn diode built in the power semiconductor device 10 is reduced, and the conventional power As in a semiconductor device, heat generation during switching operation becomes a problem. According to the method of manufacturing the power semiconductor device 10 in the present embodiment, the etching rate of the silicon oxide film in the element region and the outer peripheral region becomes substantially equal, so that the silicon oxide film can be prevented from remaining on the surface of the body layer 3. (FIG. 5B). Therefore, the power semiconductor device 10 that can suppress heat generation during the switching operation is provided.
(5) Since the first trench 5a and the second trench 5b are formed by a single trench etching process, it is not necessary to complicate the conventional manufacturing process, and the power semiconductor device 10 is manufactured at low cost. be able to.

The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.
For example, in order to reduce the contact resistance between the body layer 3 and the source electrode 10S, a p + contact layer may be formed in an island shape on the surface of the body layer 3 in the element region and the outer peripheral region. In addition, in order to form the source layer 4 in a self-aligning manner, ion implantation may be performed after a part of the gate insulating film 6a is thinned or removed.

1 Drain layer (fourth semiconductor layer)
2 Drift layer (first semiconductor layer)
3 Body layer (second semiconductor layer)
4 Source layer (third semiconductor layer)
5a First trench 5b Second trench 6a Gate insulating film (first insulating film)
6b Insulating film (second insulating film)
7a, 10G gate electrode (first conductive layer)
7b Dummy electrode (second conductive layer)
8 Interlayer insulating film 10 Power semiconductor device 10S Source electrode 10D Drain electrode

Claims (3)

A power semiconductor device divided into an element region in which a trench type semiconductor element is formed and an outer peripheral region surrounding the element region,
A first semiconductor layer having a first conductivity type provided over the element region and the outer peripheral region;
A second semiconductor layer having a second conductivity type formed on the surface of the first semiconductor layer in the element region and the outer peripheral region;
A third semiconductor layer having a first conductivity type formed on a surface of the second semiconductor layer in the element region;
A first trench reaching the first semiconductor layer through the second semiconductor layer and the third semiconductor layer in the element region;
A second trench that penetrates the second semiconductor layer and reaches the first semiconductor layer in the outer peripheral region;
A metal layer electrically connected to the surface of the second semiconductor layer and the third semiconductor layer in the element region and to the surface of the second semiconductor layer in the outer peripheral region. A characteristic power semiconductor device. First and second insulating films formed inside the first trench and the second trench;
2. The power semiconductor device according to claim 1, further comprising: first and second conductive layers formed inside the first trench and the second trench with the insulating film interposed therebetween. A method for manufacturing a power semiconductor device divided into an element region in which a trench type semiconductor element is formed and an outer peripheral region surrounding the element region,
Forming a second semiconductor layer having a second conductivity type on a surface of the first semiconductor layer having a first conductivity type;
Forming a first trench penetrating the second semiconductor layer in the element region and reaching the first semiconductor layer; and penetrating the second semiconductor layer in the outer peripheral region to form the first trench. Forming a second trench reaching the semiconductor layer;
Forming a third semiconductor layer having a first conductivity type on a surface of the second semiconductor layer in the element region;
Forming a metal film on the surfaces of the second semiconductor layer and the third semiconductor layer in the element region and the second semiconductor layer in the outer peripheral region. Device manufacturing method.

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