JP2012186259A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a semiconductor device having excellent characteristics.SOLUTION: The present invention is a manufacturing method of a semiconductor device having a p-channel MISFET in a pMIS formation region 1A, and an n-channel MISFET in an nMIS formation region 1B, comprises: a process of forming an Al film 8a on an HfON film 5; and a process of forming a Ti-rich TiN film 7a on the Al film. The manufacturing method further comprises: a step of removing the TiN film and the Al film of the nMIS formation region 1B; a step of forming La films 8b on the HfON film 5 of the nMIS formation region 1B and the TiN film 7a of the pMIS formation region 1A; a step of forming an N-rich TiN film 7b on the La film 8b; and a step of performing heat treatment. Depending on those steps, N content of the HfAlON film can be reduced in the pMIS formation region 1A, and N content of the HfLaON film can be increased in the nMIS formation region. Accordingly, eWF (effective Work Function) can be improved.

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a field effect transistor using a high dielectric film as a gate insulating film.

  Along with the miniaturization of field effect transistors, a technique of employing a high dielectric film (so-called high-k film) instead of a silicon oxide film as a gate insulating film has been studied. This is because the gate leakage current, which increases due to the tunnel effect, is suppressed, and the effective equivalent film thickness (EOT: Equivalent Oxide Thickness) is reduced to improve the gate capacitance, thereby increasing the driving capability of the field effect transistor. .

  For example, the following Patent Document 1 (Japanese Patent Laid-Open No. 2009-44051) discloses a semiconductor device having a MISFET provided with a high dielectric film as a gate insulating film. Further, this document discloses a gate insulating film [3, 4] in which an interface layer [12] made of SiON, an HfSiO film [13], and an HfSiON modified layer [5, 19] are sequentially laminated, A technique for forming the HfSiON modified layer [15, 19] by nitriding the HfSiO film [13] is disclosed. The nitrogen concentration of the HfSiON modified layer [19] constituting the gate insulating film [4] of the N-type MISFET is equal to the nitrogen concentration of the HfSiON modified layer [15] constituting the gate insulating film [3] of the P-type MISFET. It is disclosed that it is higher (see, for example, paragraphs [0029] to [0033]).

  Patent Document 2 (Japanese Patent Laid-Open No. 2009-200293) below discloses a hybrid semiconductor device having a high-k gate insulating film. Further, this document discloses an n-type MIS having a gate electrode in which an HfSiON film [4], a TiN film [7], an N-rich TiN film [10], and a poly-Si film [5] are stacked in this order from the bottom. (See paragraphs [0020] to [0025], for example). Note that the contents in [parentheses] are the symbols or paragraph numbers described in the patent literature.

JP 2009-44051 A JP 2009-200193 A

  The present inventor is engaged in research and development of a field effect transistor (MISFET: Metal Insulator Semiconductor Field Effect Transistor) having a high-k film as described above.

  The present inventor, in a semiconductor device that has been miniaturized, for example, a SoC (System On a Chip) device of 28 nm node or later, instead of a poly-Si / SiON laminated structure, poly-Si / metal / high-k. We are considering the use of a complementary MISFET (CMIS) to which a film stack structure (gate stack structure) is applied. As the high-k film, the adoption of an HfLaON film as a gate insulating film of an n-channel type MISFET and the adoption of an HfAlON film as a gate insulating film of a p-channel type MISFET are examined.

  However, in the example examined by the present inventor (comparative example described later), there arises a problem that the threshold voltage of the p-channel type MISFET increases from a desired value. As a result of investigating this cause, it was found that the nitrogen concentration in the high-k film had an influence.

  Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having good characteristics. In particular, it is to manufacture a field effect transistor with good characteristics by controlling the nitrogen concentration in the high-k film.

  Another object of the present invention is to provide a semiconductor device with good characteristics. In particular, it is to provide a field effect transistor with good characteristics by controlling the nitrogen concentration in the high-k film.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in this application, a method for manufacturing a semiconductor device shown in a representative embodiment includes a p-channel MISFET in a first region of a semiconductor substrate, and an n-channel MISFET in the first region of the semiconductor substrate. A method of manufacturing a semiconductor device in two regions, which includes the following steps (a) to (j). (A) is a step of forming an HfON film in the first region and the second region of the semiconductor substrate. (B) is a step of forming a first metal film containing aluminum on the HfON film. (C) is a step of forming a first titanium nitride film on the first metal film. (D) is a step of removing the first titanium nitride film and the first metal film in the second region. (E) is a step of forming a second metal film containing a lanthanoid metal on the HfON film in the second region and the first titanium nitride film in the first region after the step (d). is there. (F) is a step of forming a second titanium nitride film on the second metal film. In (g), after the step (f), heat treatment is performed to generate an HfAlON film by a reaction between the HfON film in the first region and the first metal film, and the HfON film in the second region and the first This is a step of generating an HfLnON film (Ln; lanthanoid metal) by reaction with two metal films. (H) is a step of removing the second titanium nitride film and the second metal film and removing the first titanium nitride film and the first metal film after the step (g). (I) is a step of forming a first gate electrode on the HfAlON film in the first region and forming a second gate electrode on the HfLnON film in the second region. (J) is a step of forming a p-type impurity region in the semiconductor substrate on both sides of the first gate electrode and forming an n-type impurity region in the semiconductor substrate on both sides of the second gate electrode. is there. When the composition ratio of Ti and N of the first titanium nitride film is 1: X1a and the composition ratio of Ti and N of the second titanium nitride film is 1: X1b, the relation of X1a <X1b is established. .

  Among the inventions disclosed in the present application, the semiconductor device shown in the representative embodiment is formed of a p-channel MISFET formed in the first region of the semiconductor substrate and the second region of the semiconductor substrate. A semiconductor device having an n-channel MISFET has the following configurations (a) and (b).

  The p-channel MISFET in (a) includes (a1) a first gate insulating film disposed on the semiconductor substrate, the first gate insulating film having an HfAlON film, and (a2) the first gate insulating film. A first gate electrode disposed on the film; and (a3) a p-type semiconductor region disposed in the semiconductor substrate on both sides of the first gate electrode. The n-channel MISFET of (b) includes (b1) a second gate insulating film disposed on the semiconductor substrate, the second gate insulating film having an HfLaON film, and (b2) the second gate insulating film. A second gate electrode disposed on the film; and (b3) an n-type semiconductor region disposed in the semiconductor substrate on both sides of the second gate electrode. When the composition ratio of Hf and N of the HfAlON film is 1: Za and the composition ratio of Hf and N of the HfLaON film is 1: Zb, the relation of Za <Zb is established.

  Among the inventions disclosed in the present application, according to the method for manufacturing a semiconductor device shown in the following representative embodiment, a semiconductor device having good characteristics can be manufactured.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the characteristics can be improved.

It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of embodiment. FIG. 2 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, and showing the process following FIG. 1; FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, following the process shown in FIG. 2; FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, and showing the process following FIG. 3; It is a top view which shows an example of a structure of the suitable multi-chamber used for the manufacturing process of the semiconductor device of embodiment. FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, and showing the process following FIG. 4; FIG. 7 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, and showing the process following FIG. 6; FIG. 8 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, following the step of FIG. 7; FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, and showing the process following FIG. 8; FIG. 10 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, following the step shown in FIG. 9; FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, and showing the process following FIG. 10; 12 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment, following the step shown in FIG. 11; FIG. FIG. 13 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of the embodiment, following the process shown in FIG. 12; FIG. 14 is a main-portion cross-sectional view illustrating the manufacturing process of the semiconductor device in the embodiment, and illustrating the process following FIG. 13; FIG. 15 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of the embodiment, following the process shown in FIG. 14; FIG. 16 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the embodiment, following the step shown in FIG. 15; FIG. 17 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the embodiment, and showing the process following FIG. 16; A nitrogen flow rate at the time of forming the TiN film of the embodiment _(N 2 Flow), is a graph showing the relationship between nitrogen composition ratio (N / Ti). A nitrogen flow rate at the time of forming the TiN film of the embodiment _(N 2 Flow), is a table showing the relationship between the nitrogen composition ratio (N / Ti). It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of the comparative example 1 of embodiment. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of the comparative example 2 of embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment)
Hereinafter, the configuration and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. 1-17 (other than FIG. 5) are principal part sectional drawings which show the manufacturing process of the semiconductor device of this Embodiment. FIG. 5 is a plan view showing an example of the configuration of a multi-chamber suitable for use in the manufacturing process of the semiconductor device of the present embodiment.

[Description of structure]
First, a characteristic configuration of the semiconductor device of the present embodiment will be described with reference to FIG. 15 which is one of main part cross-sectional views showing a manufacturing process of the semiconductor device of the present embodiment.

  As shown in FIG. 15, the semiconductor device of the present embodiment includes an n-channel MISFET (Qn) disposed in the nMIS formation region 1B of the semiconductor substrate 1 and a p disposed in the pMIS formation region 1A of the semiconductor substrate 1. A channel type MISFET (Qp). An element isolation region 2 is disposed between the nMIS formation region 1B and the pMIS formation region 1A.

  The n-channel type MISFET (Qn) is disposed on the main surface of the p-type well 3 formed in the semiconductor substrate 1 in the nMIS formation region 1B, and the p-channel type MISFET (Qp) is a semiconductor in the pMIS formation region 1A. Arranged on the main surface of an n-type well 4 formed in the substrate 1.

  The n-channel type MISFET (Qn) includes a gate electrode disposed on a semiconductor substrate 1 (p-type well 3) via a gate insulating film, and a semiconductor substrate 1 (p-type well 3) on both sides of the gate electrode. Have source / drain regions.

  The gate insulating film of the n-channel type MISFET (Qn) includes a silicon oxynitride film ON disposed on the semiconductor substrate 1 (p-type well 3) and an HfLaON film 5b disposed on the silicon oxynitride film ON. It consists of a laminated film.

  The HfLaON film 5b is an insulating film containing Hf (hafnium) and is a high dielectric film. A high dielectric film (high-k film) refers to an insulating film having a higher dielectric constant than a silicon oxide film. The HfLaON film (hafnium lanthanum oxynitride film) 5b is an insulating film composed of hafnium (Hf), lanthanum (La), oxygen (O), and nitrogen (N). The composition ratio of each element, that is, Hf: La: O: N is 1: xb: yb: zb. Here, in the present embodiment, the composition ratio (zb) of N to Hf of the HfLaON film 5b is larger than the composition ratio (za) of N to Hf of the HfAlON film 5a described later (zb> za). That is, the HfLaON film 5b is a film having a high N content, in other words, an N-rich film.

  The HfLaON film 5b is formed in the HfON film 5 by diffusing La from the La film (8b) laminated thereon. At this time, by increasing the nitrogen composition ratio (x1b described later) of the TiN film (7b) formed thereon as the antioxidant film of the La film (8b), N in the HfLaON film 5b formed is increased. The content can be increased.

  Thus, by increasing the N content in the HfLaON film 5b, the threshold value (threshold voltage) of the n-channel MISFET (Qn) can be reduced.

  The gate electrode GE1 of the n-channel type MISFET (Qn) is composed of a laminated film of a metal film (TiN film) 9 and a polycrystalline silicon film (silicon film, silicon layer) 10 disposed on the HfLaON film 5b. This gate electrode GE1 is a so-called metal gate electrode. Therefore, the n-channel MISFET (Qn) is a MISFET having a stacked structure of poly-Si / metal / high-k films. Here, metal (metal film, metal layer) constituting the metal gate electrode refers to a conductive film exhibiting metal conduction, and not only a single metal or alloy but also a metal compound film (metal nitride metal) exhibiting metal conduction. Film and metal carbide film).

The source and drain regions of the n-channel type MISFET (Qn) are composed of n-type semiconductor regions disposed in the semiconductor substrate 1 (p-type well 3) on both sides of the gate electrode GE1, and have an LDD (Lightly Doped Drain) configuration. . Specifically, it is composed of an n ⁻ type semiconductor region 11b and an n ⁺ type semiconductor region 12b.

  A p-channel type MISFET (Qp) is formed in a gate electrode disposed on a semiconductor substrate 1 (n-type well 4) via a gate insulating film, and in the semiconductor substrate 1 (n-type well 4) on both sides of the gate electrode. Have source / drain regions.

  The gate insulating film of the p-channel type MISFET (Qp) includes a silicon oxynitride film ON disposed on the semiconductor substrate 1 (n-type well 4) and an HfAlON film 5a disposed on the silicon oxynitride film ON. It consists of a laminated film.

  The HfAlON film 5a is an insulating film containing Hf (hafnium) and is a high dielectric film. A high dielectric film (high-k film) refers to an insulating film having a higher dielectric constant than a silicon oxide film. The HfAlON film (hafnium aluminum oxynitride film) 5a is an insulating film composed of hafnium (Hf), aluminum (Al), oxygen (O), and nitrogen (N). The composition ratio of each element, that is, Hf: Al: O: N is 1: xa: ya: za. Here, in the present embodiment, the composition ratio (za) of N to Hf in the HfAlON film 5a is smaller than the composition ratio (zb) of N to Hf in the HfLaON film 5b (za <zb). That is, the HfAlON film 5a is a film having a small N content.

  The HfAlON film 5a is formed by diffusing Al in the HfON film 5 from the Al film (8a) laminated thereon. At this time, by reducing the nitrogen composition ratio (x1a described later) of the TiN film (7a) formed thereon as an antioxidant film of the Al film (8a), N in the HfAlON film 5a formed is reduced. The content can be reduced.

  Thus, by reducing the N content in the HfAlON film 5a, the threshold value of the p channel MISFET (Qp) can be reduced. Here, the reduction of the threshold value of the p-channel type MISFET (Qp) is, for example, when the threshold value of the p-channel type MISFET (Qp) is expressed as -aV (a> 0), It means to reduce the absolute value.

  The gate electrode GE2 of the p-channel type MISFET (Qp) is composed of a laminated film of a metal film (TiN film) 9 and a polycrystalline silicon film (silicon film, silicon layer) 10 disposed on the HfAlON film 5a. This gate electrode GE2 is a so-called metal gate electrode. Therefore, the p-channel type MISFET (Qp) is a MISFET having a stacked structure of poly-Si / metal / high-k films.

The source and drain regions of the p-channel type MISFET (Qp) are p-type semiconductor regions arranged in the semiconductor substrate 1 (n-type well 4) on both sides of the gate electrode GE2, and have an LDD configuration. Specifically, it is composed of a p ⁻ type semiconductor region 11a and a p ⁺ type semiconductor region 12a.

[Production method explanation]
Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to FIGS. 1 to 17 and the configuration of the semiconductor device will be clarified.

  As shown in FIG. 1, a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared.

  Next, an element isolation region 2 made of, for example, a silicon oxide film is formed on the semiconductor substrate 1. The element isolation region 2 partitions (separates) the nMIS formation region 1B where the n-channel MISFET is formed and the pMIS formation region 1A where the p-channel MISFET is formed. The element formation region partitioned by the element isolation region 2 may be referred to as an active region.

  The element isolation region 2 can be formed using, for example, an STI (shallow trench isolation) method.

  For example, in the STI method, the element isolation region is formed as follows. For example, the element isolation trench 2 a is formed by etching the semiconductor substrate 1. Next, a silicon oxide film is deposited on the semiconductor substrate 1 with a film thickness sufficient to fill the element isolation trench 2a by using a CVD (Chemical Vapor Deposition) method or the like, and the oxide other than the element isolation trench 2a is oxidized. The silicon film is removed using a chemical mechanical polishing (CMP) method, an etch back method, or the like. Thereby, a silicon oxide film can be embedded in the element isolation trench 2a. Further, the element isolation region 2 may be formed using a LOCOS (local Oxidation of silicon) method instead of the STI method. In this case, for example, a silicon nitride film having an opening is formed on the semiconductor substrate 1 in a region where the element isolation region 2 is formed, and the semiconductor substrate (silicon) 1 is thermally oxidized using the film as a mask, thereby forming a silicon oxide film. An element isolation region 2 made of (thermal oxide film) is formed.

  Next, after p-type impurities such as boron (B) are ion-implanted into the nMIS formation region 1B of the semiconductor substrate 1, the p-type well 3 is formed by diffusing the impurities by heat treatment. Further, after implanting n-type impurities such as phosphorus (P) or arsenic (As) into the pMIS formation region 1A of the semiconductor substrate 1, the n-type well 4 is formed by diffusing the impurities by heat treatment. Thereafter, if necessary, ion implantation for adjusting the threshold value of the MISFET (so-called channel dope ion implantation) may be performed on the upper layer portion of the semiconductor substrate 1 (p-type well 3 or n-type well).

  Next, as shown in FIG. 2, the surface of the semiconductor substrate 1 (p-type well 3 and n-type well 4) is thermally oxidized in an atmosphere containing oxygen and nitrogen to thereby form silicon oxynitride as a first gate insulating film. A film ON is formed. The heat treatment temperature is about 1000 ° C., for example. Note that the silicon oxynitride film ON may be formed by a CVD method instead of the thermal oxidation method. Thus, by forming the silicon oxynitride film ON on the semiconductor substrate 1, the leakage current between the gate electrode and the semiconductor substrate can be reduced. That is, in the Hf-containing insulating film (HfLaON film 5b and HfAlON film 5a) described later, holes are easily formed in the film. Therefore, when only the Hf-containing insulating film is interposed between the semiconductor substrate 1 and the gate electrodes (GE1, GE2), the leakage current is passed through the gate electrode material that has penetrated into the vacancies in the Hf-containing insulating film. Is likely to occur. On the other hand, as described above, the leakage current between the gate electrodes (GE1, GE2) and the semiconductor substrate 1 can be reduced by forming the silicon oxynitride film ON under the Hf-containing insulating film. . In particular, as described above, according to film formation by heat treatment at about 1000 ° C., a dense film can be formed, and the leakage current can be further reduced. Further, a silicon oxide film (thermal oxide film) may be used as the first gate insulating film. Even when a silicon oxide film is used, the leakage current can be reduced. The silicon oxynitride film ON has a smaller EOT (Equivalent Oxide Thickness) than the silicon oxide film, and the first gate. It is suitable for use as an insulating film. EOT is the electrical equivalent film thickness of the insulating film, and the film thickness of the silicon oxide film showing the same capacitance value as the capacitance of the insulating film having a certain thickness (here, the silicon oxynitride film ON). Point to.

  Next, referring to FIGS. 3 to 9, a step of forming the second gate insulating film (5 a, 5 b) on the surface of the semiconductor substrate 1 (that is, the surface of the silicon oxynitride film ON), that is, the semiconductor substrate 1 Forming a nitrogen-rich HfLaON film 5b as a second gate insulating film in the nMIS formation region 1B, and forming a HfAlON film 5a as a second gate insulating film in the pMIS formation region 1A of the semiconductor substrate 1 Will be described.

  Hereinafter, the process of forming the nitrogen-rich HfLaON film 5b and the HfAlON film 5a will be described in detail.

First, as shown in FIG. 3, an HfO film (hafnium oxide film or hafnium oxide film, typically an HfO ₂ film) is formed in the pMIS formation region 1A and the nMIS formation region 1B on the silicon oxynitride film ON. The HfO film can be formed by, for example, a CVD method. Further, instead of the CVD method, an ALD (Atomic Layer Deposition) method may be used. Next, the HfO film (hafnium oxynitride film) 5 is formed by nitriding the HfO film. As the nitriding method, a plasma nitriding method can be used. That is, plasma is generated in an atmosphere containing nitrogen, the semiconductor substrate 1 is placed inside the plasma, and the HfO film is nitrided. Note that the HfON film 5 may be formed directly on the silicon oxynitride film ON by using the CVD method or the ALD method.

  Next, as shown in FIG. 4, an Al film 8a is formed as a pMIS threshold adjustment layer (Al diffusion film, Al implantation film, solid layer diffusion film) in the pMIS formation region 1A and the nMIS formation region 1B on the HfON film 5. . The Al film 8a is formed with a film thickness of about 1 nm in a processing chamber in an inert atmosphere using, for example, a sputtering method.

The pMIS threshold adjustment layer is formed to introduce Al (first metal element) into the underlying HfON film 5. Such element introduction between the laminated films is sometimes referred to as mixing. Thus, by including Al in the gate insulating film (5a) of the p-channel type MISFET (Qp), the absolute value of the threshold value can be lowered. The threshold adjustment layer only needs to contain Al and may contain elements other than Al. However, it is desirable that the content of oxygen (O ₂ ) is small, and the oxygen content is 30 atomic% or less. It is preferable to do. The Al film 8a alone is preferable because of its low oxygen content.

  Next, a Ti-rich TiN film (metal nitride film) 7a is formed in the pMIS formation region 1A and the nMIS formation region 1B on the Al film 8a as a hard mask serving as an antioxidant film for the lower Al film 8a. Ti-rich means a film containing a relatively large amount of Ti. Here, the composition ratio of each element of the TiN film 7a, that is, Ti: N is set to 1: x1a, and each element of the TiN film 7b described later. When the composition ratio of Ti: N is set to 1: x1b, it means that x1a <x1b. In other words, it means that the composition ratio (x1a, nitrogen composition ratio) of N in the TiN film 7a to Ti is smaller than the composition ratio (x1b, nitrogen composition ratio) of N in the TiN film 7b described later. Further, in consideration of experimental examples described later, the x1a (nitrogen composition ratio) of the TiN film 7a is preferably less than 1.2.

The Ti-rich TiN film 7a is formed with a film thickness of about 10 nm using, for example, a sputtering method. The film forming conditions in this case are, for example, an RF (Radio Frequency) power of 1 kW applied to an electrode in the processing chamber in an inert atmosphere processing chamber with an argon (Ar) flow rate of 15 sccm and a nitrogen flow rate of 12 sccm under a reduced pressure of 10 ⁻² Pa. Is applied, and Ti particles protruding from the Ti target are deposited on the semiconductor substrate 1 while nitriding to form a Ti-rich TiN film 7a. Note that the nitrogen flow rate when forming the Ti-rich TiN film 7a is smaller than the nitrogen flow rate when forming an N-rich TiN film 7b described later. “Sccm” means Standard Cubic Centimeter per Minutes, and indicates the flow rate per minute (cc = ml) in the standard state.

  In forming the Al film 8a and the TiN film 7a, it is preferable to continuously form the film using, for example, a multi-chamber shown in FIG.

  FIG. 5 is a plan view showing an example of the configuration of a multi-chamber suitable for use in the manufacturing process of the semiconductor device of the present embodiment. The multi-chamber shown in FIG. 5 includes an automatic transfer device 21, a storage chamber 22, and a transfer chamber 24. An Al film forming apparatus (film forming chamber) 25, a TiN film forming apparatus 26, an La film forming apparatus 27, and an annealing apparatus (annealing chamber) 28 are arranged in this order with the transfer chamber 24 as a center. Openable and closable doors are provided between the devices and the processing chambers. Further, in the transfer chamber 24, a robot arm 23 provided so that a semiconductor substrate (semiconductor wafer) can be transferred into each device (25, 26, 27, 28) via the transfer chamber 24 is disposed.

  In forming the Al film 8a and the TiN film 7a, for example, processing is performed as follows. First, the door between the storage chamber 22 and the transfer chamber 24 is closed, the transfer chamber 24 and each device (each chamber, 25, 26, 27, 28) are evacuated under reduced pressure, and an inert gas (for example, , Nitrogen). Next, after the semiconductor wafer is transferred into the storage chamber 22 by the automatic transfer device 21, the door between the storage chamber 22 and the automatic transfer device 21 is closed, and the storage chamber 22 is evacuated and then transferred to the storage chamber 22. The door to the chamber 24 and the door of the Al film forming apparatus 25 are opened, and the semiconductor substrate 1 in the storage chamber 22 is transferred to the Al film forming apparatus 25 by the robot arm 23 in the transfer chamber. Next, the door of the Al film forming apparatus 25 is closed, and the Al film 8 a is formed in the Al film forming apparatus 25. Next, the semiconductor substrate 1 is taken out from the Al film forming apparatus 25 by the robot arm 23 in the transfer chamber 24 and transferred to the TiN film forming apparatus 26 through the transfer chamber 24 to form the TiN film 7a. As described above, after the Al film 8a is formed, the Al film 8a is transferred to the TiN film 7a without being exposed to the atmosphere (oxygen) by being transferred through an inert atmosphere path (for example, the transfer chamber 24). Can be covered.

  Thereafter, the semiconductor substrate 1 is taken out as follows. For example, after the semiconductor substrate 1 is transferred from the TiN film forming apparatus 26 to the storage chamber 22 by the robot arm 23 in the transfer chamber 24 and the door between the storage chamber 22 and the transfer chamber 24 is closed, After eliminating the reduced pressure state and setting the room to atmospheric pressure, the automatic transfer device 21 is used to take out the semiconductor substrate 1 in the storage room 22.

  Thus, by sequentially forming the Al film 8a and the TiN film 7a using a multi-chamber, the opportunity for the Al film 8a to come into contact with the atmosphere (oxygen) is reduced, and the Al film 8a is oxidized, It is possible to reduce oxygen from being taken in. In particular, the dielectric constant of aluminum oxide is lower than that of lanthanum oxide, and the EOT increases as the composition ratio of Al and O in the HfAlON film 5a increases. Therefore, in the film forming process of the Al film 8a and the TiN film 7a, it is preferable to continuously form the Al film 8a without exposing it to the atmosphere. Note that the La film forming device 27 and the annealing device 28 are not used in the film forming process of the Al film 8a and the TiN film 7a. Therefore, a multi-chamber without the La film forming device 27 and the annealing device 28 may be used.

  Next, as shown in FIG. 6, a photoresist film PR1 is applied onto the Ti-rich TiN film (metal nitride film) 7a, and this photoresist film PR1 is exposed and developed (photolithography) to form an nMIS. The photoresist film PR1 in the region 1B is removed. Next, using the photoresist film PR1 as an etching mask, the Ti-rich TiN film 7a and the Al film 8a are removed by wet etching or the like. As a result, the HfON film 5 in the nMIS formation region 1B is exposed.

Next, as shown in FIG. 7, after removing the photoresist film PR1 by ashing or the like, the nMIS threshold adjustment is performed on the nMIS formation region 1B where the HfON film 5 is exposed and the pMIS formation region 1A where the Ti-rich TiN film 7a is exposed. A La film 8b is formed as a layer (La diffusion film, La injection film, solid layer diffusion film). The La film 8b is formed with a film thickness of about 0.3 to 1 nm by using, for example, a sputtering method. The film forming conditions in this case were, for example, 10 ^% Pa in a reduced pressure state, an argon (Ar) flow rate of 50 sccm in an inert atmosphere processing chamber, the RF power of the electrode in the processing chamber was set to 300 W, and the film protruded from the La target. A La film 8 b is formed by depositing La particles on the semiconductor substrate 1. This nMIS threshold adjustment layer is formed for introducing (mixing) La (second metal element) into the underlying HfON film 5. Thus, by including La in the gate insulating film (5b) of the n-channel MISFET (Qn), the threshold value can be lowered. The threshold adjustment layer only needs to contain La and may contain elements other than La. However, it is desirable that the content of oxygen (O ₂ ) is small, and the oxygen content is 30 atomic% or less. It is preferable to do. The La film 8b alone is preferable because it has a low oxygen content.

  In place of the La film, a film containing a lanthanoid metal may be used. The lanthanoid metal (represented as Ln) is an atomic number 57 to 71, that is, 15 elements from lanthanum (La) to lutetium (Lu). As the nMIS threshold adjustment layer, La and Pr having a relatively high dielectric constant and a large band gap are preferable among lanthanoid metals, and La is more preferable.

Next, as shown in FIG. 8, an N-rich TiN film (metal nitride) is used as a hard mask serving as an antioxidant film for the underlying La film 8b in the pMIS formation region 1A and the nMIS formation region 1B on the La film 8b. Film) 7b. N-rich means a film containing a relatively large amount of N. Here, the composition ratio of each element of the TiN film 7b, that is, Ti: N is set to 1: x1b, and the composition of each element of the TiN film 7a. When the ratio, that is, Ti: N is 1: x1a, it means that x1a <x1b. In other words, it means that the composition ratio of N to Ti (x1b, nitrogen composition ratio) in the TiN film 7b is larger than the composition ratio of N to Ti (x1a, nitrogen composition ratio) of the TiN film 7a. Further, in consideration of an experimental example to be described later, x1b (nitrogen composition ratio) of the TiN film 7b is preferably 1.2 or more. The N-rich TiN film 7b is formed with a film thickness of about 10 nm using, for example, a sputtering method. The film forming conditions in this case are, for example, applying an RF power of 1 kW to the electrodes in the processing chamber in an inert atmosphere processing chamber with an argon (Ar) flow rate of 15 sccm and a nitrogen flow rate of 24 sccm under a reduced pressure of 10 ⁻² Pa, By depositing Ti particles protruding from the Ti target on the semiconductor substrate 1 while nitriding, an N-rich TiN film 7b is formed. Note that the nitrogen flow rate when forming the N-rich TiN film 7b is larger than the nitrogen flow rate when forming the Ti-rich TiN film 7a.

  In forming the La film 8b and the N-rich TiN film 7b, it is preferable to continuously form the film using, for example, the multi-chamber shown in FIG.

  For example, in forming the La film 8b and the N-rich TiN film 7b, for example, the following processing is performed. First, the door between the storage chamber 22 and the transfer chamber 24 is closed, the transfer chamber 24 and each device (25, 26, 27, 28) are evacuated under reduced pressure, and the inside thereof is inert gas (for example, nitrogen). Purge with. Next, after the semiconductor wafer is transferred into the storage chamber 22 by the automatic transfer device 21, the door between the storage chamber 22 and the automatic transfer device 21 is closed, and the storage chamber 22 is evacuated and then transferred to the storage chamber 22. The door to the chamber 24 and the door of the La film forming device 27 are opened, and the semiconductor substrate 1 in the storage chamber 22 is transferred to the La film forming device 27 by the robot arm 23 in the transfer chamber. Next, the door of the La film forming apparatus 27 is closed, and the La film 8 b is formed in the La film forming apparatus 27. Next, the semiconductor substrate 1 is taken out from the La film forming apparatus 27 by the robot arm 23 in the transfer chamber 24 and transferred to the TiN film forming apparatus 26 via the transfer chamber 24 to form the TiN film 7b. In this manner, after the La film 8b is formed, the La film 8b is transferred to the TiN film 7b without being exposed to the atmosphere (oxygen) by being transferred through an inert atmosphere path (for example, the transfer chamber 24). Can be covered. Thereafter, the semiconductor substrate 1 may be taken out using the automatic transfer device 21 through the storage chamber 22, but may be continuously performed until an annealing process described later.

  That is, thereafter, the semiconductor substrate 1 is transferred from the TiN film forming apparatus 26 to the annealing apparatus 28 by the robot arm 23 in the transfer chamber 24, and the heat treatment described later is performed. Thereafter, the semiconductor substrate 1 is transferred from the annealing device 28 to the storage chamber 22 by the robot arm 23 in the transfer chamber 24, and the door between the storage chamber 22 and the transfer chamber 24 is closed. Is eliminated, and the interior of the room is set to atmospheric pressure, and then the semiconductor substrate 1 in the storage room 22 is taken out using the automatic transfer device 21.

  Thus, by sequentially forming the La film 8b and the TiN film 7b using a multi-chamber, the La film 8b is less exposed to the atmosphere (oxygen), the La film 8b is oxidized, and the inside It is possible to reduce oxygen from being taken in. Therefore, an increase in EOT due to an increase in the composition ratio of La and O in the HfLaON film 5b can be suppressed. Further, by forming the TiN film 7b on the La film 8b, the oxidation of the La film 8b can be further reduced. Note that the Al film forming apparatus 25 is not used in the film forming process of the La film 8b and the TiN film 7b. Therefore, a multi-chamber without the Al film forming apparatus 25 may be used.

  Next, as shown in FIG. 9, by subjecting the semiconductor substrate 1 to heat treatment, the HfON film 5 in the nMIS formation region 1B is changed to the HfLaON film 5b, and the HfON film 5 in the pMIS formation region 1A is changed to the HfAlON film 5a. . Specifically, in the laminated portion of the HfON film 5 and the Al film 8a in the pMIS formation region 1A, Al in the Al film 8a is diffused into the lower HfON film 5 by thermal diffusion reaction (mixing), and the HfAlON film 5a is formed. Further, in the laminated portion of the HfON film 5 and the La film 8b in the nMIS formation region 1B, La in the La film 8b is diffused into the lower HfON film 5 by thermal diffusion reaction (mixing) to form the HfLaON film 5b. To do.

This heat treatment step is performed in an inert gas atmosphere (for example, N ₂ (nitrogen) atmosphere) within a heat treatment temperature range of 780 to 850 ° C. Further, as described above, in this heat treatment step, the multi-chamber annealing apparatus 28 shown in FIG. 5 can be used, and the heat treatment can be continuously performed after the TiN film 7b is formed.

  Here, since the La film 8b and the N-rich TiN film 7b are formed on the HfON film 5 in the nMIS formation region 1B, the N content in the HfLaON film 5b can be increased by the mixing. . That is, the composition ratio of each element of the HfLaON film 5b, that is, Hf: La: O: N, increases the composition ratio (zb) of N of the HfLaON film 5b to Hf at 1: xb: yb: zb. For example, the composition ratio (zb) of N to Hf in the HfLaON film 5b is larger than the composition ratio (za) of N to Hf in the HfAlON film 5a (zb> za).

  On the other hand, since the Al film 8a and the Ti-rich TiN film 7a are formed on the HfON film 5 in the pMIS formation region 1A, the N content in the HfAlON film 5a can be reduced by the mixing. That is, the composition ratio of each element of the HfAlON film 5a, that is, Hf: Al: O: N, the composition ratio (za) of N of the HfAlON film 5a to Hf is small at 1: xa: ya: za. For example, the composition ratio (za) of N to Hf in the HfAlON film 5a is smaller than the composition ratio (zb) of N to Hf in the HfLaON film 5b (za <zb).

  Next, as shown in FIG. 10, the TiN film 7b and the La film 8b that have not reacted in the heat treatment step (that is, the remaining film that has not become the HfLaON film 5b) are removed by wet etching or the like. Further, the TiN film 7a and the Al film 8a (that is, the remaining film that has not become the HfAlON film 5a) that did not react in the heat treatment step are removed by wet etching or the like.

  Here, the TiN films (7a, 7b) are more difficult to wet-etch when oxygen is contained than when oxygen is not contained. For example, with regard to TiLaN and TiLaON that can occur in the heat treatment step, TiLaON is more difficult to etch than TiLaN. On the other hand, according to the present embodiment, since the oxygen concentration in the lower layer film (Al film 8a, La film 8b) of the TiN film (7a, 7b) is reduced, the TiN film (7a, 7b). The oxygen concentration inside is suppressed. Therefore, the wet etching time can be shortened, and in particular, the etching damage to the HfLaON film 5b exposed during the wet etching of the TiN film 7a can be reduced. Further, as described above, by performing the heat treatment continuously after the formation of the TiN film 7b, the oxidation of the TiN film 7b can be suppressed, and also in this respect, the etching time of the TiN film 7b can be shortened.

Next, as shown in FIG. 11, as a metal film 9 for a metal gate, for example, a TiN film is formed on the HfLaON film 5b in the nMIS formation region 1B and the HfAlON film 5a in the pMIS formation region 1A by a sputtering method or the like. The film thickness is formed. The film formation conditions in this case were, for example, that the RF power of the electrode in the processing chamber was 1 kW in a processing chamber with an argon (Ar) flow rate of 15 sccm and a nitrogen flow rate of 12 sccm under a reduced pressure of 10 ⁻² Pa and jumped out of the Ti target. A TiN film is formed by depositing Ti particles on the semiconductor substrate 1 while nitriding. As the metal film 9 for the metal gate, a tantalum nitride (TaN) film or a tantalum carbide (TaC) film can be used in addition to the TiN film. However, it is preferable to use a TiN film from the viewpoint of ease of applicability familiar to the LSI manufacturing process. Here, the metal film (metal layer) 9 for metal gate refers to a conductive film showing metal conduction, and not only a single metal or alloy but also a metal compound film (metal nitride film or carbonization) showing metal conduction. Metal film).

  Next, a silicon film 10 is formed on the metal film 9. The silicon film 10 can be a polycrystalline silicon film or an amorphous silicon film, but even if it is an amorphous silicon film at the time of film formation, heat treatment after film formation (for example, introduced for source / drain) A polycrystalline silicon film is formed by impurity activation annealing).

  Here, it is possible to omit the step of forming the silicon film 10 by increasing the thickness of the metal film 9, but by laminating the silicon film 10, the thickness of the metal film 9 can be reduced. The damage to the semiconductor substrate 1 at the time of patterning 9 can be reduced.

  Next, as shown in FIG. 12, the laminated film of the silicon film 10 and the metal film 9 is patterned by using, for example, a photolithography technique and a dry etching technique, so that the laminated film of the metal film 9 and the silicon film 10 is formed. Gate electrodes GE1 and GE2 to be formed are formed.

  The gate electrode GE1 is formed on the HfLaON film 5b in the nMIS formation region 1B, and the gate electrode GE2 is formed on the HfAlON film 5a in the pMIS formation region 1A.

  The HfLaON film 5b that is not covered with the gate electrode GE1 and the HfAlON film 5a that is not covered with the gate electrode GE2 are removed during this patterning and in the subsequent etching process.

Next, as shown in FIG. 13, phosphorus (P), arsenic (As), or the like is formed in the p-type well 3 on both sides of the gate electrode GE <b> 1 using a photoresist film (not shown) opening the nMIS formation region 1 </ b> B as a mask. The n ⁻ type semiconductor region (extension region, LDD (Lightly doped Drain) region) 11b is formed by ion implantation of the n type impurity. Further, by using a photoresist film (not shown) having an opening in the pMIS formation region 1A as a mask, a p-type impurity such as boron (B) is ion-implanted into the n-type well 4 on both sides of the gate electrode GE2. A p ⁻ type semiconductor region (extension region, LDD region) 11a is formed.

  Next, as shown in FIG. 14, sidewalls (sidewall spacers, sidewall insulating films) 13 made of an insulator are formed on the sidewalls of the gate electrodes GE1 and GE2. For example, after a silicon nitride film is formed on the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2, the silicon nitride film is anisotropically etched (etched back), whereby the respective sidewalls of the gate electrodes GE1 and GE2 are formed. In addition, the silicon nitride film 13a can be left in a self-aligned manner. Subsequently, a silicon oxide film 13b and a silicon nitride film 13c are sequentially stacked on the semiconductor substrate 1 so as to cover the gate electrodes GE1 and GE2, and the stacked films (13b and 13c) are anisotropically etched (etched back). As a result, the sidewall 13 made of the silicon nitride film 13a, the silicon oxide film 13b, and the silicon nitride film 13c can be formed on the sidewalls of the gate electrodes GE1 and GE2.

Next, as shown in FIG. 15, phosphorus (P) or p-type wells 3 on both sides of the gate electrode GE 1 and the sidewall 13 are formed using a photoresist film (not shown) having an opening in the nMIS formation region 1 B as a mask. An n ⁺ type semiconductor region 12b is formed by ion implantation of an n type impurity such as arsenic (As). The n ⁺ type semiconductor region 12b is a region having a higher impurity concentration and a deep junction depth than the n ⁻ type semiconductor region 11b. Also, a p-type impurity such as boron (B) is ion-implanted into the gate electrode GE2 and the n-type well 4 on both sides of the sidewall 13 using a photoresist film (not shown) having an opening in the pMIS formation region 1A as a mask. Thus, the p ⁺ type semiconductor region 12a is formed. The p ⁺ type semiconductor region 12a is a region having a higher impurity concentration and a deeper junction depth than the p ⁻ type semiconductor region 11a.

Thereafter, annealing treatment (activation annealing, heat treatment) at about 1000 ° C. is performed to activate the introduced impurities. Thereby, impurities introduced into the n ⁻ type semiconductor region 11b, the p ⁻ type semiconductor region 11a, the n ⁺ type semiconductor region 12b, the p ⁺ type semiconductor region 12a, and the like can be activated. By this step, the source and drain regions of the n-channel type MISFET (Qn) having an LDD configuration including the n ⁻ type semiconductor region 11b and the n ⁺ type semiconductor region 12b are formed. In addition, the source and drain regions of the p-channel type MISFET (Qp) having an LDD configuration including the p ⁻ type semiconductor region 11a and the p ⁺ type semiconductor region 12a are formed.

  Here, in this embodiment, since the silicon oxynitride film ON is formed on the main surface of the semiconductor substrate 1 in advance, even if the heat treatment such as the activation annealing is applied, Generation of a silicon oxide film that can occur at the interface of the gate insulating films (5a, 5b) can be suppressed. For example, when the silicon nitride film ON is not formed, a silicon oxide film is formed at the interface. Since this silicon oxide film cannot be formed with good controllability such as its film thickness, the element characteristics such as the threshold value may vary. On the other hand, the above problem can be reduced by forming the silicon oxynitride film ON in advance. Further, since the generation of a silicon oxide film that can occur at the interface between the semiconductor substrate 1 and the second gate insulating film (5a, 5b) can be suppressed, EOT can be reduced.

  Through the above steps, an n-channel type MISFET Qn is formed as a field effect transistor in the nMIS formation region 1B, and a p-channel type MISFET Qp is formed as a field effect transistor in the pMIS formation region 1A.

Next, as shown in FIG. 16, silicide layers 14 are formed on the upper surfaces of the n ⁺ type semiconductor region 12b, the p ⁺ type semiconductor region 12a, and the gate electrodes GE1 and GE2 by salicide technology. As the silicide layer 14, NiSi (nickel silicide), CoSi (cobalt silicide), or the like can be used.

  Subsequently, as the interlayer insulating film 31, for example, a single film of a silicon oxide film or a laminated film of a thin silicon nitride film and a thick silicon oxide film thereon is formed on the MISFET (Qn, Qp). Next, the surface of the interlayer insulating film 31 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Next, the contact hole (through hole, hole) 32 is formed by dry etching the interlayer insulating film 31 on the source / drain regions (12a, 12b) of the MISFET (Qn, Qp). A contact hole may be formed on the gate electrodes GE1 and GE2.

  Next, a plug (connecting conductor portion) 33 is formed by embedding a conductive film made of tungsten (W) or the like in the contact hole 32. For example, a barrier film (for example, a titanium film, a titanium nitride film, or a laminated film thereof, not shown) is deposited on the interlayer insulating film 31 including the inside of the contact hole 32, and then a W film is deposited. Thereafter, unnecessary barrier film and W film on the interlayer insulating film 31 are removed by a CMP method or an etch back method, thereby forming the plug 33.

  Next, as shown in FIG. 17, for example, a laminated film of a silicon nitride film and a silicon oxide film is formed as the wiring groove insulating film 35 on the interlayer insulating film 31 including the plug 33 by the CVD method or the like. This silicon nitride film is located below the silicon oxide film, and serves as an etching stopper film when forming a wiring trench to be described later.

  Next, a first layer wiring M1 is formed by a single damascene method. First, after forming the wiring groove 36 by etching the wiring groove insulating film 35, a barrier film (not shown) and a copper seed layer are formed on the wiring groove insulating film 35 including the inside of the wiring groove 36. Then, a copper plating film is formed on the seed layer using an electrolytic plating method or the like. Next, unnecessary copper plating film, seed layer, and barrier film other than the wiring trench 36 are removed by CMP or the like to form a first layer wiring M1 using copper as a main conductive material.

  Thereafter, the second and subsequent wirings may be formed through an insulating film. At this time, the wiring in the second and subsequent layers may be formed by using a dual damascene method in which the inside of the wiring trench and the contact hole in the lower layer is simultaneously filled with a copper plating method or the like. Each wiring including the first layer wiring may be formed by a method other than the damascene method. For example, a conductor film for wiring can be formed by patterning, for example, tungsten wiring or aluminum wiring.

  As described above in detail, according to the present embodiment, by increasing the N content of the HfLaON film 5b of the n-channel MISFET (Qn), the threshold value of the n-channel MISFET (Qn) can be reduced. Can do. In particular, the NCE (Narrow Channel Effect) characteristic can be improved in the nMIS formation region 1B. The NCE characteristic is a phenomenon in which the threshold value of the MISFET is increased when a metal element in a threshold adjustment layer such as La diffuses into the element isolation region 2 or the like. In particular, in the Hf-based insulating film of the n-channel type MISFET (Qn), a metal element such as La is present alone and easily diffuses, so that the NCE characteristic is deteriorated. On the other hand, according to the present embodiment, by increasing the N content of the HfLaON film 5b, La is combined with N and becomes difficult to diffuse, so that the NCE characteristic can be improved.

  On the other hand, by reducing the N content of the HfAlON film 5a of the p-channel type MISFET (Qp), the threshold value of the p-channel type MISFET (Qp) can be reduced. Further, the NBTI (Negative Bias Temperature Instability) of the p-channel type MISFET (Qp) can be improved. NBTI refers to a deterioration phenomenon in negative bias (Bias Temperature) stress of a p-channel type MISFET. This phenomenon becomes apparent as the electric field strength of the internal MISFET increases with the miniaturization of the MISFET. The cause of this phenomenon is related to an increase in the interface order and an increase in the positive charge in the gate insulating film. By reducing the N content of the HfAlON film 5a of the p-channel MISFET (Qp), the above interface can be obtained. The order and the positive charge in the gate insulating film can be reduced, and NBTI can be improved.

Next, with reference to FIGS. 18 to 21, the comparative example and the experimental example studied by the present inventor will be described, and the present embodiment will be described in more detail. FIG. 18 is a graph showing the relationship between the nitrogen flow rate (N ₂ Flow, N ₂ amount) and the nitrogen composition ratio (N / Ti) when forming the TiN films (7a, 7b) of the present embodiment. FIG. 19 is a table showing the relationship between the nitrogen flow rate (N ₂ Flow) and the nitrogen composition ratio (N / Ti). The nitrogen composition ratio (N / Ti) was measured by XPS (X-ray Photoelectron Spectroscopy) method. The XPS method is a technique that can measure the energy distribution of photoelectrons emitted by X-ray irradiation and analyze the type, abundance, chemical bonding state, and the like of an element on a sample surface (a depth of about several nm). In addition to the above nitrogen, argon (Ar) was also used. In either case, the Ar flow rate was 15 sccm.

As shown in FIG. 18 and FIG. 19, when the flow rate of nitrogen (N ₂ ) is 12 sccm under the standard TiN film formation conditions (standard conditions), if the flow rate of nitrogen is low and 4 sccm, N / Ti A Ti-rich TiN film having a (nitrogen composition ratio) of about 1.12 was obtained. Further, when the nitrogen flow rate was increased to 24 sccm with respect to the standard conditions, an N-rich TiN film having an N / Ti (nitrogen composition ratio) of about 1.27 was obtained. Therefore, a TiN film having N / Ti (nitrogen composition ratio) of 1.2 as a boundary and N / Ti (nitrogen composition ratio) of less than 1.2 is referred to as a Ti-rich TiN film and N / Ti (nitrogen composition ratio) A TiN film having a thickness of 1.2 or more can be called an N-rich TiN film.

  FIG. 20 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of Comparative Example 1 of the present embodiment. For example, as shown in FIG. 20, in Comparative Example 1, a TiN film (metal nitride film) 7 formed under standard conditions is used as a hard mask that serves as an antioxidant film for the Al film 8a. Further, after the La film 8b is formed, the upper hard mask (7b) is not formed. Under such conditions, when the same heat treatment as in this embodiment is performed to form a poly-Si / metal / high-k film laminate, the eWF (effective work function) of the laminate in the nMIS formation region 1B is formed. ) Was 4.28 eV, and the eWF of the pMIS formation region 1A was 4.62 eV. The eWF is a parameter that correlates with the threshold of the MISFET. In the n-channel MISFET, the smaller the eWF, the smaller the threshold and the better. On the other hand, in the p-channel type MISFET, the larger the eWF, the smaller the absolute value of the threshold and the better.

  FIG. 21 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of Comparative Example 2 of the present embodiment. For example, as shown in FIG. 21, in Comparative Example 2, a Ti-rich TiN film (metal nitride) formed under the “Tirich condition” shown in FIG. 19 as a hard mask serving as an antioxidant film for the Al film 8a. Membrane) 7a is used. Further, after the La film 8b is formed, the upper hard mask (7b) is not formed. Under such conditions, when the same heat treatment as in the present embodiment is performed to form a poly-Si / metal / high-k film laminate, the eWF of the laminate in the nMIS formation region 1B is 4.30 eV, The eWF of the pMIS formation region 1A was 4.64 eV.

  That is, by using the Ti-rich TiN film 7a, the N content of the HfAlON film 5a can be reduced in the pMIS formation region 1A, and the eWF is improved (4.62 → 4.64), but the nMIS formation is performed. In the region 1B, the N content of the HfLaON film 5b cannot be ensured, and eWF deteriorates (4.28 → 4.30). In other words, although the threshold value of the p-channel type MISFET (Qp) can be reduced, the threshold value of the n-channel type MISFET (Qn) is increased.

  On the other hand, according to the present embodiment, as shown in FIG. 8, in the pMIS formation region 1A, a Ti-rich TiN film 7a is used as a hard mask serving as an Al film 8a and its antioxidant film, In the nMIS formation region 1B, since the N-rich TiN film 7b is used as a hard mask serving as the La film 8b and its antioxidant film, the threshold values of both MISFETs can be improved.

  Specifically, according to the study (experimental example) of the present inventor, when the heat treatment of this embodiment is performed to form a poly-Si / metal / high-k film stack, the stack of the nMIS formation region 1B is formed. The eWF of the product was 4.28 eV, and the eWF of the pMIS formation region 1A was 4.64 eV.

  That is, in the pMIS formation region 1A, the N content of the HfAlON film 5a can be reduced and the eWF can be improved, and in the nMIS formation region 1B, the N content of the HfLaON film 5b can be increased and the eWF can be improved. In other words, the absolute value of the threshold value of the p-channel type MISFET (Qp) can be reduced, and the threshold value of the n-channel type MISFET (Qn) can be reduced.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and is particularly effective when applied to a semiconductor device having a field effect transistor using a high dielectric film as a gate insulating film.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A pMIS formation area 1B nMIS formation area 2 Element isolation area 2a Element isolation groove 3 P type well 4 N type well 5 HfON film 5a HfAlON film 5b HfLaON film 7a TiN film 7b TiN film 8a Al film 8b La film 9 Metal Film 10 Silicon film 11a p ⁻ type semiconductor region 11b n ⁻ type semiconductor region 12a p ⁺ type semiconductor region 12b n ⁺ type semiconductor region 13 Side wall 13a Silicon nitride film 13b Silicon oxide film 13c Silicon nitride film 14 Silicide layer 21 Automatic transfer device 22 Storage chamber 23 Robot arm 24 Transfer chamber 25 Al film forming device 26 TiN film forming device 27 La film forming device 28 Annealing device 31 Interlayer insulating film 32 Contact hole 33 Plug 35 Wiring groove insulating film 36 Wiring groove GE1 Gate electrode GE2 Gate Electrode M1 Wiring ON Silicon oxynitride film PR1 Photoresist film Qn n-channel MISFET
Qp p-channel MISFET

Claims (20)

A method of manufacturing a semiconductor device having a p-channel MISFET in a first region of a semiconductor substrate and an n-channel MISFET in a second region of the semiconductor substrate,
(A) forming a HfON film in the first region and the second region of the semiconductor substrate;
(B) forming a first metal film containing aluminum on the HfON film;
(C) forming a first titanium nitride film on the first metal film;
(D) removing the first titanium nitride film and the first metal film in the second region;
(E) after the step (d), forming a second metal film containing a lanthanoid metal on the HfON film in the second region and on the first titanium nitride film in the first region;
(F) forming a second titanium nitride film on the second metal film;
(G) After the step (f), heat treatment is performed to generate an HfAlON film by a reaction between the HfON film in the first region and the first metal film, and the HfON film in the second region and the second metal Producing a HfLnON film (Ln; lanthanoid metal) by reaction with the film;
(H) After the step (g), removing the second titanium nitride film and the second metal film, and removing the first titanium nitride film and the first metal film;
(I) forming a first gate electrode on the HfAlON film in the first region and forming a second gate electrode on the HfLnON film in the second region;
(J) forming a p-type impurity region in the semiconductor substrate on both sides of the first gate electrode and forming an n-type impurity region in the semiconductor substrate on both sides of the second gate electrode;
Have
When the composition ratio of Ti and N of the first titanium nitride film is 1: X1a and the composition ratio of Ti and N of the second titanium nitride film is 1: X1b, the relationship of X1a <X1b is satisfied. A method of manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the lanthanoid metal is lanthanum, and the HfLnON film (Ln; lanthanoid metal) is an HfLaON film.   The relation of Za <Zb is satisfied when the composition ratio of Hf and N of the HfAlON film is 1: Za and the composition ratio of Hf and N of the HfLaON film is 1: Zb. 3. A method for producing a semiconductor device according to 2.   The method of manufacturing a semiconductor device according to claim 2, wherein the X1a of the first titanium nitride film is less than 1.2.   The method of manufacturing a semiconductor device according to claim 2, wherein the X1b of the second titanium nitride film is 1.2 or more. The formation of the first metal film in the step (b) is performed in a first chamber in the first apparatus,
The formation of the first titanium nitride film in the step (c) is performed in a second chamber in the first apparatus,
The first metal film and the first titanium nitride film are continuously formed by transferring the first chamber to the second chamber through a path of an inert atmosphere. A method for manufacturing a semiconductor device according to claim 2. The formation of the second metal film in the step (e) is performed in a third chamber in the first apparatus,
Step (f) The second titanium nitride film is formed in the second chamber,
The second metal film and the second titanium nitride film are continuously formed by carrying the wafer from the third chamber into the second chamber through an inert atmosphere path. A method for manufacturing a semiconductor device according to claim 6. The heat treatment in the step (g) is performed in a fourth chamber in the first apparatus,
By carrying from the second chamber to the fourth chamber through a path of an inert atmosphere,
8. The method of manufacturing a semiconductor device according to claim 7, wherein the formation of the second titanium nitride film and the heat treatment are continuously performed. Before the step (a),
(K) including a step of forming an insulating film in the first region and the second region of the semiconductor substrate;
3. The method of manufacturing a semiconductor device according to claim 2, wherein the step (a) is a step of forming an HfON film on the insulating film.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the insulating film is a semiconductor oxide film or the semiconductor oxynitride film constituting the semiconductor substrate.   3. The method of manufacturing a semiconductor device according to claim 2, wherein an element isolation region is formed between the first region and the second region.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the first gate electrode and the second gate electrode in the step (i) have a metal or metal compound layer.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the metal or metal compound layer is a titanium nitride layer.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the first gate electrode and the second gate electrode in the step (i) have a silicon layer on the metal or metal compound layer. A semiconductor device having a p-channel MISFET formed in a first region of a semiconductor substrate and an n-channel MISFET formed in a second region of the semiconductor substrate,
(A) The p-channel MISFET is
(A1) a first gate insulating film disposed on the semiconductor substrate, the first gate insulating film having an HfAlON film;
(A2) a first gate electrode disposed on the first gate insulating film;
(A3) a p-type semiconductor region disposed in the semiconductor substrate on both sides of the first gate electrode,
(B) The n-channel MISFET is
(B1) a second gate insulating film disposed on the semiconductor substrate, the second gate insulating film having an HfLaON film;
(B2) a second gate electrode disposed on the second gate insulating film;
(B3) n-type semiconductor regions arranged in the semiconductor substrate on both sides of the second gate electrode,
The semiconductor device is characterized in that Za <Zb when the composition ratio of Hf and N of the HfAlON film is 1: Za and the composition ratio of Hf and N of the HfLaON film is 1: Zb. . The first gate insulating film is disposed on the semiconductor substrate, and is disposed on the first insulating film and a first insulating film which is a semiconductor oxide film or the semiconductor oxynitride film constituting the semiconductor substrate. And the HfAlON film,
The semiconductor device according to claim 15, wherein the second gate insulating film includes the first insulating film and the HfLaON film disposed on the first insulating film.   16. The semiconductor device according to claim 15, wherein an element isolation region is formed between the first region and the second region.   16. The semiconductor device according to claim 15, wherein each of the first gate electrode and the second gate electrode includes a metal layer or a metal compound layer.   19. The semiconductor device according to claim 18, wherein the metal or metal compound layer is a titanium nitride layer.   19. The semiconductor device according to claim 18, wherein the first gate electrode and the second gate electrode have a silicon layer on the metal or metal compound layer.

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