JP2012182368A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress decrease in drain current when a high-resistance component is added to one of a source and a drain.SOLUTION: In a semiconductor device according to an embodiment, a substrate, a first source and a first drain, a second source and a second drain, and a gate electrode film are provided. The first source and the first drain and the second source and the second drain are provided on a surface of the substrate. One of the second source and the second drain is arranged so as to be adjacent to one of the first source and the first drain. The other of the second source and the second drain is arranged so as to be adjacent to the other of the first source and the first drain. The gate electrode film is provided on the surface of the substrate between one of the first and second source and drain and the other of the first and second source and drain via a gate insulating film. The first source and drain and the gate electrode film forms a first FET, and the second source and drain and the gate electrode film forms a second FET.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  Various semiconductor devices such as LSIs and SoCs (system on a chip) composed of Pch MOSFETs and Nch MOSFETs have been developed as MOSFETs (metal oxide semiconductor field effect transistors) have become smaller, more highly integrated, and have lower power consumption. It is widely used in the field.

  In a Pch MOSFET, when a high resistance component such as a high resistance element or parasitic high resistance is added to the source side connected to the high potential side power supply, the potential difference between the gate and the source decreases, and the drain current flowing from the source to the drain There is a problem in that it significantly decreases. In the Nch MOSFET, when a high resistance component such as a high resistance element or parasitic high resistance is added to the source side connected to the low potential side power supply (ground potential), the potential difference between the gate and the source decreases, and the drain to source There is a problem in that the drain current flowing through the drain is greatly reduced.

JP 2009-16418 A

  An object of the present invention is to provide a semiconductor device capable of suppressing a decrease in drain current when a high resistance component is added to one of a source and a drain, and a method for manufacturing the same.

  According to one embodiment, the semiconductor device includes a substrate, one of the first source and drain, the other of the first source and drain, one of the second source and drain, the other of the second source and drain, And a gate electrode film is provided. One of the first source and the drain is provided on the substrate surface and has the first conductivity type. The other of the first source and the drain is provided on the substrate surface and has the first conductivity type. One of the second source and drain is provided on the surface of the substrate, is disposed adjacent to one of the first source and drain, and has the second conductivity type. The other of the second source and the drain is provided on the substrate surface, is disposed adjacent to the other of the first source and the drain, and has the second conductivity type. The gate electrode film is provided on the substrate surface between one of the first and second sources and drains and the other of the first and second sources and drains, and is provided via a gate insulating film. The first source and drain and the gate electrode film constitute a first FET. The second source and drain and the gate electrode film constitute a second FET.

  According to another embodiment, a method for manufacturing a semiconductor device includes first to seventh steps. In the first step, the periphery is separated by an element isolation film, and a protrusion having a quadrangular prism shape protruding from the periphery is formed. In the second step, a gate insulating film and a gate electrode film are stacked on the surface of the protrusion. In the third step, impurities of the first conductivity type are ion-implanted from an oblique direction into one end sides of the first and second regions of the protrusions divided by the gate insulating film and the gate electrode film. In the fourth step, impurities of the second conductivity type are ion-implanted from the oblique direction into the other end sides of the first and second regions of the protrusions divided by the gate insulating film and the gate electrode film. In the fifth step, the first and second conductivity type impurities are activated by heat treatment, and the first semiconductor layer serving as one of the source and drain of the first conductivity type having a high impurity concentration is formed. A second semiconductor layer which is the other of the source and drain of the conductivity type, a third semiconductor layer which is one of the source and drain of the second conductivity type having a high impurity concentration, and a source of the second conductivity type having a high impurity concentration and A fourth semiconductor layer serving as the other drain is formed. The sixth step is to etch the insulating film on the first and third semiconductor layers to form a first opening, and to etch the insulating film on the second and fourth semiconductor layers to An opening is formed, and the insulating film on the gate electrode film is etched to form a third opening. The seventh step embeds an electrode material so as to cover the first opening, forms a first terminal connected to the first and third semiconductor layers, and covers the second opening A gate terminal embedded in the electrode material to form a second terminal connected to the second and fourth semiconductor layers, and embedded in the electrode material to cover the third opening and connected to the gate electrode film Form.

It is a figure explaining MOSFET which concerns on 1st embodiment. 1 is a schematic perspective view showing a MOSFET according to a first embodiment. It is sectional drawing which shows MOSFET which concerns on 1st embodiment. It is a figure explaining the drain current at the time of addition of the high resistance element which concerns on 1st embodiment. It is a figure explaining the drain current at the time of addition of the high resistance element which concerns on 1st embodiment. It is a figure explaining the addition of the high resistance element which concerns on 1st embodiment, and the direction of drain current. It is a figure explaining the addition of the high resistance element which concerns on 1st embodiment, and the direction of drain current. It is a figure explaining operation | movement of Pch MOSFET which concerns on 1st embodiment. It is a figure explaining operation of Nch MOSFET concerning a 1st embodiment. It is a figure explaining the manufacturing process which concerns on 1st embodiment. It is a figure explaining the manufacturing process which concerns on 1st embodiment. It is a figure explaining the manufacturing process which concerns on 1st embodiment. It is a figure explaining the manufacturing process which concerns on 1st embodiment. It is a figure explaining the manufacturing process which concerns on 1st embodiment. It is sectional drawing which shows MOSFET of a modification. The top view which shows the tunnel MOSFET which concerns on 2nd embodiment. It is a model perspective view which shows the tunnel MOSFET which concerns on 2nd embodiment. It is a figure explaining addition of the high resistance element which concerns on 2nd embodiment, and operation | movement of tunnel MOSFET. It is a figure explaining addition of the high resistance element which concerns on 2nd embodiment, and operation | movement of tunnel MOSFET. It is a circuit diagram which shows the semiconductor device which concerns on 3rd embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
First, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a plan view showing a MOSFET, and FIG. 1B is a circuit diagram of the MOSFET. FIG. 2 is a schematic perspective view of the MOSFET. 3A is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3B is a cross-sectional view taken along line BB in FIG. In this embodiment, the MOSFET has a structure capable of Pch and Nch operation.

As shown in FIGS. 1A and 1B, the MOSFET 90 is provided with a P ⁺ layer 31a, a P ⁺ layer 31b, an N ⁺ layer 32a, and an N ⁺ layer 32b that serve as a source or a drain. The P ⁺ layer 31a, the P ⁺ layer 31b, the N ⁺ layer 32a, and the N ⁺ layer 32b are provided in an active region (element region) AR1 that is surrounded by the buried insulating film 2. The P ⁺ layer 31a and the P ⁺ layer 31b are semiconductor layers doped with a P-type impurity at a high concentration. The N ⁺ layer 32a and the N ⁺ layer 32b are semiconductor layers doped with N-type impurities at a high concentration. The MOSFET 90 is applied to a semiconductor device such as an IC, LSI, and SoC (system on a chip).

The P ⁺ layer 31a is provided on the upper left side in the drawing of the active region (element region) AR1. The P ⁺ layer 31b is provided on the upper right end side of the active region (element region) AR1 in the drawing. The N ⁺ layer 32a is provided on the lower left side in the drawing of the active region (element region) AR1. The N ⁺ layer 32b is provided on the lower right side in the drawing of the active region (element region) AR1.

The P ⁺ layer 31a and the P ⁺ layer 31b serve as the source or drain of the first FET that is a Pch MOSFET. The N ⁺ layer 32a and the N ⁺ layer 32b serve as the source or drain of the second FET that is an Nch MOSFET. The MOSFET 90 is an FET that operates as a Pch MOS transistor and an Nch MOS transistor.

A contact hole CH1 is provided in the insulating film on the P ⁺ layer 31a and the N ⁺ layer 32a. The first terminal FP1 made of an electrode material is provided so as to cover the contact hole CH1, and is connected to the P ⁺ layer 31a and the N ⁺ layer 32a. A contact hole CH2 is provided in the insulating film on the P ⁺ layer 31b and the N ⁺ layer 32b. The second terminal SP1 made of an electrode material is provided so as to cover the contact hole CH2, and is connected to the P ⁺ layer 31b and the N ⁺ layer 32b.

A gate electrode GD1 is provided on the substrate 3 between the P ⁺ layer 31a and the N ⁺ layer 32a and the P ⁺ layer 31b and the N ⁺ layer 32b via a gate insulating film. The substrate 3 is made of an undoped substrate and is connected to the body terminal BP1. A contact hole CH3 is provided in the insulating film on the gate electrode GD1. The gate terminal GP1 made of an electrode material is provided so as to cover the contact hole CH3, and is connected to the gate electrode GD1.

  The first FET that is the Pch MOSFET and the second FET that is the Nch MOSFET share the gate electrode GD1 and the body terminal BP1. The MOSFET 90 has a structure capable of operating as a Pch MOS transistor or an Nch MOS transistor by appropriately setting the voltages applied to the first terminal FP1, the second terminal SP1, the gate terminal GP1, and the body terminal BP1, respectively. It has become. Details will be described later.

  As shown in FIG. 2, the active region (element region) AR <b> 1 has a quadrangular prism structure protruding from the buried insulating film 2. The gate electrode GP1 has a horseshoe shape, for example. The gate electrode GP1 is provided on the first main surface (upper surface), the second main surface (side surface adjacent to the upper surface), and the third main surface (side surface adjacent to the upper surface) of the active region (element region) AR1. The MOSFET 90 is a FIN FET formed on an SOI substrate.

  As shown in FIG. 3A, the substrate 51 includes a substrate 1, a buried insulating film 2, and a substrate 3 that are stacked. The active region (element region) AR1 is formed by etching the surrounding substrate 3. On the active region (element region) AR1 and the buried insulating film 2, a gate insulating film 5 and a gate electrode film 6 are stacked. An insulating film 7 as an interlayer insulating film is provided on the gate electrode film 6. The insulating film 7 on the gate electrode film 6 is etched to provide a contact hole CH3. On the contact hole CH3 and the insulating film 7, a wiring material 8 to be the gate terminal GP1 is provided so as to cover the contact hole CH3. Although not shown, the substrate 3 is connected to the body terminal BP1 through a body contact.

As shown in FIG. 3B, a P ⁺ layer 31b and an N ⁺ layer 32b are provided on the upper surface of the active region (element region) AR1. An insulating film 7 is provided on the P ⁺ layer 31b and the N ⁺ layer 32b. The insulating film 7 on the P ⁺ layer 31b and the N ⁺ layer 32b is etched to provide a contact hole CH2. On the contact hole CH2 and the insulating film 7, a wiring material 8 to be the gate terminal GP1 is provided so as to cover the contact hole CH2.

  Next, the operation of the MOSFET when a high resistance element is added will be described with reference to FIGS.

  FIG. 4A is a diagram for explaining the drain current of a Pch MOSFET in which a high resistance element is added on the source side. FIG. 4B is a diagram for explaining the drain current of the Pch MOSFET in which a high resistance element is added on the drain side.

  As shown in FIG. 4A, in the Pch MOSFET, when a high resistance component such as a high resistance element or parasitic high resistance is added to the source side connected to the high potential side power supply Vdd, the potential difference between the gate and the source. And the drain current flowing from the source to the drain is greatly reduced.

  As shown in FIG. 4B, in the Pch MOSFET, when a high resistance component such as a high resistance element or a parasitic high resistance is added to the drain side connected to the low potential side power supply (ground potential) Vss, The potential difference between the sources does not decrease, the drain current flowing from the source to the drain can be secured at a predetermined value, and a large drain current can flow.

  FIG. 5A is a diagram for explaining the drain current of an Nch MOSFET in which a high resistance element is added on the drain side. FIG. 5B is a diagram for explaining the drain current of an Nch MOSFET in which a high resistance element is added on the source side.

  As shown in FIG. 5A, in the Nch MOSFET, when a high resistance component such as a high resistance element or parasitic high resistance is added to the drain side connected to the high potential side power supply Vdd, the potential difference between the gate and the source. The drain current flowing from the drain to the source can be secured at a predetermined value, and a large drain current can flow.

  As shown in FIG. 5B, in the Nch MOSFET, when a high resistance component such as a high resistance element or a parasitic high resistance is added to the source side connected to the low potential side power supply (ground potential) Vss, The potential difference between the sources is reduced, and the drain current flowing from the drain to the source is significantly reduced.

  That is, when a high resistance component such as a high resistance element or parasitic high resistance is added to the source side, the drain current of both the Pch MOSFET and the Nch MOSFET is greatly reduced. On the other hand, when a high resistance component such as a high resistance element or parasitic high resistance is added to the drain side, a large drain current can flow through both the Pch MOSFET and the Nch MOSFET.

  FIG. 6 is a diagram illustrating a case where the drain current of the MOSFET 90 flows from the first terminal to the second terminal, and FIG. 6A is a diagram illustrating a case where a high resistance element is added to the first terminal side. FIG. 6B is a diagram illustrating a case where a high resistance element is added to the second terminal side.

  As shown in FIG. 6A, in the MOSFET 90, the first terminal FP1 side of the Nch MOSFET as the second FET is the drain, the second terminal SP1 side is the source, the first terminal FP1, By appropriately setting the voltages applied to the terminal SP1, the gate terminal GP1, and the body terminal BP1 to appropriate values, the Nch MOSFET that is the second FET can be turned on. At this time, a large drain current can flow.

  As shown in FIG. 6B, in the MOSFET 90, the first terminal FP1 side of the Pch MOSFET as the first FET is the source, the second terminal SP1 side is the drain, the first terminal FP1, By appropriately setting the voltages applied to the terminal SP1, the gate terminal GP1, and the body terminal BP1 to optimal values, the Pch MOSFET that is the first FET can be turned on. At this time, a large drain current can flow.

  FIG. 7 is a diagram illustrating a case where the drain current of the MOSFET 90 flows from the second terminal to the first terminal, and FIG. 7A is a diagram illustrating a case where a high resistance element is added to the first terminal side. FIG. 7B is a diagram illustrating a case where a high resistance element is added to the second terminal side.

  As shown in FIG. 7A, in the MOSFET 90, the first terminal FP1 side of the Pch MOSFET as the first FET is the drain, the second terminal SP1 side is the source, the first terminal FP1, By appropriately setting the voltages applied to the terminal SP1, the gate terminal GP1, and the body terminal BP1 to optimal values, the Pch MOSFET that is the first FET can be turned on. At this time, a large drain current can flow.

  As shown in FIG. 7B, in the MOSFET 90, the Nch MOSFET as the second FET has the first terminal FP1 side as the source, the second terminal SP1 side as the drain, the first terminal FP1, the second terminal By appropriately setting the voltages applied to the terminal SP1, the gate terminal GP1, and the body terminal BP1 to appropriate values, the Nch MOSFET that is the second FET can be turned on. At this time, a large drain current can flow.

  A specific selection method of the Pch MOSFET that is the first FET of the MOSFET 90 and the Nch MOSFET that is the second FET will be described.

In the MOSFET 90, first, the gate length dimension (Lg), the gate width dimension (Wg), the material and the film thickness of the gate insulating film 5 (in other words, equivalent SiO 2) so that the enhancement type FET (the threshold voltage Vth is a positive value) ₂ equivalent film thickness EOT), the film quality of the gate electrode film 6, the substrate 3 and the like are appropriately selected. For example, the gate length dimension (Lg) is set to 30 nm or less (for example, 25 nm), the EOT is set to 1 nm, HfSiON is used for the gate insulating film 5, and TiN (titanium nitride) is used for the gate electrode film.

  FIG. 8 is a diagram for explaining the operation of the Pch MOSFET of the MOSFET 90. Here, the Pch MOSFET operates by setting the substrate voltage Vsub, the drain voltage Vd, and the source voltage Vs to fixed values and varying the gate voltage Vg.

  As shown in FIG. 8, the voltage of the high-potential-side power supply Vdd is set in the range of, for example, 0.5 V to 1.0 V, and the threshold voltage Vth1 is set in the range of the gate voltage from 0 (zero) V to Vdd. As described above, the substrate voltage Vsub is set to 0 (zero) V, the drain voltage Vd is set to the high potential side power supply Vdd voltage, and the source voltage Vs is set to the low potential side power supply (ground potential 0 (zero) V). In this setting, the drain current does not decrease even if a high resistance component is added to the drain side of the Pch MOSFET.

  FIG. 9 is a diagram for explaining the operation of the Nch MOSFET of the MOSFET 90. Here, the Nch MOSFET operates by setting the substrate voltage Vsub, the drain voltage Vd, and the source voltage Vs to fixed values and varying the gate voltage Vg.

  As shown in FIG. 9, the voltage of the high-potential-side power supply Vdd is set in the range of, for example, 0.5 V to 1.0 V, and the threshold voltage Vth2 is set in the range of the gate voltage from 0 (zero) V to Vdd. Thus, the substrate voltage Vsub is set to the high potential side power supply Vdd voltage, the drain voltage Vd is set to the high potential side power supply Vdd voltage, and the source voltage Vs is set to the low potential side power supply (ground potential 0 (zero) V). In this setting, the drain current does not decrease even if a high resistance component is added to the drain side of the Nch MOSFET.

  10 is a diagram for explaining the operating conditions of the MOSFET 90, FIG. 10 (a) is a diagram for explaining the operating conditions of the Pch MOSFET of the MOSFET 90, and FIG. 10 (b) is a diagram for explaining the operating conditions of the Nch MOSFET of the MOSFET 90.

  As shown in FIG. 10A, in the MOSFET 90, the Pch MOSFET, which is the first FET, uses the substrate voltage Vsub as the low potential side power supply (ground potential 0 (zero) V), and the drain voltage Vd as the high potential side power supply Vdd. When the voltage and source voltage Vs are set to the low potential side power supply (ground potential 0 (zero) V) and the gate voltage Vg is set to the low potential side power supply (ground potential 0 (zero) V), it is turned on. The substrate voltage Vsub is the low potential side power supply (ground potential 0 (zero) V), the drain voltage Vd is the high potential side power supply Vdd voltage, the source voltage Vs is the low potential side power supply (ground potential 0 (zero) V), and the gate voltage Vg. Is set to the high-potential-side power supply Vdd voltage, it is turned off.

  As shown in FIG. 10B, in the MOSFET 90, the Nch MOSFET as the second FET has the substrate voltage Vsub as the high potential side power supply Vdd voltage, the drain voltage Vd as the high potential side power supply Vdd voltage, and the source voltage Vs as the low voltage. It turns on when the potential side power supply (ground potential 0 (zero) V) and the gate voltage Vg are set to the high potential side power supply Vdd voltage. The substrate voltage Vsub is the high potential side power supply Vdd voltage, the drain voltage Vd is the high potential side power supply Vdd voltage, the source voltage Vs is the low potential side power supply (ground potential 0 (zero) V), and the gate voltage Vg is the low potential side power supply (grounding). Turns off when set to potential 0 (zero) V).

  Next, a method for manufacturing MOSFET 90 will be described with reference to FIGS. 11A is a plan view showing the manufacturing process of the MOSFET 90, FIG. 11B is a sectional view showing the manufacturing process of the MOSFET 90, FIG. 11C is a schematic perspective view showing the manufacturing process of the MOSFET 90, and FIG. ) Is a plan view showing the manufacturing process of the MOSFET 90, FIG. 12C is a schematic perspective view showing the manufacturing process of the MOSFET 90, FIG. 13A is a plan view showing the manufacturing process of the MOSFET 90, and FIG. FIG. 14A is a plan view showing the manufacturing process of the MOSFET 90, and FIG. 14B is a cross-sectional view showing the manufacturing process of the MOSFET 90. In addition, FIG.11 (b) and FIG.14 (b) respond | correspond to the cross-sectional part which follows the AA line of Fig.1 (a).

  As shown in FIGS. 11A, 11B, and 11C, an active region having a quadrangular prism shape protruding from the periphery by etching the substrate 3 which is the undoped silicon substrate of the SOI substrate 51 (see FIG. 11A). Element region AR1 is formed. The buried insulating film 2 is exposed around the active region (element region) AR1. A gate insulating film 5 and a gate electrode film 6 are stacked on the active region (element region) AR1 and the buried insulating film 2. Here, although HfSiON is used for the gate insulating film 5, SiO2, SiON, HfSiO2, HfO2, HfZrOx, HfLaOx, or the like may be used instead. TiN is used for the gate electrode film 6, but polycrystalline silicon, amorphous silicon, TaC, TaN, WN, or the like may be used instead. The first and second FETs are silicon channels, but may instead be SiGe channels, InAs channels, or InGaAs channels. When HfSiON is used for the gate insulating film 5, the MOSFET 90 may be referred to as a MISFET 90.

  Next, as shown in FIGS. 12A and 12C, the lower portion (the other end side) of the active region (element region) AR1 in the figure is covered with a resist film 41, and the active region (element region) is obliquely viewed. ) P-type impurities (for example, boron) are ion-implanted into the upper portion (one end side) of AR1. After the ion implantation, the resist film 41 is removed.

  Subsequently, as shown in FIGS. 13A and 13C, the upper part (one end side) of the active region (element region) AR1 in the drawing is covered with a resist film 42, and the active region (element region) is obliquely viewed. N-type impurities (for example, phosphorus) are ion-implanted into the lower part (the other end side) of AR1 in the drawing. After the ion implantation, the resist film 42 is removed.

  Here, P-type impurities are ion-implanted using the resist film 41 as a mask, and N-type impurities are ion-implanted using the resist film 42 as a mask. However, the present invention is not limited to this. For example, impurities may be selectively ion-implanted without using a resist film.

Next, as shown in FIGS. 14A and 14B, after ion implantation, the ion implantation layer is activated using, for example, an RTA (rapid thermal annealing) method to form a P ⁺ layer 31a and a P ⁺ layer 31b. , N ⁺ layer 32a, and N ⁺ layer 32b are formed. Note that the ion implantation layer may be activated by laser irradiation or high-temperature heat treatment instead of the RTA method. An insulating film 7 made of, for example, a SiOC film is formed on the gate electrode film 6 and the buried insulating film 2. The insulating film 7 on the gate electrode film 6 is etched to form an opening (contact hole CH3). On the opening (contact hole CH3) and the insulating film 7, the opening (contact hole CH3) is formed so as to cover the electrode material. Thereafter, the MOSFET 90 is completed by forming an interlayer insulating film, a via, a surface protective film, and the like using a known technique.

As described above, in the semiconductor device and the manufacturing method thereof according to the present embodiment, the P ⁺ layer 31a, the P ⁺ layer 31b, the N ⁺ layer 32a, and the N ⁺ layer 32b are provided on the surface of the active region (element region) AR1. . A gate electrode GD1 is provided on the substrate 3 between the P ⁺ layer 31a and the N ⁺ layer 32a and the P ⁺ layer 31b and the N ⁺ layer 32b via a gate insulating film. The P ⁺ layer 31a and the N ⁺ layer 32a are connected to the first terminal FP1. The P ⁺ layer 31b and the N ⁺ layer 32b are connected to the second terminal SP1. The P ⁺ layer 31a and the P ⁺ layer 31b serve as the source or drain of the Pch MOSFET that is the first FET. The N ⁺ layer 32a and the N ⁺ layer 32b serve as the source or drain of the Nch MOSFET that is the second FET. The MOSFET 90 is formed on an active region (element region) AR1 formed by etching the surrounding substrate 3.

  For this reason, even if a high resistance component such as a high resistance element or parasitic high resistance is added to the first terminal FP1 or the second terminal SP1, the first terminal FP1, the second terminal SP1, the gate terminal GP1, In addition, by setting the voltage applied to the body terminal BP1 to an optimal value as appropriate, the Pch MOSFET as the first FET or the Nch MOSFET as the second FET can be operated, thereby suppressing a decrease in drain current. be able to. Therefore, a large drain current can flow when MOSFET 90 operates.

  In the present embodiment, one set of the first and second FETs is arranged, but the present invention is not necessarily limited to this. Multiple arrangements may be repeatedly formed. The MOSFET 90 is a FIN FET, but may be a planar FET. The MOSFET 90 has a single gate structure, but may have a double gate or triple gate structure. The substrate 3 of the SOI substrate 51 removes the region other than the active region (element region) AR1, but a trench isolation (STI) may be provided on the surface of the substrate 3 around the active region (element region) AR1. . Further, as shown in FIG. 15, a substrate 1 which is an undoped silicon substrate may be used, and a MOSFET 91 formed in an active region (element region) AR <b> 1 whose periphery is separated by trench isolation (STI) 4 may be used.

(Second embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 16 is a cross-sectional view showing a tunnel MOSFET. FIG. 17 is a schematic perspective view showing a tunnel MOSFET. In this embodiment, the tunnel MOSFET has a structure capable of Pch and Nch operation.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

As shown in FIG. 16, the tunnel MOSFET 100 is provided with a P ⁺ layer 31a, a P ⁺ layer 31b, an N ⁺ layer 32a, and an N ⁺ layer 32b that serve as a source or drain. The P ⁺ layer 31a, the P ⁺ layer 31b, the N ⁺ layer 32a, and the N ⁺ layer 32b are provided in an active region (element region) AR1 that is surrounded by the buried insulating film 2. The tunnel MOSFET 100 can improve the subthreshold slope (the slope of the drain current with respect to the gate voltage) as compared with the MOSFET of the first embodiment, and can improve the on-current / off-current ratio and reduce the off-current.

The P ⁺ layer 31a is provided on the lower left side in the drawing of the active region (element region) AR1. The P ⁺ layer 31b is provided on the upper right end side of the active region (element region) AR1 in the drawing. The N ⁺ layer 32a is provided on the upper left side in the drawing of the active region (element region) AR1. The N ⁺ layer 32b is provided on the lower right side in the drawing of the active region (element region) AR1.

The N ⁺ layer 32a and the P ⁺ layer 31b serve as the source or drain of the first Nch tunnel MOSFET or the first Pch tunnel MOSFET. In the case of the first Nch tunnel MOSFET, the N ⁺ layer 32a is the drain and the P ⁺ layer 31b is the source. In the case of the first Pch tunnel MOSFET, the P ⁺ layer 31b is the source and the N ⁺ layer 32a is the drain.

The P ⁺ layer 31a and the N ⁺ layer 32b serve as the source or drain of the second Pch tunnel MOSFET or the second Nch tunnel MOSFET. In the case of the second Pch tunnel MOSFET, the P ⁺ layer 31a is the source and the N ⁺ layer 32b is the drain. In the case of the second Nch tunnel MOSFET, the N ⁺ layer 32b is the drain and the P ⁺ layer 31a is the source.

A contact hole CH1 is provided in the N ⁺ layer 32a and the P ⁺ layer 31a and the insulating film thereon. The first terminal FP1 made of an electrode material is provided so as to cover the contact hole CH1, and is connected to the N ⁺ layer 32a and the P ⁺ layer 31a. A contact hole CH2 is provided in the insulating film on the P ⁺ layer 31b and the N ⁺ layer 32b. The second terminal SP1 made of an electrode material is provided so as to cover the contact hole CH2, and is connected to the P ⁺ layer 31b and the N ⁺ layer 32b.

A gate electrode GD1 is provided on the substrate 3 between the N ⁺ layer 32a and the P ⁺ layer 31a and the P ⁺ layer 31b and the N ⁺ layer 32b via a gate insulating film. The substrate 3 is made of an undoped substrate and is connected to the body terminal BP1. A contact hole CH3 is provided in the insulating film on the gate electrode GD1. The gate terminal GP1 made of an electrode material is provided so as to cover the contact hole CH3, and is connected to the gate electrode GD1.

  The first Nch tunnel MOSFET, the first Pch tunnel MOSFET, the second Pch tunnel MOSFET, and the second Nch tunnel MOSFET share the gate electrode GD1 and the body terminal BP1. The tunnel MOSFET 100 can operate as a Pch tunnel MOS transistor or an Nch tunnel MOS transistor by appropriately setting voltages applied to the first terminal FP1, the second terminal SP1, the gate terminal GP1, and the body terminal BP1. It has a structure. Details will be described later.

  As shown in FIG. 17, the active region (element region) AR <b> 1 has a quadrangular prism structure protruding from the buried insulating film 2. The gate electrode GP1 has a horseshoe shape, for example. The gate electrode GP1 is provided on the first main surface (upper surface), the second main surface (side surface adjacent to the upper surface), and the third main surface (side surface adjacent to the upper surface) of the active region (element region) AR1. The tunnel MOSFET 100 is a FIN tunnel FET formed in the substrate 3 (active region (element region) AR1) on the buried insulating film 2 of the SOI substrate.

  Next, the operation of the tunnel MOSFET when a high resistance element is added will be described with reference to FIGS.

  FIG. 18A is a diagram for explaining the operation of the tunnel MOSFET when a drain current flows from the first terminal to the second terminal and a high resistance element is added to the first terminal side. FIG. 18B is a diagram for explaining the operation of the tunnel MOSFET when a drain current flows from the first terminal to the second terminal and a high resistance element is added to the second terminal side.

  As shown in FIG. 18 (a), the first terminal FP1 side of the first Nch tunnel MOSFET is the drain, the second terminal SP1 side is the source, the first terminal FP1, the second terminal SP1, and the gate terminal. The first Nch tunnel MOSFET can be turned on by appropriately setting the voltages applied to GP1 and body terminal BP1 to optimal values. At this time, a large drain current can flow. The second Pch tunnel MOSFET is off.

  As shown in FIG. 18B, the first terminal FP1 side of the second Pch tunnel MOSFET is the source, the second terminal SP1 side is the drain, the first terminal FP1, the second terminal SP1, and the gate terminal. The second Pch tunnel MOSFET can be turned on by appropriately setting the voltages applied to GP1 and body terminal BP1 to optimal values. At this time, a large drain current can flow. The first Nch tunnel MOSFET is off.

  FIG. 19A illustrates the operation of the tunnel MOSFET when a drain current flows from the second terminal to the first terminal and a high resistance element is added to the first terminal side. FIG. 19B is a diagram for explaining the operation of the tunnel MOSFET when a drain current flows from the second terminal to the first terminal and a high resistance element is added to the second terminal side.

  As shown in FIG. 19A, the first terminal FP1 side of the first Pch tunnel MOSFET is the drain, the second terminal SP1 side is the source, the first terminal FP1, the second terminal SP1, and the gate terminal. The first Pch tunnel MOSFET can be turned on by appropriately setting the voltages applied to GP1 and body terminal BP1 to optimal values. At this time, a large drain current can flow. The second Nch tunnel MOSFET is off.

  As shown in FIG. 19B, the first terminal FP1 side of the second Nch tunnel MOSFET is the source, the second terminal SP1 side is the drain, the first terminal FP1, the second terminal SP1, and the gate terminal. The second Nch tunnel MOSFET can be turned on by appropriately setting the voltages applied to GP1 and the body terminal BP1 to optimal values. At this time, a large drain current can flow. At this time, the first Pch tunnel MOSFET is off.

  That is, in the tunnel MOSFET 100, even if a high resistance component is added to the first terminal FP1 or the second terminal SP1 side, it is applied to the first terminal FP1, the second terminal SP1, the gate terminal GP1, and the body terminal BP1. A large drain current can be flowed by setting the voltage to be appropriately set to an optimal value.

As described above, in the semiconductor device of this embodiment, the P ⁺ layer 31a, the P ⁺ layer 31b, the N ⁺ layer 32a, and the N ⁺ layer 32b are provided on the surface of the active region (element region) AR1. A gate electrode GD1 is provided on the substrate 3 between the N ⁺ layer 32a and the P ⁺ layer 31a and the P ⁺ layer 31b and the N ⁺ layer 32b via a gate insulating film. The N ⁺ layer 32a and the P ⁺ layer 31a are connected to the first terminal FP1. The P ⁺ layer 31b and the N ⁺ layer 32b are connected to the second terminal SP1. The N ⁺ layer 32a and the P ⁺ layer 31b are sources or drains of the first Nch tunnel MOSFET and the first Pch tunnel MOSFET. The P ⁺ layer 31a and the N ⁺ layer 32b serve as the source or drain of the second Nch tunnel MOSFET and the second Pch tunnel MOSFET. Tunnel MOSFET 100 is formed on active region (element region) AR1 formed by etching the surface of substrate 3.

  For this reason, even if a high resistance component such as a high resistance element or parasitic high resistance is added to the first terminal FP1 or the second terminal SP1, the first terminal FP1, the second terminal SP1, the gate terminal GP1, And the voltage applied to the body terminal BP1 is appropriately set to an optimal value, so that one of the first Nch tunnel MOSFET, the first Pch tunnel MOSFET, the second Nch tunnel MOSFET, and the second Pch tunnel MOSFET is Since it can be operated, a decrease in drain current can be suppressed. Therefore, a large drain current can flow when the tunnel MOSFET 100 operates.

(Third embodiment)
Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 20 is a circuit diagram showing a semiconductor device. In the present embodiment, a MOSFET capable of Pch / Nch operation is used for the SRAM cell.

  As shown in FIG. 20, the semiconductor device is provided with a control unit 60 and an SRAM cell 200. The semiconductor device is a memory LSI having an SRAM.

  A plurality of SRAM cells 200 are arranged in a matrix in the SARM. The SRAM cell 200 includes a storage unit 61, a control transistor 62, and a control transistor 63. The control transistor 62 and the control transistor 63 have the same structure as the MOSFET 90 of the first embodiment and operate in the same manner. Instead, the tunnel MOSFET 100 of the second embodiment may be used.

  The control unit 60 is connected to the bit line BL, the bit line BLb, the word line WL, the word line WLb, the substrate line SL, and the substrate line Slb, and controls signals such as writing, reading, and erasing of the SRAM cell 200. Is generated.

  The storage unit 61 is provided between the node N1 and the node N2, and stores information. The storage unit 61 is provided with an inverter INV1 and an inverter INV2. The inverter INV1 has an input side connected to the node N1 and an output side connected to the node N2. The inverter INV2 has an input side connected to the node N2 and an output side connected to the node N1.

  The control transistor 62 is provided between the bit line BL and the node N1. The control transistor 62 operates at the time of writing, reading, erasing and the like. The first terminal FP1 is connected to the bit line BL. The second terminal SP1 is connected to the node N1. The gate terminal GP1 is connected to the word line WL. Body terminal BP1 is connected to substrate line SL. The control transistor 62 causes a large drain current to flow to the bit line BL side or the node N1 side even when a high resistance component such as a high resistance element or parasitic high resistance is added to the first terminal FP1 or the second terminal SP1 side. be able to. For this reason, the operation characteristics of the control transistor 62 do not deteriorate (the operation margin of the SRAM cell 200 does not decrease).

  The control transistor 63 is provided between the bit line BLb and the node N2. The control transistor 63 operates during writing, reading, erasing and the like. The first terminal FP1 is connected to the bit line BLb. The second terminal SP1 is connected to the node N2. Gate terminal GP1 is connected to word line WLb. Body terminal BP1 is connected to substrate line SLb. The control transistor 63 causes a large drain current to flow to the bit line BLb side or the node N2 side even when a high resistance component such as a high resistance element or parasitic high resistance is added to the first terminal FP1 or the second terminal SP1 side. be able to. Therefore, the operation characteristics of the control transistor 63 do not deteriorate (the operation margin of the SRAM cell 200 does not decrease).

  As described above, in the semiconductor device of this embodiment, the control unit 60 and the SRAM cell 200 are provided. The SRAM cell 200 includes a storage unit 61, a control transistor 62, and a control transistor 63. The control transistor 62 and the control transistor 63 have the same structure as the MOSFET 90 of the first embodiment and operate in the same manner.

  Therefore, even if a high resistance component is added to the bit line BL or the node N1 side and a high resistance component is added to the bit line BLb or the node N2 side, it is possible to suppress a decrease in the operation margin of the SRAM cell 200.

  In the embodiment, the present invention is applied to the MOSFET having the gate electrode film 6, but may be applied to a J-FET (junction FET), MESFET, MOSFET using a carbon nanowire for the gate, or the like. Although the third embodiment is applied to SRAM, it can be applied to MRAM (magnetic random access memory), switches, and the like.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) An undoped SOI substrate, provided on the surface of the undoped SOI substrate, one of a P-type first source and drain, provided on the surface of the undoped SOI substrate, and the other of the first source and drain Provided on the surface of the undoped SOI substrate, provided on the surface of the undoped SOI substrate, and on one of the N-type second source and drain disposed adjacent to one of the first source and drain. The other of the second source and drain disposed adjacent to the other of the source and drain, the one of the first and second source and drain and the other of the first and second source and drain. A gate electrode film provided on the surface of the undoped SOI substrate and provided via a gate insulating film, the first source and drain And the gate electrode film constitutes a Pch FET, and the second source and drain and the gate electrode film constitute an Nch FET.

(Supplementary Note 2) One of the first source and drain and one of the second source and drain are connected to a first terminal, and the other of the first source and drain and the second source and drain are connected. The semiconductor device according to attachment 1, wherein the other is connected to the second terminal.

(Supplementary note 3) The semiconductor device according to supplementary note 1 or 2, wherein the Pch FET and the Nch FET are FIN FETs.

(Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein a channel of the Pch and Nch FET is a silicon channel, a SiGe channel, an InAs channel, or an InGaAs channel.

(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein a plurality of the Pch and Nch FETs are repeatedly arranged.

(Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the gate insulating film is made of SiO2, SiON, HfSiO2, HfSiON, HfO2, HfZrOx, or HfLaOx.

(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein the gate electrode film is made of polycrystalline silicon, amorphous silicon, TiN, TaC, TaN, or WN.

(Supplementary note 8) The semiconductor device according to any one of supplementary notes 1 to 7, wherein the Pch and Nch FETs are planar FETs.

1, 3 Substrate 2 Buried insulating film 4 Shallow trench isolation (STI)
5 Gate insulating film 6 Gate electrode film 7 Insulating film 8 Wiring material 31a, 31b P ⁺ layer 32a, 32b N ⁺ layer 51 SOI substrate 60 Control unit 61 Storage unit 62, 63 Control transistor 90, 91 MOSFET
200 SRAM cell AR1 Active region (element region)
BL, BLb Bit line BP1 Body terminal CH1-3 Contact hole FP1 First terminal GD1 Gate electrode GP1 Gate terminal INV1, Inverter N1, N2 Node SL, SLb Substrate SP1 Second terminal Vd Drain voltage Vdd High potential side power supply Vg Gate voltage Vs Source voltage Vss Low potential side power supply (ground potential)
Vsub substrate voltage WL, WLb word line

Claims (6)

A substrate,
One of a first source and a drain provided on the substrate surface and having a first conductivity type;
The other of the first source and drain provided on the substrate surface and having the first conductivity type;
One of a second source and drain provided on the substrate surface, adjacent to one of the first source and drain and having a second conductivity type;
The other of the second source and drain provided on the substrate surface, adjacent to the other of the first source and drain and having the second conductivity type;
A gate electrode film provided on the substrate surface between one of the first and second sources and drains and the other of the first and second sources and drains, and a gate insulating film;
Wherein the first source and drain and the gate electrode film constitute a first FET, and the second source and drain and the gate electrode film constitute a second FET. Semiconductor device.   The semiconductor device according to claim 1, wherein the first and second FETs are FIN FETs. A substrate,
One of a first source and a drain provided on the substrate surface and having a first conductivity type;
The other of the first source and drain provided on the substrate surface and having a second conductivity type;
One of a second source and drain provided on the substrate surface, adjacent to one of the first source and drain and having a second conductivity type;
The other of the second source and drain provided on the substrate surface, adjacent to the other of the first source and drain and having the first conductivity type;
A gate electrode film provided on the substrate surface between one of the first and second sources and drains and the other of the first and second sources and drains, and a gate insulating film;
And the first source and drain and the gate electrode film constitute a first tunnel FET, and the second source and drain and the gate electrode film constitute a second tunnel FET. Semiconductor device.   4. The semiconductor device according to claim 3, wherein the first and second tunnel FETs are FIN tunnel FETs.   One of the first source and drain and one of the second source and drain are connected to a first terminal, and the other of the first source and drain and the other of the second source and drain are second. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a terminal of the semiconductor device. Forming a protrusion having a quadrangular prism shape, the periphery of which is separated by an element isolation film and protruding from the periphery;
Forming a gate insulating film and a gate electrode film on the protrusion surface; and
A step of ion-implanting a first conductivity type impurity from an oblique direction to one end side of the first and second regions of the protrusion divided by the gate insulating film and the gate electrode film;
A step of ion-implanting a second conductivity type impurity from an oblique direction to the other end side of the first and second regions of the protruding portion divided by the gate insulating film and the gate electrode film;
The first and second conductivity type impurities are activated by heat treatment, and the first semiconductor layer serving as one of the first conductivity type source and drain having a high impurity concentration, the first conductivity type source having a high impurity concentration, and The second semiconductor layer serving as the other of the drain, the third semiconductor layer serving as one of the second conductivity type source and drain having a high impurity concentration, and the other of the source and drain of the second conductivity type having a high impurity concentration. Forming a fourth semiconductor layer;
Etching the insulating film on the first and third semiconductor layers to form a first opening, and etching the insulating film on the second and fourth semiconductor layers to form a second opening. Etching the insulating film on the gate electrode film to form a third opening;
An electrode material is embedded to cover the first opening to form a first terminal connected to the first and third semiconductor layers, and an electrode material is covered to cover the second opening. A gate terminal that is buried and forms a second terminal connected to the second and fourth semiconductor layers, and an electrode material is buried so as to cover the third opening and connected to the gate electrode film Forming a step;
A method for manufacturing a semiconductor device, comprising:

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