JP2012178638A - Current mirror circuit and semiconductor device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current mirror circuit that ensures a wide output voltage range even upon a process variation.SOLUTION: The low voltage cascode current mirror circuit includes N-channel MOS transistors Q1-Q5 and a resistive element 1. An overdrive voltage Vov_Q3 of the transistor Q3 is equal to the sum of overdrive voltages Vov_Q4, Vov_Q5 of the transistors Q4, Q5. The product of a constant current Ic and a resistance value R1 of the resistive element 1 is a saturation margin Vdsm_Q5 of the transistor Q5. Even upon a process variation, the saturation margin Vdsm_Q5 of the transistor Q5 thus remains unchanged.

Description

  The present invention relates to a current mirror circuit and a semiconductor device using the same, and more particularly to a low voltage cascode current mirror circuit and a semiconductor device using the same.

  Conventionally, a cascode current mirror circuit in which two current mirror circuits are vertically stacked is known in order to increase the accuracy of the current mirror circuit. A low-voltage cascode current mirror circuit that can operate even with a low power supply voltage is also known (see Non-Patent Document 1, for example).

“CMOS Analog Circuit Design, Second Edition” Phillip E. Allen, Douglas R. Holberg, OXFORD, p133, fig 4.3-7

  In the conventional low voltage cascode current mirror circuit, the saturation margin of the N channel MOS transistor Q5 of the output circuit is generated by the N channel MOS transistor Q3 of the cascode voltage generation circuit (see FIG. 2). Therefore, when the overdrive voltage of N channel MOS transistor Q3 increases due to process variations, there is a problem that the minimum required voltage of the output voltage increases and the output voltage range becomes narrow.

  Therefore, a main object of the present invention is to provide a current mirror circuit capable of obtaining a wide output voltage range even when there is a process variation, and a semiconductor device using the current mirror circuit.

  In the current mirror circuit according to the present invention, the first transistor and its drain are connected to the source of the first transistor, its source is connected to the reference voltage line, and its gate is connected to the drain of the first transistor. Second transistor, a third transistor whose gate and drain are connected to each other, a first electrode connected to a source of the third transistor, and a second electrode connected to the reference voltage line. A first resistance element connected, a drain connected to the output terminal, a fourth transistor whose gate is connected to the gates of the first and third transistors, and a drain connected to the source of the fourth transistor The gate of which is connected to the gate of the second transistor and the source of which is connected to the reference voltage line. It is obtained by a transistor. The first to fifth transistors are transistors of the same conductivity type. The source of the second transistor, the second electrode of the first resistance element, and the source of the fifth transistor have the same voltage.

  In the current mirror circuit according to the present invention, since the saturation margin of the fifth transistor is determined by the resistance value of the first resistance element, the saturation margin of the fifth transistor does not change even when there is a process variation. Therefore, a wide output voltage range can be obtained even when there is a process variation.

It is a circuit diagram which shows the structure of the low voltage cascode current mirror circuit by Embodiment 1 of this invention. FIG. 3 is a circuit diagram showing a comparative example of the first embodiment. It is a circuit diagram which shows the structure of the low voltage cascode current mirror circuit by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the low voltage cascode current mirror circuit by Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the low voltage cascode current mirror circuit by Embodiment 4 of this invention. It is a circuit block diagram which shows the structure of the semiconductor device by Embodiment 5 of this invention. FIG. 7 is a circuit diagram showing a configuration of a constant current generating circuit shown in FIG. 6. It is a circuit diagram which shows the structure of the differential amplifier circuit by Embodiment 6 of this invention. It is a figure which shows the layout of the low voltage cascode current mirror circuit 22 shown in FIG.

[Embodiment 1]
The low voltage cascode current mirror circuit according to the first embodiment of the present invention includes N channel MOS transistors Q1 to Q5 and a resistance element 1, as shown in FIG. The drain of N channel MOS transistor Q1 receives a constant current Ic from a constant current source (not shown). N channel MOS transistor Q2 has its drain connected to the source of N channel MOS transistor Q1, its gate connected to the drain of N channel MOS transistor Q1, and its source connected to the ground voltage VSS line. N channel MOS transistors Q1 and Q2 constitute an input circuit.

  The drain of N channel MOS transistor Q3 receives a constant current Ic from another constant current source (not shown), and its gate is connected to its drain and to the gate of N channel MOS transistor Q1. The first electrode of resistance element 1 is connected to the source of N-channel MOS transistor Q3, and the second electrode is connected to the line of ground voltage VSS. N channel MOS transistor Q3 and resistance element 1 form a cascode voltage generation circuit. The resistance element 1 may be formed of polysilicon, or may be formed by diffusing impurities in a silicon substrate.

  N channel MOS transistors Q4 and Q5 constitute an output circuit. N channel MOS transistor Q4 has its drain connected to output terminal TO and a current source (not shown), and its gate connected to the gates of N channel MOS transistors Q1 and Q3. N channel MOS transistor Q5 has its drain connected to the source of N channel MOS transistor Q4, its gate connected to the gate of N channel MOS transistor Q2, and its source connected to the ground voltage VSS line. Therefore, the same voltage VSS is applied to the sources of N channel MOS transistors Q 2 and Q 5 and the second electrode of resistance element 1.

  N channel MOS transistors Q1, Q3, Q4 have their gates connected to each other, and N channel MOS transistors Q2, Q5 have their gates connected to each other. Therefore, when constant current Ic flows through N channel MOS transistors Q1, Q2 and Q3, a current having a value corresponding to constant current Ic flows through N channel MOS transistors Q4 and Q5. When the size of N channel MOS transistors Q4 and Q5 is A times the size of N channel MOS transistors Q1 and Q2 (where A is a positive real number), N channel MOS transistors Q4 and Q5 have a constant current Ic. A constant current A × Ic having a value A times the current flows. However, the size of the MOS transistor refers to the ratio of the channel width to the channel length (distance between the drain and source) of the MOS transistor, that is, the value of W / L. Here, W is the channel length, and L is the channel length.

  Further, the minimum required voltage VOmin of the output voltage VO is VOmin = Vov_Q4 + Vov_Q5 + Vdsm_Q4 + Vdsm_Q5, and a low power supply voltage operation becomes possible. Here, Vov is the overdrive voltage of the transistor, and Vdsm is the saturation margin Vdsm of the transistor. Further, the gate-source voltage Vgs of the transistor is the sum Vth + Vov of the threshold voltage Vth of the transistor and the overdrive voltage Vov. The transistor saturation margin Vdsm is the difference Vds−Vov between the drain-source voltage Vds of the transistor and the overdrive voltage Vov. Vov_Q4 and Vov_Q5 are overdrive voltages of N-channel MOS transistors Q4 and Q5, respectively, and Vdsm_Q4 and Vdsm_Q5 are saturation margins of N-channel MOS transistors Q4 and Q5, respectively.

  Next, the effect of this low voltage cascode current mirror circuit will be described. The voltage V1 at the source of N channel MOS transistor Q3 is the product Ic × R1 of constant current Ic and resistance value R1 of resistance element 1. The gate-source voltage Vgs_Q3 of the N-channel MOS transistor Q3 is a sum Vth_Q3 + Vov_Q3 of the threshold voltage Vth_Q3 and the overdrive voltage Vov_Q3. The gate-source voltage Vgs_Q4 of the N channel MOS transistor Q4 is the sum Vth_Q4 + Vov_Q4 of the threshold voltage Vth_Q4 and the overdrive voltage Vov_Q4.

  Since N channel MOS transistors Q3 and Q4 are of the same type, threshold voltage Vth_Q3 of N channel MOS transistor Q3 and threshold voltage Vth_Q4 of N channel MOS transistor Q4 are substantially equal.

Therefore, source voltage V2 of N channel MOS transistor Q4 is expressed by the following equation (1).
V2 = V1 + Vgs_Q3-Vgs_Q4
= Ic * R1 + Vov_Q3-Vov_Q4 (1)
On the other hand, the drain-source voltage Vds_Q5 of the N channel MOS transistor Q5 is Vov_Q5 + Vdsm_Q5 = V2. Substituting this into equation (1) yields equation (2) below.
Vdsm_Q5 = Vov_Q3-Vov_Q4-Vov_Q5 + Ic × R1 (2)
Here, if the current flowing through the transistor is I, the overdrive voltage Vov of the transistor is Vov = [2I / a (W / L)] ^1/2 . Here, a is a constant determined by the process. Due to process variations, a changes. Accordingly, the transistor overdrive voltage Vov can be adjusted by adjusting the W / L of the transistor.

Therefore, the W / W of N channel MOS transistor Q3 is such that overdrive voltage Vov_Q3 of N channel MOS transistor Q3 is the sum of overdrive voltage Vov_Q4 of N channel MOS transistor Q4 and overdrive voltage Vov_Q5 of N channel MOS transistor Q5. Adjust L. Thereby, Vov_Q3-Vov_Q4-Vov_Q5 of Formula (2) becomes 0, and the following Formula (3) is obtained.
Vdsm_Q5 = Ic × R1 (3)
Ic × R1 is a voltage drop caused by the constant current Ic flowing through the resistance element 1, and is independent of process variations. Therefore, the saturation margin Vds_Q5 of the N-channel MOS transistor Q5 becomes independent of process variation.

  FIG. 2 is a circuit diagram showing a configuration of a low-voltage cascode current mirror circuit as a comparative example of the first embodiment, and is a diagram to be compared with FIG. Referring to FIG. 2, this low voltage cascode current mirror circuit is different from the low voltage cascode current mirror circuit of FIG. 1 in that resistance element 1 is removed and the source of N-channel MOS transistor Q3 is connected to the ground voltage VSS line. It is a connected point.

  In this comparative example, the W / L of N channel MOS transistor Q3 is adjusted to 1/4 or less of the W / L of N channel MOS transistor Q4. Thus, the minimum required voltage VOmin of the output voltage VO is VOmin = Vov_Q4 + Vov_Q5 + Vdsm_Q4 + Vdsm_Q5, and a low power supply voltage operation is possible.

In this comparative example, the source voltage V2 of the N channel MOS transistor Q4 is expressed by the following equation (4).
V2 = Vgs_Q3-Vgs_Q4 = Vov_Q3-Vov_Q4 (4)
On the other hand, the source-drain voltage Vds_Q5 of the N-channel MOS transistor Q5 is Vov_Q5 + Vdsm_Q5 = V2. Substituting this into equation (4) yields equation (5) below.
Vdsm_Q5 = Vov_Q3-Vov_Q4-Vov_Q5 (5)
Therefore, saturation margin Vdsm_Q5 of N channel MOS transistor Q5 depends on overdrive voltage Vov_Q3 of N channel MOS transistor Q3. For this reason, when Vov_Q3 increases due to process variations, Vdsm_Q5 also increases excessively, the minimum required voltage VOmin increases, and a wide output voltage range cannot be obtained.

  On the other hand, in the present invention, as shown in the equation (3), the saturation margin Vdsm_Q5 of the N-channel MOS transistor Q5 is Ic × R1, which is irrelevant to the process variation. Therefore, the minimum voltage VOmin required for the drain of N channel MOS transistor Q4 can be reduced and the output voltage range can be widened.

  In the first embodiment, Vov_Q3 = Vov_Q4 + Vov_Q5. However, in order to operate the N-channel MOS transistor Q5 in the saturation region, it is essential to satisfy V2> Vov_Q5. Therefore, Vov_Q3 is slightly larger than Vov_Q4 + Vov_Q5. May be.

[Embodiment 2]
The low voltage cascode current mirror circuit according to the second embodiment of the present invention includes P channel MOS transistors P1 to P5 and a resistance element 2, as shown in FIG. The source of the P-channel MOS transistor P1 is connected to the power supply voltage VDD line. The source of P channel MOS transistor P2 is connected to the drain of P channel MOS transistor P1, its drain is connected to the gate of P channel MOS transistor P1, and
It is connected to a constant current source (not shown) that discharges the constant current Ic. P channel MOS transistors P1 and P2 form an input circuit.

  The first electrode of the resistance element 2 is connected to the line of the power supply voltage VDD. The source of P-channel MOS transistor P3 is connected to the second electrode of resistance element 2, its gate is connected to the gate of P-channel MOS transistor P2, its drain is connected to its gate, and constant current Ic flows out. Connected to another constant current source (not shown). Resistance element 2 and P-channel MOS transistor P3 form a cascode voltage generation circuit. The resistance element 2 may be formed of polysilicon, or may be formed by diffusing impurities in a silicon substrate.

  The source of P channel MOS transistor P4 is connected to the line of power supply voltage VDD, and its gate is connected to the gate of P channel MOS transistor P1. Therefore, the same voltage VDD is applied to the sources of P channel MOS transistors P 1 and P 4 and the first electrode of resistance element 2. The source of P-channel MOS transistor P5 is connected to the drain of P-channel MOS transistor P4, its gate is connected to the gates of P-channel MOS transistors P2 and P3, its drain is connected to output terminal TO, and current flows out. Connected to a current source (not shown).

  The gates of P channel MOS transistors P1, P4 are connected to each other, and the gates of P channel MOS transistors P2, P3, P5 are connected to each other. Therefore, when a constant current Ic is passed through the transistors P1, P2, P3, a current having a value corresponding to the constant current Ic flows through the transistors P4, P5. When the sizes of the transistors P4 and P5 are respectively A times the size of the transistors P1 and P2 (where A is a positive real number), the transistors P4 and P5 have a constant current A that is A times the constant current Ic. XIc flows.

  In addition, the minimum required voltage of VDD−VO is | Vov_P4 + Vov_P5 + Vdsm_QP + Vdsm_P5 |, and a low power supply voltage operation is possible. Note that | Vov_P4 + Vov_P5 + Vdsm_QP + Vdsm_P5 | is the absolute value of Vov_P4 + Vov_P5 + Vdsm_QP + Vdsm_P5. In the P channel MOS transistor, Vth, Vov and Vdsm are all negative voltages.

  Next, the effect of this low voltage cascode current mirror circuit will be described. The source voltage V3 of the P-channel MOS transistor P3 is lower than the power supply voltage VDD by the product Ic × R2 of the constant current Ic and the resistance value R1 of the resistance element 2, and V3 = VDD−Ic × R2. The gate-source voltage Vgs_P3 of the P-channel MOS transistor P3 is the sum Vth_P3 + Vov_P3 of the threshold voltage Vth_P3 and the overdrive voltage Vov_P3. The gate-source voltage Vgs_P5 of the P-channel MOS transistor P5 is the sum Vth_P5 + Vov_P5 of the threshold voltage Vth_P5 and the overdrive voltage Vov_P5.

  Since P channel MOS transistors P3 and P5 are of the same type, threshold voltage Vth_P3 of P channel MOS transistor P3 and threshold voltage Vth_P5 of P channel MOS transistor P5 are substantially equal.

Therefore, source voltage V4 of P channel MOS transistor P5 is expressed by the following equation (6).
V4 = V3 + Vgs_P3-Vgs_P5
= VDD-Ic * R2 + Vov_P3-Vov_P5 (6)
On the other hand, the drain voltage of the P-channel MOS transistor P4 is VDD + Vov_P4 + Vdsm_P4 = V4. Substituting this into equation (6) yields equation (7) below.
Vdsm_P4 = Vov_P3-Vov_P4-Vov_P5-Ic × R2 (7)
Here, the size of the P channel MOS transistor P3 is such that the overdrive voltage Vov_QP of the P channel MOS transistor P3 is the sum of the overdrive voltage Vov_P4 of the P channel MOS transistor P4 and the overdrive voltage Vov_P5 of the P channel MOS transistor P5. Adjust. As a result, Vov_P3-Vov_P4-Vov_P5 in Expression (7) becomes 0, and the following Expression (8) is obtained.
Vdsm_P4 = −Ic × R2 (8)
Ic × R2 is a voltage drop caused by the constant current Ic flowing through the resistance element 2, and is independent of process variations. Therefore, the saturation margin Vdsm_P4 of the N-channel MOS transistor P4 becomes independent of process variation. Therefore, the maximum voltage VOmax required for the drain of the P-channel MOS transistor P5 can be increased and the output voltage range can be widened.

  In the second embodiment, Vov_P3 = Vov_P4 + Vov_P5. However, in order to operate the P-channel MOS transistor P4 in the saturation region, it is indispensable to satisfy VDD−V4> | Vov_P4 |. Therefore, | Vov_P3 | It may be slightly larger than | Vov_P4 + Vov_P5 |.

[Embodiment 3]
FIG. 4 is a circuit diagram showing a configuration of a low-voltage cascode current mirror circuit according to the third embodiment of the present invention, which is compared with FIG. Referring to FIG. 4, this low voltage cascode current mirror circuit is different from the low voltage cascode current mirror circuit of FIG. 1 in that an N channel MOS transistor Q6 is added. N channel MOS transistor Q6 has its drain connected to the source of N channel MOS transistor Q3, its gate connected to the gates of N channel MOS transistors Q1, Q3, and Q4, and its source connected to the first electrode of resistance element 1. Is done.

  In this low voltage cascode current mirror circuit, the W / L of N channel MOS transistor Q3 is set to the same value as the W / L of N channel MOS transistors Q1 and Q4. N-channel MOS transistor Q6 is a transistor that operates in a linear region, and operates in the same manner as a resistance element. The N-channel MOS transistor Q6 has a drain-source voltage Vds_Q6 generated by the constant current Ic flowing through the N-channel MOS transistor Q6 equal to the overdrive voltage Vov_Q5 of the N-channel MOS transistor Q5. Adjust the size. In other words, the size of the N channel MOS transistor Q6 is adjusted so that the product (voltage drop) of the constant current Ic and the conduction resistance value of the N channel MOS transistor Q6 is equal to the overdrive voltage Vov_Q5 of the N channel MOS transistor Q5. .

In this case, drain voltage V2 of N channel MOS transistor Q4 is expressed by the following equation (9).
V2 = V1 + Vds_Q6 + Vgs_Q3-Vgs_Q4
= Ic * R1 + Vov_Q5 (9)
On the other hand, the drain-source voltage Vds_Q5 of the N channel MOS transistor Q5 is Vov_Q5 + Vdsm_Q5 = V2. Substituting this into equation (9) yields equation (10) below.
Vdsm_Q5 = Ic × R1 (10)
Therefore, the saturation margin Vdsm_Q5 of the N channel MOS transistor Q5 becomes constant regardless of the process variation. Since N channel MOS transistors Q6 and Q5 are of the same type, the drain-source voltages Vds of N channel MOS transistors Q6 and Q5 are always equal to each other even if there is a process variation. On the other hand, mismatch is reduced by making N-channel MOS transistors Q3 and Q4 the same transistor. For these reasons, the third embodiment can obtain the same effect as the first embodiment with high accuracy.

  In the third embodiment, the size of N channel MOS transistor Q6 is adjusted so that the product of constant current Ic and the conduction resistance value of N channel MOS transistor Q6 is equal to Vov_Q5. However, in order to operate N channel MOS transistor Q5 in the saturation region, it is essential to satisfy V2> Vov_Q5. Therefore, the product of constant current Ic and the conduction resistance value of N channel MOS transistor Q6 is slightly larger than Vov_Q5. Thus, the size of the N channel MOS transistor Q6 may be adjusted.

[Embodiment 4]
FIG. 5 is a circuit diagram showing a configuration of a low-voltage cascode current mirror circuit according to Embodiment 4 of the present invention, and is a diagram to be compared with FIG. Referring to FIG. 5, the low voltage cascode current mirror circuit is different from the low voltage cascode current mirror circuit of FIG. 3 in that a P channel MOS transistor P6 is added. The source of P channel MOS transistor P6 is connected to the second electrode of resistance element 2, its drain is connected to the source of P channel MOS transistor P3, and its gate is connected to the gates of P channel MOS transistors P2, Q3 and P5. Is done.

  In this low voltage cascode current mirror circuit, the W / L of the P channel MOS transistor P3 is set to the same value as the W / L of the P channel MOS transistors P2 and P5. The P-channel MOS transistor P6 is a transistor that operates in a linear region, and operates in the same manner as a resistance element. The P-channel MOS transistor P6 has a drain-source voltage Vds_P6 generated by the constant current Ic flowing through the P-channel MOS transistor P6 equal to the overdrive voltage Vov_P4 of the P-channel MOS transistor P4. Adjust the size. In other words, the size of the P channel MOS transistor P6 is such that the product (voltage drop) of the constant current Ic and the conduction resistance value of the P channel MOS transistor P6 is equal to the absolute value of the overdrive voltage Vov_P4 of the P channel MOS transistor P4. Adjust.

In this case, the source voltage V4 of the P channel MOS transistor P4 is expressed by the following equation (11).
V4 = V3 + Vds_P6 + Vgs_P3-Vgs_P5
= VDD-Ic * R2 + Vov_P4 (11)
On the other hand, the drain-source voltage Vds_P4 of the P-channel MOS transistor P4 is VDD + Vov_P4 + Vdsm_P4 = V4. Substituting this into equation (11) yields equation (12) below.
Vdsm_P4 = −Ic × R2 (12)
Therefore, the saturation margin Vdsm_P4 of the P-channel MOS transistor P4 becomes constant regardless of process variations. Since N channel MOS transistors P6 and P4 are of the same type, drain-source voltages Vds of P channel MOS transistors P6 and P4 are always equal to each other even if there is a process variation. On the other hand, mismatch is reduced by making P-channel MOS transistors P3 and P5 the same transistor. For these reasons, the fourth embodiment can obtain the same effect as the second embodiment with high accuracy.

  In the fourth embodiment, the size of P-channel MOS transistor P6 is adjusted so that the product of constant current Ic and the conduction resistance value of P-channel MOS transistor P6 is equal to | Vov_P4 |. However, in order to operate the P-channel MOS transistor P4 in the saturation region, it is essential to satisfy VDD−V4> | Vov_P4 |. Therefore, the product of the constant current Ic and the conduction resistance value of the P-channel MOS transistor P6 is | The size of the P-channel MOS transistor P6 may be adjusted to be slightly larger than Vov_P4 |.

[Embodiment 5]
As shown in FIG. 6, the semiconductor device according to the fifth embodiment of the present invention includes a constant current generating circuit 10 and the low voltage cascode current mirror circuit shown in FIG. Constant current generating circuit 10 supplies constant current Ic to N channel MOS transistors Q1 and Q2, and also supplies constant current Ic to N channel MOS transistors Q3 and Q6 and resistance element 1.

  As shown in FIG. 7, constant current generating circuit 10 includes an operational amplifier 11, a resistance element 12, and P channel MOS transistors P11 to P16. P-channel MOS transistors P11 and P12 and resistance element 12 are connected in series between a line of power supply voltage VDD and a line of ground voltage VSS. P channel MOS transistors P13 and P14 are connected in series between the line of power supply voltage VDD and the drain of N channel MOS transistor Q1. P channel MOS transistors P15 and P16 are connected in series between the line of power supply voltage VDD and the drain of N channel MOS transistor Q3. The transistors P11, P13, and P15 are the same size, and the transistors P12, P14, and P16 are the same size.

  The non-inverting input terminal (+ terminal) of the operational amplifier 11 receives the reference voltage VR, its non-inverting input terminal (− terminal) is connected to the drain (node N12) of the P channel MOS transistor P12, and its output terminal is the P channel. Connected to MOS transistors P11, P13, P15. The gates of P channel MOS transistors P12, P14 and P16 receive bias voltage Vbp. P-channel MOS transistors P12, P14, and P16 operate in the saturation region and pass the same value of current.

  The operational amplifier 11 controls the gate voltages of the P-channel MOS transistors P11, P13, and P15 so that the voltage V12 of the node N12 matches the reference voltage VR. When the resistance value of the resistance element 12 is R12 and the current flowing through the resistance element 12 is Ic, V12 = Ic × R12 = VR. Therefore, Ic = VR / R12, and the constant current Ic is inversely proportional to the resistance value R12 of the resistance element 12.

  In the fifth embodiment, the constant current Ic decreases when the resistance value of the resistance elements 1 and 12 increases due to process variation, and the constant current Ic increases when the resistance value of the resistance elements 1 and 12 decreases. Therefore, the interelectrode voltage V1 of the resistance element 1, that is, the saturation margin Vdsm_Q5 of the P-channel MOS transistor Q5 can be made independent of process variations, and a wider output voltage range can be taken.

[Embodiment 6]
As shown in FIG. 8, the differential amplifier circuit according to the sixth embodiment of the present invention includes a constant current generating circuit 20, low voltage cascode current mirror circuits 21, 22, and P channel MOS transistors P27, P28. The constant current generation circuit 20 is obtained by removing the P channel MOS transistors P15 and P16 from the constant current generation circuit 10 shown in FIG. 7, and generates a constant current Ic having a value inversely proportional to the resistance value R12 of the resistance element 12. .

  The constant voltage cascode current mirror circuit 21 is obtained by adding P channel MOS transistors P21 to P26 to the constant voltage cascode current mirror circuit shown in FIG. The constant voltage cascode current mirror circuit 22 is obtained by adding N-channel MOS transistors P21 to P26 to the constant voltage cascode current mirror circuit shown in FIG.

  P channel MOS transistors P13 and P14 are connected in series between the line of power supply voltage VDD and the drain of N channel MOS transistor Q1. P-channel MOS transistors P21 and P22 are connected in series between the line of power supply voltage VDD and the drain of N-channel MOS transistor Q3.

  N channel MOS transistors Q21 and Q22 are connected in series between the drain of P channel MOS transistor P3 and the line of ground voltage VSS. N channel MOS transistors Q23 and Q24 are connected in series between the drain of P channel MOS transistor P2 and the line of ground voltage VSS.

  The drain of P-channel MOS transistor P5 and the drain of N-channel MOS transistor Q4 are commonly connected to output terminal TOP. P-channel MOS transistors P23 and P24 are connected in series between the line of power supply voltage VDD and output terminal TON. N-channel MOS transistors Q25 and Q26 are connected in series between output terminal TON and the ground voltage VSS line. P-channel MOS transistors P25 and P26 are connected in series between a line of power supply voltage VDD and node N26.

  The gates of P channel MOS transistors P21, P1, P4, P23, and P25 are connected to each other. The gates of P-channel MOS transistors P22, P3, P6, P2, P5, P24, and P26 are connected to each other. N channel MOS transistors Q1, Q3, Q6, Q21, Q23, Q4, Q25 have their gates connected to each other. The gates of N channel MOS transistors Q2, Q22, Q24, Q5 and Q26 are connected to each other. Therefore, a constant current Ic flows through each of the transistors P and Q of the low voltage cascode current mirror circuits 21 and 22.

  The transistors P1 and P21 are the same size. The size of the output transistors P4 and P23 may be the same as the size of the transistor P1, but it is A times larger than the size of the transistor P1 (A is a positive real number, preferably an integer of 2 or more), and the transistor P4 , P23 may be set to A times the current flowing in the transistors P1 and P21.

  Transistors P2, P3, and P22 are the same size. The size of the output transistors P5 and P24 may be the same as the size of the transistor P2, but it is A times the size of the transistor P2, and the current flowing through the transistors P5 and P24 is A times the current flowing through the transistors P2, P3 and P22. It may be.

  Transistors Q1, Q3, Q21, and Q23 are the same size. The size of the output transistors Q4 and Q25 may be the same as the size of the transistor Q1, but the size of the transistor Q1 is set to A times the current flowing in the transistors Q1, Q3, Q21, and Q23. You may make it A times.

  Transistors Q2, Q22, and Q24 are the same size. The size of the output transistors Q5 and Q26 may be the same as the size of the transistor Q2, but the size of the transistor Q2 is set to A times, and the current flowing through the transistors Q5 and Q26 is A times the current flowing through the transistors Q2, Q22 and Q24. It may be.

  P channel MOS transistor P27 has its source connected to node N26, its gate connected to input terminal TIN, and its drain connected to the drain of N channel MOS transistor Q5. P channel MOS transistor P28 has its source connected to node N26, its gate connected to input terminal TIP, and its drain connected to the drain of N channel MOS transistor Q26. Input voltages VIN and VIP are applied to the input terminals TIN and TIP, respectively.

  When the input voltage VIN is lower than the input voltage VIP, the current flowing through the P-channel MOS transistor P27 is larger than the current flowing through the P-channel MOS transistor P28, and the voltage VOP at the output terminal TOP is higher than the voltage VON at the output terminal TON. Get higher. Conversely, when the input voltage VIN is higher than the input voltage VIP, the current flowing through the P-channel MOS transistor P28 is larger than the current flowing through the P-channel MOS transistor P27, and the voltage VON at the output terminal TON becomes the voltage at the output terminal TOP. It becomes higher than VOP.

In the sixth embodiment, the same effect as in the third to fifth embodiments can be obtained.
FIG. 9 is a diagram showing a layout of the low voltage cascode current mirror circuit 22. A resistance element 1 extending in the left-right direction (X direction) is disposed in the upper part in FIG. The resistance element 1 is composed of a polysilicon layer having a predetermined dimension formed on the surface of a silicon substrate. Resistance value R1 of resistance element 1 is set so that Ic × R1 becomes saturation margin Vdsm_Q5 of N-channel MOS transistor Q5. The left end portion (second electrode) of the resistance element 1 is connected to the line of the ground voltage VSS.

  9, N channel MOS transistors Q4, Q23, Q1, Q6, Q3, Q21, and Q25 are arranged in the X direction in order from the left side. Eighteen gate electrodes g are formed at a predetermined pitch on the surface of the P-type well. Each gate electrode g is formed of a polysilicon layer and extends in the vertical direction (Y direction). The lengths in the Y direction of the 18 gate electrodes g are the same. The width in the X direction of the gate electrode g for the N channel MOS transistor Q6 is wider than the width in the X direction of the other 17 gate electrodes g. A band-like N-type impurity diffusion region 30 is formed using the central portion of the 18 gate electrodes g as a mask.

  Each of N-channel MOS transistors Q4, Q23, Q1, Q3, Q21, and Q25 includes two adjacent gate electrodes g, a drain d between the two gate electrodes g, and the two gate electrodes. and source s on both sides of g. The sources on both sides are connected to each other by wiring.

  In each of N channel MOS transistors Q 4, Q 23, Q 1, Q 3, Q 21, Q 25, the width of gate electrode g in the X direction is channel length L, and it is covered with gate electrode g in N type impurity diffusion region 30. The channel width W is twice the length of the portion in the Y direction (twice the width of the N-type impurity diffusion region 30 in the Y direction). W / L of N channel MOS transistor Q3 is set to the same value as W / L of N channel MOS transistors Q1 and Q4.

  Three gate electrodes g between N channel MOS transistors Q4, Q23, Q1, and Q6 are all connected to a line of ground voltage VSS. N channel MOS transistors Q4, Q23, Q1 and Q6 are electrically isolated by these three gate electrodes g. Two gate electrodes g between N channel MOS transistors Q3, Q21, and Q25 are both connected to a ground voltage VSS line. By these two gate electrodes g, N channel MOS transistors Q3, Q21, Q25 are electrically isolated.

  The drains of N channel MOS transistors Q4, Q23, Q1, Q3, Q21, and Q25 are connected to the drains of P channel MOS transistors P5, P2, P14, P22, P3, and P24, respectively.

  N-channel MOS transistor Q6 includes one gate electrode g, a source s on the left side of the gate electrode g, and a drain d on the right side of the gate electrode g. The source of N-channel MOS transistor Q6 is connected to the right end (first electrode) of resistance element 1 by wiring. In the N-channel MOS transistor Q6, the width in the X direction of the gate electrode g becomes the channel length L, and the length in the Y direction of the portion covered with the gate electrode g in the N-type impurity diffusion region 30 (N-type impurity diffusion). The width of the region 30 in the Y direction) is the channel width W.

  N-channel MOS transistor Q6 is a transistor that operates in a linear region, and operates in the same manner as a resistance element. The N-channel MOS transistor Q6 has a drain-source voltage Vds_Q6 generated by the constant current Ic flowing through the N-channel MOS transistor Q6 equal to the overdrive voltage Vov_Q5 of the N-channel MOS transistor Q5. The size has been adjusted.

  Gate electrodes g of N-channel MOS transistors Q4, Q23, Q1, Q6, Q3, Q21, and Q25 are connected to each other by wiring.

  In the lower part of FIG. 9, N channel MOS transistors Q5, Q24, Q2, Q22, Q26 are arranged in the X direction in order from the left side. Ten gate electrodes g are formed at a predetermined pitch on the surface of the P-type well. Each gate electrode g is formed of a polysilicon layer and extends in the vertical direction (Y direction). The lengths of the ten gate electrodes g in the Y direction are the same. The widths in the X direction of the ten gate electrodes g are the same. A belt-like N-type impurity diffusion region 31 is formed using the central portion of the ten gate electrodes g as a mask.

  Each of N-channel MOS transistors Q5, Q24, Q2, Q22, and Q26 includes two adjacent gate electrodes g, a drain d between the two gate electrodes g, and the two gate electrodes g. And the source s on both sides.

  In each of N channel MOS transistors Q5, Q24, Q2, Q22, and Q26, the width of the gate electrode g in the X direction is the channel length L, and the portion of the N-type impurity diffusion region 30 that is covered with the gate electrode g. The channel width W is twice the length in the Y direction (twice the width in the Y direction of the N-type impurity diffusion region 30). N / channel MOS transistors Q5, Q24, Q2, Q22, and Q26 have the same W / L.

  The drains d of N channel MOS transistors Q5, Q24, Q2, Q22 and Q26 are connected to N channel MOS transistors Q4, Q23, Q1, Q21 and Q25, respectively. Gate electrodes g of N channel MOS transistors Q5, Q24, Q2, Q22, and Q26 are connected to each other and to the source of N channel MOS transistor Q1. The sources of N-channel MOS transistors Q5, Q24, Q2, Q22, and Q26 are all connected to the ground voltage VSS line.

  In the sixth embodiment, P channel MOS transistors P27 and P28 are used as input transistors, but N channel MOS transistors may be used as input transistors. Further, the differential amplifier circuit of the sixth embodiment can be applied to a sample hold circuit, an integration circuit, a PGA (Programmable Gain Amplifier), and the like.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 2, 12 Resistance element, Q N channel MOS transistor, TO output terminal, P P channel MOS transistor, 10, 20 Constant current generation circuit, 21, 22 Low voltage cascode current mirror circuit, 30, 31 N-type impurity diffusion region .

Claims (8)

A first transistor;
A second transistor having its drain connected to the source of the first transistor, its source connected to a reference voltage line, and its gate connected to the drain of the first transistor;
A third transistor whose gate and drain are connected to each other;
A first resistive element having a first electrode connected to a source of the third transistor and a second electrode connected to the reference voltage line;
A fourth transistor having its drain connected to the output terminal and its gate connected to the gates of the first and third transistors;
A fifth transistor having a drain connected to the source of the fourth transistor, a gate connected to the gate of the second transistor, and a source connected to the reference voltage line;
The first to fifth transistors are transistors of the same conductivity type,
A current mirror circuit in which the source of the second transistor, the second electrode of the first resistance element, and the source of the fifth transistor have the same voltage.   2. The current mirror circuit according to claim 1, wherein an overdrive voltage of the third transistor is substantially equal to a sum of overdrive voltages of the fourth and fifth transistors. And a sixth transistor interposed between the source of the third transistor and the first electrode of the first resistance element, the gate of which is connected to the gate of the third transistor. ,
The current mirror circuit according to claim 1, wherein the sixth transistor is a transistor having the same conductivity type as the first to fifth transistors. The overdrive voltage of the third transistor is substantially equal to the overdrive voltage of the fourth transistor;
The product of the conduction resistance value of the sixth transistor and the value of the current flowing between the drain and source of the sixth transistor is substantially equal to the overdrive voltage of the fifth transistor. Current mirror circuit. A current mirror circuit according to any one of claims 1 to 4,
A constant current generator including a second resistance element, generating a constant current whose current value is inversely proportional to the resistance value of the second resistance element, and applying the constant current to each drain of the first and third transistors; A semiconductor device comprising a current generation circuit. A current mirror circuit according to any one of claims 1 to 4,
One of the electrodes includes a second resistance element that receives the same voltage as the second electrode of the first resistance element, and a value obtained by dividing the reference voltage by the resistance value of the second resistance element. A semiconductor device comprising: a constant current generating circuit that generates a constant current and applies the constant current to each drain of the first and third transistors. A current mirror circuit according to any one of claims 1 to 4,
A seventh transistor connected between the drain of the first transistor and a power supply voltage line;
An eighth transistor connected between the drain of the third transistor and the power supply voltage line;
Each of the seventh and eighth transistors is a transistor having a different conductivity type from the first to fifth transistors,
The semiconductor device, wherein the reference voltage is a ground voltage. A current mirror circuit according to any one of claims 1 to 4,
A seventh transistor connected between the drain of the first transistor and a ground voltage line;
An eighth transistor connected between the drain of the third transistor and the ground voltage line;
Each of the seventh and eighth transistors is a transistor having a different conductivity type from the first to fifth transistors,
The semiconductor device, wherein the reference voltage is a power supply voltage.

Images