JP2012177965A - Memory control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system capable of providing high access performance to an access device of any number, subjecting high efficiency control to an arbitrary memory configuration, and further performing a flexible configuration while guaranteeing consistency.SOLUTION: A memory control device mounts caches of the same number or integral multiple of a memory bank such as SDRAM, distributes an access of a master to the caches concurrently and simultaneously by a bus matrix, and schedules a cache access optimum for the memory bank to control the cache access.

Description

  The present invention relates to a memory control device for realizing high-performance and high-efficiency memory access even when there are a large number of devices accessing the memory.

  Many processing devices, such as image processing and analysis, require large capacity and high performance memory for increasing resolution and real-time processing. Usually, an inexpensive and large-capacity SDRAM (Synchronous Dynamic RAM) is used, and high performance is often achieved by optimally controlling them. For example, the performance can be improved by using a plurality of SDRAMs having a high operating frequency or by parallelizing processing devices. Therefore, the system is optimized each time according to the operating frequency and the number of SDRAMs and the number of processing devices. Therefore, there is a need for a memory control device that can flexibly and quickly optimize a system.

  Japanese Patent Laid-Open No. 10-326225 discloses a memory control device that can flexibly optimize such a system. This will be described with reference to FIG.

  In FIG. 20, 11 to 16 are masters that are arbitrary control devices, 21 is a bus that bundles the accesses of the masters 11 to 16, 31 to 37 is a cache that temporarily stores data, and 41 is a bus that bundles accesses of the caches 31 to 37. , 51 and 52 are access control devices for controlling memory access, 61 and 62 are memories, 301 is a buffer for bypassing the bus 21 and bus 41, and 302 is a cache control device for managing addresses of the caches 31 to 37. It is. Here, reference numeral 100 denotes a memory control device including the bus 21, the caches 31 to 37, the bus 41, and the access control devices 51 and 52.

  The masters 11 to 16 access the memory 61 and the memory 62, and the access path is first to the bus 21, then to one of the caches 31 to 37, and then to either of the access control devices 51 or 52. Finally, the bus 41 is reached. In addition, in particular, instead of the caches 31 to 37, the buffer 301 may be used. The cache controller 302 manages whether to select the caches 31 to 37 or the bypass buffer 301.

  Management numbers are assigned to the caches 31 to 37, respectively, and the masters 11 to 16 transmit these numbers to the cache control device 302. Specify the number directly, or specify it indirectly by converting it with a table. Therefore, these are the selection numbers of the caches 31 to 37. On the other hand, the bypass buffer 301 is used when reading or writing directly to the memories 61 and 62 without accessing any cache. Of course, it is also used when it is desired to return data to the master or memory through the bypass buffer 301 at the same time as reading or writing to the cache.

  The access control devices 51 and 52 connected to the memories 61 and 62 are distributed according to the address information recorded in the caches 31 to 37. This address information is given each time the master accesses. When the bypass buffer 301 is used, address information issued by the master is directly used.

  Since the bus 21 and the bus 41 can be activated at the same time, one of the masters 11 to 16 accesses one of the caches 31 to 37, and one of the caches 31 to 37 accesses the access control devices 51 and 52. Sometimes it can be done at the same time.

  As described above, the conventional memory control device can select an arbitrary cache directly or indirectly from the master. Depending on the situation of the system, it is possible to allocate a large amount of cache to some masters, and to achieve high performance efficiently with a limited cache capacity. In addition, since a plurality of caches are used, the master can access different caches even when some of the caches are accessing a slow-operating memory such as an SDRAM. Performance can be realized.

Japanese Laid-Open Patent Publication No. 10-326225

  However, the conventional memory control device such as Patent Document 1 has the following problems.

  When an SDRAM having a memory bank structure (for example, 8 dynamic RAMs) is used, if access is performed over the page length (for example, 1024 bytes) which is the basic management unit in the same memory bank, access is performed for pre- and post-processing. Efficiency drops below half. On the other hand, if the memory banks are different, the access efficiency is not lowered because the pre-processing and post-processing are concealed even when the access is across the page length. From such characteristics of the SDRAM, either the latter memory addressing or the addressing that does not cross the page length in the same memory bank is indispensable for high-efficiency control. As described above, control that avoids the restrictions of the SDRAM is necessary.

  On the other hand, when a cache is used, access to the memory is difficult to predict because it occurs only when there is no data in the cache. Also, the shorter the unit of access from the master, the less waste is generated. For example, a processor such as a CPU is an access unit of about 32 bytes, which is smaller than the SDRAM page length of about 1024 bytes. As a result, access to the memory is often a random and short access unit.

  Further, since the cache operates in conjunction with the access of the master, if the master can access only one cache at the same time, only one cache can access the memory at the same time. The two are generated when the end operation of one cache is delayed and the operation of the other cache starts. Of course, as the delay becomes extremely long, the end and start overlap and the number of accesses at the same time increases. However, in such a case, under a few conditions that the masters 11 to 16 access the caches 31 to 37 in order. Only occurs.

  From the above, one or two caches sequentially access the memory. The access control device 51 or 52 can only control the SDRAM according to the order, and it cannot be avoided even when the access efficiency is lowered due to the restrictions of the SDRAM. That is, it is difficult for the conventional memory control device to optimally control the SDRAM or the like.

  As described above, even if there are a plurality of caches, there are at most two caches activated at the same time, that is, a cache that receives access from the master and a cache that accesses the memory. Therefore, the bus 21 connecting the master and the cache eventually becomes a bottleneck. In order to solve this, it is necessary to increase the access width of the bus 21, but since all the masters need countermeasures, the circuit becomes expensive. In addition, since the basic unit of master access is proportionally long, it is disadvantageous in terms of performance, for example, for performing fine addressing such as random access.

  Similarly, even if there are a plurality of memories and cannot be simultaneously accessed from the cache, the bus 41 connecting the cache and the memory eventually becomes a bottleneck. In order to solve this problem, it is necessary to increase the access width of the bus 41. However, changing the bus width of a memory such as an SDRAM may be difficult because it leads to an increase in the number of terminals of an LSI or a substrate, for example.

  Further, in the conventional memory control device, since a plurality of masters allocate a specific cache, it is conceivable that the same address is managed between the caches. For example, assume that the master 11 writes data Y to the cache 31 at address X. On the other hand, assume that the master 12 reads data from the address X to the cache 32. In this case, since the cache is different, the data Y written by the master 11 cannot be read from the master 12.

  As another example, assume that the master 11 writes data Y at address X in the cache 31. Assume that the master 12 writes the data Z at the address X in the cache 32 with a delay. Also in this case, since the caches are different, it cannot be guaranteed that what is written in the final memory is Y or Z. This is because the order of writing out the cache is not guaranteed.

  Since these are operations that lack coherence (consistency), one of the following must be selected. Otherwise, the processing order of the data in the system will be changed, resulting in unexpected results or a fatal state such as a hang-up.

  One is to control the master so as to access an address clearly different for each master by software or the like. The other is hardware, which constantly monitors the access of the master, for example, by the cache control device 302, and when the corresponding data is found in the cache not designated by the master, the contents of the found cache are once written to the memory. Or invalidate.

  The former cannot achieve perfect coherence but is inexpensive. The latter can realize complete coherence, but is expensive because a total check of addresses managed in the cache is necessary, and an excessive memory access occurs at the time of conflict, and the performance is also deteriorated.

  When the former is employed, for example, in order to process an image by the master 11 and reprocess an image processed by the master 12, the same cache must be specified to access the same data. Therefore, in a series of data processing, the same cache group is often specified, and there is a possibility that an unused cache will appear.

  Therefore, no matter which one is selected, a great restriction is imposed on guaranteeing coherence.

  A memory device composed of a plurality of memory banks; a bus matrix that receives access from a plurality of master devices; a plurality of caches that are accessed from the bus matrix and store temporary data; An access control device that selects one and accesses the memory device.

  The number of the plurality of caches is equal to the number of memory banks of the memory device, and the bus matrix accesses the plurality of caches equally and exclusively according to a portion specified from address information of the plurality of access generation devices, The access control device manages the state of the memory bank of the memory device and selects the cache access that can be accessed earliest.

  According to the present invention, even if a plurality of masters access simultaneously, it is possible to access the cache or the buffer at the same time. Therefore, performance (logical bandwidth) exceeding the performance (physical bandwidth) of the mounted memory can be realized. Since the logical bandwidth is proportional to the number of caches, it is only necessary to increase or decrease the caches according to system requirements.

  Since the cache corresponds to the bank managed by the SDRAM or the like instead of each master, uniform access performance is provided to the master. At the same time, there is a synergistic effect that a plurality of caches simultaneously access the memory, and the most suitable access to the SDRAM or the like can be performed. Therefore, the maximum performance of SDRAM or the like can be extracted. In addition, the limited cache can be used evenly.

  In addition, since the banks managed by the SDRAM or the like, that is, the addresses specified by the master are distributed equally and exclusively, the coherence between the respective caches is completely maintained. The cost involved is relatively small because only the mutual check between masters and in the cache is performed.

  Even if the memory system such as the number and speed of SDRAMs to be used changes, a plurality of caches absorb these differences, so that all masters need not be aware of these at all. The same is true if the number of masters increases. That is, it has the flexibility to handle various master configurations and memory configurations while maximizing the performance of a memory system such as SDRAM.

  SDRAM or the like may be replaced with RDRAM, FLASH, or other memory, and the number of mounted memory is not limited, and different types of memory can be mixed.

  Performance adjustment for each master is easy. This is done by combining priority and round-robin arbitration. As a result, applications such as giving priority to the processing of some masters, changing the priority according to the acquisition status of the memory bandwidth, and automatically allocating the bandwidth are possible.

  Also, by dividing the cache into several areas and providing IDs, it is possible to allow access only to a specific master or to cache flush only a specific area. Since these can be controlled by software, they can be conveniently implemented according to the operation of the system.

It is a figure explaining the memory control apparatus of this invention. It is a figure explaining operation | movement of the bus matrix of Example 1 of this invention. It is a figure explaining the operation | movement performance (density 1) of the bus matrix of Example 1 of this invention. It is a figure explaining the operation | movement performance (density 0.5) of the bus matrix of Example 1 of this invention. It is a figure explaining the relationship between the cache and SDRAM of Example 1 of this invention. It is a figure explaining the relationship between the cache (double) and SDRAM of Example 1 of this invention. It is a figure explaining the cache (half) and SDRAM of Example 1 of this invention. It is a figure explaining the relationship between the cache of Example 1 of this invention, and SDRAM (2 pieces). It is a figure explaining the access of the bank in SDRAM of Example 1 of this invention. It is a figure explaining selection of access in SDRAM of Example 1 of this invention. It is a figure explaining distribution to SDRAM (same characteristic) of Example 1 of this invention. It is a figure explaining distribution to SDRAM (different characteristics) of Example 1 of the present invention. It is a figure explaining operation | movement of the bus matrix of Example 2 of this invention. It is a figure explaining the arbitration operation | movement of Example 2 of this invention. It is a figure explaining the access operation by the arbitration of Example 2 of this invention. It is a figure explaining the structure of SDRAM of Example 3 of this invention. It is a figure explaining the address mapping (performance importance) of Example 3 of this invention. It is a figure explaining the address mapping (electric power emphasis) of Example 3 of this invention. It is a figure explaining the operation | movement by ID assignment of the cache of Example 4 of this invention. It is a figure explaining the conventional memory control apparatus.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A memory control apparatus according to Embodiment 1 of the present invention will be described. In the present embodiment, an example in which an SDRAM widely used in a computer system is applied will be described with reference to FIG.

  In FIG. 1, 11 to 16 are masters which are arbitrary control devices, 21 is a bus matrix which uniformly separates access of masters by referring to addresses and arbitrates if there is an access collision, and 31 to 38 temporarily store data. A cache for storing; 41, a separating device that separates accesses of the caches 31 to 38 by referring to addresses for each SDRAM target; 51 and 52, an access control device for selecting an optimum access to the SDRAM from a plurality of memory access requests; Reference numerals 62 denote SDRAMs. Here, 1 is a memory control device according to the present invention comprising a bus matrix 21, caches 31 to 38, a separation device 41, and access control devices 51 and 52.

  The bus matrix 21 connects six accesses from the masters 11 to 16 to eight accesses to the caches 31 to 38. FIG. 2 shows this connection. In FIG. 2, reference numerals 211 to 218 denote arbitration devices that collect accesses that access the same cache and select one access. For simplicity of explanation, only the connection between each of the masters 11 to 16 and the arbitrating device 211 is shown. Actually, the arbitration devices 212 to 218 are similarly connected to the masters 11 to 16, respectively. Note that the arbitrating devices 211 to 218 have the same structure.

  Each of the arbitration devices 211 to 218 includes a selection device. For the sake of simplicity, only the selection device 2111 in the arbitration device 211 is shown here. The selection device 2111 functions as a filter that extracts only the access corresponding to the cache 31 by the selector signal.

  The selector signal is a number for selecting the caches 31 to 38, and is equal to the order of the adjusting devices 211 to 218. For example, the adjustment device 211 is 0, the adjustment device 212 is 1, the adjustment device 218 is 7, and so on. By comparing this selector signal with the master address signal, the filter of the selection device 221 is implemented. The reference bit of the address signal may be designated in advance or may be indicated by a register or the like.

  For example, it is assumed that there are 32 bits of address signals to be accessed in byte units. If the lower 6th, 5th, and 4th bits are designated in advance as reference bits, the accesses from address 0 to 15 are all 0 for the lower 6th, 5th, and 4th bits, so the selector signal 231 of the selector 231 To pass through. Access to addresses 16 to 127 is blocked because the lower 6th, 5th and 4th bits are not all 0's. Addresses 128 to 143 pass in the same way as the operation in the case of addresses 0 to 15, and addresses 144 to 255 are cut off in the same way as the operation in the case of addresses 16 to 127, and so on.

  Arbitration devices 212 to 218 perform the same filtering process by referring to the lower 6, 5, and 4 bits only when the selector signal changes from 1 to 7.

  If the address reference bits are in the LSB (Least Significant Bit) direction, they are distributed to the caches 31 to 38 in fine units. Conversely, in the MSB (Most Significant Bit) direction, the caches 31 to 38 are distributed in coarse units. For example, image data is often stored in continuous address areas, but in the former case, access is distributed to the caches 31 to 38 in small units. In the latter case, a specific cache is accessed in all or a large unit. These will be described in more detail in the description of the third embodiment.

  There are a maximum number of accesses that have passed through the selection device 2111 as many as the number of masters. In order to process these uniformly, mediation shall be performed in a round robin format. The round robin format has, for example, a pointer that designates a master number, and selects the nearest master pointed to by the pointer when there is a conflict. The pointer points to the pointer of the master or the master + 1 when the access is successful, and subtracts the number of masters when the number exceeds the number of masters. That is, the pointer circulates. If such a method is adopted, an access that is not selected in the contention access is suspended, and the same arbitration is performed at the next timing, and the access is always performed until the pointer makes a round.

  There are various types of mediation, such as generating a random number and using it as a pointer, or selecting it uniformly in ascending or descending order of the master number. However, the essence of the present invention does not change according to the mode of arbitration.

  The arbitration devices 212 to 218 correspond to the caches 31 to 38, respectively, and can operate simultaneously. From this, each of the masters 11 to 16 can access the cache at the same time if there is no contention for the same cache. This means that the caches 31 to 38 can be activated simultaneously.

  Contention does not always occur, but if it occurs, the access time (latency) is extended and the access performance is degraded. FIG. 3 shows a latency distribution when random access for reading is performed using a model corresponding to 8 masters and 8 caches. The horizontal axis represents latency, and the vertical axis represents the distribution P (%). The bar graph (solid line) is a simulation value, and the dotted line is a theoretical value.

  Next, FIG. 4 shows a case where the access density of the master is changed to half, for example, once every two cycles.

  A pipeline delay composed of several flip-flops is added before the master accesses and data returns. In FIGS. 3 and 4, the latency starts at 9 because this delay occurs even if there is no contention in this model. The delay is inevitably generated in the computer system, and the value varies depending on the operating frequency and the configuration.

  The theoretical theoretical value of the distribution P (%) in FIGS. 3 and 4 can be calculated as follows using the relative latency x obtained by subtracting the initial latency and the access density ρ per cycle. Here, exp () is an exponential function of Napier e.

  P (x) = 100 · exp (−ρ) · (1-exp (−ρ)) ^ x.

  In FIG. 3 and FIG. 4, by multiplying and integrating the latency x and the latency distribution P, the expected value of latency can be calculated. 3 when the master of FIG. 3 always accesses (ρ = 1) and 9.5 when the master of FIG. 4 accesses at a rate of 1/2 (ρ = 0.5). As can be seen from this, there is no significant performance degradation compared to the initial latency 9. In the case of the first embodiment, since the number of masters is 6, if the masters 11 to 16 are all accessing, the maximum value of ρ is 6/8.

  In an ordinary computer system, there is little opportunity for all masters to always access, and the actual ρ is smaller than 1. That is, the increase in latency is smaller than 1 when ρ = 1. As described above, the configuration of the bus matrix 21 allows the master to access all the caches, and at the same time, the cache access performance x the performance of the number of mounted caches 8 (logical bandwidth) can be exhibited.

  Access distributed in the bus matrix 21 is connected to each of the caches 31 to 38. Each cache operation corresponds to a cache used in a general computer.

  There are eight caches 31 to 38 corresponding to the number of banks of the SDRAM 61 and the SDRAM 62. This will be described with reference to FIG. In FIG. 5, 631 to 638 are DRAM banks divided into eight in the SDRAM, and 641 is an SDRAM controller for controlling the entire SDRAM and separating access to the DRAM banks 631 to 638. For simplicity of explanation, only the connection between each of the caches 31 to 38 and the SDRAM 61 is shown.

  As shown in FIG. 5, data is stored in a one-to-one correspondence such as a cache 31 and a DRAM bank 631 and a cache 32 and a DRAM bank 632. Therefore, the access control device 51 and the SDRAM control device 641 perform multiplexing and demultiplexing. The separation device 41 will be described later.

  The SDRAM control device 641 sequentially performs activation (Activate), data access, and deactivation (Pre-Charge), which are the characteristics of the DRAM, for each of the DRAM banks 631 to 638. Only the data access period is used to read and write the actual data.

  This will be briefly described with reference to FIG. In FIG. 9, the horizontal axis represents time, and the vertical axis represents the operation in the SDRAM control device 641 and the eight DRAM banks 631 to 638. In the operation of the SDRAM control device 641, only the read data access period is shown by a solid line. In the operations of the eight DRAM banks 631 to 638, Activate and Pre-Charge are indicated by dotted lines, and read data access periods are indicated by solid lines.

  The most optimal control for the SDRAM is to always use physically connected data terminals for data transmission and reception in order to obtain maximum performance. That is, it is sufficient that there is no gap in the solid line of the SDRAM control device 641 in FIG. Since the basic unit of access to the caches 31 to 38 is shorter than the page length of the SDRAM as shown in the description of the conventional memory control device, the access period of the read data of each DRAM bank is as shown in FIG. It is necessary to perform control to arrange the banks without gaps while switching the banks finely.

  However, since the activation and pre-charge of each DRAM bank are required before and after the data access period, the DRAM bank once used cannot be used immediately. For example, in FIG. 7, if the DRAM bank 631 accesses data at the timing of 1-2, the next activation timing 2-1 cannot be overlapped at the subsequent pre-charge timing 1-3. In addition, it is necessary to perform actual data access in consideration of delays of Activate timings 1-1 and 2-1.

  In this embodiment, the respective caches corresponding to the DRAM banks 631 to 638 make access requests simultaneously. This is because a plurality of masters distribute access equally at the same time. Therefore, the access control device 51 selects a DRAM bank that is optimal for the superposition of each timing, and passes the corresponding cache access to the SDRAM 61.

  Control of the access control apparatus 51 manages each period of FIG. 9 with a table. For example, each period of Activate, data access, and pre-charge is given in advance as a time parameter, and is recorded in a reservation table prepared for each of the DRAM banks 631 to 638 every time access occurs.

  The access control device 51 looks at the reservation table, selects an unreserved DRAM bank, selects a cache access to it, and instructs the reservation table to start reservation. When the reservation start is instructed, the reservation table sets the sum of the respective time parameters in the counter for the corresponding DRAM bank. And as time goes by, those counters are decremented. It is considered that a DRAM bank whose counter is non-zero is reserved.

  However, even if the SDRAM accesses the same DRAM bank, the activation work is unnecessary if it is within the SDRAM page length. Therefore, even if it is reserved, access is permitted by looking at the previous history. In FIG. 9, 8-3 following 8-2 indicates this.

  Further, the access control device 51 refers to the reservation table so as to read and write data corresponding to the data access period, and determines the data access timing. Specifically, the determination is made based on whether the pre-charge period <the counter value <the pre-charge period + the data access period is true or false.

  Note that writing following reading or reading following writing causes switching of input / output of the terminal, and it is usually necessary to delay about one cycle in consideration of electrical characteristics. In order to avoid this, the reading or writing may be controlled to be continuous.

  FIG. 10 shows a flowchart relating to selection of cache access that can access the SDRAM 61 in the access control device 51. The access control device 51 performs this check on the caches 31 to 38, arbitrates the last remaining one, and actually accesses the SDRAM 61.

  Regarding arbitration, in order to perform uniform access regardless of the caches 31 to 38, it is assumed that cyclic arbitration by round robin is performed as performed by the arbitration devices 212 to 218. As described above, the arbitration format may be changed. For example, the same cache may continuously access the SDRAM pages. At this time, the other caches cannot be accessed, so that there is a biased latency as seen from the master. In order to prevent this, an upper limit of the number of consecutive accesses of the same cache is set, and when the upper limit is exceeded, the priority of arbitration may be lowered.

  As shown in FIG. 7, the caches 31 to 38 and the DRAM banks 631 to 638 are associated with each other on a one-to-one basis. However, when the number of masters increases, there is a case where the cache is increased and the logical bandwidth is increased.

  In many cases, the number of DRAM banks of the SDRAM has already been determined, such as four or eight. Therefore, when the cache is increased, the number of caches may be larger than the number of DRAM banks. In such a case, the cache is constituted by an integer multiple of the number of DRAM banks. This will be described with reference to FIG.

  FIG. 6 is obtained by doubling the number of caches from FIG. Here, 31a to 38a and 31b to 38b are simply copies of the same cache (however, the cache capacity may be different from that of caches 31 to 38), and 31c is an arbitration device that arbitrates access to caches 31a and 31b. It is. 32c to 38c are similar arbitration devices.

  The arbitration is the same as the access control device 51. That is, in order to perform uniform access regardless of each cache, it is assumed that cyclic arbitration by round robin is performed as performed by the arbitration devices 222 to 228. As described above, the arbitration format may be changed.

  As can be seen from FIG. 6, when viewed from the access control device 51, the caches 31 a and 31 b and the adjustment device 31 c are equivalent to the cache 31. Therefore, the access control device 51 does not have to do anything special to optimally control the DRAM bank of the SDRAM. The same applies to the other caches 32a to 38a and the caches 32b to 38b.

  As described above, even if the number of caches is increased, it is possible to increase the logical bandwidth viewed from the master without changing the SDRAMs 61 and 62 and to perform optimum control of the SDRAM. The same applies except when the number of caches is doubled.

  Conversely, when the number of masters decreases, there is a case where it is desired to reduce the cost by reducing the cache.

  As described above, the number of DRAM banks of the SDRAM is not changed. Therefore, when the cache is reduced, the number of caches is smaller than the number of DRAM banks. In such a case, the number of caches is 1/2 of the number of DRAM banks, 1/4 of the number of caches, and 1 to the power of 2. This will be described with reference to FIG.

  FIG. 7 is obtained by reducing the number of caches to 1/2 from FIG. Here, the caches 32, 34, 36, and 38 are thinned out. Further, the access of the adjacent caches 31, 33, 35, and 37 is input to the separation device 41 for the thinned cache access. However, the access to the original caches 31, 33, 35, and 37 and the access that is put in place of the caches 32, 34, 36, and 38 are exclusively masked by any bit of the address. For example, when the LSB of the address is 0, only accesses for the caches 31, 33, 35, and 37 are performed, and when the LSB is 1, the access is divided by odd and even numbers, such as only accesses for the caches 32, 34, 36, and 38.

  As can be seen from FIG. 7, the access of the cache 32 thinned out as viewed from the access control device 51 also serves as the access of the cache 31. However, since the above-described access masking is performed, there is no simultaneous access. Accordingly, only one of the DRAM banks 631 and 632 of the SDRAM is selected. The same applies to other caches.

  Therefore, as compared with the case where there are eight caches, there are fewer choices when selecting access, so that the SDRAM in the DRAM bank cannot be optimally controlled. For this reason, it is better to reduce the cost by reducing the cache capacity than to reduce the cost by reducing the number of caches. For example, if the cache capacity is 32 KByte × 8, it is better to use 16 KByte × 8 rather than 32 KByte × 4. However, the present invention is not limited to this.

  Next, a case where the number of DRAM banks of the SDRAM 61 is reduced to four will be described. This has the same characteristics as the case where the number of caches is 16 and the number of DRAM banks is 8 because of the proportional relationship. Further, if the number of caches is reduced to four, the same characteristics as in the case where the number of caches is eight and the number of DRAM banks is eight from the same proportional relationship.

  On the other hand, there is a method of increasing the apparent number of DRAM banks using two of the same SDRAM while keeping the number of caches to be 8, and matching the number of caches with the number of DRAM banks. This will be described with reference to FIG.

  FIG. 8 shows that the number of SDRAMs 61 is two from FIG. 5 (two Sets), and the number of DRAM banks is reduced to four. Here, 61a and 61b are SDRAMs having four DRAM banks, and 641a and 641b are SDRAM control devices of SDRAMs 61a and 61b, respectively.

  As can be seen from FIG. 8, the caches 31 to 38, the separation device 41, and the access control device 51 are basically the same. Although there are two SDRAMs, the control shown in FIG. 9 is the same. However, since the access control device 51 uses the SDRAMs 61a and 61b separately, it is necessary to prepare separate chip selects. The chip select can be easily generated by the number of the DRAM bank associated with the address. For example, DRAM bank numbers 0 to 3 are chip select of SDRAM 61a, DRAM bank numbers 4 to 7 are chip select of DRAM 61b, and so on.

  Note that the address information of the caches 31 to 38 is exclusive, and the bit portion used for distribution in the bus matrix 21 represents bank information. For example, the corresponding bit of the cache 31 is 0 and the corresponding bit of the cache 32 is 1, which corresponds to the DRAM bank number as it is.

  From the above, the system performance can be adjusted by the three parameters of the number of caches, the number of DRAM banks of the SDRAM, and the number of SDRAMs. This means that a very flexible choice can be made in determining the system.

  In FIG. 6, the number of caches is set to 8 only 31a to 38a, a special master is prepared, and the access is distributed to 8 accesses by the one having the same function as the selection device 2111, and the cache is replaced with 31b to 38b. It is also possible to make it. This is used when a special master bypasses the cache and accesses the SDRAM directly. For example, it can be applied to a master such as a CPU that already has a cache.

  On the other hand, as a different method of increasing the number of SDRAMs, a case where the separation device 41 is used will be described.

  In FIG. 1, the separation device 41 refers to specific address bits in the caches 31 to 38 and distributes them to the access control devices 51 and 52 (two groups). Similar to the selection device 231 in FIG. 2, this operation is performed by assigning a selector signal in advance and comparing with a bit at a specific address.

  When the address reference bits are in the LSB direction, they are distributed to the SDRAMs 61 and 62 in fine units. Conversely, in the MSB direction, the data is distributed to the SDRAMs 61 and 62 in coarse units. This is the same as the explanation of the arbitrating devices 211 to 218.

  8 differs from the one using two SDRAMs (two sets) shown in FIG. 8 in that the caches 31 to 38 can simultaneously access the SDRAM 61 and the SDRAM 62. For example, the cache 31 can access the SDRAM 61 through the access control device 51, and the cache 32 can access the SDRAM 62 through the access control device 52.

  As described above, the configuration of the separation device 41 can exhibit the SDRAM access performance x the performance (physical bandwidth) of several SDRAMs. In the separation device 41, the allocation may be performed exclusively using a cache number instead of the allocation according to the address.

  However, since the access control devices 51 and 52 manage only the respective SDRAMs, the mutual states are unknown. For this reason, when access to different SDRAMs approaches in the same cache, there is a problem that, for example, read data of SDRAM 61 and SDRAM 62 overlap. In order to solve this problem, the separator 41 automatically inserts an access prohibition period when accessing an SDRAM different from the SDRAM accessed last time in the same cache.

  This will be described with reference to FIG. In FIG. 11, the horizontal axis represents time, and the vertical axis represents the work in the separation device 41 and the SDRAMs 61 and 62. For simplicity of explanation, the operations of the access control devices 51 and 52 are omitted. In the operations of the SDRAMs 61 and 62, only the read data access period is indicated by a solid line and a dotted line, respectively. As an operation of the separation device 41, access issuance timing is indicated by a black circle, and a data reception period is indicated by a solid line and a dotted line.

  As shown in FIG. 11, when accessing the SDRAM different from the previous time, the separating device 41 prohibits access for a predetermined period of CYC cycles (no black circle exists in the CYC period). By making this prohibition period, the data read from the SDRAMs 61 and 62 do not overlap. The CYC cycle is obtained by adding an actual data access period and a delay time until the start of access.

  Of course, the separation device 41 does not provide these prohibition periods as long as the access to the same SDRAM continues. Even if different caches accessed different SDRAMs last time, no prohibition period is provided. This is because the buses are separated as caches and therefore do not overlap.

  Furthermore, SDRAMs with different characteristics can be mounted. For example, assume that the access time of the SDRAM 62 is delayed by Delta. In this case, as shown in FIG. 12, the access prohibition period is obtained by adding Delta to CYC only when accessing a fast SDRAM from a slow SDRAM. That is, access across the SDRAM accessed last time is prohibited. Thereby, the access can be adjusted in accordance with the access timing of the slow SDRAM.

  Delta is given in advance or specified by a register. A difference may be automatically calculated by giving a different CYC cycle for each SDRAM. Also, if the bus width used by the SDRAM is different, the data must be multiplexed or demultiplexed to match the bus width of the caches 31 to 38, but these are performed by the access control devices 51 and 52. If only the difference in time is taken, only the above-described response is required.

  As described above, the separation device 41 distributes access to a plurality of SDRAMs, expands the physical band, and enables mounting of SDRAMs having different characteristics. These have no relation to the number of caches and the number of masters, and can be freely changed according to system requirements.

  In the embodiment, the number of SDRAMs has been described as two. However, even if the number of SDRAMs is more than that, there is no problem because the number of branches of the separation device 41 increases.

  Further, the method of using a plurality of SDRAMs described in FIG. 8 and the method of using a plurality of SDRAMs described in FIG. 1 may be combined (arbitrary Set and arbitrary Group). By combining them, it is possible to both increase the physical bandwidth and improve the access efficiency of the SDRAM.

  Furthermore, it can be applied to a memory adopting a bank structure such as RDRAM or FLASH memory instead of SDRAM.

  A memory control apparatus according to Embodiment 2 of the present invention will be described. This embodiment will be described with reference to Example 1.

  Access from the master 11 to 16 reaches the desired cache 31 to 38 by the bus matrix 21, but the arrival time depends on the arbitration of the bus matrix 21 and cannot be guaranteed. For example, when the master 11 accesses the cache 31 and the cache 32 in succession, fluctuation occurs between the time when the access reaches the cache 31 and the time when the access reaches the cache 32. For this reason, there is a possibility that before and after access is switched.

  If the access before and after is switched, the master data management must be switched accordingly. For example, assume that the master 11 requests the address A from the cache 31 and returns the data X. On the other hand, it is assumed that the address B is requested to the cache 32 and the data Y is returned. In this case, data may be returned in the order of Y and X, not in the order of X and Y. By returning this data exchange information to the master, the master must change the order of data processing (Out-of-Order control).

  Since these depend on how to make the master, it cannot be connected if it cannot be handled by the master. In the present embodiment, In-Order control that arranges the order internally and eliminates this will be described with reference to FIG.

  In FIG. 13, reference numerals 71 to 76 denote interface devices corresponding to the masters 11 to 16, respectively. The interface devices 71 to 76 serve as a bridge between the masters 11 to 16 and the bus matrix 21. Since the interface devices 71 to 76 have the same structure and perform the same operation, only the interface device 71 will be described in detail.

  The interface device 71 includes a burst decomposition device 711, a write buffer 712, and a read buffer 713.

  When the master 11 performs burst access, the burst decomposing device 711 decomposes them into words that are the minimum access units. By disassembling, subsequent devices such as a cache do not need to consider bursts, and can be simplified to control in units of words. Further, if processing is performed in units of bursts, latencies for individual masters are integrated, but the latency can also be averaged by decomposing into words.

  For example, when all the masters perform 16-word burst access, the timing at which the actual data can be accessed is worst, 16 words × 6 masters for one round of arbitration = 96 cycles. On the other hand, if it is broken down into words, one round of arbitration requires 1 word x 6 masters = 6 cycles. Of course, the throughput performance is not changed just by averaging the delay as a whole.

  The bus matrix 21 generates a unique number tag when arbitrating. For example, the tag is generated by combining the master number and the access order or time.

  When the master 11 performs write access, a tag is generated and transmitted to the buffer 712. On the other hand, the buffer 712 stores write data from the master 11. Since the data can be stored, the master 11 does not have to wait for writing unless the buffer 712 is full.

  Since the tag has the writing order as information, it uses the buffer 712 to extract the corresponding data. The extracted data is written to the cache 31 according to the access order after arbitration. As described above, the master 11 performs In-Order control for the buffer 712, and the buffer 712 performs Out-of-Order control for the cache 31.

  When the master 11 performs read access, a tag is generated and transmitted to the cache 31 in the same manner. The cache 31 stores the tag until data is returned, and finally returns the data and tag to the buffer 713 as a set.

  The buffer 713 checks whether or not the data in the access order expected by the master 11 is returned by the tag, and returns to the master 11 as it is when a valid tag is returned. If invalid tags are returned, they are stored. Of course, if there is accumulated data that can be returned to the master 11, the accumulated data is returned. As described above, the master 11 performs In-Order control for the buffer 713, and the buffer 713 performs Out-of-Order control for the cache 31.

  The same applies to masters other than the master 11 and caches other than the cache 31. As described above, the master can perform processing in In-Order, and the memory control device of this embodiment can select and process an optimal access order in Out-of-Order.

  Next, the arbitration method of the bus matrix 21 will be described in detail.

  Here, the accesses from the masters 11 to 16 are not particularly synchronized, and can be accessed arbitrarily. For example, it is assumed that the master 11 processes a certain amount of images within time and outputs them to the outside, and the master 12 initializes another image without time constraints.

  It is assumed that both the master 11 and the master 12 can always issue access requests and only access the SDRAM 61. Further, it is assumed that the logical bandwidth of each master and the physical bandwidth between the access control device 51 and the SDRAM 61 are equal.

  In this example, since the master 11 and the master 12 access the SDRAM 61 as a target, if there is always no data in the caches 31 to 38 (cache miss), the physical bandwidth between the access control device 51 and the SDRAM 61 becomes a bottleneck. Become. Therefore, the logical bandwidth of the two masters shares the physical bandwidth of the SDRAM.

  Here, as shown in the first embodiment, when the arbitrating devices 211 to 218 arbitrate access in a round robin format, the access of the master 11 and the master 12 is alternately accepted. This causes inconvenience that when the master 11 needs to work near the maximum logical band, it cannot be processed in time.

  For this reason, the arbitrating devices 211 to 218 perform priority control. The priority control for the arbitrating device 211 will be described with reference to FIG. Since the arbitration devices 212 to 218 have the same structure, a description thereof will be omitted.

  In FIG. 14, 2112 to 2115 are priority selection devices, 2116 to 2119 are round robin arbitration devices, and 2120 is a priority arbitration device. The masters 11 to 16 indicate the priority Priority with 2 bits at an arbitrary timing. The priority Priority indicates that the higher the number, the higher the priority.

  As described in the first embodiment, the selection device 2111 selects access to each of the caches 31 to 38. In FIG. 14, only the selection for the cache 31 is shown for simplicity. After the selection device 2111 extracts accesses to the cache 31 for each master, they are all input to the priority selection devices 2112 to 2115.

  Priority selection device 2112 has only priority Priority 0, priority selection device 2113 has priority Priority 1 only, priority selection device 2114 has priority Priority 2 only, priority The selection device 2115 extracts only those having the priority Priority 3. The extraction results are input to the round robin arbitration devices 2116 to 2119, respectively.

  Round-robin arbitration devices 2116 to 2119 replace the role of the arbitration device 211 described in the first embodiment as a device, and all perform the same operation.

  The priority arbitration device 2120 selects the final access to the cache 31 from the results of the round robin arbitration devices 2116 to 2119. In the selection, the priority is determined in the order of round robin arbitration device 2116 <round robin arbitration device 2117 <round robin arbitration device 2118 <round robin arbitration device 2119. For example, if there is an access to the round robin arbitration device 2119 (there is no master instructing the priority Priority 3 if there is no access), the round robin arbitration device 2119 is regarded as the final access regardless of the results of other round robin arbitration devices.

  From the above, it is possible to preferentially assign a bandwidth to an access requiring urgent mastering by instructing a high priority Priority. For example, since the master 11 performs processing in time, a high priority Priority is designated. Next, since there is no time restriction, the master 12 instructs a low priority Priority. In this way, even if there is a conflict, the master 11 can preferentially access, and the constraints given to the master 11 can be satisfied.

  Furthermore, if the priority Priority is dynamically controlled, it is possible to control to give an arbitrary band for each master. Details will be described below.

  For example, a feasible target bandwidth is set for each master. Each master is provided with a difference counter that adds an access if an access request is accepted, and subtracts a target bandwidth every cycle or every predetermined interval using a system timer otherwise.

  The range of the value of this counter is set to 3 levels, thereby correcting the priority Priority by adding +1, ± 0, -1. The priority Priority does not directly affect the access itself and is controlled at an arbitrary timing.

  Further, in order to perform control under certain conditions, the priority Priority that is the base of each master is set to either 1 or 2.

  This method provides stable feedback control and converges the used band to the target band. FIG. 15 shows a waveform of a model of the memory control device of this embodiment configured with 8 masters and 8 caches, and simulated with random addresses and a burst length of 4. Here, Diff Count is the difference counter described above, Priority is the amount of correction of the priority Priority described above, and Allocation is the moment when the master access request is accepted (the burst length is 4, so the number of data is multiplied by 4) ) These subscripts are master numbers, and the horizontal axis is part of the simulation time. Master 0 and 1 are set to 1/16, Masters 2 and 3 are set to 1/8, Masters 4 and 5 are set to 1/4, Master 6 is set to 15/16, and Master 7 is set to 1/1. is there.

  As can be seen from Allocation in FIG. 15, it can be seen that a relatively large number of master accesses with a large target bandwidth set are accepted. Also, looking at the Diff Count, which shows the bandwidth acquisition status of the master, the master with the target bandwidth set low has acquired enough bandwidth, so the priority is low, and conversely the master with the target bandwidth set high is acquired. Since the bandwidth fluctuates before and after the target bandwidth, Priority is also assigned.

  As described above, by setting the priority Priority and allocating access to the cache accordingly, a highly flexible memory control device capable of bandwidth control can be provided.

  Although the priority Priority has been described with 2 bits, the number of bits may be further increased to increase the granularity, or conversely, the number of bits may be decreased and controlled roughly. Further, the control for the target bandwidth may be performed by the memory control device of this embodiment instead of the master.

  Furthermore, the arbitration device of the present embodiment may be duplicated outside to increase the number of masters. For example, if an arbitration device that mediates 6 masters is attached instead of the master 11, 6 masters can be expanded (the remaining 5 + 6, a total of 11). However, since the access is bundled by the extended arbitration device, the extended masters cannot simultaneously access the cache.

  A memory control apparatus according to Embodiment 3 of the present invention will be described. This embodiment will be described with reference to Example 1.

  Distribution of access from the caches 11 to 38 in the selection device 2111 (bank division), distribution of access to the SDRAMs 61 and 62 in the separation device 41 (Group division), and distribution of access to the SDRAMs 61a and 61b in the access control device 51 (Set) Each of these will be described.

  The selection device 2111, the separation device 41, and the access control device 51 are provided with a reference bit of an address by a register. The same applies to the separation devices in the arbitration devices 212 to 218 and the access control device 52. By giving it by a register, mapping of which SDRAM and in which DRAM bank the data is stored can be arbitrarily designated by the address.

  FIG. 16 is a configuration diagram in which two SDRAMs 61a and 61b are substituted for the SDRAM 61, and two SDRAMs 62a and 62b are substituted for the SDRAM 62, respectively. SDRAMs 61a and 61b have a group number 0 and set numbers 0 and 1, respectively. SDRAMs 62a and 62b have a group number 1 and set numbers 0 and 1, respectively.

  In FIG. 17, the selection device 2111 and other selection devices in the adjustment device are instructed to refer to the address 4, 5, and 6 bits as bank divisions, and then the separation device 41 to refer to the address 12 bits as Group divisions. This is the memory mapping when the access control devices 51 and 52 are instructed to refer to the 13th bit of the address as the Set division. In FIG. 17, B0, B1, and B2 are bank division bits, Grp is a Group division bit, and Set is a Set division bit.

  The memory mapping shown in FIG. 17 is an example in which data is distributed to the DRAM banks of each SDRAM every 16 bytes, to different groups of SDRAM every 4 Kbytes, and to different sets of SDRAM every 8 Kbytes. In this example, the data is divided finely and stored in the SDRAM. Since the access is averaged when divided, a plurality of caches and a plurality of SDRAMs often operate at the same time, and the memory performance is easily obtained.

  In FIG. 18, the selection device 2111 and other selection devices in the adjustment device are instructed to refer to the address 9, 10, and 11 bits as bank division, and then the separation device 41 to refer to the address 31 bit as Group division. This is memory mapping when the access control devices 51 and 52 are instructed to refer to the 30th bit of the address as the Set division. In FIG. 18, B0, B1, and B2 are bank division bits, Grp is a Group division bit, and Set is a Set division bit.

  The memory mapping shown in FIG. 18 is an example in which data is distributed to a DRAM bank of each SDRAM every 512 bytes, to a different group SDRAM every 2 Gbytes, and to a different set SDRAM every 1 Gbyte. In this example, the data is consolidated and stored in the SDRAM. When it is solidified, access is localized, so that four SDRAMs are less likely to operate simultaneously, and it is easy to suppress power consumption.

  As described above, access can be distributed to an arbitrary space by referring to a bit at an arbitrary position of an address. Note that there is no problem even if the bit reference position of the address is disjoint or the front and rear are switched.

  All of the aforementioned distributions are exclusive. For example, since the access addresses distributed by the selection device 2111 are completely exclusive, management in the cache is also exclusive. These also apply to different SDRAMs and DRAM banks within the SDRAM.

  Since the data is managed exclusively, the coherence between the cache and the SDRAM is guaranteed. However, the order until the accesses from the masters 11 to 16 are arbitrated by the arbitration devices 211 to 218 must be observed. This is different from the above-described In-Order control and Out-of-Order control for the same master data.

  For example, when the master 11 writes to the address A and the master 12 reads the address A, as long as the order of reaching any of the arbitration devices 211 to 218 is observed, the processing is performed in order in any of the caches 31 to 38. Therefore, inconsistency does not occur. However, if the order of reaching any one of the arbitration devices 211 to 218 is changed, the master 12 is read earlier and returns incorrect data.

  A method of keeping the order of reaching any of the arbitration devices 211 to 218 will be described. The write addresses of the masters 11 to 16 are registered in each of the interface devices 71 to 76 in FIG. 13, and the registration is deleted when the write address reaches the arbitration device. The registered address can be cross-referenced from all the interface devices 71 to 76 prepared for each master.

  When an arbitrary master performs reading or writing, it confirms a match with the address registered in each interface device 71 to 76 except for itself. If they do not match, the access is accepted as it is, otherwise the access is suspended. The access suspension is canceled when the registered address reaches the arbitration device.

  With this operation, the preceding write access is not overtaken. With such a simple address mutual confirmation mechanism, coherence between masters can be ensured.

  Next, it is necessary to pay attention to the reading and writing that the cache performs on the SDRAM. For example, when a read from the master misses a cache, data corresponding to the storage location on the left is once written in the SDRAM in order to make a new storage location. Thereafter, the necessary data is read from the SDRAM to a storage location freed. This sequence of actions must also be observed.

  In this case as well, a write address for the SDRAM is registered and a match with the address for the SDRAM is confirmed. If they match, the access is suspended until the registered write access reaches the separation device 41. However, since the caches 31 to 38 are mutually exclusive unlike the masters 11 to 16, the mutual check is unnecessary.

  With this operation, the preceding write access is not overtaken. This simple address mutual confirmation mechanism can ensure coherence in the cache.

  As described above, by introducing the address mutual check function in each of the interface devices 71 to 76 and the caches 31 to 38, coherence in the entire memory control device can be completely guaranteed.

  It is not necessary to perform address registration and match confirmation for all bits. In order to reduce the circuit scale, only a certain range of bits may be targeted. However, if processing is performed with only a certain range of bits, the access that is suspected of address matching is also suspended, and the performance deteriorates. For example, if a part of 16 bits is targeted with respect to 32 bits, an extra access is suspended about once in 65536 accesses (which is further reduced by the frequency of access requests).

  A memory control apparatus according to Embodiment 4 of the present invention will be described. This embodiment will be described with reference to Example 1.

  As the caches 31 to 38, any one of a direct map, a set associative, and a full associative can be selected. Performance and cost vary depending on the method. Here, among several methods, a set associative with a good balance between performance and cost is used.

  The set associative cache has a bank called “Way” in which each data management is exclusive. That is, only one of the ways is accessed. Which access is made depends on the current state. For example, it is assumed that there are four ways, something is registered in three, and nothing is registered in one. Access to a registered way requires work to create a vacancy, resulting in degraded performance. Therefore, priority is given to access to a way where nothing is registered.

  In the present embodiment, since accesses from the masters 11 to 16 are equally distributed to the caches 31 to 38, each of the caches 31 to 38 is shared by a plurality of masters. However, as described in the second embodiment, when the logical bandwidth requested by the master is different, it may be advantageous in terms of performance to assign it to a specific master preferentially in the cache.

  Here, an ID serving as an identifier is attached to the cache way. Also, the master is accessed by designating the ID at the same time as the address. Only the Ways whose IDs match can be accessed.

  This means that a cache dedicated to a specific ID is prepared. Of course, different masters may access using the same ID, or only one master may access using a unique ID. The same applies to IDs assigned to Ways. Note that the ID to be assigned to the Way is given in advance by a register or the like.

  This will be described in detail with reference to FIG. In FIG. 19, 311 to 314 are four ways having the same operation and the same capacity.

  Ways 311 to 314 are assigned IDs of 0, 0, 0, and 1, respectively. The master accesses by specifying an arbitrary ID. When the ID designated by the master is 1, only the Way 314 to which ID = 1 is assigned is the access target. If there is desired data in this Way 314, a cache hit occurs, otherwise a cache miss occurs.

  On the other hand, when the ID specified by the master is 0, Ways 311, 312, and 313 to which ID = 0 is assigned are to be accessed. Since data managed in the way is exclusive, only one of the ways 311, 312, and 313 is selected last.

  However, when the ID specified by the master is 2, no way can be accessed. In this case, it is necessary to select either invalidating access as an error, forcibly accessing any one of the ways, or bypassing the cache and directly accessing the memory. These may be selected and mounted, or all may be mounted and the system may be switched by a register or the like.

  In addition, the cache needs to be flushed. In the flash, the data stored in the cache is written into the SDRAM all at once, and the contents of the cache are matched with the contents of the SDRAM. If the entire cache is flushed, memory access for the maximum cache capacity occurs, which may cause performance problems such as difficulty in accepting access from the master.

  In this embodiment, since an ID is assigned to the way, it is possible to select and flash only a specific ID. For example, if only the Way 314 with ID = 1 is flushed, a flush in the range of ¼ is sufficient compared to flushing the entire cache.

  Here, instead of way, there is also a method of assigning an ID for each specific address range. Further, there is a method of assigning an ID by combining a specific way and a specific address range. For example, it is possible to access only when a specific ID and a specific address range are matched. Even in the case of flash, there may be a case where a specific ID and a specific address range are flashed.

  The cache data replacement method includes a method of writing to the memory at the same time as writing, and a method of saving the accumulated data to the memory only when there is no free space due to access to a new cache. Any memory control device may be used.

  Further, even if the cache is replaced with a simple buffer such as FIFO, the efficiency of the repeated access by the master is reduced, and therefore the essence of the present embodiment is not affected.

  The memory control device of the present invention can be applied to digital AV equipment, mobile terminals, mobile phones, computer equipment, in-vehicle control equipment, medical equipment, and the like, which are applications of computer systems.

1 Memory control device 11 Master 0 which is an arbitrary control device
12 Master 1 which is an arbitrary control device
13 Master 2 which is an arbitrary control device
14 Master 3 which is an optional control device
15 Master 4 which is an arbitrary control device
16 Master 5 which is an arbitrary control device
21 Bus matrix 31 Cache (Bank 0)
32 cash (bank 1)
33 Cash (Bank 2)
34 Cash (Bank 3)
35 cash (bank 4)
36 Cash (Bank 5)
37 Cash (Bank 6)
38 cash (bank 7)
41 Separation device 51 Access control device 0
52 Access Control Device 1
61 SDRAM0
62 SDRAM1

Claims (11)

A memory device composed of a plurality of memory banks; a bus matrix that receives access from a plurality of master devices; a plurality of caches that are accessed from the bus matrix and store temporary data; A memory control device comprising an access control device that selects one and accesses the memory device,
The number of the plurality of caches is equal to the number of memory banks of the memory device, and the bus matrix accesses the plurality of caches equally and exclusively according to a portion specified from address information of the plurality of master devices, The access control device manages the state of the memory bank of the memory device and selects the cache access that can be accessed earliest. The memory control device according to claim 1,
The access control device includes a table for managing a state for each memory bank of the memory device, extracts a memory bank suitable for access from the table as a reserved bank, and simultaneously selects and prioritizes a memory bank accessed immediately before from the table. An access suitable for the priority bank is taken out from a plurality of the caches as an access to the previous memory device, and if not, one access suitable for the reserved bank is taken out from the plurality of caches. A memory control device characterized by access to The memory control device according to claim 1,
A plurality of the memory devices,
The number of the plurality of caches is equal to the sum of the number of memory banks of the plurality of memory devices, and the access control unit manages the state of the memory banks of the plurality of memory devices and selects the cache access that can be accessed earliest. A memory control device that accesses only the corresponding memory device. The memory control device according to claim 1,
A plurality of the access control devices that access the plurality of memory devices, and a separation device that is accessed from the plurality of caches and accesses the plurality of access control devices,
The number of the plurality of access control devices is connected to be equal to the number of the plurality of memory devices, respectively, and the separation device is equally and exclusive to the plurality of access control devices according to a portion specified from the address information of each of the plurality of caches. Memory control device characterized in that it is accessed periodically. The memory control device according to claim 4,
The access device forbids access to the access control device for the immediately preceding data access period if the access is made across a plurality of the memory devices, and accesses the access control device as it is if there is no access across the memory devices. A memory control device. The memory control device according to claim 1,
A plurality of coupling devices accessed from the cache;
The number of the plurality of caches is equal to an integral multiple of the number of memory banks of the memory device, and the coupling device is configured according to the part designated from the address information of each of the plurality of caches or the identification information given to the cache in advance. A memory control device that performs arbitration so as to have the number of memory banks of the memory device and accesses the access control device. The memory control device according to claim 1,
It consists of interface devices that are accessed from multiple master devices,
The interface device includes a plurality of write buffers and read buffers for the cache,
The interface device notifies the bus matrix of the write access of the access control device as it is, stores the data of the master device in the write buffer in order, and writes the data based on the write information specified by the bus matrix. Retrieves data from the buffer and sends it to the caches,
The interface device notifies the bus matrix of read access of the access control device as it is, stores data from the cache to the read buffer based on read information specified by the cache, and stores data in the read buffer. In turn to the master device,
A plurality of the caches manage read information specified by the bus matrix together with access, and return read information together with read data. The memory control device according to claim 1,
It consists of address monitoring devices that are accessed from multiple master devices,
The address monitoring device registers all or part of the write address information of each of the plurality of master devices, removes the registration if the corresponding access of the registered address is accepted by the bus matrix, and all of the new address information of the master device. Or compare the part with the registered address, if they match, defer access to the bus matrix, otherwise allow access,
The cache registers all or part of the write address information, removes the registration if the corresponding access of the registered address is accepted by the access control device, compares all or part of the new address information with the registered address, A memory control device characterized in that access to the access control device is suspended if they match, and access is permitted otherwise. The memory control device according to claim 1,
The master device adds priority information for access,
The bus matrix includes an arbitration device corresponding to each of the plurality of caches,
The arbitration device divides access for each priority specified by the master device, arbitrates in a round-robin manner, checks the presence / absence of the round-robin arbitration result in descending order of priority, and responds if there is an access. A memory control device for accessing the cache. The memory control device according to claim 1,
The cache is composed of several banks, ID values are assigned to the respective banks, the master device adds ID information for access, and the bus matrix transmits the ID information to the plurality of caches.
The cache accesses one of the banks in which the assigned ID value is equal to the designated ID information, and invalidates the access if the given ID value does not match the designated ID information in all the banks. Or a memory control device that accesses one of the banks or directly accesses the access control device. The memory control device according to claim 1,
A memory control apparatus, wherein all or a part of the cache is replaced with a FIFO (First-In-First-Out) buffer.

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