JP2009251652A - Multi-core system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-core system for reducing the memory cost of the whole system by reducing overall latency. <P>SOLUTION: Input buffer parts 5-1 to 5-m store transfer data from bus masters 2-1 to 2-m. A grid queue memory 6 is configured to store transfer data by a number acquired by multiplying the number of the bus masters 2-1 to 2-m by the number of bus slaves 3-1 to 3-n, and to simultaneously output the stored transfer data. The transfer data from the grid queue memory 6 are arbitrated by a cross bar 8, and outputted to output buffer parts 9-1 to 9-n installed corresponding to the bus slaves 3-1 to 3-n. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multi-core system that is connected between a plurality of bus masters and a plurality of bus slaves and performs data transfer between the plurality of bus masters and the plurality of bus slaves.

  Some conventional multi-core systems distribute transfer data from a plurality of bus masters and simultaneously communicate from a plurality of bus masters to a plurality of bus slaves (see, for example, Patent Document 1).

JP 2006-39677 A

  However, in the conventional multi-core system, it is necessary to hold the maximum number of data accumulated in each input queue, and when all the input queues do not hold the maximum number of data at a certain time at the same time. However, there was a problem that the buffer capacity was wasted.

  In general, read data and write data are stored in the same input queue regardless of their data structure and data size, and in systems where read data and write data are transferred to the same extent from the bus master. There was a problem that the memory use efficiency deteriorated.

  Further, in the conventional multi-core system, each bus master and each bus slave are connected equally, and there is a problem that the average latency is large without considering the band between a specific bus master and the bus slave. .

  In addition, in the conventional multi-core system, the state of each other is not monitored between the request communication system that transfers the request request from the bus master to the bus slave and the response communication system that transfers the response from the bus slave to the bus master. In this case, there is a problem that the memory cannot be arranged efficiently, and efficient data transfer cannot be performed due to the occurrence of busy.

  The present invention has been made to solve the above-described problems, and is a multi-core system capable of reducing the overall latency of a plurality of transfer data from a plurality of bus masters and reducing the memory cost of the entire system. The purpose is to obtain.

  The multi-core system according to the present invention is a multi-core system for transferring transfer data from a plurality of data transfer sources to a data transfer destination, an input buffer unit for storing the transfer data, and transfer data output from the input buffer for data transfer. Grid queue memory that can store as many times as the original number and the number of data transfer destinations, and can output the same number of data as the number of data transfer sources and the number of data transfer destinations, and input An address management unit that manages addresses for storing transfer data from the buffer in the grid queue memory, a crossbar that arbitrates and outputs the transfer data output from the grid queue memory, and stores the transfer data output from the crossbar. And an output buffer unit for sequentially transferring the data to the data transfer destination.

  The multi-core system of the present invention can store transfer data by the number of data transfer sources multiplied by the number of data transfer destinations, and simultaneously store the number of data multiplied by the number of data transfer sources and the number of data transfer destinations. Since a grid queue memory that can output data is provided and a plurality of transfer data from the data transfer source is transferred to the data transfer destination, the buffer capacity can be reduced while efficiently transferring data. .

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a multi-core system according to Embodiment 1 of the present invention.
In FIG. 1, a multi-core system 1 includes a plurality of bus masters (M1 to Mm) 2-1 to 2-m that are data transfer sources and a plurality of bus slaves (S1 to Sn) 3-1 to 3 that are data transfer destinations. -N. This multi-core system 1 includes a request communication system 4-1 for transferring transfer data from bus masters 2-1 to 2-m to bus slaves 3-1 to 3-n, and bus slaves 3-1 to 3-n. The response communication system 4-2 transfers transfer data serving as a response to the bus masters 2-1 to 2-m. It is assumed that M bus masters 2-1 to 2-m and N bus slaves 3-1 to 3-n are provided. In addition, the request communication system 4-1 and the response communication system 4-2 have input buffer units 5-1, 5-2,..., 5-m, a grid queue memory 6, an address management unit 7, a crossbar 8, and an output, respectively. Buffer units 9-1, 9-2,..., 9-n are provided. In addition, illustration regarding the structure in the response communication system 4-2 is abbreviate | omitted.

  The plurality of bus masters 2-1 to 2-m are devices that request data transfer, and the plurality of bus slaves 3-1 to 3-n are based on requests from the plurality of bus masters 2-1 to 2-m. This is a device for reading / writing data 2-1 to 2-m. The request communication system 4-1 is a system for transferring requests from the bus masters 2-1 to 2-m to the bus slaves 3-1 to 3-n, and the response communication system 4-2 is a bus slave 3-1 to 3-1. This is a communication system that transfers transfer data from 3-n to bus masters 2-1 to 2-m.

  M input buffer units 5-1 to 5-m are provided corresponding to the M bus masters 2-1 to 2-m, and temporarily transfer data requested from the bus masters 2-1 to 2-m, respectively. Is the buffer to store in The grid queue memory 6 can store data by a number (M1S1 to MmSn) obtained by multiplying the number M of bus masters 2-1 to 2-m and the number N of bus slaves 3-1 to 3-n, and at the same time, M × N. It is configured to output data. The address management unit 7 is configured to manage the addresses of the input buffer units 5-1 to 5-m and the grid queue memory 6. In other words, the address management unit 7 performs address management so that the data 100-1 to 100-m are written to the grid queue memory 6 from the input buffer units 5-1 to 5-m if the grid queue memory 6 is free. The crossbar 8 performs arbitration from a plurality of transfer request data sent from the grid queue memory 6, and N output buffer units 9 are provided corresponding to the N bus slaves 3-1 to 3-n. It is configured to transfer data to -1 to 9-n. That is, the crossbar 8 performs arbitration from among a plurality of transfer data sent from the grid queue memory 6 and transfers the transfer data to the output buffer units 9-1 to 9-n. The output buffer units 9-1 to 9-n sequentially transfer the transfer data transferred from the crossbar 8 to the corresponding bus slaves 3-1 to 3-n, and the bus slaves 3-1 to 3-n are busy. When the transfer data is not accepted, the buffer unit temporarily holds the data.

  Regarding the response communication system 4-2, N input buffer units 5-1 to 5-m are provided corresponding to N bus slaves 3-1 to 3-n that are data transfer sources, and output. There are M buffer units 9-1 to 9-n corresponding to the M bus masters 2-1 to 2-m serving as data transfer destinations. Since this is the same as 1, description thereof is omitted here.

Next, the operation of the multi-core system according to the first embodiment will be described.
First, when a data transfer request is issued from the bus masters 2-1 to 2-m, the input buffer units 5-1 to 5-m corresponding to the bus masters 2-1 to 2-m Retain data.

FIG. 2 is an example of a data transfer request issued from the bus master.
The request data includes a request, control information, and data. For example, the request includes a request indicating a request, a master ID indicating an identification ID of an issuing bus master, and a thread ID indicating an identification of a destination bus slave. The control information includes R / W indicating a write or read request, an address indicating an address of a destination bus slave, and a transfer type indicating a transfer type (whether it is a burst transfer). Finally, as data, there is data to be written to the bus slave, which is composed of total Mbits. The address management unit 7 stores the transfer data 100-1 to 100-m from the input buffer units 5-1 to 5-m in the grid queue memory 6 from the master ID and the address of the bus slave as the destination information 101.

  The grid queue memory 6 sends all the data stored at the same time to the crossbar 8 as transfer request candidates. The crossbar 8 performs arbitration from the transfer data sent from the grid queue memory 6 and sends the transfer data to the corresponding output buffer units 9-1 to 9-n. If the bus slaves 3-1 to 3-n are not busy, the output buffer units 9-1 to 9-n transfer data to the bus slaves 3-1 to 3-n.

  When data is transferred from the crossbar 8 to the output buffer units 9-1 to 9-n, the crossbar 8 notifies the address management unit 7 as transferred data information 103. In response to this notification, if there is data transferred to the grid queue memory 6, the address management unit 7 writes data to be newly transferred from the input buffer units 5-1 to 5-m to the grid queue memory 6. The storage state information 102 which is an address and write instruction information is notified to the input buffer units 5-1 to 5-m. In this way, in the request communication system 4-1, the data stored in the input buffer units 5-1 to 5-m is transferred from the grid queue memory 6 to the output buffer units 9-1 to 9-n via the crossbar 8. Sent out.

  In the response communication system 4-2 for transferring transfer data from the bus slaves 3-1 to 3-n to the bus masters 2-1 to 2-m, data transfer is performed by the same operation as that of the request communication system 4-1. .

  As described above, according to the multicore system of the first embodiment, in a multicore system that transfers transfer data from a plurality of data transfer sources to a data transfer destination, an input buffer unit that accumulates transfer data and an output from the input buffer It is possible to store the transferred data as many as the number of data transfer sources and the number of data transfer destinations, and simultaneously output as many data as the number of data transfer sources and the number of data transfer destinations. Possible grid queue memory, address management unit that manages the address where transfer data from the input buffer is stored in the grid queue memory, crossbar that arbitrates and outputs the transfer data output from the grid queue memory, and outputs from the crossbar Output buffer section that stores the transferred data and sequentially transfers it to the data transfer destination While efficient data transfer can be reduced buffer capacity.

Embodiment 2. FIG.
FIG. 3 is a block diagram showing a multi-core system 1a according to Embodiment 2 of the present invention. In FIG. 3, a multi-core system 1a is a device provided between a plurality of bus masters 2-1 to 2-m and a plurality of bus slaves 3-1 to 3-n, and performs arbitration from a plurality of transfer data. A communication system 10, a bypass control unit 11, a selection unit 12, and a selection control unit 13 are provided that transfer a plurality of selected transfer data or one of them. This embodiment shows a case where there are relatively many transfer requests from the bus master 2-1 to the bus slave 3-1.

  In the case of transfer data to the bus slave 3-1 from the transfer request data from the bus master 2-1, the bypass control unit 11 transfers the data as bypass transfer data 110 via the bypass path to the selection unit 12. Transfer data other than the bus slave 3-1 is a control unit that transfers to the communication system 10. The communication system 10 is configured to select and output a plurality of transfer data or one transfer data by arbitration from among a plurality of transfer request data, and the request communication system 4-1 according to the first embodiment. It has the same configuration. The selection unit 12 selects one of the bypass transfer data 110 sent via the bypass path and the transfer data 111 selected from the communication system 10 by the selection control signal 112 generated by the selection control unit 13. Then, it is configured to output to the bus slave 3-1.

Next, the operation of the second embodiment will be described.
The bypass control unit 11 sends the bypass transfer data 110 via the bypass path if it is transfer data to the bus slave 3-1, based on the address of the data transferred from the bus master 2-1. If so, the transfer data is sent to the communication system 10.
The communication system 10 selects one or a plurality of transfer data from a plurality of transfer data from the bus masters 2-1 to 2-m, and outputs the selected data to the bus slaves 3-1 to 3-n. In the second embodiment, transfer data from the bus master 2-1 to the bus slave 3-1 is not input to the communication system 10.

  The selector 12 selects one of the bypass transfer data 110 from the bypass path and the transfer data from the bus masters 2-2 to 2-m other than the bus master 2-1 to the bus slave 3-1, which is selected by the communication system 10. Transfer data 111 is input. Further, the selection control unit 13 selects one transfer selected by the communication system 10 from the transfer data from the bus masters 2-2 to 2-m other than the bus master 2-1 and the bus master 2-1, to the bus slave 3-1. A selection control signal 112 indicating which one of the data 111 is to be selected is generated. This control method can be realized, for example, by weighted round robin or fixed arbitration. Alternatively, if there is no transfer request to the bus slave 3-1 in the stored data in the communication system 10, the bypass transfer data 110 can be selected.

  The selection unit 12 selects one of the selection control signals 112 generated by the selection control unit 13 and transfers the data to the bus slave 3-1. When the bypass transfer data 110 is not selected by the selection control unit 13, the selection unit 12 holds the bypass transfer data 110.

  In the second embodiment, the case where the bandwidth of the bus master 2-1 and the bus slave 3-1 is large is shown for easy understanding. However, this combination is free, and a plurality of combinations can be easily realized. it can. An example will be described below.

  For example, as shown in the multi-core system 1b of FIG. 4, M bypass control units 11-1 to 11-m are provided corresponding to the bus masters 2-1 to 2-m, and the selection unit 12 is connected to the crossbar 8 By replacing with, a configuration that can handle any combination is possible. In the bypass control units 11-1 to 11-m, combinations of the bus masters 2-1 to 2-m and the bus slaves 3-1 to 3-n are determined, respectively, and a specific bus master is determined by the bypass selection signal 113. And a specific bus slave is selected. That is, the bypass control units 11-1 to 11-m determine a combination of one or more specific bus masters and specific bus slaves based on the bypass selection signal 113, and bypass transfer data 110-1 to 110-. Output to the crossbar 8 as m. The crossbar 8 selects either the bypass transfer data 110-1 to 110-m or the transfer data 111-1 to 111-n output from the communication system 10 based on the selection control signal 112, and the corresponding bus slave 3-1. Output to ~ 3-n. Note that the bypass selection signal 113 in FIG. 4 is an input to the multi-core system, and can be arbitrarily set.

  Further, as shown in the multi-core system 1c of FIG. 5, a bandwidth monitoring unit 14 for monitoring the number of transfer data from the bus masters 2-1 to 2-m is provided, and dynamically to the bypass control units 11-1 to 11-m. It is also possible to control whether the bypass path is selected. That is, the bandwidth monitoring unit 14 counts the transfer data from all the bus masters 2-1 to 2-m, and identifies the bus masters 2-1 to 2-m and the bus slaves 3-1 to 3-n with a large amount of transfer data. As a bus master and a specific bus slave, a bypass selection signal 113a for selecting the corresponding bypass control units 11-1 to 11-m is output. The bypass control units 11-1 to 11-m to which the bypass selection signal 113a is input output the bypass transfer data 110-1 to 110-m of the corresponding bus masters 2-1 to 2-m to the crossbar 8. The bypass selection signal 113a is input to the selection control unit 13, and the selection control unit 13 outputs the selection control signal 112 to the crossbar 8 based on the bypass selection signal 113a. Similarly to the example shown in FIG. 4, the crossbar 8 selects either the bypass transfer data 110-1 to 110-m or the transfer data 111-1 to 111-n output from the communication system 10, and the corresponding bus Output to slaves 3-1 to 3-n.

  In the second embodiment, data transfer from the bus masters 2-1 to 2-m to the bus slaves 3-1 to 3-n has been described as an example. The transfer of the response data to 1-2m can be realized with the same configuration.

  As described above, according to the multi-core system of the second embodiment, in a multi-core system that transfers transfer data from a plurality of data transfer sources to a plurality of data transfer destinations, from a specific data transfer source to a specific data transfer destination In the case of transfer data, select the bypass control unit that outputs as bypass transfer data, the transfer data from the data transfer source other than the specific data transfer source to the specific data transfer destination, and the bypass transfer data. For example, when the bandwidth between a specific bus master and a bus slave is large, a specific bus master that occupies a relatively large part of the transfer of the entire system and Data transfer latency between bus slaves can be reduced, resulting in an average latency for the entire system. Small it is possible.

  Further, according to the multi-core system of the second embodiment, a plurality of bypass control units are provided corresponding to a plurality of data transfer sources, and these bypass control units are configured to specify specific data transfer sources based on a given bypass control signal. The bypass transfer data is sent from the data transfer destination to the specific data transfer destination, and the selection unit selects either the bypass transfer data or the transfer data from the data transfer source other than the specific data transfer source to the specific data transfer destination. Since the data is selected and output to a specific data transfer destination, it is possible to set an arbitrary data transfer source and bypass of the data transfer destination.

  Further, according to the multi-core system of the second embodiment, transfer data from all data transfer sources is counted, and a data transfer source and a data transfer destination having a large amount of transfer data are designated as a specific data transfer source and a specific data transfer. Since a band monitoring unit that outputs a bypass selection signal for selecting a corresponding bypass control unit is provided as a destination, a bypass can be dynamically set between a data transfer source having a large amount of transfer data and a data transfer destination.

  Further, according to the multi-core system of the second embodiment, when there is no transfer data from a data transfer source other than the specific data transfer source to the specific data transfer destination, the selection unit receives the specific data from the specific data transfer source. Since the bypass transfer data to the transfer destination is selected, data transfer to a specific data transfer destination can be performed efficiently.

Embodiment 3 FIG.
FIG. 6 is a block diagram showing a multi-core system according to Embodiment 3 of the present invention.
In FIG. 6, a multi-core system 1d is a device provided between a plurality of bus masters 2-1 to 2-m and a plurality of bus slaves 3-1 to 3-n, and includes input buffer units 31-1 to 31-31. -M and the communication system 32. The multi-core system 1d is a system configured to input transfer data from a plurality of bus masters 2-1 to 2-m through the same input port without being divided into read request data and write request data.

  The input buffer units 31-1 to 31-m are M buffer units corresponding to the M bus masters 2-1 to 2-m, and store transfer data of the bus masters 2-1 to 2-m. . In the input buffer units 31-1 to 31-m, read buffers (read data input buffers) 33-1 to 33-1 for storing transfer data of read requests among transfer data from the bus masters 2-1 to 2-m. 33-m, write buffers (ride data input buffers) 34-1 to 34-m for storing transfer data of write requests, and data from the read buffers 33-1 to 33-m and write buffers 34- Read / write selection units 35-1 to 35-m for selecting any one of the transfer data from 1 to 34-m are provided. The communication system 32 is a functional unit that arbitrates transfer request data output from the input buffer units 31-1 to 31-m and transfers a plurality or one of selected transfer data. This corresponds to a configuration in which the input buffer units 5-1 to 5-m are removed from the request communication system 4-1.

Next, the operation of the third embodiment will be described.
In the multi-core system 1d, request data is transmitted from the bus masters 2-1 to 2-m to the bus slaves 3-1 to 3-n. The bus slaves 3-1 to 3-n that have received the request data transmit response data to the bus masters 2-1 to 2-m, and the bus masters 2-1 to 2-m receive the response data.

FIG. 7 shows the data structures of read request transfer data, write request data, write response data, and read response data.
As shown in the figure, the read (read) request data includes a bus slave address and control information. The write request data is composed of the contents to be written, the address to be written, and control information. The read response data is composed of read data and control information, and the write response data is composed only of control information. In general, there are many interfaces having such a data structure. However, if these read request data and write request data or read response data and write response data are stored in the same buffer in a multi-core system, it is necessary to store even empty information, which is useless. Therefore, as shown in the third embodiment, when the number of read and write transfer requests from the bus masters 2-1 to 2-m is about the same, a separate read buffer and write buffer are provided, thereby eliminating unnecessary space. The memory cost can be reduced because it is not necessary to store the data.

  In the multi-core system 1d according to the third embodiment, read / write for selecting one of the transfer data output from the read buffers 33-1 to 33-m and the write buffers 34-1 to 34-m. Although the selectors 35-1 to 35-m are provided, the same effect can be obtained even if the read / write request data is output from the single bus master to the communication system 32.

  In the third embodiment, data transfer from the bus masters 2-1 to 2-m to the bus slaves 3-1 to 3-n has been described as an example. The transfer of the response data to 1-2m can be realized with the same configuration.

  As described above, according to the multi-core system of the third embodiment, transfer data from a plurality of data transfer sources is transferred to a plurality of data transfer destinations, and as transfer data from a plurality of data transfer sources, read data and In a multi-core system that inputs write data through the same input port, a read data input buffer that stores read data through the input port, a write data input buffer that stores write data through the input port, and a read data input buffer Since there is provided a communication system that selects the output of the data or the output of the write data input buffer and transfers it to a plurality of data transfer destinations, it is not necessary to store useless empty data, and the memory cost can be reduced.

Embodiment 4 FIG.
FIG. 8 is a block diagram showing a multi-core system according to Embodiment 4 of the present invention.
In FIG. 8, a multi-core system 1e is a device provided between a plurality of bus masters 2-1 to 2-m and a plurality of bus slaves 3-1 to 3-n. A response communication system 41-2 and a monitoring unit 42 are provided, and arbitration units 43-1 and 43-2 are provided in the respective communication systems 41-1 and 41-2.

  The request communication system 41-1 and the response communication system 41-2 include a buffer unit (not shown) that holds data therein, and are configured to perform a plurality of data communications. The request communication system 41-1 and the response communication system 41-2 are the same as the request communication system 4-1 and the response communication system 4-2 in the first embodiment except for the arbitrating units 43-1 and 43-2. It is. The arbitration units 43-1 and 43-2 also arbitrate data transfer to the bus slaves 3-1 to 3-n based on the arbitration information from the monitoring unit 42, and respond to the bus masters 2-1 to 2-m. This is a functional unit that performs data arbitration.

  The monitoring unit 42 monitors internal information of the communication system such as the buffer unit, transfer data passing number, and busy information of the connected communication systems 41-1 and 41-2. The arbitration units 43-1 and 43-2 in the other communication system are notified.

Next, the operation of the fourth embodiment will be described.
The multi-core system shown in FIG. 8 transfers request data from the bus masters 2-1 to 2-m to the bus slaves 3-1 to 3-n by the request communication system 41-1, and receives the bus slave 3-1. From ~ 3-n, the response data is transferred to the bus masters 2-1 to 2-m via the response communication system 41-2. Here, if there is no collision, the transfer data from the bus masters 2-1 to 2-m is transferred as it is to the bus slaves 3-1 to 3-n. Issues a transfer request and a collision occurs. The collided data is temporarily held in the buffer in the request communication system 41-1, and the data held in the next cycle becomes a new transfer data candidate. However, if such collisions occur frequently, the communication system requires a buffer having a large capacity. When data exceeding the preset buffer capacity is input to the communication system, the communication system is in a busy state in which no more data is accepted, and the transfer efficiency of the entire system deteriorates.

  Therefore, in the fourth embodiment, a monitoring unit 42 that monitors the internal state of the request communication system 41-1 and the response communication system 41-2 is provided. The response communication system 41-2 monitors each other to make data transfer more efficient and reduce the memory capacity.

FIG. 9 shows information input to the monitoring unit 42 and information output from the monitoring unit 42.
The monitoring unit 42 receives information on the number of transfer data to the bus slave, information on the number of transfer data from the bus master, response information on the transfer data from the bus master, busy occurrence information, buffer storage number information, and the like. Here, the information on the number of data transferred to the bus slave is, for example, information that there are many data transfers to a specific bus slave 3-1. The transfer data number information from the bus master is, for example, information that a lot of transfer data of the bus master 2-1 has passed. The response information of the transfer data from the bus master is information indicating how many cycles the transferred data is input to the crossbar (not shown) in the response communication system 41-2. The busy occurrence information is information indicating whether busy is occurring in the request communication system 41-1 or the response communication system 41-2. The buffer storage number information is information that the data storage number of the buffer unit in the request communication system 41-1 and the response communication system 41-2 is large.

  The monitoring unit 42 calculates which data is transferred from these pieces of information with the highest memory efficiency and can be transferred efficiently, and sends this information to the request communication system 41-1 and the response communication system 41-2. Is notified as mediation information. In the request communication system 41-1 and the response communication system 41-2, the respective arbitration units 43-1 and 43-2 perform arbitration based on the arbitration information from the monitoring unit. Specific examples are shown below.

  In the conventional configuration, for example, when the bus master 2-1 performs many data transfers to the bus slave 3-1, the transfer data to the bus master 2-1 or the respective bus slaves are included in the response communication system 41-2. The number of buffers stored corresponding to the number increases. If the maximum capacity of the buffer is exceeded, the system will be busy and the entire system or part of it will not work. Therefore, in the fourth embodiment, the monitoring unit 42 counts how much data is currently stored in each buffer in the response communication system 41-2. The counted communication data is notified to the request communication system 41-1, and the request communication system 41-1 transfers the data to the bus slave so that the required memory cost of the buffer in the response communication system 41-2 is reduced. For example, as a monitoring result in the monitoring unit 42, when the transfer data accumulation number to a specific bus master in the response communication system 41-2 is larger than the transfer data accumulation number to another bus master, the request communication system 41-1 The arbitration is performed by setting the transfer priority of the transfer data from one bus master lower than the transfer priority of the other bus masters. Furthermore, by quickly notifying the request communication system 41-1 of the busy that has occurred in the response communication system 41-2, it is possible to prevent deterioration in transfer efficiency due to busy propagation.

  Similarly, by monitoring the number of data passing through the request communication system 41-1, and notifying the response communication system 41-2 of the number of passing data, there is an equivalent effect. The monitoring unit 42 counts the number of transfer data to each of the bus slaves 3-1 to 3-n in the request communication system 41-1. The monitoring unit 42 counts the number of data transfers according to the data transfer destination within a certain period of time, and notifies the response communication system 41-2 that the number of data to be transmitted as a response from the bus slave will increase. By doing so, the response communication system 42-2 knows that a lot of response transfer data will be stored in a specific buffer from now on. Therefore, the response communication system 41-2 gives priority to the transfer data of this buffer. By selecting this, it is possible to reduce the buffer capacity and suppress the occurrence of busy.

  Furthermore, the time from the arrival of data from the request communication system 41-1 to the bus slaves 3-1 to 3-n until the response is sent, the number of cycles depends on the transfer command, burst transfer and transfer data size. Judgment may be possible. In that case, the request communication system 41-1 and the response communication system 41-2 can predict in advance what kind of transfer request will occur after that. Therefore, the monitoring unit 42 calculates the data transfer timing so as to reduce the memory cost based on the information in the request communication system 41-1 and the response communication system 41-2, and outputs this as arbitration information. Hereinafter, such a specific example is shown.

  The reason why arbitration is necessary within the response communication system 41-2 is that responses to the same bus master are simultaneously transferred from a plurality of bus slaves to the response communication system 41-2. However, when the time or cycle at which the response is transferred from the bus slave to the response communication system 41-2 is known in advance, responses to the same bus master are not simultaneously transferred from the plurality of bus slaves to the response communication system 41-2. As a result, there is an effect that arbitration is not required in the response communication system 41-2. That is, when the monitoring unit 42 determines that responses to the same bus master are simultaneously generated from a plurality of bus slaves, arbitration information that sets data transfer to the plurality of bus slaves as a timing at which no contention of response data to the bus master occurs. Is sent out.

  As a simple example, assume that there are two transfer data from a specific bus master. One is already transferred to a specific bus slave, but the response is not yet transferred to the response communication system 41-2. At this time, it is assumed that the request communication system 41-1 knows that the response of the transferred transfer data is transferred to the response communication system 41-2 after four cycles. In this case, when another transfer data in the request communication system 41-1 that has not yet been transferred is transferred to a different bus slave, the response is transferred to the response communication system 41-2 after four cycles. And transfer data after 4 cycles. Therefore, in this case, the transfer data in the request communication system 41-1 is not transferred. If there is other data as a transfer candidate, it is transferred. As described above, since the transfer data to the same bus master is not simultaneously transferred to the response communication system 41-2, the response communication system 41-2 does not require arbitration, and the memory cost in the response communication system 41-2 is also reduced. it can.

  Also, the monitoring unit 42 causes the request communication system 41-1 to transfer the response to the response communication system 41-2 the latest from the burst length, command, and status of the bus slaves 3-1 to 3-n to be accessed. Transfer data to be extracted is output as arbitration information. The arbitration unit 43-1 of the request communication system 41-1 performs arbitration based on the arbitration information, and transfers the data with priority. Thereby, it is also possible to reduce the worst latency.

The request communication system 41-1 and the response communication system 41-2 may perform transfer data arbitration based on master busy or slave busy, which will be described next.
FIG. 10 notifies the monitoring unit 42a of busy information from the bus masters 2-1 to 2-m and the bus slaves 3-1 to 3-n in addition to the configuration of FIG.
The monitoring unit 42a monitors the internal buffer capacity of the request communication system 41-1 and the response communication system 41-2, and when the buffer is in a full state in which data cannot be stored any more, Determined as busy at. The busy states at the bus masters 2-1 to 2-m are input as master busys 121-1 to 121-m, and the busy states at the bus slaves 3-1 to 3-n are slave busys 120-1 to 120-n. Is entered as That is, there are four types of busy information sent to the monitoring unit 42a. The monitoring unit 42a determines the next transfer data from the busy information and notifies the arbitration units 43-1 and 43-2 as arbitration information.

First, it cannot be transferred to the bus masters 2-1 to 2-m and the bus slaves 3-1 to 3-n in which the master busys 121-1 to 121-m and the slave busys 120-1 to 120-n occur. When the buffers in the communication systems 41-1 and 41-2 are busy, the bus masters 2-1 to 2-m and the bus slaves 3-1 to 3-n are connected to the communication systems 41-1 and 41-2. The transfer data cannot be sent.
In the worst case, first, master busy occurs, and then a response cannot be transferred from the response communication system 41-2 to this bus master, so that the buffer in the response communication system 42-2 becomes full so that no more data can be stored. . As a result, since the response communication system 42-2 is busy and the slave is busy with the response communication system 41-2, the response cannot be transferred to the response communication system 41-2, and slave busy occurs. . Furthermore, due to the slave busy, the request communication system 41-1 cannot be transferred to the slave, the transfer data is accumulated in the request communication system 41-1, and busy occurs in the request communication system 41-1. The master cannot send the transfer data to the request communication system 41-1, and the system stops. As described above, due to busy propagation, the transfer efficiency decreases, the buffer capacity required inside increases, and the entire system may stop.

Therefore, the monitoring unit 42a manages each piece of busy information at once. In the monitoring unit 42a, the transfer data is transferred to the arbitration units 43-1 and 43-2 so that the busy does not occur, and even if the busy occurs, the transfer efficiency is not deteriorated and the system is not stopped. Selection information is given as mediation information.
For example, when a certain bus master is busy, the request communication system 41-1 transfers a buffer in the response communication system 41-2 that is not busy and transfer data other than the bus master to the bus slave. In this way, the frequency of busy occurrence can be reduced.

  Further, in the fourth embodiment, the busy information in the communication system input to the monitoring unit 42 may be a busy signal. Even if the transfer data is determined after becoming busy, there is a possibility that the data is transferred to a place that is already busy before that. Therefore, by notifying the monitoring unit 42 (42a) of a signal indicating that it is becoming busy instead of the busy signal, it is possible to expect further improvement in transfer efficiency.

  As described above, according to the multicore system of the fourth embodiment, a request communication system that transfers transfer data from a plurality of bus masters to a bus slave, and a response communication that transfers transfer data from a plurality of bus slaves to a plurality of bus masters The system, the transfer data in the request communication system and the response communication system are monitored, and based on the monitoring results, arbitration information for reducing the capacity for storing the transfer data in the request communication system and the response communication system is obtained, and this arbitration is performed. A monitoring unit that notifies the request communication system and the response communication system of information, and the request communication system and the response communication system perform transfer data arbitration based on the arbitration information. And It is possible to reduce the re capacity.

  Further, according to the multi-core system of the fourth embodiment, when the number of transfer data stored in a specific bus master in the response communication system is larger than the number of transfer data stored in other bus masters as a monitoring result in the monitoring unit, request communication The system performs arbitration by setting the transfer priority of transfer data from a specific bus master lower than the transfer priority of other bus masters, thus reducing the frequency of busy occurrence of the entire system and further reducing the number of stored data. Can be reduced.

  Further, according to the multi-core system of the fourth embodiment, when the number of transfer data to a specific bus slave in the request communication system is larger than the number of transfer data to other bus slaves as a monitoring result in the monitoring unit, response communication Since the system performs arbitration by setting the transfer priority of transfer request data from a specific bus slave higher than the transfer priority of other bus slaves, the busy occurrence frequency of the entire system is reduced and further accumulated. The number of data can be reduced.

  Further, according to the multi-core system of the fourth embodiment, the response time or the number of cycles for the transfer data reception in each bus slave is obtained in advance, and the monitoring unit generates responses to the same bus master simultaneously from a plurality of bus slaves. If it is determined, the arbitration information is sent with the data transfer to the plurality of bus slaves set to a timing at which no contention with the bus master occurs, and the request communication system performs arbitration to the plurality of bus slaves based on the arbitration information. As a result, the entire system can efficiently transfer data, and the memory capacity can be reduced. Furthermore, by eliminating contention for response data, the number of circuits required for arbitration in the response communication system can be reduced. Can do.

  Further, according to the multi-core system of the fourth embodiment, the number of response cycles for transfer data reception in each bus slave is obtained in advance, and the request communication system takes a lot of latency based on the transfer data and the number of cycles. Since arbitration is performed with a higher priority for the data transferred to the bus slave, the worst latency can be reduced.

  Further, according to the multi-core system of the fourth embodiment, the monitoring unit requests the bus master based on the bus master busy information, the bus slave busy information, the request communication system busy information, and the response communication system busy information. Since arbitration information for reducing the capacity for storing transfer data in the communication system and the response communication system is obtained, it is possible to suppress a decrease in transfer efficiency due to busy propagation.

  Further, according to the multi-core system of the fourth embodiment, the monitoring unit is configured to use the request communication system and the response communication system based on the signal that the request communication system is busy and the signal that the response communication system is busy. Since arbitration information for reducing the capacity for storing transfer data is obtained, it is possible to suppress the occurrence of busy and further improve transfer efficiency.

Embodiment 5 FIG.
FIG. 11 is a block diagram showing a multi-core system according to Embodiment 5 of the present invention.
In FIG. 11, a multi-core system 1g is a device provided between a plurality of bus masters 2-1 to 2-m and a plurality of bus slaves 3-1 to 3-n, and includes a communication system 50. In addition, the communication system 50 includes arbitration information adding units 51-1 to 51-m and an arbitration unit 52. Here, the communication system 50 selects a plurality of transfer data or one transfer data by arbitration from among the transfer data from the plurality of bus masters 2-1 to 2-m, and bus slaves 3-1 to 3-3. The basic configuration other than the arbitration information adding units 51-1 to 51-m and the arbitration unit 52 is the request communication system 4-1 according to the first embodiment and the implementation of the implementation. The communication system 10 according to the second embodiment, the communication system 32 according to the third embodiment, and the request communication system 41-1 according to the fourth embodiment have the same configuration.

The arbitration information adding units 51-1 to 51-m detect when transfer data that needs to be transferred with the highest priority that requires urgent input is input to the multi-core system 1g, and detect the data required for arbitration. This is a functional unit that sets the value to the maximum value or the minimum value. The arbitration unit 52 arbitrates transfer data from each of the bus masters 2-1 to 2-m based on information necessary for arbitration transmitted from the arbitration information adding units 51-1 to 51-m.
In this way, by notifying the arbitration unit 52 of transfer data candidates to which information necessary for arbitration is added, arbitration for selecting transfer data that needs to be transferred with the highest priority that requires urgentness by conventional arbitration is performed. You can do it. In normal arbitration, transfer data having the longest waiting time is selected from transfer data information such as arrival time. Therefore, this transfer data information, here, the arrival time is set to the minimum value, and the waiting time is set to the maximum value, so that this emergency transfer data is selected. Thus, the emergency transfer data can be performed by the conventional arbitration with a small increase in hardware.

  In the above description, the transfer from the bus masters 2-1 to 2-m to the bus slaves 3-1 to 3-n has been described with emphasis. However, these relationships are opposite, that is, the bus slave 3-1. It is apparent that the present invention can be realized by the same configuration and method in the transfer from ~ 3-n to the bus masters 2-1 to 2-m. That is, such a configuration can be realized by using the response communication systems 4-2 and 41-2 as the communication system 50.

  As described above, according to the multi-core system of the fifth embodiment, the arbitration information adding unit that adds specific information to the transfer data that needs to be transferred earliest among the transfer data, and the arbitration information addition And the arbitration unit that performs arbitration with the highest priority given to the transfer data to which specific information is added, so the number of steps required for arbitration and the slight increase in the amount of hardware, Data transfer can be supported.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the communication multi-core system by Embodiment 1 of this invention. It is explanatory drawing which shows the data transfer request issued from the bus master in the multi-core system by Embodiment 1 of this invention. It is a block diagram of the multi-core system by Embodiment 2 of this invention. It is a block diagram which shows the other example of the multi-core system by Embodiment 2 of this invention. It is a block diagram which shows the further another example of the multi-core system by Embodiment 2 of this invention. It is a block diagram of the multi-core system by Embodiment 3 of this invention. It is explanatory drawing of the read data and write data in the multi-core system by Embodiment 3 of this invention. It is a block diagram of the multi-core system by Embodiment 4 of this invention. It is explanatory drawing of the information input into the monitoring part of the multi-core system by Embodiment 4 of this invention. It is a block diagram of the other example of the multi-core system by Embodiment 4 of this invention. It is a block diagram of the multi-core system by Embodiment 5 of this invention.

Explanation of symbols

  1, 1a to 1g multi-core system, 2-1 to 2-m bus master, 3-1 to 3-n bus slave, 4-1, 41-1 request communication system, 4-2, 41-2 response communication system, 5 -1 to 5-m, 31-1 to 31-m input buffer unit, 6 grid queue memory, 7 address management unit, 8 crossbar, 9-1 to 9-n output buffer unit, 10, 32, 50 communication system, 11, 11-1 to 11-m Bypass control unit, 12 selection unit, 13 selection control unit, 14 band monitoring unit, 33-1 to 33-m read buffer, 34-1 to 34-m write buffer, 42 42a monitoring unit, 43-1, 43-2, 52 arbitration unit, 51-1 to 51-m arbitration information addition unit.

Claims (14)

In a multi-core system that transfers transfer data from multiple data transfer sources to a data transfer destination,
An input buffer unit for storing the transfer data;
The transfer data output from the input buffer can be stored by the number of data transfer sources multiplied by the number of data transfer destinations, and the number of data transfer sources multiplied by the number of data transfer destinations. Grid queue memory that can output only data at the same time,
An address management unit that manages an address for storing transfer data from the input buffer in the grid queue memory;
A crossbar for arbitrating and outputting the transfer data output from the grid queue memory;
A multi-core system comprising: an output buffer unit that stores transfer data output from the crossbar and sequentially transfers the transfer data to the data transfer destination. In a multi-core system that transfers transfer data from multiple data transfer sources to multiple data transfer destinations,
In the case of transfer data from a specific data transfer source to a specific data transfer destination, a bypass control unit that outputs as bypass transfer data,
A selection unit that selects either the transfer data from the data transfer source other than the specific data transfer source to the specific data transfer destination and the bypass transfer data, and outputs the selected data to the specific data transfer destination; Multi-core system. A plurality of bypass control units are provided corresponding to a plurality of data transfer sources, and these bypass control units send bypass transfer data from a specific data transfer source to a specific data transfer destination based on a given bypass control signal. And
The selecting unit selects either the bypass transfer data or transfer data from a data transfer source other than the specific data transfer source to the specific data transfer destination, and outputs the selected data to the specific data transfer destination. The multi-core system according to claim 2, wherein:   A bypass that counts transfer data from all data transfer sources and selects the corresponding data transfer source and data transfer destination as a specific data transfer source and a specific data transfer destination as the corresponding data transfer source and data transfer destination. The multi-core system according to claim 3, further comprising a band monitoring unit that outputs a selection signal.   The selection unit selects bypass transfer data from the specific data transfer source to the specific data transfer destination when there is no transfer data from a data transfer source other than the specific data transfer source to the specific data transfer destination. The multi-core system according to any one of claims 2 to 4, wherein In a multi-core system that transfers transfer data from a plurality of data transfer sources to a plurality of data transfer destinations and inputs read data and write data through the same input port as transfer data from the plurality of data transfer sources,
A read data input buffer for storing the read data via the input port;
A write data input buffer for storing the write data via the input port;
A multi-core system including a communication system that selects an output of the read data input buffer or an output of the write data input buffer and transfers the selected data to the plurality of data transfer destinations. A request communication system for transferring transfer data from a plurality of bus masters to a bus slave;
A response communication system for transferring transfer data from a plurality of bus slaves to a plurality of bus masters;
Monitoring transfer data inside the request communication system and the response communication system, and based on the monitoring result, seeking arbitration information for reducing the capacity for storing transfer data in the request communication system and the response communication system, A monitoring unit for notifying arbitration information to the request communication system and the response communication system,
The request communication system and the response communication system perform transfer data arbitration based on the arbitration information. As a monitoring result in the monitoring unit, when the transfer data accumulation number to a specific bus master in the response communication system is larger than the transfer data accumulation number to other bus masters,
8. The multi-core system according to claim 7, wherein the request communication system performs arbitration by setting a transfer priority of transfer data from the specific bus master lower than a transfer priority of other bus masters. As a monitoring result in the monitoring unit, when the number of transfer data to a specific bus slave in the request communication system is larger than the number of transfer data to other bus slaves,
9. The response communication system performs arbitration by setting a transfer priority of transfer request data from the specific bus slave higher than a transfer priority of other bus slaves. Multi-core system. Obtain the response time or cycle number for transfer data reception in each bus slave in advance,
When the monitoring unit determines that responses to the same bus master are generated simultaneously from a plurality of bus slaves, it sends arbitration information with data transfer to the plurality of bus slaves as a timing at which no conflict with the bus master occurs,
The multi-core system according to claim 7 or 8, wherein the request communication system performs arbitration to the plurality of bus slaves based on the arbitration information. Obtain the cycle number of response to transfer data reception in each bus slave beforehand,
11. The request communication system performs arbitration at a higher priority for transfer data to a bus slave having a high latency based on the transfer data and the number of cycles. The multi-core system of any one of these.   The monitoring unit stores the transfer data in the request communication system and the response communication system based on the bus master busy information, the bus slave busy information, the request communication system busy information, and the response communication system busy information. The multi-core system according to claim 7, wherein arbitration information for reducing a capacity to be obtained is obtained.   The monitoring unit is configured to reduce a capacity for storing transfer data in the request communication system and the response communication system based on a signal in which the request communication system is busy and a signal in which the response communication system is busy. 12. The multi-core system according to claim 7, wherein arbitration information is obtained. Among transfer data, an arbitration information adding unit that adds specific information to transfer data that needs to be transferred earliest;
An arbitration unit that performs arbitration with the highest priority given to transfer data to which specific information is added by the arbitration information addition unit, according to claim 1, 2, 6, or 7. The multi-core system according to any one of the above.

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