JP2012175635A - Image display control circuit, image display control method, and image display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display control circuit, an image display control method, and an image display system which reduce a crosstalk between right and left images without 3D eyeglasses.SOLUTION: An image display system 1 comprises an image control circuit 17 for a 3D image corresponding to a frame sequential system; a display device 14; and 3D eyeglasses 15. The image control circuit 17 comprises: a frame memory 13 for storing the right and left image; a PLL 18 which generates an output clock which is N-times (N is an integer of 2 or more) as large as the period of an input clock synchronizing with the frame rate of an input image; and a control circuit 11 which performs control to read the right and left images stored in the frame memory 13 with different rates of the number of frames, using the output clock.

Description

  The present invention relates to a 3D (stereoscopic) display image display control circuit, an image display control method, and an image display system, and more particularly to a frame sequential image display control circuit, an image display control method, and an image display system.

  The 3D display method using 3D glasses includes a frame sequential method for continuously displaying left and right images, a side-by-side method for displaying each column at the same time, and a line-by-line method for displaying each line at the same time. There are three types. There is a passive method in which left and right images are polarized on the display device side, and an active method in which the 3D glasses side performs.

  Here, a frame sequential 3D display device will be described. As described in Non-Patent Document 1, a right-eye image and a left-eye image are alternately displayed on the stereoscopic image display device. Only necessary images are transmitted to the left and right eyes through 3D glasses equipped with a passive polarization filter or an active liquid crystal shutter. As a result, the parallax between the left and right eyes is reproduced, and stereoscopic viewing is possible.

  FIG. 14 is a block diagram showing a conventional display system. The display system 100 includes an image control circuit 117, a display device 114, and 3D glasses 115. From the image control circuit, an image signal Pixel, a horizontal synchronization signal HS, a vertical synchronization signal VS, a left / right frame discrimination signal L / R, and a clock signal CLK are output to the display device 114.

  The display device 114 includes left and right image display circuits 105 and 106 and an output synchronization circuit 112. Input signals are Pixel × 2, HS × 2, VS × 2, L, R, and CLK × 2. In the case of the passive method, the outputs are left and right images having different polarizations modulated by the synchronous output circuit 112. The display images 105 and 106 are displayed on the same screen, but the direction of polarization is different. In the case of the active method, the outputs are the left and right image signals, and the left frame discrimination signal L and the right frame discrimination signal R that are modulated wirelessly (radio waves and infrared rays) by the output synchronization circuit 112. The output synchronization circuit 112 modulates the signal L / R wirelessly and outputs it. The wireless system uses invisible high-speed transmission means such as radio waves or infrared rays.

  The 3D glasses 115 include a right glasses shutter 104 and a left glasses shutter 103. The right eyeglass shutter 104 and the left eyeglass shutter 103 have different polarization directions, and have a deflection characteristic in phase with the left and right of the display device 114 when the signal L / R is ON. The shutter is a liquid crystal shutter. The right eyeglass shutter 104 has means for receiving a radio signal R transmitted from the output synchronization circuit 112 of the display device 114, and opens and closes in synchronization therewith. The left eyeglass shutter 103 has means for receiving a radio signal L transmitted from the output synchronization circuit 112 of the display device 114, and opens and closes in synchronization with this.

  FIG. 15 is a diagram for explaining the operation of the conventional image display system. The 2D image 108 and the 3D image 107 are similar images. That is, the output synchronization circuit 112 outputs a synchronization signal for opening and closing the right glasses shutter 104 and the left glasses shutter 103 in synchronization with the frame output of the right image and the left image of the input image (2D image). A right frame image is obtained through glasses, and a left frame image is obtained through left glasses.

Honda Ikuo (supervised), 3D image technology-latest trends in spatial expression media (Electronics Series), CMC Publishing Co., Ltd., July 31, 2008, first printing, pages 212-216

  FIG. 16 is a conceptual diagram showing a conventional 3D display image. On the display device, a frame sequential 3D image including parallax is displayed with a left eye image 105 and a right eye image 106 at a time ratio of 1: 1. From the left-right closed state of the left eyeglass shutter 103 and the right eyeglass shutter 104 of the 3D glasses, left open → left close → right open → right close →... As a result, the 3D viewer obtains the left and right 3D images 107 having a time ratio of 1: 1. Similarly, a 2D viewer who does not wear 3D glasses obtains a 2D image 108 including parallax.

  As described above, in the conventional 3D display image, since the moving images having the same luminance on the left and right are used, a 2D viewer who does not have 3D glasses cannot recognize an image with a large crosstalk (shift between left and right images). I will watch it. That is, the 3D moving image has the problem that without 3D glasses, the left and right images have the same brightness, and the images shifted by the amount of parallax appear to overlap, making it difficult to recognize as a 2D image.

  An image display control circuit according to the present invention is an image display control circuit for a 3D image corresponding to a frame sequential method, and the right and left images are displayed so that at least one of display times or luminances of the input left and right images is different from each other. It has a control circuit for controlling the output of an image.

  An image display control method according to the present invention is an image display control method for 3D images corresponding to a frame sequential method, and the left and right images are controlled so that at least one of display times or luminances of input left and right images is different from each other. It controls image output.

  An image display system according to the present invention includes an image display control circuit for 3D images corresponding to a frame sequential method, a display device that displays left and right images output from the image display control circuit, and synchronous control by the display device. 3D glasses having left and right eyeglass shutters, and the image display control circuit controls the output of the left and right images so that at least one of the display time or the luminance of the input left and right images is different from each other. It has a control circuit.

  In the present invention, in order to control the output of the left and right images so that at least one of the display time or the brightness of the input left and right images is different from each other, the 2D image when the display for 3D images is viewed without 3D glasses The shift between the left and right images can be reduced.

  According to the present invention, it is possible to provide an image display control circuit, an image display control method, and an image display system in which crosstalk between left and right images is reduced without 3D glasses.

1 is a block diagram illustrating an image display system according to a first embodiment of the present invention. It is a block diagram which shows the image input circuit in the image display system concerning Embodiment 1 of this invention. It is a block diagram which shows the frame memory in the image display system concerning Embodiment 1 of this invention. It is a figure which shows the timing chart of the frame memory in the image display system concerning Embodiment 1 of this invention. It is a block diagram which shows the image output circuit in the image display system concerning Embodiment 1 of this invention. It is a block diagram which shows the control circuit in the image display system concerning Embodiment 1 of this invention. It is a timing chart which shows the image format in the image display system concerning Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the image display system concerning Embodiment 1 of this invention. FIG. 9 is a conceptual diagram showing a display image according to the embodiment of the present invention. It is a block diagram which shows the display system concerning Embodiment 2 of this invention. It is a timing chart of the image system concerning Embodiment 2 of the present invention. It is a block diagram which shows the image display system concerning Embodiment 3 of this invention. It is a timing chart of the image display system concerning Embodiment 3 of the present invention. It is a block diagram which shows the conventional display system. It is a timing chart which shows operation | movement of the conventional image display system. It is a conceptual diagram which shows the conventional 3D display image.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a frame sequential stereoscopic image display system.

  In the present embodiment, the output of the left and right images is controlled so that at least one of the display time or luminance of the input left and right images is different from each other so as not to affect the 3D image display. As a result, even when the image is viewed in 2D, the phenomenon that the parallax is too large and the image is difficult to recognize is reduced.

Embodiment 1 of the present invention.
FIG. 1 is a block diagram showing an image display system according to the present embodiment. The image display system 1 includes an image control circuit 17, a display device 14, and 3D glasses 15. Signals between the image control circuit 17 and the display device 14 are electrically connected. A signal from the display device 14 to the 3D glasses 15 is transmitted by optical or electromagnetic means. In the present embodiment, the image control circuit 17 and the display device 14 are described as separate devices, but the image control circuit 17 may be included in the display device 14 as a matter of course.

  The image control circuit 17 controls the output of the left and right images so that the display times of the input left and right images are different from each other. In the present embodiment, the image control circuit 17 doubles the number of frames per unit time and converts the display ratio of the left and right images to 1: 3. The image control circuit 17 includes an image input circuit 10, an image frame memory 13, an image output circuit 16, a control circuit 11, a PLL 18 as a clock generation circuit, and a frequency divider circuit 19.

  The input signals are an image signal: Pixel, a horizontal synchronization signal: HS, a vertical synchronization signal: VS, a left / right frame discrimination signal: L / R, and a clock signal: CLK. The output signals are a left frame discrimination signal: L, a right frame discrimination signal: R, an image signal: Pixel × 2, a horizontal synchronization signal: HS × 2, a vertical synchronization signal: VS × 2, and a clock signal: CLK × 2. Note that x2 at the end of the signal name indicates that the frame rate is twice that of the input signal. Details of each block will be described below.

  First, the image input circuit 10 will be described. FIG. 2 is a block diagram showing the image input circuit 10. The image input circuit 10 includes a line buffer 31 (8 bits × 3), an address generation circuit 34, an RGB-YCbCr conversion circuit 32 (ITU-BT.601) as a first conversion circuit, and a 64-bit register (4 pixels × 16 bits). The input signals are image data: Pixel, horizontal synchronization signal: HS, clock signal: CLK, and four-frequency clock signal: CLK1 / 4. The output signal is image data for four pixels: Idata64.

  The address generation circuit 34 is reset at the rising edge of the horizontal synchronizing signal HS, counts the clock, and outputs the incremented address to the line buffer 31. The line buffer 31 receives the image signal: Pixel and outputs image data to the RGB-YCBCR conversion circuit 32 (ITU-BT.601). The RGB-YCBCR conversion circuit 32 converts the image data from RGB to YCBCR, compresses the data from 24 bits to 16 bits, and outputs the compressed data to the 64-bit register 33. The 64-bit register 33 collects four pixels, thereby converting the band from the frequency to the bus width and dropping the frequency.

  As described above, in the present embodiment, the RGB-YCbCr conversion circuit 32 is provided as a first conversion circuit for converting the input signal from the RGB signal to the YCbCr signal in the previous stage of the image frame memory 13. Then, a second conversion circuit (a YCbCr-RGB conversion circuit 35 to be described later) for converting the YCbCr signal into the RGB signal is provided at the subsequent stage of the image output circuit 16, that is, the image frame memory 13. As a result, the image data can be compressed, and the amount of image data stored in the image frame memory 13 can be reduced. That is, the memory capacity can be reduced.

  Next, the image frame memory 13 will be described. FIG. 3 is a block diagram showing the frame memory. The frame memory 13 includes a 2-port memory 42 for the left screen and a 2-port memory 41 for the right screen. Writing speed and reading speed are different, and reading is performed at double speed of writing. The input terminals are: input image data: Idata 64, frame write signal: FWR, left / right frame distinction signal: L / R, input address signal: IA, write clock signal: CLK 1/4, frame read signal: FRD, output left screen signal: L, output address signal: OA, read clock signal: CLK1 / 2. The output terminal is output image data: Odata64. FIG. 4 is a timing chart of the image frame memory 13.

  The left and right frame discrimination signal L / R and the output left screen signal L are used for selection of the left and right screen 2-port memory 41 by using the inverting circuits 43 and 44. The selector 45 selects and outputs the outputs of the right screen 2-port memory 41 and the left screen 2-port memory 42. The output image data Odata 64 of the frame memory 13 is connected to the input of the image output circuit 16.

  The image frame memory 13 outputs input image data: Idata 64 by a read clock signal CLK1 / 2 at a speed twice as fast as the write clock signal CLK1 / 4. Here, as shown in FIG. 4, in the present embodiment, the Hi period of the output left screen signal is three times the Low period. That is, when one frame of the right image is output, three frames of the left image are output.

  Next, the image output circuit 16 will be described. FIG. 5 is a block diagram showing the image output circuit 16. The image output circuit 16 includes a 64-bit register 36 (4 pixels × 16 bits), a YCbCr-RGB conversion circuit 35 (ITU-BT.601), a line buffer 37 (8 bits × 3) corresponding to RGB data, and an address generation circuit 38. The input signals are image data for four pixels: Idata64, horizontal synchronization signal: HS × 2, divide-by-2 clock: CLK1 / 2, and double-speed clock: CLK × 2. The output signal is image data: Pixel × 2.

  The 64-bit register 36 reads four pixels at a time, converts the band from the bus width to the frequency, and separates each pixel. The YCbCr-RGB conversion circuit 35 restores data from 16 bits to 24 bits by converting the image data from YCbCr signals to RGB signals, and outputs the data to the line memory 37. The line memory 37 stores the data of the YCbCr-RGB conversion circuit 35 for one line and outputs it as an image signal: Pixel × 2. The address generation circuit 38 is reset at the rising edge of HS × 2, outputs the address incremented by counting the clock CLK × 2 to the line memory 37.

  The PLL 16 of the image control circuit 17 multiplies the input clock CLK to generate a system clock. The image input clock and the system clock may be separated. For example, in the case of HDTV (1920 * 1080), 60 frames × 2 (left and right) + 5% blanking (the time required for HS (horizontal synchronization) and VS (vertical synchronization) signals is 5% of the total), 262 MHz. The image control circuit 17 uses the image output circuit 16 to read the right image for one frame from the left and right images from the image frame memory 13, and then repeatedly reads the same frame three times, thereby Read the image. In the present embodiment, the frame rate is set to double speed, and four frames of images are output while two frames of normal left and right images are output one frame at a time. At that time, one frame of the right image and three frames of the left image are output. Here, when one frame of the left and right images is output by one frame, the image output circuit 16 outputs the other frame by (2N−1) (N is an integer of 2 or more). That is, one frame is output as one frame, the other as five frames, one as one frame, and the other as seven frames. At this time, it is preferable that the clock used for reading is also N times the clock. As a result, even if the other display period of the left and right images is longer than the one display period, the frame rate does not slow down in 3D display.

  When viewing a 3D image, one frame and the other N frame may be displayed on the 3D glasses. That is, when displaying one frame of the right image and three frames of the left image (N = 2), the shutter of the 3D glasses is controlled so that the first frame of the right image and the second frame of the left image can be viewed. When displaying one frame of the right image and five frames of the left image (N = 3), the shutter of the 3D glasses is controlled so that the first frame of the right image and the third frame of the left image can be viewed. Similarly, when displaying one frame of the right image and seven frames of the left image (N = 4), the shutter of the 3D glasses is controlled so that the first frame of the right image and the fourth frame of the left image can be viewed.

  Next, the control circuit 11 will be described. FIG. 6 is a block diagram showing the control circuit 11. As described above, the control circuit 11 controls the image output circuit 16 to read out one frame of the right image and (2N−1) frames of the left image from the image frame memory 13, and the first timing to read out the right frame and First and second synchronization signals L and R at a second timing for reading the Nth frame of the left image are generated and supplied to the output synchronization circuit 12. The L and R signals are supplied to the 3D glasses 15 used by the user via the display device 14 to switch the shutters of the right glasses shutter 4 and the left glasses shutter 3.

  The control circuit 11 includes an address generation circuit 51 (for frame memory writing), an address generation circuit 52 (for frame memory reading), an IX counter 53, an IY counter 54, an OX counter 55, an OY counter 56, an X register (X-REG). ) 57, Y register (Y-REG) 58, HS × 2 generation circuit 59, VS × 2 generation circuit 60, frequency divider 61, VS × 2 counter 64, L register (L-REG) 62, R register (R -REG) 63, an L generation circuit 65, and an R generation circuit 66. Here, the VS × 2 counter 64 functions as a counter that counts the N-fold vertical synchronization signal, and the L generation circuit 65 serves as a first synchronization signal generation unit that generates a first synchronization signal based on the count value of the counter. The R generation circuit 66 functions as a second synchronization signal generation unit that generates a second synchronization signal based on the count value of the counter.

  The IX counter 53 counts the input clock CLK with the horizontal synchronization signal HS and outputs the number of X pixels to the X register 57. The value is cleared when the horizontal synchronization HS becomes L level. The X register 57 is a 19-bit register indicating the number of X pixels. When the value of the IX counter becomes small, the value is held. That is, the IX counter 53 counts CLK during the HS period, and resets the count when HS is inverted. Since the output value of the IX counter 53 becomes small at the time of resetting, the maximum value of the IX counter is stored in the X register 57.

  The IY counter 54 counts the horizontal synchronization HS with the vertical synchronization VS and outputs the number of Y pixels to the Y register 58. The Y register 58 is a 17-bit register indicating the number of Y pixels. Thus, the image size can be specified.

  The address generation circuit 51 (for frame memory input) generates control signals for the image input circuit 10 and the frame memory 13.

  The OX counter 55 counts the output CLK × 2 and resets it with HS × 2. The HS × 2 generation circuit 59 generates the horizontal synchronization signal HS × 2 by comparing the value of the OX counter 55 with the value of the X register 57 that is the number of X pixels. That is, since the X register 57 counts the value of the output CLK × 2, by generating half the timing of the IX counter 53 counting with CLK between the horizontal synchronization signals, the horizontal synchronization signal HS × 2 is generated.

  The OY counter 55 counts the horizontal synchronization signal HS × 2 and resets it with VS × 2. The VS × 2 generation circuit 60 generates a vertical synchronization signal VS × 2 by comparing the value of the OY counter 56 with the value of the Y register 58 that is the number of Y pixels. That is, the IY counter 54 counts the number of CLKs between the vertical synchronization signals, and the OY counter 56 counts the number of CLK × 2 and therefore generates a timing half the count period of the IY counter 54. Thus, the vertical synchronization signal VS × 2 is generated.

  The VS × 2 counter 64 is reset at the rising edge of L / R and counts VS × 2. That is, in this embodiment, 1 to 4 are counted. The output of the counter is input to the L generation circuit 65 and the R generation circuit 66.

  An L register 62 that holds the expected value of the counter is connected to the L generation circuit 65. The L generation circuit 65 compares the value of the VS × 2 counter 64 with the value of the L register 62 and outputs the result as a signal L.

  An R register 63 that holds an expected value of the counter is connected to the R generation circuit 66. The R generation circuit 66 compares the value of the VS × 2 counter 64 with the value of the R register 63 and outputs the result as a signal R.

  That is, according to the present embodiment, the L generation circuit 65 generates a Hi L signal when the counter value is 1, and the R generation circuit 66 generates a Hi R signal when the counter value is 3. To do. With this signal, the right glasses shutter 4 is opened during the display period of the right frame, and the left glasses shutter 3 is opened at the timing of the second frame among the left frames displayed in three frames.

  Next, the display device 14 shown in FIG. 1 will be described. The display device 14 includes display images 5 and 6 and an output synchronization signal 12. Input electric signals of the display device 14 are Pixel × 2, HS × 2, VS × 2, L, R, and CLK × 2. In the case of the passive method, the outputs are left and right images having different polarizations modulated by the synchronization output 12. The display images 5 and 6 are displayed on the same screen, but the directions of polarization are different. In the case of the active method, outputs are left and right images and signals L and R modulated wirelessly (radio waves and infrared rays) by the output synchronization circuit 12.

  In display images 5 and 6, the image signal: Pixel × 2 is displayed at a left-right frame ratio of 1: 3 in synchronization with the vertical synchronization signal VS × 2.

  The output synchronization signal 12 wirelessly modulates the signals L and R output from the image control circuit 17 and outputs them to the 3D glasses 15. The wireless system includes invisible high-speed transmission means such as radio waves or infrared rays.

  The 3D glasses 15 include a right glasses shutter 4 and a left glasses shutter 3. The right eyeglass shutter 4 and the left eyeglass shutter 3 have different polarization directions and are controlled to have the same phase deflection characteristics as the left and right sides of the display device when the signal L / R is ON (Hi). A liquid crystal shutter is used as the shutter. The right eyeglass shutter 4 has means for receiving a radio signal R transmitted from the output synchronization circuit 12 of the display device 14 by an invisible high-speed transmission means such as infrared rays, and opens and closes in synchronization with this. The left eyeglass shutter 3 has means for receiving a radio signal L transmitted from the output synchronization circuit 12 of the display device 14 by an invisible high-speed transmission means, and opens and closes in synchronization therewith.

  FIG. 7 is a timing chart showing an image format. It consists of pixel data Pixel, synchronization signal CLK, horizontal synchronization signal HS, vertical synchronization signal VS, and left and right frame distinction signal L / R. One cycle of the vertical synchronization signal VS is one frame of the image.

  Next, the image control method according to the present embodiment will be described. FIG. 8 is a timing chart showing the operation of the display system according to the present embodiment. In FIG. 8, a square frame in which L1, R1, etc. are written indicates that the data is one frame. The input is frame data composed of Pixel, HS, VS, and CLK, L indicates a left image, R indicates a right image, and numbers indicate time series.

  The input L image is held in the L area of the frame memory 13 based on the L / R signal. A retained image (41) and a retained image (42) indicate an R image written in the 2-port memory 41 and an L image written in the 2-port memory 42, respectively. When these L and R images are held for one frame, CLK × 2 in which CLK is doubled by the PLL 16 is used and read out from the frame memory 13 as an output image. As shown in the output 2D image 78, one frame is output at double speed in synchronization with the signal L.

  The input R image is held in the R region of the frame memory 13 based on the L / R signal. When the half is held, CLK × 2 obtained by doubling CLK by the PLL 16 is used and read out from the frame memory 13 as an output image. In synchronization with the inverted signal of the signal L, the same image is output for three frames as shown in the output 2D image 78. Each R image and L image is displayed in synchronization with the vertical synchronization signal VS × 2.

  Here, the signal interval between the input image signal and the output 2D image 78 is basically 2: 1. Note that the interval between the L1 signal and the R1 signal in the output 2D image 78 is the vertical synchronization signal VS × 2, and the intervals are the same. Further, each interval of the vertical synchronization signal VS × 2 is ½ of the vertical synchronization signal VS.

  Here, in the present embodiment, as shown in FIG. 6, the signal L and the signal R are generated based on the count value of the counter 64 that counts VS × 2 with the L / R signal reset. In the present embodiment, the case where the ratio of the left and right output frames is 1: 3 will be described.

  In this case, paying attention only to the lower 2 bits, the L generation circuit 65 is a signal L which becomes 1 when the counter value is the same as the value of the L register 62 and is 00 (when the second bit from the LSB becomes 0). This indicates the position of the L image. The R generation circuit 66 generates a signal R that becomes 1 when the counter value is 10, which is the same as the value of the R register 63 (when the second bit from the LSB becomes 1), and thereby outputs 3 frames continuously. The position of the second R image among the R images to be displayed is shown. Note that the ratio of the Hi width to the Low width for both the signals L and R is 1: 3. The phases of the signals L and R are shifted by ½ period.

  As a result, the output 2D image 8 is repeatedly displayed as L1 → R1 → R1 → R1 →... In this example, the output ratio of the number of left and right frames is 1: 3. In the control circuit 11 of FIG. 6, a signal L (left eyeglass synchronization signal) that becomes Hi when L1 is low and the other is Low, and a signal R that becomes Hi when the second R1 is low and the other is Low. (Right glasses synchronization signal) is generated. When the right / left ratio is 1: 7, the rising and falling of the third bit from the LSB may be used as a trigger. By making this selection variable using a register or the like, it is possible to flexibly cope with the left / right frame ratio.

  FIG. 9 is a conceptual diagram showing a display image according to the embodiment of the present invention. The output synchronization circuit 12 transmits the signals L and R to the right glasses shutter 4 and the left glasses shutter 3 of the 3D glasses 15, and the 3D viewer 71 obtains a 3D image 77.

  For the 2D viewer 72, the left-right frame ratio 1: 3 image 78, that is, the right image 76 is dominant, and the left image 75 is a noisy image.

  On the display device 14, a frame sequential 3D image including parallax, and a left eye image 75 and a right eye image 76 are displayed at a time ratio of 1: 3. The left eyeglass shutter 3 and the right eyeglass shutter 4 of the 3D glasses are repeated as left open → left close → right open → right close →. Thereby, the 3D viewer 71 obtains the left and right 3D images 77 having a time ratio of 1: 1. On the other hand, the 2D viewer 72 who does not wear the 3D glasses obtains the 2D image 78 with the left and right luminances of 1: 3 by performing time smoothing.

  In this embodiment, the input image to be input is a left-right 1: 1 image, but by saving this in the frame memory, the frame rate of the output image is doubled than the frame rate of the input image. increase. Then, by assigning the doubled frames uniformly to the right image, a continuous 2D image 78 of left: 1 frame and right: 3 frames can be obtained. When the frame rate is 60 Hz, which is sufficiently faster than human moving image recognition capability, the number of frames is time-smoothed and can be converted into luminance as it is. That is, it is possible to obtain an image in which the luminance ratio is enhanced by 3: 1 in the right frame. As a result, the 2D viewer 72 can reduce the crosstalk (in the left frame) to 1/3, and can recognize the image in the right frame as the main image.

  That is, in the present embodiment, the left and right images are distinguished based on one system of L / R signals in the input image, whereas left glasses synchronization 3 and right glasses synchronization, which are independent two systems of signals. 4 is generated with one frame width shifted by two frames in the output 2D image 78, the 3D viewer 71 can obtain a 3D image 77 having the same number of left and right frames from a 2D image 78 having a different number of left and right frames. it can.

  When the ratio of the number of left and right output frames is 1: 7, the stability of the 2D image 78 is emphasized. When the input image is HD and 120 Hz, the output 2D image 78 is HD and 240 Hz, and the output 3D image 77 is HD and 60 Hz.

  When the ratio of the number of left and right output frames is 1: 3, the stability of the 3D image 77 is emphasized. When the input image is HD and 120 Hz, the output 2D image 78 is HD and 240 Hz, and the output 3D image 77 is HD and 120 Hz.

  In the present embodiment, the right frame is displayed for a period three times longer than the left frame. As a result, the time-smoothed right frame is displayed with a brightness three times that of the left frame, and crosstalk of the 2D image is reduced. On the other hand, by doubling the frame rate, it is possible to display a 3D image in which the display timing of the left and right frames is the same as the original state.

Embodiment 2 of the present invention.
Next, a second embodiment of the present invention will be described. FIG. 10 is a block diagram showing a display system according to Embodiment 2 of the present invention. The image control circuit 17 according to the present embodiment includes an address generation circuit 25, a frame memory 24, a selector 23, an inversion circuit 26, an L counter 27, an L generation circuit 28, and an R generation circuit 29.

  In this embodiment, it has a frame memory 24 that holds only the right image, and has a selector 23 that selects either the through image signal or the image signal stored in the frame memory 24. Unlike the above-described first embodiment, no PLL is required because the number of frames is not doubled. The left and right image outputs may be reversed.

  The address generation circuit 25 uses HS and VS as enable signals, counts the number of CLKs, and generates an address of the frame memory 24 for storing the image data Pixel in the frame memory 24. Addressing is performed only when the inverted signal of the L / R signal is 1.

  The selector 23 selects the left and right images based on the output signal of the R generation circuit 29. That is, in the case of the left image, a Pixel through image is selected, and in the case of the right image, the retained image is read from the frame memory 24.

  When the input image is the right image, the frame memory 24 stores the image data, thereby realizing the second and third image output of the right image data. The output of the frequency dividing circuit 30 that divides the L / R signal by two is input to the L2 bit counter 27, and the number of VSs during the period in which the L / R signal is divided into two periods is counted. The L generation circuit 28 outputs an L signal when the value of the L2bit counter is 00. The R generation circuit 29 outputs an R signal when the value of the L2bit counter is 10.

  FIG. 11 is a timing chart of the image system according to the present embodiment. As in FIG. 8, a square indicates one frame. The input right image is held in the frame memory 24 at the falling edge of the L / R signal. In accordance with the R signal, a retained image (24) (right frame) or a through image (left frame) is selected to obtain a 2D image 68 in which the number of left and right frames is 1: 3. Also in the present embodiment, crosstalk can be reduced by setting the output period of the right frame to be three times that of the left frame. On the other hand, by controlling the left and right eyeglass shutters so that the left and right frames are displayed at equal timing by the L and R signals, the user can view the 3D image without any trouble.

  Note that. When the input image is HDTV, 120 Hz, the output 2D image 8 is HDTV, 120 Hz, and the output 3D image 7 is HDTV, 60 Hz. Since the number of frames is reduced to ½, the smoothness is inferior, but the circuit scale is reduced, so that the cost can be reduced.

Embodiment 3 of the present invention.
Next, a third embodiment of the present invention will be described. FIG. 12 is a block diagram showing an image display system according to Embodiment 3 of the present invention. The image control circuit 17 according to the present embodiment includes an RGB-YCbCr conversion circuit 20 that converts an input image from RGB to YCbCr, a right image luminance control circuit 85 that reduces only the luminance Y of the entire right image frame by half, A YCbCr-RGB conversion circuit 21 that converts an internally processed image from YCbCr to RGB and a control circuit 86.

  The 3D glasses 15 have the 3D glasses 15 in which the light transmittance of the right glasses 84 is twice as bright as that of the left glasses 23 so as to store the right image luminance control circuit 85. Conversely, the light transmittance of the left spectacles 83 may be realized by halving that of the right spectacles 24. 1/2 and 2 are convenient, and are actually determined depending on the transmittance of the deflection lens. Therefore, the left-right master-slave relationship of the 2D image 78 depends on the luminance ratio. Unlike the first embodiment, there is no change in the number of frames, so that no PLL is required. Instead of the right image luminance control circuit 85, the left image luminance control may be performed as a left image luminance control circuit.

  FIG. 13 is a timing chart of the image display system according to the third embodiment of the present invention. As in FIG. 8, the square represents one frame, and the height represents luminance or transmittance. The input image is the right image luminance control circuit 85, and the luminance of only the right image is halved. As a result, 2D images 78 with different left and right luminances are obtained. By setting the brightness of the left lens of the 3D glasses 23 to be 1/2 of that of the right lens, the luminance is reduced to 1/2 when only the left image is passed through the 3D glasses. As a result, a 3D image 77 having a luminance of 1/2 is obtained for the left and right images.

  In the present embodiment, the crosstalk between the left and right images can be reduced by changing the luminance of the left and right images of the 2D image 78 to 2: 1. In the 3D image 77, by changing the transmittance of the left and right lenses of the 3D glasses, the left and right luminance becomes 1: 1, and there is no hindrance to 3D image display.

  In the present embodiment, an RGB-YCbCr conversion circuit 20 serving as a first conversion circuit that converts an input signal from an RGB signal to a YCbCr signal and a right image luminance control circuit are provided in the preceding stage of the right image luminance control circuit 85. 85 is provided with a YCbCr-RGB conversion circuit 21 as a second conversion circuit for converting the YCbCr signal into the RGB signal. As a result, the brightness control signal can be generated by compressing the data, and the processing speed is increased.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the method of changing the left and right luminances as in the third embodiment is not applied to the image control circuit 17 in the passive method, and the polarizing plate is arranged in front of the screen when displaying on the image displays 5 and 6. It is also possible to realize this by switching the transmittance of the left and right.

  Furthermore, in the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and arbitrary processing may be realized by causing a CPU (Central Processing Unit) to execute a computer program. Is possible. In this case, the computer program can be stored using various types of non-transitory computer readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W and semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (random access memory)) are included. The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

DESCRIPTION OF SYMBOLS 1 Image display system 3 Left spectacle shutter 4 Right spectacle shutter 5, 6 Display image 10 Image input circuit 11 Control circuit 12 Output synchronization circuit 13 Image frame memory 14 Display apparatus 15 3D glasses 16 Image output circuit 17 Image control circuit 18 PLL
19 Dividing circuit 31 Line buffer 32 RGB-YCbCr conversion circuit 33 64 bit register 34 Address generating circuit 41, 42 2-port memory 51 Address generating circuit 52 Address generating circuit 53 IX counter 54 IY counter 55 OX counter 56 OY counter 57 X register 58 Y register 59 HS × 2 generating circuit 60 VS × 2 generating circuit 61 Dividing circuit 64 VS × 2 counter 62 L register 63 R register 65 L generating circuit 66 R generating circuit HS horizontal synchronizing signal VS vertical synchronizing signal Pixel image data CLK clock CLK1 / 4 divided by 4 clock

Claims (17)

An image display control circuit for 3D images corresponding to a frame sequential method,
An image display control circuit having a control circuit for controlling the output of the left and right images so that at least one of the display times or luminances of the input left and right images is different from each other. It has a frame memory that stores only one of the left and right images,
2. The image display control circuit according to claim 1, wherein the control circuit controls the read timing of the one image stored in the frame memory to make the output time of the one image longer than the other image. A frame memory for storing left and right images;
A clock generation circuit for generating an output clock obtained by multiplying the period of the input clock synchronized with the frame rate of the input image by N (N is an integer of 2 or more);
The image display control circuit according to claim 1, wherein the control circuit reads the left and right images stored in the frame memory at a ratio of a different number of frames using the output clock.   4. The image display control circuit according to claim 3, wherein the control circuit controls to read out one frame of the left and right images from the frame memory and then to read out (2N−1) frames of the other image. 5. . The control circuit generates a first synchronization signal and a second synchronization signal respectively for a first timing for reading the one image and a second timing for reading the Nth frame of the other image;
The image display control circuit according to claim 4, wherein the first and second synchronization signals are supplied to 3D image glasses used by a user via a display device.   The control circuit generates an N-fold vertical synchronization signal obtained by multiplying a period of the vertical synchronization signal by N times based on the output clock, and generates the first and second synchronization signals based on the N-fold vertical synchronization signal. The image display control circuit according to claim 5. The control circuit includes:
A counter for counting the N-fold vertical synchronization signal;
A first synchronization signal generation unit that generates the first synchronization signal based on a count value of the counter;
The image display control circuit according to claim 6, further comprising: a second synchronization signal generation unit that generates the second synchronization signal based on a count value of the counter. A luminance control circuit that changes the luminance of one of the left and right images;
The image display control circuit according to claim 1, wherein the control circuit alternately outputs one image whose luminance is controlled by the luminance control circuit and the other image whose luminance is not controlled. A first conversion circuit that converts an input signal from an RGB signal to a YCbCr signal is provided in the previous stage of the frame memory or the luminance control circuit,
9. The image display control circuit according to claim 3, further comprising a second conversion circuit that converts the YCbCr signal into the RGB signal at a subsequent stage of the frame memory or the luminance control circuit. 10. An image display control method for 3D images corresponding to a frame sequential method,
An image display control method for controlling output of left and right images so that at least one of display times or luminances of input left and right images is different from each other.   The image display control according to claim 10, wherein an output clock obtained by multiplying an input clock cycle by N (N is an integer of 2 or more) is used, and the left and right images stored in the frame memory are read at a ratio of different frame numbers. Method.   12. The image display control method according to claim 11, wherein one frame of the left and right images is read from the frame memory and then the other image is read out by (2N−1) frames. Generating first and second synchronization signals of a first timing for reading the one image and a second timing for reading the Nth frame of the other image, respectively;
The image display control method according to claim 12, wherein the first and second synchronization signals are supplied to 3D image glasses used by a user via a display device. Based on the output clock, an N-fold vertical synchronization signal is generated by multiplying the period of the vertical synchronization signal by N times
The image display control method according to claim 13, wherein a synchronization signal supplied to 3D image glasses used by a user via a display device is generated based on the N-fold vertical synchronization signal.   10. An image display semiconductor integrated circuit on which the image display control circuit according to claim 1 is mounted.   An image display device on which the semiconductor integrated circuit for image display according to claim 16 is mounted. An image display control circuit for 3D images corresponding to the frame sequential method;
A display device for displaying left and right images output from the image display control circuit;
3D glasses having left and right eyeglass shutters synchronously controlled by the display device,
The image display control circuit includes a control circuit that controls output of the left and right images so that at least one of display times or luminances of the input left and right images is different from each other.

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