JP2012175532A - Amplification circuit, and reception device and communication device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplification circuit that controls a gain in response to a variation in the amplitude of an input signal.SOLUTION: The amplification circuit includes: a variable gain amplifier circuit 10 for amplifying a first signal S1 input thereinto to output a second signal S2; a detection circuit 20 for detecting the first signal S1 to output a third signal S3; and a converter circuit 30 for receiving the third signal S3 to output a fourth signal S4 having a voltage varying exponentially relative to the voltage of the third signal S3, and controls the gain of the variable gain amplifier circuit 10 with the fourth signal S4. Even when the amplitude of the first signal S1 input varies greatly, the amplification circuit can control the gain in response to the variation in the amplitude of the first signal S1. This can reduce a variation in the amplitude of the second signal S2 even when the amplitude of the first signal S1 varies greatly.

Description

  The present invention relates to an amplifying circuit, a receiving apparatus and a communication apparatus using the same, and more particularly to an amplifying circuit whose gain is automatically controlled and a receiving apparatus and a communication apparatus using the amplifying circuit.

  Conventionally, in a receiving circuit, an amplifier circuit whose gain is automatically controlled has been used in order to keep the level of an input signal to the demodulator constant. As such an amplifier circuit, one using a feedforward circuit that detects an input signal to the amplifier circuit with a detection circuit and uses the output signal from the detection circuit to control the gain of the variable gain amplifier circuit is known. (For example, see Patent Document 1).

JP 2006-333111 A

  In the conventional amplifier circuit using the feedforward circuit, the change in the voltage of the output signal from the detection circuit cannot follow the sudden change in the amplitude of the input signal due to the parasitic capacitance etc. of the detection circuit. There was a problem that there was something. As a result, there has been a problem that the gain change of the variable gain amplifier circuit cannot follow the change of the amplitude of the input signal, and the amplitude of the output signal from the amplifier circuit varies greatly.

  The present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide an amplifier circuit capable of controlling gain in accordance with fluctuations in the amplitude of an input signal, and a receiving apparatus using the same. And providing a communication device.

  A first amplifier circuit of the present invention includes a variable gain amplifier circuit that amplifies an input first signal and outputs a second signal, a detection circuit that detects the first signal and outputs a third signal, A conversion circuit that receives the third signal and outputs a fourth signal having a voltage that exponentially changes with respect to the voltage of the third signal, and the variable gain amplification using the fourth signal The gain of the circuit is controlled.

  According to a second amplifier circuit of the present invention, in the first amplifier circuit, the conversion circuit includes an NMOS transistor and first and second PMOS transistors, and the source terminal of the NMOS transistor is a reference. The third signal is input to the back gate terminal, the gate terminal and the drain terminal of the first PMOS transistor are connected to the NMOS transistor. The second PMOS transistor has a gate terminal connected to the gate terminal of the first PMOS transistor, and a source terminal connected to the power supply potential. The drain terminal is connected to a reference potential via a resistor, and the drain It is characterized in that outputs the fourth signal from the down terminal.

The receiving circuit of the present invention includes the first amplifier circuit, a frequency converting circuit that converts the frequency of the received signal and outputs the signal as the first signal, and a demodulating circuit that demodulates the second signal. It is characterized by.

  The receiving apparatus of the present invention includes the receiving circuit and an antenna connected to the receiving circuit.

  The communication apparatus of the present invention includes the receiving circuit, an antenna connected to the receiving circuit, and a transmitting circuit connected to the antenna.

  According to the amplifier circuit of the present invention, it is possible to obtain an amplifier circuit capable of controlling the gain in accordance with the fluctuation of the amplitude of the input signal.

  According to the receiving apparatus of the present invention, it is possible to obtain a receiving apparatus that can accurately demodulate a received signal even if the amplitude of the received signal varies.

  According to the communication device of the present invention, it is possible to obtain a communication device that can accurately demodulate a received signal even if the amplitude of the received signal varies.

It is a block diagram which shows the amplifier circuit of the 1st example of embodiment of this invention. FIG. 2 is a circuit diagram of a conversion circuit in FIG. 1. It is a block diagram which shows the receiver of the 2nd example of embodiment of this invention. It is a block diagram which shows the communication apparatus of the 3rd example of embodiment of this invention. It is a graph which shows the simulation result of the amplifier circuit of the 1st example of embodiment of this invention. It is a graph which shows the simulation result of the amplifier circuit of a comparative example. It is a graph which shows the input signal in simulation.

  Hereinafter, an amplifier circuit of the present invention will be described in detail with reference to the accompanying drawings.

(First example of embodiment)
FIG. 1 is a block diagram showing an amplifier circuit according to a first example of the embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of the conversion circuit in FIG.

  As shown in FIG. 1, the amplifier circuit of this example includes a terminal 1, a terminal 2, a variable gain amplifier circuit 10, a detection circuit 20, and a conversion circuit 30.

  The first signal S1 is input to the terminal 1 from an external circuit (not shown). The variable gain amplifier circuit 10 is connected to the terminals 1 and 2 and outputs a second signal S2 obtained by amplifying the first signal S1 input from the terminal 1 to the terminal 2.

  The detection circuit 20 is connected to the terminal 1 and the conversion circuit 30, detects the first signal S <b> 1 input from the terminal 1, and outputs the third signal S <b> 3 to the conversion circuit 30. In the amplification circuit of this example, the detection circuit 20 outputs a third signal S3 having a voltage that increases or decreases in reverse to the increase or decrease of the amplitude of the first signal S1.

The conversion circuit 30 is connected to the detection circuit 20 and the variable gain amplification circuit 10, and receives a third signal S3 from the detection circuit 20, and generates a voltage that changes exponentially with respect to the voltage of the third signal S3. The fourth signal S4 having the same is output to the variable gain amplifier circuit 10. The fourth signal S4 is input to a control terminal (not shown) of the variable gain amplifier circuit 10, and the gain of the variable gain amplifier circuit 10 is controlled by the fourth signal S4.

  Thus, in the amplification circuit of this example, the gain of the variable gain amplification circuit 10 is controlled using the fourth signal S4 output from the conversion circuit 30. Similar to the voltage of the third signal S3, the voltage of the fourth signal S4 increases and decreases opposite to the increase and decrease of the amplitude of the first signal S1. For this reason, by controlling the gain of the variable gain amplifier circuit 10 using the fourth signal S4, the gain of the variable gain amplifier circuit 10 increases or decreases inversely with the increase or decrease of the amplitude of the first signal S1. Thereby, even when the amplitude of the first signal S1 input to the amplifier circuit varies greatly, the variation of the amplitude of the second signal S2 output from the amplifier circuit can be reduced.

  When the third signal S3 output from the detection circuit 20 is directly input to the variable gain amplifier circuit 10 and the gain of the variable gain amplifier circuit 10 is controlled by the third signal S3 as in the conventional amplifier circuit, The following problems may occur. That is, there is a problem that the waveform of the third signal S3 output from the detection circuit 20 becomes dull due to a parasitic capacitance or the like that the detection circuit 20 has. As a result, when the amplitude of the first signal S1 changes suddenly, the change in the voltage of the third signal S3 cannot follow the change in the amplitude of the first signal S1, and the variable gain is changed to the change in the amplitude of the first signal S1. A change in gain of the amplifier circuit 10 cannot follow. The sudden change in the amplitude of the input first signal S1 cannot be canceled out by the change in the gain of the variable gain amplifier circuit 10, and the change in the amplitude of the second signal S2 output from the amplifier circuit becomes large. End up.

  The amplifier circuit of this example inputs the third signal S3 output from the detection circuit 20 to the conversion circuit 30, and controls the gain of the variable gain amplifier circuit 10 using the fourth signal S4 output from the conversion circuit 30. . Since the fourth signal S4 has a voltage that changes exponentially with respect to the voltage of the third signal S3, the waveform of the fourth signal S4 is blunt even when the waveform of the third signal S3 is blunt. Becomes smaller. Therefore, the voltage of the fourth signal S4 changes following a sudden change in the amplitude of the first signal S1 than the voltage of the third signal S3. Therefore, by controlling the gain of the variable gain amplifier circuit 10 using the fourth signal S4, the gain of the variable gain amplifier circuit 10 can be changed in response to a sudden change in the first signal S1, so that the output The change in the amplitude of the second signal S2 can be reduced.

  Thus, according to the amplifier circuit of this example, it is possible to obtain an amplifier circuit whose gain can be controlled in accordance with a change in the amplitude of the input first signal S1.

  In the amplification circuit of this example, a known detection circuit such as a detection circuit using a mixer can be preferably used as the detection circuit 20.

  Further, in the amplifier circuit of this example, the example in which the detection circuit 20 outputs the third signal S3 having a voltage that increases / decreases inversely with respect to the increase / decrease of the amplitude of the first signal S1 has been shown, but the present invention is not limited thereto. It is not something. The detection circuit 20 may output the third signal S3 having a voltage that increases or decreases in the same manner as the amplitude of the first signal S1. In such a case, for example, the fourth signal S4 is subtracted from the reference signal to generate the fifth signal. Since the voltage of the fifth signal increases or decreases opposite to the increase or decrease of the amplitude of the first signal S1, the amplitude of the first signal S1 is increased or decreased by controlling the gain of the variable gain amplifier circuit 10 using the fifth signal. Conversely, the variable gain amplifier circuit 10 can be controlled so that the gain increases or decreases.

  FIG. 2 is a circuit diagram showing an example of the conversion circuit 30 in FIG. As shown in FIG. 2, the conversion circuit 30 includes an NMOS transistor 33, PMOS transistors 35 and 36, a voltage source 34, a resistor 37, and terminals 31 and 32.

  The NMOS transistor 33 has a source terminal connected to a reference potential (ground potential) and a gate terminal connected to a reference potential (ground potential) via a voltage source 34. The back gate terminal is connected to the terminal 31, and the third signal S3 is input from the terminal 31 to the back gate terminal.

  The PMOS transistor 35 has a gate terminal and a drain terminal connected to the drain terminal of the NMOS transistor 33 and a source terminal connected to the power supply potential Vdd.

  The PMOS transistor 36 has a gate terminal connected to the gate terminal of the PMOS transistor 35, a source terminal connected to the power supply potential Vdd, and a drain terminal connected to the reference potential (ground potential) via the resistor 37. Yes. The drain terminal of the PMOS transistor 36 is connected to the terminal 32, and the fourth signal S 4 is output from the drain terminal of the PMOS transistor 36 to the terminal 32.

  The operation of the conversion circuit 30 having such a configuration will be described. The present inventors have found that when the voltage applied to the back gate terminal of the NMOS transistor is sufficiently small, the drain current of the NMOS transistor changes exponentially with respect to the voltage applied to the back gate terminal. Therefore, when the third signal S3 is input from the terminal 31 to the back gate terminal of the NMOS transistor 33, the drain current of the NMOS transistor 33 becomes a current that changes exponentially with respect to the voltage of the third signal S3.

  The drain terminal of the NMOS transistor 33 is connected to the drain terminal of the PMOS transistor 35, and the drain current of the PMOS transistor 35 is also equal to the drain current of the NMOS transistor 33. Since the drain terminals of the PMOS transistors 35 and 36 are connected to form a current mirror circuit, the drain current of the NMOS transistor 33 is copied to the drain current of the PMOS transistor 36.

  Then, the drain current of the PMOS transistor 36 flows through the resistor 37, whereby a voltage is generated across the resistor 37. This voltage becomes a voltage that changes exponentially with respect to the voltage of the third signal S3 input from the terminal 31, and the fourth signal S4 having this voltage is output from the terminal 32.

(Second example of embodiment)
FIG. 3 is a block diagram showing a receiving apparatus according to a second example of the embodiment of the present invention. As shown in FIG. 3, the receiving apparatus of this example includes an antenna 71 and a receiving circuit 72 connected to the antenna. The reception circuit 72 includes a high frequency amplification circuit 73, a frequency conversion circuit 74, an amplification circuit 75 of the first example of the embodiment of the present invention, and a demodulation circuit 76.

  The high frequency amplifier circuit 73 is connected to the antenna 71 and amplifies and outputs the received signal. The frequency conversion circuit 74 converts the frequency of the amplified received signal and outputs it as the first signal S1. The amplifier circuit 75 amplifies the first signal S1 and outputs a second signal S2 having a constant amplitude. The demodulation circuit 76 demodulates the input second signal S2. According to the receiving apparatus of this example having such a configuration, even when the amplitude of the received signal fluctuates greatly, the fluctuation of the signal level input to the demodulation circuit 76 can be reduced. A receiving apparatus capable of accurately demodulating the received signal even when the frequency fluctuates can be obtained.

In the receiving circuit 72 of this example, an example in which the received signal from the antenna 71 is amplified by the high frequency amplifier circuit 73 and then input to the frequency conversion circuit 74 is shown, but the present invention is not limited to this. When the intensity of the received signal is sufficient, the received signal from the antenna 71 may be input to the frequency conversion circuit 74 as it is. Further, other circuits may be interposed between the respective circuits.

(Third example of embodiment)
FIG. 4 is a block diagram showing a communication apparatus according to a third example of the embodiment of the present invention. Note that in this example, only differences from the receiving apparatus of the second example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.

  As shown in FIG. 4, the communication apparatus of this example includes a reception circuit 72, an antenna 71 connected to the reception circuit, and a transmission circuit 77 connected to the antenna 71. An antenna sharing circuit 78 is inserted between the receiving circuit 72 and the transmitting circuit 77 and the antenna 71. That is, the receiving circuit 72 and the transmitting circuit 77 are connected to the antenna 71 via the antenna sharing circuit 78. According to the communication apparatus of this example having such a configuration, it is possible to obtain a communication apparatus that can accurately demodulate the reception signal even if the amplitude of the reception signal varies.

  The electrical characteristics in the amplifier circuit of the first example of the embodiment of the present invention shown in FIG. 1 were calculated by circuit simulation. In this simulation, the input signal (first signal S1) to the terminal 1 has a carrier frequency of 0.7 GHz, a carrier power of −10 dBm, a modulation frequency of 20 MHz, and a modulation index of 0.99. An AM modulated wave was used. The detection circuit 20 is a detection circuit having a Linear in dB characteristic that outputs a detection voltage that increases and decreases inversely with the increase and decrease of the amplitude of the input signal (first signal S1). The conversion circuit 30 converts the voltage waveform exponentially without changing the maximum and minimum voltage amplitudes of the third signal S3 output from the detection circuit 20.

  The result of this simulation is shown in the graph of FIG. Further, the graph of FIG. 6 shows a simulation result of the amplifier circuit of the comparative example in which the conversion circuit 30 is removed from the amplifier circuit shown in FIG. The input signal (first signal S1) in each simulation is shown in the graph of FIG. In each graph, the horizontal axis represents time, and the vertical axis represents voltage.

  According to the graph of FIG. 6, it can be seen that the change in gain cannot follow the change in amplitude of the input signal (first signal S1), and the amplitude of the output signal (second signal S2) varies greatly. On the other hand, according to the graph shown in FIG. 5, it can be seen that the change in the amplitude of the output signal is reduced by controlling the gain of the amplifier circuit following the fluctuation of the amplitude of the input signal. Thereby, the effectiveness of the present invention was confirmed.

10: Variable gain amplifier circuit 20: Detector circuit 30: Converter circuit 33: NMOS transistor 35, 36: PMOS transistor 34: Voltage source 71: Antenna 72: Receiver circuit 74: Frequency converter circuit 75: Amplifier circuit 76: Demodulator circuit 77: Transmitter circuit

Claims (5)

A variable gain amplifier circuit that amplifies the input first signal and outputs the second signal;
A detection circuit for detecting the first signal and outputting a third signal;
A conversion circuit that receives the third signal and outputs a fourth signal having a voltage that changes exponentially with respect to the voltage of the third signal;
An amplifier circuit, wherein the gain of the variable gain amplifier circuit is controlled using the fourth signal. The conversion circuit includes an NMOS transistor and first and second PMOS transistors,
The NMOS transistor has a source terminal connected to a reference potential, a gate terminal connected to a reference potential via a voltage source, and the third signal input to a back gate terminal,
The first PMOS transistor has a gate terminal and a drain terminal connected to the drain terminal of the NMOS transistor, a source terminal connected to a power supply potential, and the second PMOS transistor has a gate terminal connected to the first terminal. The PMOS transistor is connected to the gate terminal, the source terminal is connected to the power supply potential, the drain terminal is connected to the reference potential via a resistor, and the fourth signal is output from the drain terminal. The amplifier circuit according to claim 1. An amplifier circuit according to claim 1;
A frequency conversion circuit that converts the frequency of the received signal and outputs the first signal as the first signal;
A receiving circuit comprising: a demodulating circuit for demodulating the second signal. A receiving circuit according to claim 3;
A receiving apparatus comprising: an antenna connected to the receiving circuit. A receiving circuit according to claim 3;
An antenna connected to the receiving circuit;
And a transmission circuit connected to the antenna.

Images