JP2012175420A - Constant current circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constant current circuit that has a small variation in current value.SOLUTION: P-channel transistors 3, 9 function as first and second constant current sources for outputting proportional constant currents. A capacitor 5 is connected in series with the P-channel transistor 3. An N-channel transistor 6 as a discharge switch periodically discharges the capacitor 5 of a stored charge. A comparator 7 turns on P-channel transistors 4, 10 to output the currents from the first and second constant current sources as long as a charge voltage V1 of the capacitor 5 is within a reference voltage Va. A smoothing circuit 19 comprising a capacitor 11, a resistance 12 and a capacitor 13 smooths the output current of the second constant current source. An output current mirror comprising N-channel transistors 14, 15 outputs a current proportional to the current smoothed by the smoothing circuit 19.

Description

  The present invention relates to a constant current circuit used for various analog circuits and the like.

  As a constant current circuit that is commonly used, there is known a configuration in which a voltage between both ends of a reference resistor is made constant and a current proportional to a current flowing through the reference resistor is output by a current mirror. FIG. 6 is a circuit diagram showing a configuration example of a constant current circuit using this type of reference resistance. In this constant current circuit, P-channel MOS (Metal Oxide Semiconductor) field effect transistors (hereinafter simply referred to as transistors) 21 and 22 constitute a current mirror. Here, the P channel transistors 21 and 22 are respectively formed in an N well which is an N type isolated region formed in a P type semiconductor substrate. The source of the P channel transistor 21 and the N well in which the P channel transistor 21 is formed are connected to the power supply VDD. The source of the P-channel transistor 22 and the N-well in which the P-channel transistor 22 is formed are also connected to the power supply VDD. In this example, P-channel transistors 21 and 22 have the same transistor size. The reference resistor 23 has a resistance value r and is interposed between the drain of the P-channel transistor 21 and the ground line. In the comparator 24, the voltage at the common connection point of the resistor 23 and the drain of the P-channel transistor 21 is applied to the inverting input terminal, and the reference voltage Vref is applied to the non-inverting input terminal. The output voltage of the comparator 24 is applied to the gates of the P channel transistors 21 and 22. The drain of the P channel transistor 22 is the output terminal of this constant current circuit.

  According to this configuration, the comparator 24 controls the voltage applied to the gates of the P-channel transistors 21 and 22 so that the voltage across the reference resistor 23 becomes the reference voltage Vref. As a result, the current Vref / r flows through the reference resistor 23 and the P-channel transistor 21, and the current I = Vref / r is output from the P-channel transistor 22 that forms a current mirror together with the P-channel transistor 21. A constant current circuit using such a reference resistor is disclosed in, for example, Patent Document 1.

JP-A-6-282338

  In the constant current circuit using the reference resistor described above, the accuracy of the constant current depends on the accuracy of the resistance value of the reference resistor. However, when the reference resistor is formed in the semiconductor integrated circuit, there is a variation of ± 20% in the resistance value, so that it is difficult to make the variation of the constant current obtained by the constant current circuit 20% or less. was there.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a constant current circuit with small variations in current value.

  The present invention initializes the charging voltage of the capacitor in synchronization with the first and second constant current sources that output a constant current proportional to each other, the capacitor, and a periodic clock, and after the initialization, Charging or discharging of the capacitor by the first constant current source is started, and charging of the capacitor by the first constant current source is performed until an amount of change in the charging voltage of the capacitor due to charging or discharging reaches a reference voltage. Or a control circuit that repeats an operation to continue discharging and continue output of current from the second constant current source only while continuing to charge or discharge the capacitor by the first constant current source; And a smoothing circuit for smoothing the output current of the constant current source.

  According to this invention, the constant current is output from the second constant current source to the smoothing circuit during the period until the charging voltage of the capacitor is changed by the reference voltage by charging or discharging by the first constant current source. . For this reason, the average current supplied from the second constant current source to the smoothing circuit includes the reference voltage, the capacitance value of the capacitor, the cycle of charging or discharging the capacitor, the first current source, and the second current. The constant current is determined by the current ratio with the source, and a constant current corresponding to this average current is output from the smoothing circuit. Here, when the capacitor and the resistor are formed in the semiconductor integrated circuit, the variation in the capacitance value of the capacitor can be made smaller than the variation in the resistance value. Therefore, it is possible to realize a constant current circuit with higher current value accuracy than a constant current circuit using a reference resistor.

1 is a circuit diagram showing a configuration of a constant current circuit according to a first embodiment of the present invention. It is a time chart which shows the waveform of each part of an identification current circuit. It is a circuit diagram which shows the structure of the constant current circuit which is 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the constant current circuit which is 3rd Embodiment of this invention. It is a time chart which shows the waveform of each part of an identification current circuit. It is a circuit diagram which shows the structural example of the conventional constant current circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of a constant current circuit according to a first embodiment of the present invention. In FIG. 1, N-channel transistors 6, 14, and 15 are each formed on a P-type semiconductor substrate. The P-type semiconductor substrate is fixed at the ground potential. P-channel transistors 1, 3, 4, 9 and 10 are formed in N wells which are isolated N-type impurity regions formed in a P-type semiconductor substrate.

  P-channel transistor 1 and constant current source 2 are inserted in series between power supply VDD and the ground line. More specifically, the source of the P channel transistor 1 and the N well to which the P channel transistor 1 belongs are connected to the power source VDD, and the gate and drain of the P channel transistor 1 are connected in common. A constant current source 2 having a current value Ia is interposed between the common connection point of the gate and drain of the P-channel transistor 1 and the ground line. The constant current source 2 may have a configuration using a resistor such as the constant current circuit shown in FIG. A feature of this embodiment is that a high-accuracy output current IOUT can be obtained from a constant current circuit even if the current accuracy of the constant current source 2 is not good. The reason why a highly accurate output current IOUT can be obtained even if the current of the constant current source 2 is not accurate will be described later.

  P-channel transistors 1 and 3 constitute a first current mirror. More specifically, the source of the P channel transistor 3 and the N well to which the P channel transistor 3 belongs are connected to the power supply VDD, and the gate of the P channel transistor 3 is connected to the common connection point of the gate and drain of the P channel transistor 1. ing. The drain of the P-channel transistor 3 is the current output terminal of the first current mirror.

  P-channel transistors 1 and 9 form a second current mirror. More specifically, the source of the P channel transistor 9 and the N well to which the P channel transistor 9 belongs are connected to the power supply VDD, and the gate of the P channel transistor 9 is connected to the common connection point of the gate and drain of the P channel transistor 1. ing. The drain of the P channel transistor 9 is the current output terminal of the second current mirror.

  Here, P-channel transistors 1, 3 and 9 have the same channel length. When the channel width of the P channel transistor 1 is W, the channel width of the P channel transistor 3 is W, and the channel width of the P channel transistor 9 is nW (n is an arbitrary constant). Therefore, the P-channel transistor 3 functions as a constant current source having a current value Ia, and the P-channel transistor 9 functions as a constant current source having a current value nIa. Thus, in this embodiment, the P-channel transistors 3 and 9 function as first and second constant current sources that output constant currents proportional to each other.

  The capacitor 5 has a capacitance value C, and one electrode is grounded. The drain of the P-channel transistor 4 that is the first switch is connected to the other electrode of the capacitor 5. The source of the P channel transistor 4 and the N well in which the P channel transistor 4 is formed are connected to the drain of the P channel transistor 3 which is the output terminal of the first current mirror.

  The N-channel transistor 6 is provided as a discharge switch that periodically discharges the charge of the capacitor 5. The drain of the N-channel transistor 6 is connected to a common connection point between the drain of the P-channel transistor 4 and the electrode of the capacitor C, and the source is connected to the ground line. The gate of the N channel transistor 6 is supplied with a clock CLK having a constant frequency f.

  The P-channel transistor 10 is provided as a second switch. The source of the P channel transistor 10 and the N well in which the P channel transistor 10 is formed are connected to the drain of the P channel transistor 9 constituting the second current mirror.

  The capacitor 11, the resistor 12, and the capacitor 13 constitute a smoothing circuit 19 that smoothes the output current of the second current mirror that is output via the second switch. More specifically, the capacitor 11 is interposed between the drain of the P-channel transistor 10 that is the second switch and the ground line. The resistor 12 and the capacitor 13 are inserted in series between the electrode of the capacitor 11 connected to the drain of the P-channel transistor 10 and the ground line. A common connection point between the resistor 12 and the capacitor 13 is an output terminal of the smoothing circuit 19.

  The comparator 7 is supplied with the reference voltage Va output from the reference voltage source 8 at the inverting input terminal, and supplied with the charging voltage V1 of the capacitor 5 at the non-inverting input terminal. The comparator 7 sets the gate voltages for the P-channel transistors 4 and 10 as the first and second switches to L level only during the period when the charging voltage V1 of the capacitor 5 is within the reference voltage Va, and the P-channel transistors 4 and 10 Set to ON. In this embodiment, the comparator 7 and the P channel transistors 4 and 10 allow the current from the P channel transistor 3 (first constant current source) to the capacitor 5 only during the period when the charging voltage V1 of the capacitor 5 is within the reference voltage Va. And a control circuit that outputs current from the P-channel transistor 9 (second constant current source) to the smoothing circuit 19 is configured.

  The N channel transistors 14 and 15 constitute an output current mirror that outputs an output current IOUT proportional to the current smoothed by the smoothing circuit 19. More specifically, the sources of N-channel transistors 14 and 15 are each grounded. The gates of the N-channel transistors 14 and 15 and the drain of the N-channel transistor 14 are connected to a common connection point of the resistor 12 and the capacitor 13 that are output terminals of the smoothing circuit 19. The drain of the N-channel transistor 15 is an output terminal of an output current mirror that outputs a current IOUT.

  FIG. 2 is a time chart showing waveforms of respective parts of the constant current circuit according to the present embodiment. Hereinafter, the operation of the present embodiment will be described with reference to FIG. In this embodiment, as shown in FIG. 2, a positive clock CLK having a predetermined pulse width is generated at a time interval of 1 / f, and each time this clock CLK is generated, an N-channel transistor serving as a discharge switch 6 is turned ON, the capacitor 5 is discharged, and the charging voltage V1 of the capacitor 5 becomes 0V.

  When the charging voltage V1 of the capacitor 5 becomes lower than the reference voltage Va in this way, the comparator 7 sets the gate voltages for the P-channel transistors 4 and 10 to the L level and turns on the P-channel transistors 4 and 10. When the clock CLK becomes L level and the N-channel transistor 6 is turned OFF, the constant current I1 = Ia from the P-channel transistor 3 as the first constant current source flows into the capacitor 5 through the P-channel transistor 4. The charging voltage V1 of the capacitor 5 increases linearly. On the other hand, the constant current I2 = nIa from the P channel transistor 9 which is the second constant current source passes through the P channel transistor 10 and is supplied to the smoothing circuit 19 including the capacitor 11, the resistor 12 and the capacitor 13. Supplying constant current I1 = Ia from P-channel transistor 3 to capacitor 5 and supplying constant current I2 = nIa from P-channel transistor 9 to smoothing circuit 19 are such that charging voltage V1 of capacitor 5 is within reference voltage Va. Is continued for a certain period. During this time, in the smoothing circuit 19, the charging voltage V2 of the capacitor 11 increases.

When the charging voltage V1 of the capacitor 5 reaches the reference voltage Va, the comparator 7 sets the gate voltages for the P-channel transistors 4 and 10 to the H level and turns off the P-channel transistors 4 and 10. As a result, the current I1 flowing into the capacitor 5 via the P channel transistor 4 becomes 0, and the current I2 supplied to the smoothing circuit 19 via the P channel transistor 10 also becomes 0. Therefore, after the charging voltage V1 of the capacitor 5 reaches the reference voltage Va, the charging voltage V1 of the capacitor 5 maintains the same level as the reference voltage Va until the clock CLK is generated again. Further, in the smoothing circuit 19, the electric charge charged in the capacitor 11 is discharged to the capacitor 13 and the N-channel transistor 14 side through the resistor 12, and the charging voltage V <b> 2 of the capacitor 11 is the combined capacitance of the capacitors 11 and 13 and the resistor 12. It gradually decreases in accordance with a time constant determined by the resistance value.
In the constant current circuit according to the present embodiment, the above operation is repeated every time the clock CLK is generated.

Here, the time Ta required for the charging voltage V1 of the capacitor 5 to rise from 0 V to the reference voltage Va after the generation of the clock CLK is given by the following equation.
Ta = Va · C / Ia (1)
The charge Qa supplied to the smoothing circuit 19 via the P-channel transistor 10 during this time Ta is given by the following equation.
Qa = n · Ia · Ta (2)
Therefore, the average current I3ave flowing into the N-channel transistor 14 via the smoothing circuit 19 is given by the following equation, and a current proportional to the average current I3ave is the output current IOUT of the constant current circuit.
I3ave = f · Qa
= F · n · Ia · Ta
= F · n · Ia · (Va · C / Ia)
= F · Va · C · n (3)
Here, if the time constant of the smoothing circuit 19 is made sufficiently large, the ripple of the output current IOUT of the constant current circuit is made sufficiently small, and the output current IOUT is stabilized at a current value proportional to I3ave in the above equation (3). Can be

  As described above, according to the present embodiment, the output current IOUT of the constant current circuit depends on the capacitance value C and does not depend on the current value Ia of the constant current source 2. Therefore, even if the constant current source 2 has a configuration using a resistor such as the constant current circuit of FIG. 6 and the current value Ia varies greatly, the output current of the constant current circuit is affected by the influence. IOUT does not vary. The output current IOUT of the constant current circuit depends on the capacitance value C of the capacitor 5, but when the capacitor is formed in the semiconductor integrated circuit, the variation in the capacitance value of the capacitor is about ± 10%, and the variation in resistance is Is small enough. Therefore, variation in the output current IOUT of the constant current circuit can be reduced. Further, according to the present embodiment, since the output current IOUT proportional to the current I3ave smoothed by the smoothing circuit 19 is output by the output current mirror, even in a situation where the load to which the output current IOUT is supplied varies. The output current IOUT can be stabilized.

Second Embodiment
FIG. 3 is a circuit diagram showing a configuration of a constant current circuit according to the second embodiment of the present invention. In the first embodiment, the first and second constant current sources (the first current mirror by the P-channel transistor 3 and the second current by the P-channel transistor 9 are used only during the period when the charging voltage V1 of the capacitor 5 is within the reference voltage Va. A control circuit for outputting current by a current mirror is composed of P-channel transistors 4 and 10 and a comparator 7. In contrast, in the present embodiment, the P-channel transistors 4 and 10 are removed, and instead, the P-channel transistor 16 is interposed between the P-channel transistor 1 and the constant current source 2. Then, the output signal of the comparator 7 is given to the gate of the P-channel transistor 16. A resistor 17 is interposed between the common connection point of the gates of the P-channel transistors 1, 3 and 9 and the power supply VDD. The resistor 17 is a resistor for setting the gate voltages of the P-channel transistors 1, 3 and 9 to the H level when the P-channel transistor 16 is turned off and turning off the P-channel transistors 1, 3 and 9.

  In the present embodiment, the comparator 7 and the P-channel transistor 16 constitute a control circuit. In other words, in the present embodiment, the comparator 7 turns on the P-channel transistor 16 only during a period in which the charging voltage V1 of the capacitor 5 is within the reference voltage Va, and from the P-channel transistor 3 as the first current source to the capacitor 5. Current output and a current output from the P-channel transistor 9 as the second current source to the smoothing circuit 19 are performed. In the present embodiment, since the resistor 17 is provided, the current flowing through the P-channel transistor 1 is smaller than the current value Ia of the constant current source 2. However, a proportional relationship is established between the currents flowing through the P-channel transistors 3 and 9, and the average current I3ave of the above equation (3) flows through the N-channel transistor 14. Therefore, also in this embodiment, the same effect as the first embodiment is obtained.

<Third Embodiment>
FIG. 4 is a circuit diagram showing a configuration of a constant current circuit according to the third embodiment of the present invention. In FIG. 4, P-channel transistors 26, 34 and 35 are formed on an N-type semiconductor substrate. The N-type semiconductor substrate is connected to the power supply VDD. Further, the N-channel transistors 21, 23, 24, 29 and 30 are formed in isolated P-wells formed on the N-type semiconductor substrate.

  N-channel transistor 21 and constant current source 22 are inserted in series between power supply VDD and the ground line. More specifically, the source of the N channel transistor 21 and the P well to which the N channel transistor 21 belongs are grounded, and the gate and drain of the N channel transistor 21 are commonly connected. A constant current source 22 having a current value Ia is interposed between the common connection point of the gate and drain of the N-channel transistor 21 and the power supply VDD. As in the first embodiment, the constant current source 22 may have a configuration using a resistor such as the constant current circuit of FIG.

  N-channel transistors 21 and 23 form a first current mirror, and the drain of N-channel transistor 23 is the current output terminal of the first current mirror. The N channel transistors 21 and 29 constitute a second current mirror, and the drain of the N channel transistor 29 is a current output terminal of the second current mirror.

  Here, N-channel transistors 21, 23, and 29 have the same channel length. When the channel width of the N channel transistor 21 is W, the channel width of the N channel transistor 23 is W, and the channel width of the N channel transistor 29 is nW (n is an arbitrary constant). Therefore, the N-channel transistor 23 functions as a first constant current source having a current value Ia, and the P-channel transistor 29 functions as a second constant current source having a current value nIa.

  The capacitor 25 has a capacitance value C, and one electrode is grounded. The N-channel transistor 24 has a drain connected to the other electrode of the capacitor 25. The source of the N-channel transistor 24 and the P-well in which the N-channel transistor 24 is formed are connected to the drain of the N-channel transistor 23 that is the output terminal of the first current mirror. The N-channel transistor 24 functions as a first switch that connects the N-channel transistor 23 that is the first constant current source to the capacitor 25.

  The P-channel transistor 26 is provided as a charging switch that periodically initializes the charging voltage of the capacitor 25 to the level of the power supply VDD. The drain of the P-channel transistor 26 is connected to a common connection point between the drain of the N-channel transistor 24 and the electrode of the capacitor C, and the source is connected to the power supply VDD. The gate of the P channel transistor 26 is supplied with a clock CLKB having a constant frequency f.

  The N-channel transistor 30 functions as a second switch that connects the N-channel transistor 29 that is the second current source to the smoothing circuit 39. More specifically, the source of the N-channel transistor 30 and the P-well in which the N-channel transistor 30 is formed are connected to the drain of the N-channel transistor 29 constituting the second current mirror. The drain of the N channel transistor 30 is connected to the smoothing circuit 39.

  The smoothing circuit 39 includes a capacitor 31, a resistor 32, and a capacitor 33. Here, the capacitor 31 is interposed between the drain of the N-channel transistor 30 and the power supply VDD. The resistor 32 and the capacitor 33 are inserted in series between the electrode of the capacitor 31 connected to the drain of the N-channel transistor 30 and the power supply VDD. A common connection point between the resistor 32 and the capacitor 33 is an output terminal of the smoothing circuit 39.

  A reference voltage source 28 that outputs a reference voltage Va is interposed between the inverting input terminal of the comparator 27 and the power supply VDD, and the voltage VDD−Va is applied to the inverting input terminal. Further, the charging voltage V <b> 1 ′ of the capacitor 25 is applied to the non-inverting input terminal of the comparator 27. The comparator 27 sets the gate voltages for the N-channel transistors 24 and 30 to the H level and turns on the N-channel transistors 24 and 30 only when the charging voltage V1 'of the capacitor 25 is equal to or higher than the voltage VDD-Va. In the present embodiment, the comparator 27 and the N-channel transistors 24 and 30 serving as the first and second switches allow only a period during which the amount of decrease of the charging voltage V1 ′ of the capacitor 25 from the power supply voltage VDD is within the reference voltage Va. A control circuit for discharging the capacitor 25 by the N-channel transistor 23 (first constant current source) and outputting a current from the N-channel transistor 29 (second constant current source) to the smoothing circuit 39 is configured. .

  The P-channel transistors 34 and 35 constitute an output current mirror that outputs a current IOUT proportional to the current smoothed by the smoothing circuit 39. More specifically, the sources of the P-channel transistors 34 and 35 are connected to the power supply VDD. The gates of the P-channel transistors 34 and 35 and the drain of the P-channel transistor 34 are connected to a common connection point of the resistor 32 and the capacitor 33 that are output terminals of the smoothing circuit 39. The drain of the P-channel transistor 35 is an output terminal of an output current mirror that outputs a current IOUT.

  FIG. 5 is a time chart showing waveforms of respective parts of the constant current circuit according to the present embodiment. Hereinafter, the operation of the present embodiment will be described with reference to FIG. In this embodiment, as shown in FIG. 5, a negative clock CLKB having a predetermined pulse width is generated at a time interval of 1 / f, and each time this clock CLKB is generated, a P-channel transistor serving as a charging switch 26 is turned ON, and the charging voltage V1 ′ of the capacitor 25 is initialized to the power supply voltage VDD.

  When the charging voltage V1 ′ of the capacitor 25 is initialized to the power supply voltage VDD in this way, the comparator 27 sets the gate voltages for the N-channel transistors 24 and 30 to the H level and turns on the N-channel transistors 24 and 30. To do. When the clock CLKB becomes H level and the P-channel transistor 26 is turned OFF, the current I1 = Ia flows from the capacitor 25 to the N-channel transistor 23 that is the first constant current source via the N-channel transistor 24. 25 charge voltage V1 'falls linearly. On the other hand, the current I2 = nIa is supplied from the N-channel transistor 29 which is the second constant current source to the smoothing circuit 39 via the N-channel transistor 30. The discharge of the current I1 = Ia from the capacitor 25 and the supply of the current I2 = nIa from the N-channel transistor 29 to the smoothing circuit 39 are caused by a decrease amount of the charging voltage V1 ′ of the capacitor 25 from the power supply voltage VDD. It continues for a period that is within Va. During this time, in the smoothing circuit 39, the capacitor 31 is charged, and the drain voltage V2 'of the N-channel transistor 30 decreases.

  When the amount of decrease in the charging voltage V1 ′ of the capacitor 25 from the power supply voltage VDD reaches the reference voltage Va, the comparator 27 sets the gate voltages for the N-channel transistors 24 and 30 to L level, and the N-channel transistors 24 and 30 Set to OFF. As a result, the current I1 flowing from the capacitor 25 into the N channel transistor 23 via the N channel transistor 24 becomes 0, and the current I2 supplied to the smoothing circuit 39 via the N channel transistor 30 also becomes 0. For this reason, after the charging voltage V1 'of the capacitor 25 reaches the voltage VDD-Va, the charging voltage V1' of the capacitor 25 maintains the same level as the voltage VDD-Va until the clock CLKB is generated again. Further, in the smoothing circuit 39, the electric charge charged in the capacitor 31 is discharged to the capacitor 33 and the P-channel transistor 34 side through the resistor 32, and the voltage V2 ′ is the combined capacitance of the capacitors 31 and 33 and the resistance value of the resistor 32. It rises slowly according to the time constant determined by.

  In the constant current circuit according to the present embodiment, the above operation is repeated every time the clock CLKB is generated. Also in this embodiment, the same effect as the first embodiment can be obtained. That is, the average current I3ave that flows out from the P-channel transistor 34 has the same current value as that shown in Expression (3).

<Other embodiments>
Although the first to third embodiments of the present invention have been described above, other embodiments can be considered in addition to this. For example:

(1) In the first embodiment, instead of providing the P-channel transistors 4 and 10, a switch is inserted between the common connection point of the gates of the P-channel transistors 1, 3, and 9 and the power supply VDD, and the comparator 7 This switch may be turned off when the output signal is at the L level, and this switch may be turned on when the output signal of the comparator 7 is at the H level. According to this aspect, during the period when the charging voltage V1 of the capacitor 5 is within the reference voltage Va, the switch is turned off, the P-channel transistors 3 and 9 output a constant current, and the charging voltage V1 of the capacitor 5 is the reference voltage. When Va is reached, the switch is turned on and the P-channel transistors 3 and 9 are turned off, and the current output by the P-channel transistors 3 and 9 is stopped. Therefore, the same effect as the first embodiment can be obtained.

(2) In each of the above embodiments, the field effect transistor is used as the switching element constituting the constant current circuit, but a bipolar transistor may be used.

(3) Although the output current mirror is used in each of the above embodiments, the output current of the smoothing circuit 19 may be used as the output current IOUT of the constant current circuit.

(4) The modification from the first embodiment to the second embodiment may be applied to the third embodiment. That is, in the third embodiment (FIG. 4), the N-channel transistors 24 and 30 are omitted, and the output signal of the comparator 27 is connected between the common connection point of the gate and drain of the N-channel transistor 21 and the constant current source 22. An N-channel transistor that is turned on only when H is at an H level is provided, and a resistor is interposed between the common connection point of the gate and drain of the N-channel transistor 21 and the ground line. Also in this aspect, the same effects as those in the above embodiments can be obtained.

(5) In the first and second embodiments, the charging voltage V1 of the capacitor 5 is periodically initialized to 0V. In the third embodiment, the charging voltage V1 'of the capacitor 25 is periodically initialized to the power supply voltage VDD. However, the initial voltage of the capacitor does not have to be such a voltage, and may be an arbitrary voltage.

(6) As apparent from the above equation (3), the current value of the output current IOUT of the constant current circuit is the same as that of the capacitor 5 in the first embodiment (FIG. 1) and the second embodiment (FIG. 3). The capacitor 25 in the third embodiment (FIG. 4) has a capacitance value C, the reference voltage source 8 in the first embodiment (FIG. 1), the second embodiment (FIG. 3), or the third embodiment (FIG. 4). The voltage value Va of the reference voltage source 28 and the ratio n of the channel width of the P-channel transistor 9 to the channel width of the P-channel transistors 1 and 3 in the first embodiment (FIG. 1) and the second embodiment (FIG. 3) or This depends on the ratio n of the channel width of the N-channel transistor 29 to the channel width of the N-channel transistors 21 and 23 in the third embodiment (FIG. 4).

Therefore, a constant current circuit in which the current value of the output current IOUT is variable may be configured as follows.
a. By using the capacitor 5 in the first embodiment (FIG. 1) and the second embodiment (FIG. 3) or the capacitor 25 in the third embodiment (FIG. 4) as a capacitor having a variable capacitance value C, the output current IOUT A constant current circuit with a variable current value is configured. As the capacitor 5 or 25 having a variable capacitance value C, for example, a capacitor having a known configuration including a plurality of capacitors and a switch for switching the number of capacitors connected in parallel by switching the connection state between these capacitors is used. do it.
b. The reference voltage source 8 in the first embodiment (FIG. 1), the second embodiment (FIG. 3) or the reference voltage source 28 in the third embodiment (FIG. 4) is a reference voltage source having a variable voltage value Va. Thus, a constant current circuit in which the current value of the output current IOUT is variable is configured.
c. By varying the channel width of, for example, the P-channel transistor 9 in the first embodiment (FIG. 1) and the second embodiment (FIG. 3) or the N-channel transistor 29 in the third embodiment (FIG. 4), an output is obtained. A constant current circuit in which the current value of the current IOUT is variable is configured. For example, a transistor with a variable channel width may be a transistor having a known configuration including a plurality of transistors and a switch for switching the number of transistors connected in parallel by switching the connection state between these transistors.

1, 3, 4, 9, 10, 16, 26, 34, 35... P-channel transistors, 6, 14, 15, 21, 23, 24, 29, 30... N-channel transistors, 5, 11, 13, 25, Reference numerals 31 and 33, capacitors, 2, 22 constant current sources, 8, 28 reference voltage sources, 19, 39 smoothing circuits, 12, 17, 32 resistors, 27, 27 comparators.

Claims (6)

First and second constant current sources that output constant currents proportional to each other;
A capacitor;
The capacitor charging voltage is initialized in synchronization with a periodic clock, and after the initialization, charging or discharging of the capacitor by the first constant current source is started, and charging voltage of the capacitor by charging or discharging is started. Until the amount of change reaches a reference voltage, charging or discharging of the capacitor by the first constant current source is continued and charging or discharging of the capacitor by the first constant current source is continued. A control circuit that repeats the operation of continuing the output of the current from the second constant current source;
A constant current circuit comprising: a smoothing circuit for smoothing an output current of the second constant current source. The first and second constant current sources are configured by first and second current mirrors that generate a constant current proportional to an output current of a common constant current source,
The control circuit includes:
A first switch interposed in series between the first current mirror and the capacitor;
A second switch connected in series between the second current mirror and the smoothing circuit;
2. The constant current circuit according to claim 1, wherein the first and second switches are turned on only during a period in which a change amount after initialization of the charging voltage of the capacitor is within the reference voltage. The first and second constant current sources are configured by first and second current mirrors that generate a constant current proportional to an output current of a common constant current source,
2. The control circuit according to claim 1, wherein the control circuit causes the common current source to output a current only during a period in which a change amount after initialization of the charging voltage of the capacitor is within the reference voltage. Constant current circuit. Comprising a discharge switch connected in parallel to the capacitor;
The control circuit initializes a charge voltage of the capacitor by discharging the charge of the capacitor by turning on the discharge switch in synchronization with a periodic clock, and after the initialization, Charging of the capacitor by the constant current source is continued, and charging of the capacitor by the first constant current source is continued until the charging voltage of the capacitor increases by a reference voltage due to charging, 4. The operation according to claim 1, wherein the operation of continuing the output of the current by the second constant current source is repeated only while the charging of the capacitor by the constant current source is continued. 5. Constant current circuit. Comprising a charging switch connected in series to the capacitor;
The control circuit initializes the charging voltage of the capacitor to a predetermined voltage by turning on the charging switch in synchronization with a periodic clock. After the initialization, the control circuit uses the first constant current source. The discharge of the capacitor is started, and the discharge of the capacitor by the first constant current source is continued until the charging voltage of the capacitor decreases by a reference voltage due to the discharge, and the first constant current source 4. The constant current circuit according to claim 1, wherein the operation of continuing the output of the current by the second constant current source is repeated only while the discharge of the capacitor is continued. 5.   6. The constant current circuit according to claim 1, further comprising an output current mirror that outputs a current proportional to the current smoothed by the smoothing circuit.

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