JP2012174317A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-port semiconductor storage device important in signal processing.SOLUTION: A semiconductor storage device comprises a memory cell including: a latch circuit comprised of a cross-coupled inverter having two data holding nodes connected to a first bit line; a first switch part provided between the first bit line and each of the data holding nodes of the inverter; and a first word line for controlling the conduction of the first switch part. It also comprises: a second switch part for switching between a first mode, in which respective data holding nodes of a plurality of memory cells are separated for each memory cell and one bit is comprised of one memory cell, and a second mode, in which the respective data holding nodes of the plurality of memory cells are connected in parallel and one bit is comprised of the plurality of memory cells; and further, a third switch part for switching between whether or not to connect one data holding node of the respective data holding nodes of the plurality of memory cells to a second bit line.

Description

  The present invention relates to a semiconductor memory device in which reliability can be controlled dynamically, and in particular, according to the power consumption of the semiconductor memory device, the requirement for memory capacity, and the importance of bit reliability, QoB (Quality of a Bit: 1 bit). The present invention relates to a semiconductor memory device capable of changing the quality of information.

  In recent years, memory processing such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) has progressed with CMOS process technology mounted on SOC (System On a Chip), and the processing dimensions (scaling size) of integrated circuits have increased. Reduced, higher chip density and lower chip cost are realized, and memory capacity is increasing. Such a reduction in the scaling size increases the variation in threshold voltage of the transistors constituting the memory cell such as SRAM, lowers the noise margin for reading and writing in the memory cell, and makes the memory cell operation unstable. Increase the bit error rate (BER). In addition, since the operating voltage and noise margin of the circuit are reduced, soft errors caused by cosmic rays cannot be ignored.

  Regarding the operation limit voltage of the SRAM with respect to the LSI manufacturing process node, generally, as the LSI manufacturing process node is changed from 250 nm to 130 nm and 90 nm, the operation margin between the standard operation voltage and the operation limit voltage decreases. (For example, refer to FIG. 1 of Patent Document 3). When the scaling size is further reduced and the LSI manufacturing process node becomes 65 nm, the standard operating voltage and the operating limit voltage are expected to be reversed, and the bit error rate (BER) increases rapidly.

  As a measure for reducing the bit error rate (BER), there is a method of increasing the number of transistors in the memory cell. However, the method of increasing the number of transistors has a problem that the area overhead of the memory cell is large and there is a problem that there is a speed overhead because differential reading is not possible. As another countermeasure for reducing the bit error rate (BER), there is a method in which the memory cell operation is not voltage controlled but voltage controlled. However, the method of voltage control has a problem that a separate power source and an additional circuit are separately required.

  The importance of reliability depends on the application, and there are applications that require reliability and applications that do not require reliability. An application that requires high reliability is, for example, cryptographic processing. On the other hand, examples of applications that do not require high reliability include moving image processing such as screen saver processing and video.

  FIG. 17 is a schematic diagram showing a configuration of a semiconductor memory device according to the first conventional example. In the case of the SRAM configuration of FIG. 17, any block (BLK0 to BLK5 in FIG. 17) is operated at a standard voltage (hereinafter referred to as a normal mode, indicated by LD in FIG. 17) and has the same reliability. is there. Each block has a large number of memory cells (MC), and one bit is composed of one memory cell. In the following, a case where one bit is composed of one memory cell is defined as a 1 bit / 1 cell mode. The reliability of 1 bit largely depends on the variation due to the process of the transistors constituting the memory cell. Further, when the manufacturing process node becomes thinner due to scaling, the operation margin is lowered, and thus process variation greatly affects the reliability of 1 bit. For example, Patent Documents 1 and 2 are known as techniques related to a conventional SRAM.

  As described above, with the miniaturization of the process, the variation in the threshold voltage of the transistors constituting the memory cell increases, the operation margin of the memory cell constituting the memory such as SRAM is deteriorated, and the operation of the memory cell is stabilized. There was a problem that sex was inhibited. On the other hand, since the memory is installed in mobile devices such as mobile phones, there is a strong demand for reducing the power consumption of the memory, and it is necessary to take measures to ensure the bit reliability of the memory cell with low power and low voltage There is sex. In addition, progress in process technology is dizzying, and the memory capacity of one chip has been dramatically increased. Further, the demand for reducing the power consumption of the memory, the requirement for securing the necessary memory capacity, and the requirement for bit reliability differ depending on the application. That is, the QoB required for each application changes.

  In order to solve the above problems, the present inventors can dynamically change the bit reliability of the memory cell according to the application and the memory condition, and ensure the operation stability and low power consumption. A semiconductor memory that can realize high reliability and high reliability has been proposed (for example, see Patent Document 3).

  FIG. 18 is a schematic diagram showing a configuration of a semiconductor memory device according to a second conventional example disclosed in Patent Document 3, and FIG. 19 shows two memory cells MC101 of the SRAM used in the semiconductor memory device of FIG. 2 is a circuit diagram showing a configuration of MC102. FIG. 19 shows a configuration of a 7-transistor / 14-transistor switching type SRAM (hereinafter referred to as 7T / 14 SRAM, hereinafter the same).

  When the power supply voltage is lowered due to the recent reduction in power supply voltage of semiconductor integrated circuits, the logical threshold voltage of the inverter of the SRAM memory cell is also relatively lowered, and the noise margin is reduced. If this noise margin is not ensured, an error occurs in which the inverter of the memory cell is inverted and the stored content of the memory cell changes. However, in the semiconductor memory device according to the second conventional example, even in the case of a low power supply voltage, the memory contents can be reliably held in the memory cell, and the read and write operations for the memory cell can be stabilized. it can.

  In FIG. 18, blocks (BLK0 to BLK4) are blocks LD that operate in a mode (1 bit / 1 cell mode) in which 1 bit is composed of one memory cell, whereas blocks (BLK4 to BLK5). Is a block HD that operates in a mode (1 bit / 2 cell mode) in which one bit is formed by connecting two memory cells. The 1-bit / 1-cell mode block (BLK0 to BLK4) does not store important program codes and data such as encryption programs and encryption data, and those important program codes and data are stored in the 1-bit / 2-cell mode. Are stored in the blocks (BLK4 to BLK5). The 1-bit / 2-cell mode blocks (BLK4 to BLK5) have half the memory capacity compared to the 1-bit / 1-cell mode blocks (BLK0 to BLK4), but realize excellent QoB. Hereinafter, the control method of QoB will be described.

  As shown in FIG. 19, the semiconductor memory device according to the second conventional example has a circuit configuration in which two memory cells MC101 and MC102 used in the SRAM are connected. That is, the memory cells MC101 and MC102 have a pair of cross-coupled connections in which each output terminal is connected to a path leading to each of the pair of bit lines BL and / BL arranged corresponding to the column of the memory cells. And a pair of MOS transistors P1, P2, N1, and N2 and MOS transistors P5, P6, N5, and N6, and a pair provided between the bit lines BL and / BL and the output terminal of the inverter. Switch section (comprised of MOS transistors N3 and N4 and MOS transistors N7 and N8) and two word lines WL0 and WL1 capable of controlling the conduction of the switch section. A concatenation of two memory cells MC101 and MC102 is used as a 1-bit area, and 1-bit / 2-cell mode blocks (BLK4 to BLK5) are configured. On the other hand, in the 1-bit / 1-cell mode block (BLK0 to BLK3), one memory cell is a 1-bit area as in the first conventional example.

  In the 1-bit / 2-cell mode in which two memory cells MC101 and MC102 are connected as a 1-bit region, the same data is held in the two memory cells MC101 and MC102. The two word lines WL0 and WL1 are driven to the high mode “H” (WL0 = “H”, WL1 = “H”). In the read operation, one of the two word lines WL0 and WL1 is driven to the high mode “H” (for example, WL0 = “L”, WL1 = “H”). In both the 1-bit / 1-cell mode and the 1-bit / 2-cell mode, the read access and the write access are the same processing except for the control of the word line.

JP 2005-025863 A JP 2003-132684 A International Publication No. WO2009 / 088020

  That is, in the first conventional example, the low voltage operation performance of the SRAM limits the low power supply voltage characteristics of the entire system, and there is a problem that the SRAM does not operate at a low power supply voltage. As a solution to this, there has been proposed a semiconductor memory device according to a second conventional example in which the low voltage characteristic is enhanced by doubling the number of transistors per bit although the capacity is halved.

  However, the configuration of the 7T / 14T SRAM in the semiconductor memory device according to the second conventional example is a single port and does not correspond to the multiport particularly required for signal processing. With the 7T / 14T SRAM configuration, a plurality of simultaneous read / write requests must be processed individually, which requires a read / write time, which results in a delay time.

  An object of the present invention is to solve the above problems and provide a multiport semiconductor memory device that is important in signal processing in the semiconductor memory device according to the second conventional example.

A semiconductor memory device according to the present invention includes a pair of inverters having two data holding nodes connected to a pair of first bit lines arranged corresponding to a column of memory cells and cross-coupled to each other. A latch circuit;
A pair of first switch portions respectively provided between the pair of first bit lines and the data holding nodes of the pair of inverters;
A memory cell of a semiconductor memory device configured to include a first word line that controls conduction of the pair of first switch portions,
A first mode in which each data holding node of each of the plurality of memory cells is separated for each memory cell and each bit has one memory cell, and each data holding of each of the plurality of memory cells is held. In a semiconductor memory device comprising: a second switch unit that connects nodes in parallel and selectively switches a second mode in which one bit is composed of a plurality of the memory cells;
In response to a signal from the second word line, a third mode in which one data holding node of each of the data holding nodes of the plurality of memory cells is connected to the second bit line and a first mode not connected And a third switch section for selectively switching between the four modes.

  In the semiconductor memory device, the second mode is characterized in that each data holding node of the two memory cells is connected in parallel and one bit is composed of the first and second memory cells. .

  In the semiconductor memory device, in the third mode, the third switch unit is responsive to a signal from the second word line in each data holding node of the first memory cell. Are connected to one bit line of the pair of second bit lines, and one data holding node of each data holding node of the second memory cell is connected to a pair of second bit lines. The bit line is connected to the other bit line.

  Further, in the semiconductor memory device, in the third mode, the third switch unit is responsive to a signal from the second word line in the data holding nodes of the first memory cell. Are connected to one bit line of the pair of second bit lines, and one data holding node of each data holding node of the second memory cell is connected to a pair of second bit lines. It is connected to one of the bit lines.

Still further, in the semiconductor memory device, when the first mode is set by the second switch unit and the fourth mode is set by the third switch unit, the data is stored in the latch circuit. The data is differentially read from each of the data holding nodes through the pair of first switch units and the pair of first bit lines, respectively.
When the first mode is set by the second switch unit and the third mode is set by the third switch unit, the data stored in the latch circuit is transferred from each data holding node. Each read out in a single end via the pair of third switch sections and the pair of second bit lines,
When the second mode is set by the second switch unit and the fourth mode is set by the third switch unit, the data stored in the latch circuit is transferred from each data holding node. Each differentially read through the pair of first switch sections and the pair of first bit lines,
When the second mode is set by the second switch unit and the third mode is set by the third switch unit, the data stored in the latch circuit is transferred from each data holding node. Each of the data is read out differentially through the pair of third switch sections and the pair of second bit lines.

  Further, the semiconductor memory device is characterized in that the first bit lines are shared by the memory cells adjacent to each other in a predetermined first direction.

  Still further, in the semiconductor memory device, the memory cells adjacent to each other in a second direction substantially orthogonal to the first direction are configured to share the first word line. To do.

  According to the semiconductor memory device of the present invention, it is possible to provide a multi-port semiconductor memory device that operates at a lower power supply voltage compared to the prior art. In particular, since an additional read port circuit is provided, it is possible to operate without worrying about the static noise margin for the so-called “disturb-free” read operation. As a result, it is possible to operate stably as compared with the prior art under the threshold voltage fluctuation. According to the measurement result of the prototype device prototyped using the 65 nm triple well process by the present inventor, the threshold voltage fluctuation is not detected in the read operation in the high reliability mode using the additional read port circuit. The operating voltage could be reduced to 0.45V. On the other hand, the read operation in the high reliability mode using the conventional internal read port requires an operating voltage of 0.54V. Further, in the semiconductor memory device, each memory cell adjacent to each other in a predetermined first direction is configured to share the first bit line, or substantially orthogonal to the first direction. By sharing the first word line among the memory cells adjacent to each other in the second direction, the occupied area can be greatly reduced as compared with the prior art.

FIG. 3 is a circuit diagram showing a configuration of two memory cells MC0 and MC1 of an SRAM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a 9T / 18T SRAM configured using the memory cell of FIG. 1. (A) is a circuit diagram showing memory access of one read / write between a single port SRAM and two processors PRA and PRB, and (b) is a time of reading or writing at the time of memory access of (a). It is a timing chart which shows division | segmentation access. (A) is a circuit diagram showing two read / write memory access between a dual port SRAM and two processors PRA and PRB, and (b) is a simultaneous read or write at the time of memory access of (a). It is a timing chart which shows access. (A) is a circuit diagram showing differential reading through the inner bit lines BL and / BL in the normal mode (standard voltage operation) of the SRAM of FIG. 1, and (b) is a normal mode of the SRAM of FIG. FIG. 11 is a circuit diagram showing single-ended reading via outer bit lines RBL, / RBL during (standard voltage operation). (A) is a circuit diagram showing differential reading through the inner bit lines BL, / BL in the high reliability mode (low voltage operation) of the SRAM of FIG. 1, and (b) is a circuit diagram of the SRAM of FIG. FIG. 6 is a circuit diagram showing differential reading through outer bit lines RBL, / RBL in a high reliability mode (low voltage operation). FIG. 6 is a circuit diagram showing a configuration of two memory cells MC0a and MC1a of an SRAM according to a first modification of the present invention. FIG. 10 is a circuit diagram showing a configuration of two memory cells MC0b and MC1 of an SRAM according to a second modification of the present invention. FIG. 11 is a circuit diagram showing a configuration of two memory cells MC0 and MC1 of an SRAM according to a third modification of the present invention. It is a top view which shows the layout of 9T / 18T bit cell pair made as an experiment by the 65-nm process based on one Example of this invention. 11 is a photograph showing a macro layout of a 9T / 18T SRAM using the 9T / 18T bit cell pair of FIG. 6 is a graph showing a bit error rate (BER) with respect to operating voltages at the time of four read operations in a prototype 9T / 18T SRAM. 6 is a graph showing a power supply voltage Vdd with respect to an access time at the time of differential reading via an inner bit line in a normal mode in a prototype 9T / 18T SRAM. 6 is a graph showing a power supply voltage Vdd with respect to an access time at the time of single-end reading via an outer side bit line in a normal mode in a prototype 9T / 18T SRAM. 6 is a graph showing a power supply voltage Vdd with respect to an access time at the time of differential reading via an inner bit line in a high reliability mode in a prototype 9T / 18T SRAM. 6 is a graph showing a power supply voltage Vdd with respect to an access time at the time of differential reading via an outer bit line in a high reliability mode in a prototype 9T / 18T SRAM. It is a schematic diagram which shows the structure of the semiconductor memory device based on a 1st prior art example. It is a schematic diagram which shows the structure of the semiconductor memory device based on a 2nd prior art example. FIG. 19 is a circuit diagram showing a configuration of two memory cells MC101 and MC102 of an SRAM used in the semiconductor memory device of FIG.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a circuit diagram showing a configuration of two memory cells MC0 and MC1 of an SRAM according to an embodiment of the present invention. The SRAM according to the embodiment of the present invention includes memory cells MC1 and MC0 further including dedicated read port circuits RP1 and RP0, respectively, as compared with the SRAM of FIG. 19 according to the second conventional example, and includes 9T / 18T dual It is characterized by configuring a port SRAM. Here, since the additional read port circuits RP1 and RP0 are “disturb-free”, they can operate at a lower voltage than the 7T / 14T SRAM according to the second conventional example. Here, “disturb-free” has a specific effect that internal data is not destroyed at the time of reading, that is, internal data can be read without being affected by an external circuit. The proposed SRAM has a normal mode that operates at a standard voltage using a pair of nine transistors, and a high-reliability mode that operates at a low voltage lower than the standard voltage using 18 transistors. . Here, an interleaved bit line scheme is employed to incorporate the two modes, and the proposed 9T / 18T SRAM is suitable for use in multimedia processor and multi-core DSP architectures.

  In FIG. 1, the SRAM according to the present embodiment has a circuit configuration in which two memory cells MC0 and MC1 used in the SRAM are connected. Here, the memory cells MC0 and MC1 are cross-sections in which output terminals (data holding nodes) are connected to paths that reach each of a pair of bit lines BL and / BL arranged corresponding to the column of the memory cells. A latch circuit comprising a pair of inverters V2 and V1 (coupled by MOS transistors P1, P2, N1, and N2, and MOS transistors P5, P6, N5, and N6, respectively) and bit lines BL and / BL And a pair of switch parts (consisting of MOS transistors N3 and N4 and MOS transistors N7 and N8) which are transfer gates provided between the inverter and the output terminal of the inverter, and 2 which can control conduction of the switch part. It consists of two word lines WL0 and WL1.

  When the control line / CL is at a low level (hereinafter referred to as L level), the MOS transistors P3 and P4 are turned on, the output terminals of the inverters V1 and V3 are turned on, and the output terminals of the inverters V2 and V4. , The two memory cells MC0 and MC1 are connected to form a 1-bit region, which constitutes a 1-bit / 2-cell mode block (high reliability mode blocks: blocks BLK4 to BLK5 in FIG. 18). . On the other hand, when the control line / CL is set to the high level (hereinafter referred to as H level), the MOS transistors P3 and P4 are turned off, the output terminals of the inverters V1 and V3 are cut off, and the inverters V2 and V4 are connected. When the output terminal is cut off, the two memory cells MC0 and MC1 are cut off, and each of them has 1 bit to form a total of 2 bits, and each block is in 1 bit / 1 cell mode (normal mode block: in FIG. 18). Blocks BLK0 to BLK3) are configured.

  In the 1-bit / 2-cell mode in which two memory cells MC0 and MC1 are connected to each other as a 1-bit area, the same data is held in the two memory cells MC0 and MC1, so that the read or write operation is not performed. At this time, the two word lines WL0 and WL1 are driven to the high mode “H” (WL0 = “H”, WL1 = “H”). In both the 1-bit / 1-cell mode and the 1-bit / 2-cell mode, the read access and the write access are the same except for the control of the word lines WL0 and WL1.

  The output terminal of the inverter V2 is connected to the additional bit line / RBL via the MOS transistors N10 and N9 of the read port circuit RP1, and the output terminal of the inverter V3 is added via the MOS transistors N11 and N12 of the read port circuit RP0. Connected to bit line / RBL. At the time of reading data, the read word line RWL connected to the gates of the MOS transistors N9 and N11 is set to H level, and the bit line / RBL is charged to H level by precharging for reading data. When the stored data is at the H level, the bit line / RBL remains at the H level and the data is read to the sense amplifier. On the other hand, when the stored data is at the L level, the bit line / RBL is discharged and becomes the L level. Data is read out to the sense amplifier.

  As described above, in the SRAM according to the present embodiment, the control line / CL is provided for switching between the normal mode (/ CL = “H”) and the high reliability mode (/ CL = “L”). In the high reliability mode, the 14T bit cell pair or the 18T bit cell pair functions as a single bit cell, and in the 9T / 18T bit cell, four NMOS transistors N9 to N12 and dedicated read bit lines RBL and / RBL are 7T. / 14T bit cell has been added. A read word line RWL is added to control the read port circuits RP1 and RP0.

  FIG. 2 is a circuit diagram showing a configuration of a 9T / 18T SRAM configured using the memory cell of FIG. FIG. 2 shows an arrangement structure of interleaved bit lines having the read port circuits RP1 and RP0 of the proposed 9T / 18TSRAM. The additional bit lines RBL are upper left and lower right (or upper right, lower left) bit cells. Shared. The read word line RWL is also shared but connected to all other bit cells.

  As is clear from FIG. 2, the bit line is shared by the memory cells adjacent to each other in the left-right direction, and the word line is shared by the memory cells adjacent to each other in the vertical direction, so that the 9T / 18TSRAM according to the present embodiment. In order to reduce the area and the overhead of the area, the array structure of the interleaved bit lines of the read port circuits RP1 and RP0 is used. A pair of left and right bit cells share an additional bit line RBL. Instead, the two read word lines RWL need to be interconnected through each row of the bit cell array.

  For example, when the read word line RWL0 of FIG. 2 is asserted, the read ports of the even columns in Row0 and Row1 are activated. The stored data is read out via the bit line RBL. When the control line / CL is asserted, all bit line RBL pairs are used for differential reading. As a result, an additional multiplexer (not shown) is required to select single-ended or differential readout. In addition, the proposed 9T / 18T SRAM has the other inner read port circuit. This is because the SRAM is a dual port SRAM, and data is read from the pair of inner bit lines BL and is read via the outer read port circuits RP1 and RP0. Therefore, 9T / 18T SRAM achieves a wider memory bandwidth than 7T / 14T SRAM. This is useful for multimedia processors such as video processing, multi-core DSP architecture.

  In FIG. 2, bit lines are shared by memory cells adjacent to each other in the left-right direction, and word lines are shared by memory cells adjacent to each other in the vertical direction. However, the present invention is not limited to this. Each memory cell adjacent to each other in the first direction may share a bit line, and each memory cell adjacent to each other in a second direction substantially orthogonal to the first direction may share a word line. .

  FIG. 3A is a circuit diagram showing one read / write memory access between the single-port SRAM and the two processors PRA and PRB, and FIG. 3B is the memory access time of FIG. 3A. 10 is a timing chart showing time-division access for reading or writing. FIG. 4A is a circuit diagram showing two read / write memory access between the dual port SRAM and the two processors PRA and PRB, and FIG. 4B is a memory diagram of FIG. 4A. It is a timing chart which shows the simultaneous access of reading or writing at the time of access. 3 and 4, PRA and PRB indicate processors, and BUS indicates a data bus. In the prior art, the one-read / write memory access in FIG. 3 is used, but in the SRAM according to the present embodiment, the two-read / write memory access is performed. There is an effect that the SRAM can be accessed via the buses BUSA and BUSB.

  The 9T / 18T SRAM according to this embodiment has four types of read modes, which are shown in FIGS. 5A is a circuit diagram showing differential reading through the inner bit lines BL and / BL in the normal mode (standard voltage operation) of the SRAM of FIG. 1, and FIG. 5B is a circuit diagram of FIG. FIG. 5 is a circuit diagram showing single-ended reading via outer bit lines RBL, / RBL in the normal mode (standard voltage operation) of the SRAM. 6A is a circuit diagram showing differential reading through the inner bit lines BL and / BL in the high reliability mode (low voltage operation) of the SRAM of FIG. 1, and FIG. FIG. 2 is a circuit diagram showing differential reading via outer bit lines RBL, / RBL in the high reliability mode (low voltage operation) of the SRAM of FIG. 1;

  In the normal mode (standard voltage operation) of FIG. 5, the control line / CL is at the H level, the MOS transistors P3 and P4 are turned off, and the 1 bit / 1 cell mode is set. Here, if the word line WL1 is set to the H level, as shown in FIG. 5A, the stored data from the latch circuit composed of the inverters V1 and V2 is transferred to the sense amplifier SA via the bit lines BL and / BL, respectively. Read by dynamic reading. If the read word line RWL is set to the H level, as shown in FIG. 5B, the stored data from the latch circuit composed of the inverters V1 and V2 are read from the read port circuits RP1 and RP0 and the bit lines / RBL and RBL, respectively. And read out to the sense amplifiers SA1 and SA2 respectively.

  In the high reliability mode (low voltage operation) of FIG. 6, the control line / CL is at the L level, the MOS transistors P3 and P4 are turned on, and the 1 bit / 2 cell mode is set. Here, if the word line WL1 is set to the H level, as shown in FIG. 6A, the stored data from the latch circuit composed of the inverters V1 and V2 is transferred to the sense amplifier SA via the bit lines BL and / BL, respectively. Read by dynamic reading. If the read word line RWL is set to the H level, as shown in FIG. 6B, the stored data from the latch circuit composed of the inverters V1 and V2 are read from the read port circuits RP1 and RP0 and the bit lines / RBL and RBL, respectively. To the sense amplifier SA through differential reading.

  As described above, according to the present embodiment, there is a difference between the standard operation mode and the high reliability mode in the write operation. In the normal mode write operation, the condition is the same as that of the conventional 6TSRAM. It is the same. In a reliable mode write operation, both word lines of a pair of bit cells are enabled to ensure the conductance of the access transistor, so that the conductance of the access transistor is averaged and the threshold voltage It is shown that the variation of is suppressed. This increases the write margin.

FIG. 7 is a circuit diagram showing a configuration of two memory cells MC0a and MC1a of the SRAM according to the first modification of the present invention. The SRAM according to the first modification of FIG. 7 differs from the embodiment of FIG. 1 in the following points.
(A) A read port circuit RP1a including PMOS transistors P9 and P10 is provided instead of the read port circuit RP1 including NMOS transistors N9 and N10.
(B) A read port circuit RP0a including PMOS transistors P11 and P12 is provided instead of the read port circuit RP0 including NMOS transistors N11 and N12.
(C) A read word line / RWL which is a signal line of the inverted signal is provided instead of the read word line RWL.
Even if comprised as mentioned above, it has the same effect as embodiment.

FIG. 8 is a circuit diagram showing a configuration of two memory cells MC0b and MC1 of the SRAM according to the second modification of the present invention. The SRAM according to the second modification of FIG. 8 differs from the embodiment of FIG. 1 in the following points.
(A) A read port circuit RP0b including NMOS transistors N11a and N12a connected to the bit line / RBL is provided in place of the read port circuit RP0 including NMOS transistors N11 and N12. As a result, data is read from the same bit line / RBL. Even when configured as described above, the same effects as those of the embodiment are obtained except for the reading operation described above.

FIG. 9 is a circuit diagram showing a configuration of two memory cells MC0 and MC1 of the SRAM according to the third modification of the present invention. The SRAM according to the third modification of FIG. 9 differs from the embodiment of FIG. 1 in the following points.
(A) In addition to the read port circuit RP1 including the NMOS transistors N9 and N10, the read port circuit including the NMOS transistors N9-1 and N10-1 connected to the read word line RWL-1 and the bit line / RBL-1. RP1-1,..., From NMOS transistors N9- (N-1) and N10- (N-1) connected to the read word line RWL- (N-1) and the bit line / RBL- (N-1). Read port circuit RP1- (N-1), and a plurality of N read port circuits.
(B) In addition to the read port circuit RP0 including the NMOS transistors N11 and N12, the read port circuit RP0 including the NMOS transistors N11-1 and N12-1 connected to the read word line RWL-1 and the bit line RBL-1. −1,..., Read-out composed of NMOS transistors N11- (N-1) and N12- (N-1) connected to the read word line RWL- (N-1) and the bit line RBL- (N-1). A port circuit RP0- (N-1) is provided, and a plurality of N read port circuits are provided.
When configured as described above, a multi-port SRAM having three or more ports can be configured.

FIG. 10 is a plan view showing a layout of a 9T / 18T bit cell pair prototyped by a 65 nm process according to an embodiment of the present invention. The design is based on the following logic design rules: all transistors have a minimum size (W / L = 170/60 μm). The area of the pair cells is 3.075 × 1.100μm ^2, the area of each 7T / 14T SRAM (= 2.43 × 1.1μm 2) and 2-bit 8T memory cell (= 2.70 × 1.1 .mu.m ² ) With 26.54% and 12.20% overhead. As shown in FIG. 10, the entire SRAM area can be reduced by inserting a different memory cell in the upper left portion and inserting another memory cell in the lower right portion.

FIG. 11 is a photograph showing a macro layout of a 9T / 18T SRAM using the 9T / 18T bit cell pair of FIG. The inventors prototyped a 128 Kb SRAM macro with 65 nm process technology for measurement and evaluation. The core size of the 9T / 18T SRAM macro is 1130 × 413 μm ² . The macro includes 8 blocks (block size, 141 × 413 μm ² ), each of which has a 16 kb array (128 rows × 8 columns × 16 bits), an address decoder, a write driver, and an external single-ended read bit line. And two sets of sense amplifiers for the inner and outer differential read bit lines. The sense amplifier circuit employs a latch-type sense amplifier that is generally used.

  FIG. 12 is a graph showing a bit error rate (BER) with respect to operating voltages at the time of four read operations in a prototype 9T / 18T SRAM. The frequency was 1 MHz. As is clear from FIG. 12, in the case of the inner differential read bit line and the outer single-ended bit line in the normal mode, the minimum operating voltages were 0.67V and 0.72V, respectively. Here, the minimum operating voltage in the case of a single-ended bit line is deteriorated by 50 mV compared to the case of a differential bit line. This is because a single swing bit line requires a full swing. However, in the high reliability mode, in the case of the outer bit line, the minimum operating voltage is reduced to 0.45 V (reduction of 90 mV) for so-called “disturb-free” differential reading, while the inner differential In the case of a bit line, 0.54 V is required as the minimum operating voltage. This reduction in the minimum operating voltage has a specific effect of significantly reducing the power consumption in the low voltage region.

  SRAM macros were designed in a triple well process to apply substrate bias and evaluate operation at various process corners. In other words, the substrate bias control gives a global threshold voltage fluctuation, which can be said to evaluate the reliability under the global threshold fluctuation. In order to guarantee the accuracy of threshold voltage control, PMOS and NMOS test transistors were formed on the chip for characteristic measurement.

  Table 1 shows the substrate bias settings emulating four process corners (FF, FS, SF, and SS). ΔVtn represents the threshold voltage difference of the NMOS transistor from the manufactured CC transistor, and Δ | Vtp | represents the threshold voltage difference of the PMOS transistor from the manufactured CC transistor.

  FIG. 13 is a graph showing the power supply voltage Vdd with respect to the access time at the time of differential reading via the inner bit line in the normal mode in the prototype 9T / 18T SRAM. FIG. 14 is a graph showing the power supply voltage Vdd with respect to the access time at the time of single-ended reading via the outer side bit line in the normal mode in the prototype 9T / 18T SRAM. Further, FIG. 15 is a graph showing the power supply voltage Vdd with respect to the access time at the time of differential reading via the inner bit line in the high reliability mode in the prototype 9T / 18T SRAM. FIG. 16 is a graph showing the power supply voltage Vdd with respect to the access time at the time of differential reading via the outer bit line in the high reliability mode in the prototype 9T / 18T SRAM.

  13 to 16 show the power supply voltage with respect to the access time when the substrate bias is applied according to Table 1. FIG. The access time is the time from when the clock rises until the output is fixed, and includes the delay time in the decoder, word line, bit line charge and discharge, sense amplifier, and terminal input / output buffer. . The substrate bias voltage is applied not only to the bit cell array but also to all peripheral circuits except the input / output buffer.

  FIG. 13 shows the result of the inner differential reading in the normal mode, which is most affected by the threshold voltage fluctuation, and each operating voltage varies widely. FIG. 14 shows the result of the outer single-ended reading in the normal mode. The data reading inverter requires a full swing, which causes a particularly slow operation at the process corners of FF and SF. This is because a more powerful PMOS transistor discharges the bit line even when reading at the H level, which may cause an error in the read operation. 15 and 16 show the results in the case of inner differential reading and outer differential reading in the high reliability mode, respectively. In the case of the outer differential reading, improved performance is shown due to the so-called “disturb-free” feature, but in the case of the inner differential reading, the result is slower particularly in the process corner of the SF.

  As described above, according to the present embodiment, it is possible to provide a 9T / 18T SRAM having an operating voltage margin improved more than that of a conventional 7T / 14T SRAM. The topology of the 9T / 18T bit cell according to this embodiment includes a conventional 7T / 14T cell and additional read port circuits RP0 and RP1. In the 9T / 18T SRAM, the additional read port circuits RP0 and RP1 can be operated without worrying about the static noise margin for the so-called “disturb-free” read operation. As a result, the 9T / 18T SRAM operates more stably than the 7T / 14T SRAM under fluctuations in threshold voltage. The inventors made a trial manufacture of the SRAM according to the present embodiment using a triple well process of 65 nm. As a result of the measurement, in the read operation in the high reliability mode using the additional read port circuits RP0 and RP1, the fluctuation of the threshold voltage can be suppressed and the operation voltage can be lowered to 0.45V. It was. On the other hand, the read operation in the high reliability mode using the conventional inner port requires an operating voltage of 0.54V. Further, the substrate bias control exposes the weakness of the conventional 7T / 14T SRAM, and the 9T / 18TSRAM according to the present embodiment is more resistant to various unbalanced process corners than the 7T / 14T SRAM, especially to the SF process corners. It was clarified that it has high reliability.

  As described above in detail, according to the semiconductor memory device of the present invention, it is possible to provide a multi-port semiconductor memory device that operates at a lower power supply voltage compared to the prior art. In particular, since an additional read port circuit is provided, it is possible to operate without worrying about the static noise margin for the so-called “disturb-free” read operation. As a result, it is possible to operate stably as compared with the prior art under the threshold voltage fluctuation. According to the measurement result of the prototype device prototyped using the 65 nm triple well process by the present inventor, the threshold voltage fluctuation is not detected in the read operation in the high reliability mode using the additional read port circuit. The operating voltage could be reduced to 0.45V. On the other hand, the read operation in the high reliability mode using the conventional internal read port requires an operating voltage of 0.54V. Further, in the semiconductor memory device, each memory cell adjacent to each other in a predetermined first direction is configured to share the first bit line, or substantially orthogonal to the first direction. By sharing the first word line among the memory cells adjacent to each other in the second direction, the occupied area can be greatly reduced as compared with the prior art.

LD ... Normal mode block,
HD ... High reliability mode block,
BL, / BL, RBL, / RBL, RBL-n, / RBL-n ... bit lines,
/ CL: Control line,
P1-P12, N1-N12, N11a, N12a, N9n, N10n ... MOS transistors,
RP0, RP1, RP0a, RP1a, RP0b, RP0-n, RP1-n... Read port circuit,
RWL, / RWL ... Read word line,
MC0, MC1, MC0a, MC1a, MC0b ... memory cells,
SA, SA1, SA2 ... sense amplifier,
V1 to V4 ... inverter,
WL, / WL, WL0 to WL1,.

Claims (7)

A latch circuit comprising a pair of inverters having two data holding nodes connected to a pair of first bit lines arranged corresponding to a column of memory cells and being cross-coupled;
A pair of first switch portions respectively provided between the pair of first bit lines and the data holding nodes of the pair of inverters;
A memory cell of a semiconductor memory device configured to include a first word line that controls conduction of the pair of first switch portions,
A first mode in which each data holding node of each of the plurality of memory cells is separated for each memory cell and each bit has one memory cell, and each data holding of each of the plurality of memory cells is held. In a semiconductor memory device comprising: a second switch unit that connects nodes in parallel and selectively switches a second mode in which one bit is composed of a plurality of the memory cells;
In response to a signal from the second word line, a third mode in which one data holding node of each of the data holding nodes of the plurality of memory cells is connected to the second bit line and a first mode not connected 4. A semiconductor memory device, further comprising a third switch section for selectively switching between the four modes.   2. The semiconductor according to claim 1, wherein in the second mode, each data holding node of the two memory cells is connected in parallel and one bit is constituted by the first and second memory cells. Storage device.   In the third mode, the third switch unit connects one data holding node among the data holding nodes of the first memory cell in response to a signal from the second word line. One data holding node of each of the data holding nodes of the second memory cell is connected to one bit line of the second bit lines, and the other bit of the pair of second bit lines 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is connected to a line.   In the third mode, the third switch unit connects one data holding node among the data holding nodes of the first memory cell in response to a signal from the second word line. One data holding node of each of the data holding nodes of the second memory cell is connected to one bit line of the second bit lines, and one bit of the pair of second bit lines. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is connected to a line. When the first mode is set by the second switch unit and the fourth mode is set by the third switch unit, the data stored in the latch circuit is transferred from each data holding node. Each differentially read through the pair of first switch sections and the pair of first bit lines,
When the first mode is set by the second switch unit and the third mode is set by the third switch unit, the data stored in the latch circuit is transferred from each data holding node. Each read out in a single end via the pair of third switch sections and the pair of second bit lines,
When the second mode is set by the second switch unit and the fourth mode is set by the third switch unit, the data stored in the latch circuit is transferred from each data holding node. Each differentially read through the pair of first switch sections and the pair of first bit lines,
When the second mode is set by the second switch unit and the third mode is set by the third switch unit, the data stored in the latch circuit is transferred from each data holding node. 4. The semiconductor memory device according to claim 3, wherein the data is read out differentially through the pair of third switch sections and the pair of second bit lines.   6. The semiconductor memory according to claim 1, wherein each of the memory cells adjacent to each other in a predetermined first direction is configured to share the first bit line. apparatus.   7. The semiconductor memory device according to claim 6, wherein each of the memory cells adjacent to each other in a second direction substantially perpendicular to the first direction shares the first word line. .