JP2012169512A - Electronic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic circuit which can distribute accurately synchronized clocks to respective substrates despite its simple structure.SOLUTION: An electronic circuit comprises: a first substrate 11 which has a first oscillator 21 including a first resonance circuit made up of a first coil L1 and a first capacitor C1; and a second substrate 12 which has a second oscillator 22 including a second resonance circuit made up of a second coil L2 and a second capacitor C2. The first coil L1 and the second coil L2 are inductively coupled to each other so that the first oscillator 21 and the second oscillator 22 resonate in a coupled manner.

Description

  The present invention can be used when a plurality of semiconductor chips (or electronic circuit boards) are stacked in multiple layers in the same apparatus (or arranged sideways and a magnetic material is used to guide magnetic flux), or semiconductor chips (or When a plurality of devices equipped with an electronic circuit board) are placed close together (closely placed by inserting the device into a slot or in close contact with a predetermined surface), the clock is wirelessly distributed to the semiconductor chip (or electronic circuit board) The present invention relates to an electronic circuit that can be used. The clock distributed to each board can be used as a system clock for each board. For example, it is suitable to construct a system in which a plurality of chips are stacked and mounted, and to operate each chip in synchronization with a common system clock. Further, high-speed serial data transmission can be performed using the clock. For example, it can be used for timing control of serial data communication between chips when the same memory chip such as a NAND flash memory or DRAM is stacked and mounted in a package. . Alternatively, it can also be used for timing control of serial data communication between chips when different chips such as a processor and DRAM are stacked in a package. Further, for example, a printed circuit board that can be inserted and removed, such as between a memory card and a personal computer, can be used for timing control of serial data communication between boards when they are arranged close to each other to form an interface.

  The present inventors have proposed an electronic circuit that performs data communication between stacked chips and substrates by using inductive coupling of coils formed by wiring of a semiconductor integrated circuit chip and an electronic circuit substrate (Patent Literature). 1-13, a nonpatent literature 1-3 reference).

The typical ones are as follows.
(1). Electronic circuit capable of wireless data communication between three or more substrates using inductive coupling of coils formed by wiring on the substrate when three or more substrates are stacked and mounted (Patent Document 1) .

(2). An electronic circuit having the same basic structure and capable of performing data communication using inductive coupling between substrates mounted in layers and supplying power by wiring (Patent Document 5).

(3). An electronic circuit capable of performing burst transfer of data at a speed higher than the system clock by using inductive coupling between semiconductor chips (Patent Document 6). This electronic circuit generates a high-speed timing signal on the transmission side, and uses this to multiplex transmission data by parallel-serial conversion, and the multiplexed data is combined with the timing signal from the transmission chip to the reception chip using inductive coupling. The original data can be restored by serial-to-parallel conversion of the received signal at the timing generated from the received timing signal. The timing signal generated by a simple oscillator on the transmitter chip does not have a constant frequency due to device variations or fluctuations in power supply voltage or temperature, or contains relatively large jitter due to noise. High-speed data transmission can be ensured by using a signal source synchronous method that sends the signals in parallel.

(4) Receiving the signal from the transmitter, recognizing the transmission source and the reception destination, and if there is a chip between the transmission source and the reception destination, the received signal is relayed, so that the dimensions of the coil An electronic circuit that can transfer data to a farther chip at a high speed (Patent Document 9).

(5) An electronic circuit in which a processor and an SRAM chip are stacked and mounted in a package so that the processor can read and write data to and from the SRAM by wireless data communication between chips (Non-patent Document 1).

(6) An electronic circuit in which a NAND flash memory is stacked and mounted in a package, and data can be read from and written to the memory by inter-chip wireless data communication (Non-Patent Document 2).

(7) An electronic circuit capable of high-speed data transfer without contact between a personal computer and a memory card inserted in the slot (Non-patent Document 3).

JP 2005-228981 A JP 2005-348264 A JP 2006-066644 A JP 2006-173986 A International Publication No. 2009/069532 JP 2009-188468 A JP 2009-266109 A JP 2009-277842 A JP 2009-295699 A JP 2010-015654 A JP 2010-045166 A JP 2010-199280 A JP 2010-287113 A

K. Niitsu, Y. Shimazaki, Y. Sugimori, Y. Kohama, K. Kasuga, I. Nonomura, M. Saen, S. Komatsu, K. Osada, N. Irie, T. Hattori, A. Hasegawa, and T Kuroda, "An Inductive-Coupling Link for 3D Integration of a 90nm CMOS Processor and a 65nm CMOS SRAM," IEEE International Solid-State Circuits Conference (ISSCC'09), Dig. Tech. Papers, pp.480-481, Feb. 2009 . Y. Sugimori, Y. Kohama, M. Saito, Y. Yoshida, N. Miura, H. Ishikuro, T. Sakurai and T. Kuroda, "A2Gb / s 15pJ / b / chip Inductive-Coupling Programmable Bus for NAND Flash MemoryStacking , "IEEE International Solid-State Circuits Conference (ISSCC'09), Dig. Tech. Papers, pp.244-245, Feb. 2009. S. Kawai, H. Ishikuro, and T. Kuroda, “A 2.5Gb / s / ch Inductive-Coupling Transceiver for Non-Contact Memory Card,” IEEE International Solid-State Circuits Conference (ISSCC'10), Dig.Tech. Papers , pp.264-265, Feb. 2010. Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, HisakatuYamaguchi, Junji Ogawa, and Tadahiro Kuroda, “18-GHz ClockDistribution Using a Coupled VCO Array,” IEICE Trans. Electron, Vol. E90-C, No. 4, pp.811-822 , April 2007.

  Focusing on the timing signals for serial communication of data in these conventional inventions, the signals are transferred from the substrate to the substrate by inductive coupling in parallel with the data. That is, the timing signal generated on the first board is transferred from the transmission circuit on the first board to the reception circuit on the second board, and then transferred from the transmission circuit on the second board to the reception circuit on the third board, In the same manner, timing signals were transferred and distributed from substrate to substrate (see Patent Document 9). As a result, the transmission circuit and the reception circuit consume power every transfer, and the power consumption is relatively large. Further, in order to prevent an unintended signal from being received from the transmission circuit to the reception circuit, each chip requires three coils: a transmission coil, a reception coil, and an unused coil.

  In order to solve this problem, even if each substrate is provided with an oscillation circuit, the oscillation frequency of the oscillation circuit is typically 10% due to differences in device characteristics due to manufacturing variations, differences in power supply voltage, and the like. There were variations of the degree, and it was difficult to distribute an accurate clock and to synchronize serial communication.

  Also, even if the clock is distributed over the wire instead of wirelessly, when generating the clock on one board and distributing the clock to the other board, the phase of the clock may shift due to the delay due to the wiring between the chips, There has been a problem that power consumption increases due to a parasitic capacitance in wiring between chips and a circuit for preventing electrostatic breakdown necessary for wiring between chips.

As another viewpoint, there is known an example in which output signals of a plurality of LC oscillators provided on the same chip are coupled through a transmission line to oscillate (see Non-Patent Document 4). Therefore, it cannot be applied to clock distribution between chips.
In view of the above problems, an object of the present invention is to provide an electronic circuit that can distribute clocks accurately synchronized to each board with a simple configuration.

  An electronic circuit according to a first aspect of the present invention includes a first substrate having a first oscillator including a first resonance circuit including a first coil and a first capacitor, and a second resonance circuit including a second coil and a second capacitor. And a second substrate having a second oscillator, wherein the first coil and the second coil are inductively coupled, and the first oscillator and the second oscillator are coupled and resonated.

  The electronic circuit of the present invention according to claim 2 is characterized in that the change in magnetic flux passing through all the coils that are coupled and resonated is in phase.

  The electronic circuit of the present invention according to claim 3 is characterized in that the absolute values of the negative resistances of all the oscillators are smaller than the impedances of all the resonance circuits at the coupling resonance frequency of the resonance circuit, and the frequencies other than the coupling resonance frequency. The absolute value of the negative resistance is larger than the impedance.

  In the electronic circuit according to a fourth aspect of the present invention, the first to nth substrates are sequentially stacked (n is an integer of n ≧ 4. Hereinafter, the coils of each substrate are referred to as “kth coils” or the like). The degree of coupling between the first coil and the second coil and the degree of coupling between the (n-1) th coil and the nth coil are greater than the degree of coupling between the second coil and the adjacent (n-1) th coil. It is characterized by.

  The electronic circuit of the present invention according to claim 5 is characterized in that all the substrates are semiconductor chips having the same structure.

  The electronic circuit of the present invention according to claim 6 is characterized in that a clock having the same frequency and phase is generated between the substrates by the oscillator.

  The electronic circuit of the present invention according to claim 7 is characterized in that serial data communication is performed between the substrates according to the timing by the clock.

  An electronic circuit according to an eighth aspect of the present invention is characterized in that a phase necessary for serial data communication is generated by extracting a phase from a received signal at the frequency of the clock.

  An electronic circuit according to a ninth aspect of the present invention includes a substrate having an oscillator including a resonance circuit including a coil and a capacitor, the coil is inductively coupled to another coil, and the oscillator is coupled and resonated, and is generated by the oscillator. Serial data communication is performed according to the timing of the clock.

  According to the present invention, it is possible to distribute clocks that are accurately synchronized with each other using a smaller power and layout area than in the past. The clock distributed to each board according to the present invention can be used as a system clock for each board. For example, it is suitable to construct a system in which a plurality of chips are stacked and mounted, and to operate each chip in synchronization with a common system clock. Further, it is suitable for application to serial communication of data between the substrates in synchronization with the clock signal.

It is a figure which shows the structure of the electronic circuit by Example 1 of this invention. It is a figure which shows the specific circuit example of Example 1 of this invention. It is a figure which shows the measurement result of the oscillation when the tail current of Example 1 of this invention is changed. It is a figure which shows the example of the waveform of the coupling resonance of Example 1 of this invention. It is a figure which shows the measurement result of the oscillation when the value of the capacitor of Example 1 of this invention is changed. It is a figure for demonstrating Example 2 of this invention. It is a figure which shows the structure of the electronic circuit by Example 3 of this invention. It is a figure which shows the actual measurement result of the communication quality of Example 3 of this invention. It is a figure which shows the example of the waveform of the received signal of Example 3 of this invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings.

  1 is a diagram illustrating a configuration of an electronic circuit according to a first embodiment of the present invention. FIG. 1A is a conceptual diagram showing the entire electronic circuit, and FIG. 1B is a circuit diagram showing a specific circuit on each substrate. A substrate 11 having an oscillator 21 including an LC resonance circuit of a coil L1 and a capacitor C1, and a substrate 12 having an oscillator 22 including an LC resonance circuit of a coil L2 and a capacitor C2 are stacked one above the other. Each of the oscillators 21 and 22 includes an LC resonance circuit of a coil 31 and a capacitor 32, a negative resistance having a value of −1 / gm, which includes two NMOS transistors 33 and 34 having a gate and a current source 35, Oscillates at the resonant frequency of the LC resonant circuit. When the central axes of the two coils L1 and L2 are approximately coincident and close to each other, the generated magnetic flux is shared by both the coils L1 and L2 due to the mutual inductance M12 of the coils L1 and L2, thereby causing coupled resonance. Various circuits other than the circuit shown in the figure are known as the LC resonance circuit, and the present invention is not limited to this embodiment.

  FIG. 2 is a diagram illustrating a specific circuit example of the first embodiment of the present invention. FIG. 2 (a) is the same as FIG. 1 (b). Oscillation continues when the absolute value 1 / gm of the negative resistance is smaller than the impedance ZLC of the LC resonance circuit. The absolute value of the negative resistance can be adjusted by changing the transconductance gm by changing the drain current of the NMOS transistor, that is, the tail current Itail (the transconductance gm is proportional to the square root of the drain current). That is, when the tail current Itail is increased, the transconductance gm increases and the absolute value 1 / gm of the negative resistance decreases.

  Here, as the tail current Itail is increased, the magnetic flux generated by the coils is increased, and the degree of coupling, which is the strength of coupling between the coils, is increased. The degree of coupling is also determined by the coupling coefficient kij between the coils shown in FIG. FIG. 2 (b) shows an oscillator of each substrate composed of negative resistors 41 to 4N and LC resonance circuit impedances ZLC, 1 to ZLC, N (capacitors are not shown), and the coupling coefficient kij represents the shape of each coil and It depends on the arrangement (mainly coil diameter and coil spacing). Therefore, the greater the tail current Itail and the greater the coupling coefficient k, the stronger the degree of coupling between the coils. However, the power consumption becomes larger or the layout area becomes larger. FIG. 2 (c) shows the result of simulating the condition for oscillation by coupled resonance. It can be seen that it is necessary to increase the coupling coefficient k of the coil or increase the tail current Itail in order to resonate.

  FIG. 3 is a diagram showing an actual measurement result of oscillation when the tail current of Example 1 of the present invention is changed. A test chip was actually manufactured with 0.18 μm CMOS technology and measured. When the tail current Itail is set to a certain value or more, coupling resonance occurs. Although the frequencies of the output signals Clk1 to Clk4 of the four oscillators are originally different, they coincide when the tail current Itail is increased and reaches a predetermined value (here, Itail = 0.21 mA) and coupling resonance occurs. I understand that The jitter of the output signal of each oscillator at the time of coupled resonance is 2.4% or less of one period, and is small enough to be used as a clock for communication or the like.

  FIG. 4 is a diagram illustrating an example of a waveform of coupling resonance according to the first embodiment of the present invention. That is, the waveforms of the output signals Clk1 to Clk4 when the four oscillators used in the actual measurement shown in FIG. The horizontal axis is time, and the vertical axis is an arbitrary scale. When coupled resonance occurs, it can be seen that the frequency and phase of each output signal are aligned.

  FIG. 5 is a diagram showing an actual measurement result of oscillation when the value of the capacitor of Example 1 of the present invention is changed. A chip was manufactured by changing only the capacitor of each oscillator used in the actual measurement of FIG. 3 so that other values were the same, and the state of coupling resonance was actually measured. The tail current Itail = 0.3 mA. When the value of the capacitor changes, the oscillation frequency fLC naturally changes. It can be seen that if the capacitor value varies and the oscillation frequency fLC of the oscillator is greatly different, coupled resonance cannot be achieved, but if the variation ΔC in the capacitor value is less than ± 17.5%, coupled resonance occurs. This indicates that when the capacitor manufacturing variation ΔC is within the normal range (10%), the coupling resonance is sufficiently achieved.

  Thus, the output of the oscillator having the same frequency and phase can be used as the system clock of each chip. A system in which a plurality of chips are stacked and built is constructed, and each chip can operate in synchronization with a common system clock.

  The output of the oscillator having the same frequency and phase can be used as a clock for inter-chip communication. Data transmitted at the timing of the clock of the first chip can be received by a timing signal generated from the clock of the second chip.

  FIG. 6 is a diagram for explaining a second embodiment of the present invention. The absolute value 1 / gm (three types) of the negative resistance and the impedance of each resonance circuit when the LC resonance circuits on the four substrates shown in Example 1 are coupled to the frequency on the horizontal axis are shown. This is a result obtained by combining electromagnetic field analysis and electronic circuit analysis simulation. As described above, oscillation continues when the absolute value 1 / gm of the negative resistance is smaller than the impedance of the LC resonance circuit. Further, when the tail current Itail is increased, the transconductance gm increases, and the absolute value 1 / gm of the negative resistance decreases.

In FIG. 6, the two solid lines represent the impedances ZLC, 1, ZLC, 4 of the resonance circuits on the substrate disposed at both ends, and the two broken lines represent the impedances of the resonance circuits on the substrate sandwiched between them. ZLC, 2 and ZLC, 3 are shown. In the frequency response of the impedance, peaks appear around 5.2 GHz, 6.6 GHz, and 7.5 GHz in addition to 2.5 GHz. At the 2.5 GHz peak, the four oscillators are all in phase. At the peak of 5.2 GHz, the phases of three adjacent oscillators are in phase, and the phase of the oscillator arranged at the extreme end is in reverse phase. That is, for example, the first, second and third are in phase and the fourth is out of phase. At the peak around 6.6 GHz, the phases of two adjacent oscillators, eg the first and second, are in phase, the other two adjacent oscillators, the third and fourth phases are out of phase with them. is there. At the peak around 7.5 GHz, they are alternately in-phase and anti-phase. That is, the first and third are in phase, and the second and fourth are in reverse phase. As the number of boundaries whose phases are different from each other increases, the mutual magnetic flux cancels out and the inductance appears to be small, so the oscillation frequency increases.
Resonance angular frequency ω = √ (1 / LC) (1)
Q = ωL / R = √ (L / C) / R (2)
Where L: Resonance circuit inductance
C: Resonance circuit capacitance
R: Parasitic resistance of resonant circuit
Q: If the inductance L appears to be ¼, the oscillation frequency is doubled if the inductance L appears to be ¼, but if the parasitic resistance R does not change, the Q value becomes ½ and the peak value. Becomes smaller.

  From the above, if the tail current Itail is increased and the absolute value 1 / gm of the negative resistance is adjusted to be smaller than the impedance of the resonant circuit at 2.5 GHz, which is the frequency at which the coupling resonance occurs, oscillation occurs at 2.5 GHz. . At the same time, if the absolute value 1 / gm of the negative resistance is larger than the impedance of the resonance circuit in other frequencies, particularly in the frequency region of 5 GHz or more which is twice that frequency, the oscillation circuit has a frequency other than 2.5 GHz. Will not oscillate.

  FIG. 7 is a diagram showing a configuration of an electronic circuit according to the third embodiment of the present invention. Each of the N chips 1 to N has the same basic configuration, but here, a configuration that operates to explain a case where a signal is transmitted from the transmitter 71 of the chip 1 to the receiver 73 of the chip N is indicated by a solid line. A configuration that does not operate here is indicated by a broken line. Each of the chips 1 to N has an oscillator that is composed of negative resistors 41 to 4N and LC resonance circuit impedances ZLC, 1 to ZLC, N and generates a clock. In the chip 1, a transmission clock Txc (flip-flop (FF) 74) divides transmission data from a clock (for example, 5 GHz) from an oscillator into 1 / m (m is a natural number, for example, 2) by a frequency dividing circuit 75. For example, the serial signal Txd is sent to the transmitter 71. The transmitter 71 transmits the serial signal Txd to the receiver 73 of the chip N through or without the relay 72 of the chip 2. In the chip N, first, the frequency dividing circuit 75 divides the clock from the coupled resonant oscillator by 1 / m × n (n is a natural number, for example, 4; therefore, in this case, 2 × 4 = 8). The result is 625 MHz.) Further, the phase-locked loop (PLL) 76 including the phase frequency detection circuit 77, the 1 / n frequency divider 78, the charge pump 79, and the voltage control oscillator 80 is connected to the oscillation signal ( For example, the signal (for example, 625 MHz) obtained by dividing the 1 / n frequency divider 78 by 1 / n and the frequency and phase of the clock from the frequency divider 75 are detected and charged so that they are the same. A control voltage VCT is supplied to the voltage controlled oscillator 80 via the pump 79. Further, the phase-locked loop 76 supplies the control voltage VCT to the voltage controlled oscillator 81, and controls the voltage controlled oscillator 81 to oscillate at the same frequency and arbitrary phase as the voltage controlled oscillator 80. On the other hand, the edge detection circuit 82 detects the rising or falling edge of the signal received by the receiver 73, and the voltage controlled oscillator 81 is injection-locked at that timing. The FF 83 converts the serial reception signal Rxd into parallel data to obtain reception data. At that time, the clock from the voltage controlled oscillator 81 is adjusted to a phase at which the FF 83 can capture data with a sufficient time margin.

  In the third embodiment, the clock frequency of each chip is adjusted by coupling resonance, and the clock phase is adjusted by the received signal. As a result, when data is transmitted from chip 1 to chip N, even if the signal is delayed due to parallel-serial conversion, transmission, (relay), reception, serial-parallel conversion, etc., manufacturing variations or environmental time changes Even if the delay amount fluctuates, a clock having an appropriate timing for reception can be generated.

  FIG. 8 is a diagram illustrating actual measurement results of communication quality according to the third embodiment of this invention. The bit error rate when a test chip is actually manufactured by 0.18 μm CMOS technology, 16 chips are stacked and coupled and oscillated and serial data communication is performed for 8 channels in parallel is shown. It has been demonstrated that high-speed serial communication can be reliably performed up to a data transfer rate of 2.4 Gb / s.

FIG. 9 is a diagram illustrating an example of a waveform of a reception signal according to the third embodiment of the present invention. Following the measurement shown in FIG. 7, a large number of waveforms of received signals at a data transfer rate of 2.4 Gb / s were superimposed and photographed. This is a so-called eye pattern, and since the window is large, it has been demonstrated that high-speed serial communication can be reliably performed.
In addition, this invention is not limited to the said Example.

74, 83 Flip-flop 76 Phase-locked loop 77 Phase frequency detection circuit 78 n frequency division circuit 79 Charge pump 80, 81 Voltage controlled oscillator 82 Edge detection circuit

Claims (9)

A first substrate having a first oscillator including a first resonant circuit with a first coil and a first capacitor;
A second substrate having a second oscillator including a second resonance circuit including a second coil and a second capacitor, wherein the first coil and the second coil are inductively coupled, and the first oscillator and the second oscillator are coupled and resonated. An electronic circuit characterized by:   2. The electronic circuit according to claim 1, wherein changes in magnetic flux passing through all the coils that are coupled and resonated are in phase.   The absolute value of the negative resistance of all the oscillators is smaller than the impedance of all the resonant circuits at the coupled resonant frequency of the resonant circuit, and the absolute value of the negative resistance than the impedance at a frequency other than the coupled resonant frequency. The electronic circuit according to claim 1, wherein the electronic circuit is large.   The first to nth substrates are sequentially stacked (n is an integer of n ≧ 4. Hereinafter, a coil of each substrate is referred to as a “kth coil” or the like), and the degree of coupling between the first coil and the second coil. The coupling degree between the (n-1) th coil and the nth coil is larger than the coupling degree between the second coil and the adjacent (n-1) th coil. The electronic circuit described.   5. The electronic circuit according to claim 1, wherein all the substrates are semiconductor chips having the same structure.   6. The electronic circuit according to claim 1, wherein clocks having the same frequency and phase are generated between the substrates by the oscillator.   The electronic circuit according to claim 6, wherein serial data communication is performed between the substrates according to timing based on the clock.   8. The electronic circuit according to claim 7, wherein a phase necessary for serial data communication is generated by extracting a phase from a received signal at the frequency of the clock. A substrate having an oscillator including a resonance circuit including a coil and a capacitor, wherein the coil is inductively coupled to another coil, the oscillator is coupled and resonated, and serial data communication is performed at a timing based on a clock generated by the oscillator. A featured electronic circuit.