JP2012169444A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a transistor having different threshold voltages for different uses, and to provide a manufacturing method of the semiconductor device that prevents the increase of the number of processes.SOLUTION: A semiconductor device 100 includes a first MISFET 150 of a first conductive type which has a first gate insulation film 110a formed on a semiconductor substrate 101, a first gate electrode 109a formed on the first gate insulation film 110a, and a first side wall insulation film 140a formed on a side surface of the first gate insulation film 110a and a side surface of the first gate electrode 109a. A chemical element for inducing positive or negative fixed electric charges in the first gate insulation film 110a is included in at least a part of the first side wall insulation film 140a.

Description

  The technology described in this specification relates to a semiconductor device including a MIS transistor having a high-k gate insulating film and a so-called metal gate electrode.

  In a semiconductor device, it is necessary to make several types of transistors such as a core transistor and an I / O (Input / Output) transistor according to the purpose of use.

  Core transistors are used in circuits that require high-speed operation. In a core transistor that requires high-speed operation, the gate insulating film is thinned to increase the capacity of the transistor, thereby obtaining a high driving capability. Further, since the gate insulating film is thin, the threshold voltage is lowered.

  On the other hand, the I / O transistor is in charge of data input / output. In an I / O transistor, the gate insulating film is thickened to increase the withstand voltage of the transistor. Since the gate insulating film of the I / O transistor is thick, the threshold voltage is higher than that of the core transistor.

  A low standby power (LSTP) transistor is used when the standby power consumption needs to be as small as possible. In LSTP transistors, the thickness of the gate insulating film is often between the gate insulating film of the core transistor and the gate insulating film of the I / O transistor.

  Thus, a desired semiconductor device can be obtained by adjusting the thickness of the gate insulating film and adjusting the threshold voltage for each transistor for each application.

  Japanese Patent Application Laid-Open No. H10-133707 discloses a method of separately creating transistors for each application when a silicon oxynitride film is used as the gate insulating film. In this method, the thickness of the silicon oxynitride film and the nitrogen concentration in each transistor are adjusted stepwise by repeatedly patterning the insulating film and combining radical nitriding. By changing the dielectric constant of the gate insulating film by adjusting the nitrogen concentration, the electrical effective oxide thickness (EOT: Equivalent Oxide Thickness) can be reduced. As a result, the gate leakage current can be reduced and the driving capability can be improved.

JP 2002-368122 A

  However, the above-described method requires multiple times of patterning for forming a gate insulating film for each application, and there is room for further reduction in the number of steps.

  In a transistor employing a high-k gate insulating film and a metal gate, a cap layer containing an element capable of adjusting the work function of the metal gate is formed on the high-k gate insulating film, and the work function is obtained from the cap layer. The threshold voltage is adjusted by diffusing the element for adjustment up to the interface between the high-k gate insulating film and the underlying silicon oxide film. The adjustment of the threshold voltage needs to be considered in a comprehensive system including the metal gate electrode material, the cap layer, the high-k gate insulating film, and the underlying silicon oxide film. Therefore, when the above-described conventional technique of repeatedly patterning is applied to a high-k gate insulating film / metal gate system, more complicated and many steps are required.

  In view of the above, an object of the present invention is to form a semiconductor device having a transistor having a different threshold voltage depending on the application while suppressing an increase in the number of steps.

  In order to solve the above problems, a semiconductor device according to an example of the present invention includes a first gate insulating film formed over a semiconductor substrate, and a first gate electrode formed over the first gate insulating film. A first conductivity type first MISFET having a first sidewall insulating film formed on a side surface of the first gate insulating film and on a side surface of the first gate electrode, At least part of the sidewall insulating film contains a first element for inducing positive or negative fixed charges in the first gate insulating film. Note that an element for inducing a fixed charge in the gate insulating film can be restated as an element for adjusting the work function of the gate electrode.

  According to this configuration, since the first element for inducing positive or negative fixed charges is included in the first sidewall insulating film, the first element is converted into the first element by heat treatment during manufacturing. Can be diffused into the gate insulating film. Since the concentration of the first element diffused from the first sidewall insulating film decreases as the gate length increases, the threshold value of the MISFET can be adjusted by the length of the gate length. In general, the MISFET has a sidewall. In the semiconductor device according to an example of the present invention, the first element contained in the first sidewall is diffused into the first gate insulating film. Since the threshold value can be controlled, the threshold value can be controlled while suppressing an increase in the number of steps.

  A semiconductor device according to an example of the present invention is formed on the second gate insulating film formed on the semiconductor substrate and the second gate insulating film, and has a gate length shorter than that of the first gate electrode. A second MISFET of the first conductivity type having a second gate electrode and a second sidewall insulating film formed on the side surface of the second gate insulating film and on the side surface of the second gate electrode May be further provided. In this case, at least a part of the second sidewall insulating film contains a second element for inducing a fixed charge having the same polarity as the first element in the second gate insulating film. If so, the concentration of the first element diffused into the first gate insulating film and the concentration of the second element diffused into the second gate insulating film can be made different. Therefore, the threshold value of the first MISFET and the threshold value of the second MISFET can be made different, and each MISFET can be used for different applications.

  The semiconductor device according to the present invention further includes a third MISFET and a fourth MISFET of the second conductivity type both formed on the semiconductor substrate, wherein the first element is the first gate insulating film. An element for inducing a positive fixed charge therein, the second element is an element for inducing a positive fixed charge in the second gate insulating film, and the third MISFET has: A third gate insulating film formed on the semiconductor substrate; a third gate electrode formed on the third gate insulating film; a side surface of the third gate insulating film; and the third gate insulating film. A third sidewall insulating film formed on a side surface of the gate electrode and including at least part of a third element for inducing a negative fixed charge in the third gate insulating film, The fourth MISFET has the semiconductor substrate. A fourth gate insulating film formed thereon, a fourth gate electrode formed on the fourth gate insulating film and having a gate length shorter than the third gate electrode; and the fourth gate insulating film A fourth side formed on the side surface of the film and on the side surface of the fourth gate electrode and including at least part of a fourth element for inducing a negative fixed charge in the fourth gate insulating film; You may have a wall insulating film.

  A method of manufacturing a semiconductor device according to an example of the present invention includes a first conductivity type first having a first gate insulating film, a first gate electrode, and a first sidewall insulating film formed on a semiconductor substrate. This is a method for manufacturing a semiconductor device including the MISFET. Specifically, the step (a) of forming the first gate insulating film and the first gate electrode provided on the first gate insulating film, and the first gate insulating film The first sidewall insulation including at least a part of a first element for inducing positive or negative fixed charges in the first gate insulating film on the side surface and the side surface of the first gate electrode. And (b) forming a film.

  According to this method, since the first sidewall insulating film containing the first element for inducing a fixed charge is formed in the first gate insulating film, the first element is transferred to the first gate insulating film. By diffusing into the insulating film, the threshold value of the first MISFET can be adjusted. At this time, if the gate length of the first MISFET is lengthened, the concentration of the element diffused into the first gate insulating film is lowered, so that the threshold voltage varies according to the gate length. Therefore, by adjusting the gate length of the first MISFET, the threshold value of the first MISFET can be adjusted to an appropriate value according to the application.

  In addition, since the threshold value can be adjusted using an element contained in the sidewall insulating film for forming the extension region or the source / drain region, the work function adjusting film is used as the gate insulating film and the gate electrode. It is possible to adjust the threshold value of the MISFET to an appropriate value with fewer steps than in the case of forming between the two. Further, according to the above-described method, the threshold value can be controlled even when the MISFET is miniaturized.

  Further, if the method further includes a step (c) of performing a heat treatment to diffuse the first element contained in the first sidewall insulating film into the first gate insulating film, the first MISFET This is preferable because the threshold value can be reliably controlled.

  The semiconductor device further includes a first conductivity type second MISFET having a second gate insulating film, a second gate electrode, and a second sidewall insulating film formed on the semiconductor substrate. In the step (a), the second gate insulating film and the second gate electrode provided on the second gate insulating film and having a gate length shorter than that of the first gate electrode are formed. Further, in the step (b), positive or negative fixed charges are induced on the second gate insulating film on the side surface of the second gate insulating film and on the side surface of the second gate electrode. The second sidewall insulating film containing at least part of the second element for forming the second element is formed, and in the step (c), the second sidewall insulating film contained in the second sidewall insulating film is formed by heat treatment. The second gate isolation element It may be diffused into the film.

  According to this method, it is possible to simultaneously produce a plurality of MISFETs having the same conductivity type and different threshold values.

  The semiconductor device includes: a third MISFET of a second conductivity type having a third gate insulating film, a third gate electrode, and a third sidewall insulating film formed on the semiconductor substrate; and the semiconductor substrate A fourth MISFET of the second conductivity type having a fourth gate insulating film, a fourth gate electrode, and a fourth sidewall insulating film formed thereon, before the step (b) Or after the step (b) and before the step (c), on the side surface of the third gate insulating film and the side surface of the third gate electrode; Forming the third sidewall insulating film including at least part of an element for inducing a negative fixed charge on the side surface of the fourth gate insulating film and the side surface of the fourth gate electrode; , Negative in the fourth gate insulating film It may further include a step of forming the fourth side wall insulating film at least partially including an element for inducing a constant charge (d). In this case, in the step (a), the third gate insulating film and the third gate electrode provided on the third gate insulating film are further formed, and the fourth gate insulating film is formed. And a fourth gate electrode provided on the fourth gate insulating film and having a gate electrode shorter than the third gate electrode. In the step (c), the first gate electrode is formed by heat treatment. An element for inducing a fixed charge contained in the third side wall insulating film and an element for inducing a fixed charge contained in the fourth side wall insulating film. Is diffused into the fourth gate insulating film.

  By this method, MISFETs having different conductivity types can be manufactured by a common process while suppressing an increase in the number of processes. Further, by controlling the gate length, the threshold value of each conductivity type MISFET can be appropriately adjusted to a value according to the application.

  According to the method for manufacturing a semiconductor device according to an example of the present invention, it is possible to manufacture a MISFET having an appropriate threshold voltage for each application by changing the gate length while suppressing an increase in the number of steps.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the modification of the 1st Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In this specification, “High-k film (or high dielectric constant film)” refers to a film containing a High-k material having a dielectric constant larger than that of at least silicon nitride. "Means a material having a dielectric constant greater than at least silicon nitride. Further, the “metal gate (electrode)” refers to a gate electrode having an electrode made of a metal or a conductive metal compound.

(First embodiment)
-Description of manufacturing method-
1 to 13 are sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 1, an element isolation region 102 is formed on an upper portion of a semiconductor substrate 101, and a p-type well region (second conductive region) surrounded by the element isolation region 102 is further formed in the first region 10 of the semiconductor substrate 101. Type well region) 103 is formed, and an n-type well region (first conductivity type well region) 104 surrounded by the element isolation region 102 is formed in the second region 11 of the semiconductor substrate 101. Next, a base gate insulating film 105 and a high dielectric constant film 106 are sequentially formed on the semiconductor substrate 101. Here, the first region 10 is a region for forming a first conductivity type (for example, n-channel type) MISFET in the semiconductor substrate 101, and the second region 11 is the first region in the semiconductor substrate 101. This is a region for forming a two-conductivity type (for example, p-channel type) MISFET.

  In this step, the element isolation region 102 is formed, for example, by etching a predetermined region of the semiconductor substrate 101 to form a trench, and then embedding silicon oxide in the trench by a chemical vapor deposition (CVD) method. The element isolation region 102 is formed by removing the layer by chemical mechanical polishing (CMP) or the like.

  The p-type well region 103 is formed by implanting p-type impurity ions such as boron (B) into the first region 10 of the semiconductor substrate 101. Similarly, the n-type well region 104 is formed by implanting n-type impurity ions such as phosphorus (P) into the second region 11 of the semiconductor substrate 101.

The above-described base gate insulating film 105 is made of, for example, silicon oxide, and is formed with a film thickness of 1.0 nm or less by oxidizing the upper surface of the semiconductor substrate 101 by a thermal oxidation method or a plasma oxidation method. . The high dielectric constant film 106 includes at least one of hafnium (Hf) oxide and zirconium (Zr) oxide, and is formed on the base gate insulating film 105 by an atomic layer deposition (ALD) method, a CVD method, or the like. . In the present embodiment, for example, an HfO ₂ film having a thickness of 2.0 nm or less is formed as the high dielectric constant film 106.

  Next, as shown in FIG. 2, a first gate electrode film containing a conductive metal compound such as TiN or TaN on the high dielectric constant film 106 by physical vapor deposition (PVD), ALD, CVD, or the like. 107 and a second gate electrode film 108 made of polysilicon, for example, are sequentially formed.

  In the present embodiment, for example, a TiN film having a thickness of 20 nm or less is formed as the first gate electrode film 107. Further, as the second gate electrode film 108, for example, a polysilicon film having a thickness of 100 nm or less is formed on the first gate electrode film 107.

  Next, as shown in FIG. 3, a laminated structure including the second gate electrode film 108, the first gate electrode film 107, the high dielectric constant film 106, and the base gate insulating film 105 is known by photolithography and etching. Patterning is performed by As a result, the gate insulating film 110a, the gate electrode 109a formed thereon, the gate insulating film 110b, and the gate electrode 109b formed thereon are formed on the first region 10, respectively. The gate electrode 109c, the gate insulating film 110d formed thereon, and the gate electrode 109d formed thereon are formed on the second region 11, respectively. That is, in this step, a so-called gate stack structure including a gate insulating film and a gate electrode is formed.

  Here, the gate insulating film 110a is composed of a base gate insulating film 105a and a high dielectric constant film 106a, and the gate insulating film 110b is composed of a base gate insulating film 105b and a high dielectric constant film 106b. The gate insulating film 110c is composed of a base gate insulating film 105c and a high dielectric constant film 106c, and the gate insulating film 110d is composed of a base gate insulating film 105d and a high dielectric constant film 106d.

  The gate electrode 109a includes a first gate electrode film 107a and a second gate electrode film 108a, and the gate electrode 109b includes a first gate electrode film 107b and a second gate electrode film 108b. The gate electrode 109c is composed of a first gate electrode film 107c and a second gate electrode film 108c, and the gate electrode 109d is composed of a first gate electrode film 107d and a second gate electrode film 108d. The base gate insulating films 105a, 105b, 105c, and 105d may be made of silicon oxide or silicon oxynitride.

  The gate lengths of the gate electrode 109a and the gate electrode 109b (the length in the left-right direction shown in FIG. 3) are different from each other, and the gate lengths of the gate electrode 109c and the gate electrode 109d are also different from each other. In this embodiment, the gate length of the gate electrode 109a and the gate electrode 109c is 100 nm or more, preferably 400 nm, for example, and the gate length of the gate electrode 109b and the gate electrode 109d is less than 100 nm, preferably 40 nm.

Next, as shown in FIG. 4, lanthanum (La), scandium (Sc), or the like is formed on the semiconductor substrate 101 and on each upper surface and each side surface of the gate electrodes 109a, 109b, 109c, and 109d by the PVD method or the ALD method. The work function adjusting film 111 containing at least one work function adjusting element selected from rare earth elements and magnesium (Mg) is formed. Here, the element for adjusting the work function means an element for inducing positive fixed charges in the gate insulating films 110a and 110b. In the present embodiment, for example, a La ₂ O ₃ film having a thickness of 10 nm or less is formed as the work function adjusting film 111. The work function adjusting film 111 has an insulating property.

  Next, as shown in FIG. 5, after a portion of the work function adjustment film 111 formed on the first region 10 is covered with a resist 112a, as shown in FIG. The portion formed on the second region 11 is removed by etching, and the work function adjusting film 111 is left on the first region 10.

Next, as shown in FIG. 7, after removing the resist 112a, the work function adjustment film 111 provided on the first region 10, the second region 11 of the semiconductor substrate 101, and the gate electrode 109c, A work function adjusting film 113 containing an element for adjusting at least one work function selected from Al, Ti, Ta, and Hf is formed on each upper surface and each side surface of 109d by PVD method or ALD method. . Here, the element for adjusting the work function means an element for inducing a negative fixed charge in the gate insulating films 110c and 110d. In the present embodiment, for example, an Al ₂ O ₃ film having a thickness of 10 nm is formed as the work function adjusting film 113. The work function adjusting film 113 has an insulating property.

  Next, as shown in FIG. 8, after a portion of the work function adjustment film 113 formed on the second region 11 is covered with a resist 112b, as shown in FIG. The portion formed on the first region 10 is removed by etching, and the work function adjusting film 113 is left on the second region 11. Thereafter, the resist 112b is removed.

  In the above description, the work function adjustment film 113 is formed after the work function adjustment film 111 is formed. However, the work function adjustment film 111 may be formed after the work function adjustment film 113 is formed.

  Next, as shown in FIG. 10, the work function adjusting film 111 on the first region 10 and the work function adjusting film 113 on the second region 11 are dry-etched, respectively. Thus, the offset spacer 114a is formed on the side surfaces of the gate insulating film 110a and the gate electrode 109a, and the offset spacer 114b is formed on the side surfaces of the gate insulating film 110b and the gate electrode 109b. Further, an offset spacer 115a is formed on the side surfaces of the gate insulating film 110c and the gate electrode 109c, and an offset spacer 115b having an L-shaped cross section is formed on the side surfaces of the gate insulating film 110d and the gate electrode 109d.

  Next, as shown in FIG. 11, after the second region 11 is covered with a resist 112c, the p-type well region 103 is formed using the gate electrodes 109a and 109b and the offset spacers 114a and 114b on the first region 10 as a mask. N-type (first conductivity type) impurity ions are implanted to form n-type extension regions 117a on both sides of the gate electrode 109a, and n-type extension regions 117b on both sides of the gate electrode 109b.

  Subsequently, after forming an insulating film on the semiconductor substrate 101, the insulating film is etched to form a sidewall spacer 116a on the outer surface of the offset spacer 114a and on the outer surface of the offset spacer 114b. Sidewall spacers 116b are formed. Then, n-type impurity ions are implanted into the p-type well region 103 using the gate electrodes 109a and 109b, the offset spacers 114a and 114b, and the side wall spacers 116a and 116b as masks, and are extended on both sides of the gate electrode 109a. A source / drain region 118a is formed in the outer region of the region 117a. At the same time, source / drain regions 118b are formed on both sides of the gate electrode 109b and outside the extension region 117b. In FIG. 11, the offset spacer 114a and the sidewall spacer 116a are collectively shown as a sidewall insulating film 140a, and the offset spacer 114b and the sidewall spacer 116b are collectively shown as a sidewall insulating film 140b.

  Next, as shown in FIG. 12, after removing the resist 112c, the first region 10 is covered with a resist 112d. Subsequently, p-type (second conductivity type) impurity ions are implanted into the n-type well region 104 using the gate electrodes 109c and 109d and the offset spacers 115a and 115b on the second region 11 as masks, and are formed on both sides of the gate electrode 109c. A p-type extension region 117c is formed, and a p-type extension region 117d is formed on both sides of the gate electrode 109d.

  Subsequently, after an insulating film is formed on the semiconductor substrate 101, the insulating film is etched to form a sidewall spacer 136a on the outer surface of the offset spacer 115a and on the outer surface of the offset spacer 115b. Sidewall spacers 136b are formed on the substrate. Then, p-type impurity ions are implanted into the n-type well region 104 using the gate electrodes 109c and 109d, the offset spacers 115a and 115b, and the side wall spacers 136a and 136b as masks, and the extension is formed on both sides of the gate electrode 109c. A source / drain region 118c is formed in the outer region of the region 117c. At the same time, source / drain regions 118d are formed on both sides of the gate electrode 109d and outside the extension region 117d. In FIG. 12, the offset spacer 115a and the sidewall spacer 136a are collectively shown as a sidewall insulating film 140c, and the offset spacer 115b and the sidewall spacer 136b are collectively shown as a sidewall insulating film 140d.

  In this example, the extension regions 117c and 117d and the source / drain regions 118c and 118d are formed after the extension regions 117a and 117b and the source / drain regions 118a and 118b are formed. However, the extension regions 117c and 117d and the source / drain regions 118c and 118d The extension regions 117a and 117b and the source / drain regions 118a and 118b may be formed after the formation of the drain regions 118c and 118d.

  Next, as shown in FIG. 13, the resist 112d is removed. Subsequently, heat treatment at about 1000 to 1300 ° C. is performed to activate impurities contained in the extension regions 117a, 117b, 117c, and 117d and the source / drain regions 118a, 118b, 118c, and 118d, and offset spacers 114a and 114b. , 115a and 115b are diffused from both sides of the gate insulating films 110a, 110b, 110c, and 110d toward the center in the gate length direction. As a result, the work functions of the gate electrodes 109a and 109b of the n-channel MISFETs 150 and 152 on the first region 10 and the work functions of the gate electrodes 109c and 109d of the p-channel MISFETs 154 and 156 on the second region vary. And adjusted to the desired value. Note that the element for work adjustment diffuses in each gate electrode, but the effect of the element diffused in the gate electrode on the work function is compared to the effect of the element diffused in the gate insulating film on the work function. small. The semiconductor device 100 of this embodiment can be obtained through the above steps.

  According to the above manufacturing method, a transistor having a high-k gate insulating film / metal gate stack structure having different threshold voltages depending on the gate length can be obtained.

  This is due to the following reason. In the case of MISFETs having the same conductivity type and different gate lengths, the thickness of each offset spacer (for example, offset spacers 114a and 114b) is the same, whereas the volume of the gate insulating film (for example, gate insulating films 110a and 110b) is A MISFET with a long gate length is larger than a short MISFET. Therefore, the MISFET having a shorter gate length can diffuse more work function adjusting elements per unit volume into the gate insulating film than the MISFET having a longer gate length.

  As a result, in both the n-channel MISFET and the p-channel MISFET, the concentration of the work function adjusting element in the gate insulating film is relatively high in the MISFET having a short gate length, so that the threshold voltage is lowered. can do. On the other hand, in the MISFET having a long gate length, the concentration of the work function adjusting element in the gate insulating film is relatively low, so that the threshold voltage can be increased. That is, according to the manufacturing method of the present embodiment, the threshold voltage of the MISFET can be appropriately controlled by appropriately setting the length of the gate length.

  Further, in the method of the present embodiment, the type of the work function adjusting element included in the offset spacer is set to MISFET while the configuration of the gate insulating film and the configuration of the gate electrode are common to the n-channel type MISFET and the p-channel type MISFET. Therefore, the n-channel MISFET and the p-channel MISFET can be simultaneously formed on the same substrate without increasing the number of processes.

  That is, as compared with the case where a work function adjusting film (cap film) is formed on the first region 10 and the second region 11 between the step shown in FIG. 1 and the step shown in FIG. In the method of the present embodiment, an offset spacer for adjusting the formation position of the extension region is used as a work function adjusting element supply source. Therefore, the work function is adjusted appropriately according to the conductivity type of the MISFET, and the I / O is adjusted. Adjustment of an appropriate work function according to the use of MISFET such as a transistor and a core transistor can be realized while suppressing an increase in the number of processes. In addition, since a step of forming a cap film and a step of selectively removing the cap film are not necessary, film loss of the element isolation region 102 having a shallow trench isolation (STI) structure can be prevented. For this reason, the leakage current between the source and the drain can be reduced. Furthermore, since it is not necessary to remove the cap film, the high dielectric constant films 106a, 106b, 106c, and 106d are not damaged, and the deterioration of the reliability of the gate insulating films 110a, 110b, 110c, and 110d is suppressed. Can do.

  Further, when the work function adjusting film is formed between the high dielectric constant film and the first gate electrode film, the work function adjusting element such as La becomes the base gate insulating film and the high dielectric constant when the gate length is shortened. It becomes difficult to be sufficiently supplied to the interface with the film, and the fluctuation amount of the threshold voltage becomes small.

  On the other hand, according to the method of the present embodiment, even when the gate length is short, the work function adjusting element can be supplied from the offset spacer in the same amount as when the gate length is long. Can be adjusted to a desired value, and the threshold voltage of the MISFET can be adjusted to a desired value.

  In the method of this embodiment, the offset spacers 114a, 114b, 115a, and 115b contain work function adjusting elements. These offset spacers are made of silicon nitride, silicon oxide, or the like, and sidewall spacers are used. 116a and 116b include at least one element selected from rare earth elements such as La and Sc and Mg, and the sidewall spacers 136a and 136b include at least one selected from Al, Ti, Ta, and Hf. One element may be included. In other words, it is only necessary that at least a part of the sidewall insulating film including the offset spacer formed on the side surface of the gate electrode of the MISFET includes an element for adjusting the work function. In the case where the side wall spacers 116a, 116b, 136a, and 136b contain work function adjusting elements, the work function adjusting elements diffuse into the central portion of the gate insulating film through the offset spacers by heat treatment. Even when the offset spacer is not provided, the same effect as that of the semiconductor device of this embodiment can be obtained by adding an element for adjusting the work function to the sidewall spacer for forming the source / drain region. be able to.

  Further, by reducing the thickness of the offset spacer 114b, the amount of elements diffusing into the gate insulating film can be reduced, and the threshold value can be finely adjusted. A step of thinning only the offset spacer 115b of the MISFET having a short gate length may be added on the second region 11 for the same reason. According to this method, the threshold voltage of the MISFET can be controlled not only by the gate length but also by the thickness of the offset spacer.

-Description of semiconductor devices-
As shown in FIG. 13, the semiconductor device 100 according to this embodiment manufactured by the above-described method includes a first region 10, a second region 11, and a p-type formed on the first region 10. A well region 103, an n-type well region 104 formed on the second region 11, and an element isolation region 102 surrounding the p-type well region 103 and the n-type well region 104 are provided.

  An n-channel MISFET 150 having a relatively long gate length and an n-channel MISFET 152 having a relatively short gate length are provided on the first region 10, and a gate length is relatively on the second region 11. A long p-channel MISFET 154 and a p-channel MISFET 156 having a relatively short gate length are provided. Although FIG. 13 schematically shows a case where the MISFETs are provided adjacent to each other, the MISFETs do not necessarily have to be provided adjacent to each other.

  The n-channel type MISFET 150 is provided on the gate insulating film 110a formed on the p-type well region 103, the gate electrode 109a provided on the gate insulating film 110a, and the side surfaces of the gate insulating film 110a and the gate electrode 109a. For example, an offset spacer 114a having an I-shaped cross section, a sidewall spacer 116a provided on the outer surface of the offset spacer 114a, and an n-type extension region 117a formed on the p-type well region 103, respectively. Source / drain region 118a.

  The n-channel MISFET 152 includes a gate insulating film 110b formed on the p-type well region 103, a gate electrode 109b that is provided on the gate insulating film 110b and has a gate length shorter than the gate electrode 109a, a gate insulating film 110b, For example, an offset spacer 114b having an I-shaped cross section, a side wall spacer 116b provided on the outer surface of the offset spacer 114b, and an upper portion of the p-type well region 103 are provided on the side surface of the gate electrode 109b. Each has an n-type extension region 117b and a source / drain region 118b.

  The p-channel MISFET 154 is provided on the gate insulating film 110c formed on the n-type well region 104, the gate electrode 109c provided on the gate insulating film 110c, and the side surfaces of the gate insulating film 110c and the gate electrode 109c. For example, an offset spacer 115a having an I-shaped cross section, a sidewall spacer 136a provided on the outer surface of the offset spacer 115a, and a p-type extension region 117c formed on the n-type well region 104, respectively. Source / drain region 118c.

  The p-channel type MISFET 156 is provided on the gate insulating film 110d formed on the n-type well region 104, the gate electrode 109d provided on the gate insulating film 110d, and the side surfaces of the gate insulating film 110d and the gate electrode 109d. For example, an offset spacer 115b having an I-shaped cross section, a sidewall spacer 136b provided on the outer surface of the offset spacer 115b, and a p-type extension region 117d formed on the n-type well region 104, respectively. Source / drain region 118d.

  Each of the gate insulating films 110a, 110b, 110c, and 110d has a base gate insulating film and a high dielectric constant film, and each of the gate electrodes 109a, 109b, 109c, and 109d is a metal or a conductive material such as TiN or TaN. A first gate electrode film made of metal and a second gate electrode film made of conductive silicon such as polysilicon are included.

In the semiconductor device of this embodiment, the offset spacers 114a and 114b of the n-channel type MISFETs 150 and 152 include at least one element selected from rare earth elements such as La and Sc and Mg, and the p-channel type MISFET 154. The 156 offset spacers 115a and 115b contain at least one element selected from Al, Ti, Ta, and Hf. For example, La and Sc cause positive fixed charges in the gate insulating films 110a and 110b (specifically, near the interface between the high dielectric constant films 106a and 106b and the base gate insulating films 105a and 105b). Negative fixed charges are generated in the gate insulating films 110c and 110d (specifically, near the interface between the high dielectric constant films 106c and 106d and the base gate insulating films 105c and 105d). Here, the offset spacers 114a and 114b are each composed of La ₂ O ₃ , and the offset spacers 115a and 115b are each composed of Al ₂ O ₃ .

  The gate insulating films 110a and 110b both contain the same work function adjusting element (for example, La) as the elements contained in the offset spacers 114a and 114b. For this reason, in the MISFET having these gate insulating films, the work function of the gate electrode is reduced and the threshold voltage is lowered as compared with the case where the gate insulating film does not contain an element for adjusting the work function. Note that the concentration of the work function adjusting element in the gate insulating films 110a and 110b is high at both ends in the gate length direction and low at the center.

  Furthermore, the gate insulating film 110b of the n-channel type MISFET 152 having a short gate length contains the above-described work function adjusting element at a higher concentration than the gate insulating film 110a of the n-channel type MISFET 150 having a long gate length. Thus, when the gate insulating films 110a and 110b have the same film thickness, the threshold voltage of the n-channel type MISFET 152 is lower than the threshold voltage of the n-channel type MISFET 150.

  The gate insulating films 110c and 110d both contain the same work function adjusting element (for example, Al) as the elements contained in the offset spacers 115a and 115b. For this reason, the work function of the gate electrode is reduced and the threshold voltage is lower in these MISFETs than in the case where the gate insulating film does not contain an element for adjusting the work function. Note that the concentration of the work function adjusting element in the gate insulating films 110c and 110d is high at both ends in the gate length direction and low at the center.

  Further, the gate insulating film 110d of the p-channel type MISFET 156 having a short gate length contains the above-described work function adjusting element at a higher concentration than the gate insulating film 110c of the p-channel type MISFET 154 having a long gate length. Thus, when the gate insulating films 110c and 110d have the same film thickness, the threshold voltage of the p-channel type MISFET 156 is lower than the threshold voltage of the p-channel type MISFET 154.

  As described above, in the semiconductor device 100 according to the present embodiment, the concentration of the work function adjusting element in the gate insulating film varies depending on the length of the gate length, so that the threshold voltage of the MISFET depends on the application. It is adjusted to an appropriate value. In addition, for both the n-channel type and the p-channel type, MISFETs having different threshold voltages can be manufactured with fewer steps.

(Modification of the first embodiment)
-Description of manufacturing method-
14 to 29 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a modification of the first embodiment. The manufacturing method according to this modification differs from the method according to the first embodiment in that the work function adjustment layer is formed after the formation of the high dielectric constant film 106 and before the formation of the first gate electrode film 107. Yes.

  First, as illustrated in FIG. 14, an element isolation region 102 is formed on the semiconductor substrate 101 by an STI method or the like, and a p-type well region surrounded by the element isolation region 102 in the first region 10 of the semiconductor substrate 101. 103 is formed, and an n-type well region 104 surrounded by the element isolation region 102 is formed in the second region 11 of the semiconductor substrate 101. Next, a base gate insulating film 105 and a high dielectric constant film 106 are sequentially formed on the semiconductor substrate 101.

The base gate insulating film 105 is made of, for example, silicon oxide, and is formed with a film thickness of 1.0 nm or less by oxidizing the upper surface of the semiconductor substrate 101 by a thermal oxidation method or a plasma oxidation method. The high dielectric constant film 106 includes at least one of Hf oxide and Zr oxide, and is formed on the base gate insulating film 105 by an ALD method, a CVD method, or the like. In this modification, for example, an HfO ₂ film having a thickness of 2.0 nm or less is formed as the high dielectric constant film 106.

Next, as shown in FIG. 15, the high dielectric constant film 106 includes an element that adjusts at least one work function selected from Al, Ti, Ta, and Hf by the PVD method or the ALD method. A work function adjusting film 119 is formed. Here, as the work function adjusting film 119, for example, an Al ₂ O ₃ film having a film thickness of 0.5 nm or less is formed.

  Next, as shown in FIG. 16, a portion of the work function adjusting film 119 provided on the first region 10 is removed by etching. As a result, the work function adjusting film 119 is left on the second region 11.

Next, as shown in FIG. 17, an element that adjusts at least one work function selected from rare earth elements such as La and Sc and Mg is formed on the high dielectric constant film 106 and the work function adjusting film 119. The included work function adjustment film 120 is formed. Here, as the work function adjusting film 120, for example, a La ₂ O ₃ film having a film thickness of 0.5 nm or less is formed. Thereafter, a portion of the work function adjusting film 120 formed on the second region 11 is removed by etching. As a result, the work function adjusting film 120 is left on the first region 10. Although the method of forming the work function adjusting film 120 after the work function adjusting film 119 has been described here, the work function adjusting film 120 may be formed before the work function adjusting film 119.

  Next, as shown in FIG. 18, the first gate containing a conductive metal compound such as TiN or TaN on the work function adjusting film 119 and the work function adjusting film 120 by the PVD method, the ALD method, the CVD method, or the like. An electrode film 107 and a second gate electrode film 108 made of, for example, polysilicon are sequentially formed.

  In this modification, for example, a TiN film having a thickness of 20 nm or less is formed as the first gate electrode film 107. Further, as the second gate electrode film 108, for example, a polysilicon film having a thickness of 100 nm or less is formed on the first gate electrode film 107.

  Next, as shown in FIG. 19, a stacked structure including the second gate electrode film 108, the first gate electrode film 107, the work function adjusting films 119 and 120, the high dielectric constant film 106, and the base gate insulating film 105. Is patterned by a known method such as photolithography and etching. As a result, the stacked structure constituted by the gate insulating film 110a, the work function adjusting film 120a, and the gate electrode 109a, and the laminated structure constituted by the gate insulating film 110b, the work function adjusting film 120b, and the gate electrode 109b are respectively provided. 1 region 10 is formed. In addition, a stacked structure including the gate insulating film 110c, the work function adjusting film 119a, and the gate electrode 109c, and a stacked structure including the gate insulating film 110d, the work function adjusting film 119b, and the gate electrode 109d are respectively provided in the second structure. Is formed on the region 11. That is, a so-called gate stack structure is formed.

  Here, the gate insulating film 110a is composed of a base gate insulating film 105a and a high dielectric constant film 106a, and the gate insulating film 110b is composed of a base gate insulating film 105b and a high dielectric constant film 106b. The gate insulating film 110c is composed of a base gate insulating film 105c and a high dielectric constant film 106c, and the gate insulating film 110d is composed of a base gate insulating film 105d and a high dielectric constant film 106d.

  The gate electrode 109a includes a first gate electrode film 107a and a second gate electrode film 108a, and the gate electrode 109b includes a first gate electrode film 107b and a second gate electrode film 108b. The gate electrode 109c is composed of a first gate electrode film 107c and a second gate electrode film 108c, and the gate electrode 109d is composed of a first gate electrode film 107d and a second gate electrode film 108d.

  The gate lengths of the gate electrode 109a and the gate electrode 109b (the length in the left-right direction shown in FIG. 3) are different from each other, and the gate lengths of the gate electrode 109c and the gate electrode 109d are also different from each other. In this modification, the gate length of the gate electrode 109a and the gate electrode 109c is 45 nm, for example, and the gate length of the gate electrode 109b and the gate electrode 109d is 30 nm, for example.

Next, as shown in FIG. 20, rare earth elements such as La and Sc and Mg are formed on the semiconductor substrate 101 and on the upper surfaces and side surfaces of the gate electrodes 109a, 109b, 109c, and 109d by the PVD method or the ALD method. A work function adjusting film 111 containing an element for adjusting at least one work function selected from among them is formed. In this modification, for example, a La ₂ O ₃ film having a film thickness of 10 nm or less is formed as the work function adjusting film 111. The work function adjusting film 111 has an insulating property. The work function adjusting film 111 may be made of the same material as the work function adjusting film 120 formed in the step shown in FIG. 17, but may be made of a different material.

  Next, as shown in FIG. 21, after a portion of the work function adjusting film 111 formed on the first region 10 is covered with a resist 112e, as shown in FIG. The portion formed on the second region 11 is removed by etching, and the work function adjusting film 111 is left on the first region 10.

Next, as shown in FIG. 23, after removing the resist 112e, the work function adjustment film 111 provided on the first region 10, the second region 11 of the semiconductor substrate 101, and the gate electrode 109c, A work function adjusting film 113 containing an element for adjusting at least one work function selected from Al, Ti, Ta, and Hf is formed on each upper surface and each side surface of 109d by PVD method or ALD method. . In this modification, for example, an Al ₂ O ₃ film having a thickness of 10 nm is formed as the work function adjusting film 113. The work function adjusting film 113 has an insulating property. The work function adjusting film 113 may be made of the same material as the work function adjusting film 119 formed in the steps shown in FIGS. 15 and 16, but may be made of a different material.

  Next, as shown in FIG. 24, after a portion of the work function adjustment film 113 formed on the second region 11 is covered with a resist 112f, as shown in FIG. The portion formed on the first region 10 is removed by etching, and the work function adjusting film 113 is left on the second region 11. Thereafter, the resist 112f is removed. In the above description, the work function adjustment film 113 is formed after the work function adjustment film 111 is formed. However, the work function adjustment film 111 may be formed after the work function adjustment film 113 is formed.

  Next, as shown in FIG. 26, the work function adjusting film 111 on the first region 10 and the work function adjusting film 113 on the second region 11 are etched. Thus, the offset spacer 114a is formed on the side surfaces of the gate insulating film 110a, the work function adjusting film 120a, and the gate electrode 109a, and the offset spacer is formed on the side surfaces of the gate insulating film 110b, the work function adjusting film 120b, and the gate electrode 109b. 114b is formed. Further, an offset spacer 115a is formed on the side surfaces of the gate insulating film 110c, the work function adjusting film 119a, and the gate electrode 109c, and the offset spacer 115b is formed on the side surfaces of the gate insulating film 110d, the work function adjusting film 119b, and the gate electrode 109d. Form.

  Next, as shown in FIG. 27, after the second region 11 is covered with a resist 112g, the p-type well region 103 is formed using the gate electrodes 109a and 109b and the offset spacers 114a and 114b on the first region 10 as a mask. Then, n-type impurity ions are implanted to form n-type extension regions 117a on both sides of the gate electrode 109a, and n-type extension regions 117b on both sides of the gate electrode 109b.

  Subsequently, after forming an insulating film on the semiconductor substrate 101, the insulating film is etched to form a sidewall spacer 116a on the outer surface of the offset spacer 114a and on the outer surface of the offset spacer 114b. Sidewall spacers 116b are formed. Then, n-type impurity ions are implanted into the p-type well region 103 using the gate electrodes 109a and 109b, the offset spacers 114a and 114b, and the side wall spacers 116a and 116b as masks, and are extended on both sides of the gate electrode 109a. A source / drain region 118a is formed in the outer region of the region 117a. At the same time, source / drain regions 118b are formed on both sides of the gate electrode 109b and outside the extension region 117b. In FIG. 27, the offset spacer 114a and the sidewall spacer 116a are collectively shown as a sidewall insulating film 140a, and the offset spacer 114b and the sidewall spacer 116b are collectively shown as a sidewall insulating film 140b.

  Next, as shown in FIG. 28, after removing the resist 112g, the first region 10 is covered with a resist 112h. Subsequently, p-type impurity ions are implanted into the n-type well region 104 using the gate electrodes 109c and 109d and the offset spacers 115a and 115b on the second region 11 as a mask, and p-type extension regions 117c are formed on both sides of the gate electrode 109c. And p-type extension regions 117d are formed on both sides of the gate electrode 109d.

  Subsequently, after an insulating film is formed on the semiconductor substrate 101, the insulating film is etched to form a sidewall spacer 136a on the outer surface of the offset spacer 115a and on the outer surface of the offset spacer 115b. Sidewall spacers 136b are formed on the substrate. Then, p-type impurity ions are implanted into the n-type well region 104 using the gate electrodes 109c and 109d, the offset spacers 115a and 115b, and the side wall spacers 136a and 136b as masks, and the extension is formed on both sides of the gate electrode 109c. A source / drain region 118c is formed in the outer region of the region 117c. At the same time, source / drain regions 118d are formed on both sides of the gate electrode 109d and outside the extension region 117d. In FIG. 28, the offset spacer 115a and the sidewall spacer 136a are collectively shown as a sidewall insulating film 140c, and the offset spacer 115b and the sidewall spacer 136b are collectively shown as a sidewall insulating film 140d.

  Next, as shown in FIG. 29, heat treatment at about 1000 to 1300 ° C. is performed to activate impurities contained in the extension regions 117a, 117b, 117c, and 117d and the source / drain regions 118a, 118b, 118c, and 118d. At the same time, the work function adjusting elements contained in the offset spacers 114a, 114b, 115a, and 115b are diffused from both sides of the gate insulating films 110a, 110b, 110c, and 110d toward the center in the gate length direction.

  At this time, the very thin work function adjusting films 120a and 120b on the first region 10 are mixed with the high dielectric constant films 106a and 106b, respectively, and become insulating films 106A and 106B containing work function adjusting elements. . At the same time, the very thin work function adjusting films 119a and 119b on the second region 11 are mixed with the high dielectric constant films 106c and 106d, respectively, and the insulating films 106C and 106D containing elements for adjusting the work function, Become. Through the above steps, the semiconductor device 200 of the present modification can be obtained.

  According to the above manufacturing method, it is possible to obtain a MISFET having a high-k gate insulating film / metal gate stack structure having different threshold voltages depending on the gate length.

  In the case of MISFETs having the same conductivity type and different gate lengths, the thickness of each offset spacer (for example, offset spacers 114a and 114b) is the same, whereas the volume of the gate insulating film (for example, gate insulating films 110a and 110b) is A MISFET with a long gate length is larger than a short MISFET. Therefore, the MISFET having a shorter gate length can diffuse more work function adjusting elements per unit volume into the gate insulating film than the MISFET having a longer gate length.

  As a result, in both the n-channel MISFET and the p-channel MISFET, the concentration of the work function adjusting element in the gate insulating film is relatively high in the MISFET having a short gate length, so that the threshold voltage is lowered. can do. On the other hand, in the MISFET having a long gate length, the concentration of the work function adjusting element in the gate insulating film is relatively low, so that the threshold voltage can be increased. That is, according to the manufacturing method of this modification, the threshold voltage of the MISFET can be appropriately controlled by appropriately setting the gate length.

  Further, according to the manufacturing method according to this modification, the work function adjusting element is diffused in the lateral direction from the offset spacers 114a, 114b, 115a, 115b to the gate insulating films 110a, 110b, 110c, 110d, respectively. In addition, the work function adjusting elements can be diffused in the vertical direction from the work function adjusting films 120a, 120b, 119a, and 119b to the gate insulating films 110a, 110b, 110c, and 110d, respectively. For this reason, since the amount of work function adjusting element diffusion into each gate insulating film can be increased, the adjustment range of the threshold voltage of the MISFET can be further expanded as compared with the method according to the first embodiment. it can.

-Description of semiconductor devices-
As shown in FIG. 29, the semiconductor device 200 manufactured by the above-described method includes a first region 10, a second region 11, and a p-type well region 103 formed on the first region 10. , An n-type well region 104 formed on the second region 11, and a p-type well region 103 and an element isolation region 102 surrounding the n-type well region 104.

  An n-channel MISFET 160 having a relatively long gate length and an n-channel MISFET 162 having a relatively short gate length are provided on the first region 10, and a gate length is relatively on the second region 11. A long p-channel MISFET 164 and a p-channel MISFET 166 having a relatively short gate length are provided.

  The n-channel MISFET 160 is provided on the gate insulating film 110a formed on the p-type well region 103, the gate electrode 109a provided on the gate insulating film 110a, and the side surfaces of the gate insulating film 110a and the gate electrode 109a. For example, an offset spacer 114a having an I-shaped cross section, a sidewall spacer 116a provided on the outer surface of the offset spacer 114a, and an n-type extension region 117a formed on the p-type well region 103, respectively. Source / drain region 118a.

  The n-channel MISFET 162 includes a gate insulating film 110b formed on the p-type well region 103, a gate electrode 109b that is provided on the gate insulating film 110b and has a shorter gate length than the gate electrode 109a, a gate insulating film 110b, For example, an offset spacer 114b having an I-shaped cross section, a side wall spacer 116b provided on the outer surface of the offset spacer 114b, and an upper portion of the p-type well region 103 are provided on the side surface of the gate electrode 109b. Each has an n-type extension region 117b and a source / drain region 118b.

  The p-channel type MISFET 164 is provided on the gate insulating film 110c formed on the n-type well region 104, the gate electrode 109c provided on the gate insulating film 110c, and the side surfaces of the gate insulating film 110c and the gate electrode 109c. For example, an offset spacer 115a having an I-shaped cross section, a sidewall spacer 136a provided on the outer surface of the offset spacer 115a, and a p-type extension region 117c formed on the n-type well region 104, respectively. Source / drain region 118c.

  The p-channel type MISFET 166 is provided on the gate insulating film 110d formed on the n-type well region 104, the gate electrode 109d provided on the gate insulating film 110d, and the side surfaces of the gate insulating film 110d and the gate electrode 109d. For example, an offset spacer 115b having an I-shaped cross section, a sidewall spacer 136b provided on the outer surface of the offset spacer 115b, and a p-type extension region 117d formed on the n-type well region 104, respectively. Source / drain region 118d.

  The gate insulating film 110a includes a base gate insulating film 105a and an insulating film 106A formed thereon, and the gate insulating film 110b includes a base gate insulating film 105b and an insulating film 106B formed thereon. The gate insulating film 110c has a base gate insulating film 105c and an insulating film 106C formed thereon, and has a base gate insulating film 105d and an insulating film 106D formed thereon.

  The insulating films 106A and 106B are made of a high dielectric material containing a work function adjusting element such as La. The insulating films 106C and 106D are also made of a high dielectric material containing an element for adjusting the work function such as Al.

  Each of the gate electrodes 109a, 109b, 109c, and 109d includes a first gate electrode film made of a metal or a conductive metal such as TiN or TaN, and a second gate electrode film made of a conductive silicon such as polysilicon. Yes.

  The offset spacers 114a and 114b of the n-channel type MISFETs 160 and 162 include at least one element selected from rare earth elements such as La and Sc and Mg, and the offset spacers 115a and 115b of the p-channel type MISFETs 164 and 166. Contains at least one element selected from Al, Ti, Ta, and Hf. For example, La and Sc cause positive fixed charges in the gate insulating films 110a and 110b (specifically, in the vicinity of the interface between the high dielectric constant films 106a and 106b and the base insulating films 105a and 105b), and Al and Ti are the gates. Negative fixed charges are generated in the insulating films 110c and 110d (specifically, near the interface between the high dielectric constant films 106c and 106d and the base insulating films 105c and 105d).

  As described above, the gate insulating films 110a, 110b, 110c, and 110d each contain an element for adjusting the work function. For this reason, in the MISFET having these gate insulating films, the work function of the gate electrode is reduced and the threshold voltage is lower than when the gate insulating film does not contain an element for adjusting the work function.

  Further, the gate insulating film 110b of the n-channel type MISFET 162 having a short gate length contains a work function adjusting element at a higher concentration than the gate insulating film 110a of the n-channel type MISFET 160 having a long gate length. Thereby, when the gate insulating films 110a and 110b have the same film thickness, the threshold voltage of the n-channel type MISFET 162 is lower than the threshold voltage of the n-channel type MISFET 160.

  Further, the gate insulating film 110d of the p-channel type MISFET 166 having a short gate length contains a work function adjusting element at a higher concentration than the gate insulating film 110c of the p-channel type MISFET 164 having a long gate length. Accordingly, when the gate insulating films 110c and 110d have the same film thickness, the threshold voltage of the p-channel type MISFET 166 is lower than the threshold voltage of the p-channel type MISFET 164.

  Furthermore, the concentration of the work function adjusting element contained in the gate insulating films 110a, 110b, 110c, and 110d can be made higher than the concentration of the element in the semiconductor device according to the first embodiment. Both the channel type MISFETs 160 and 162 and the p channel type MISFETs 164 and 166 can extend the adjustment range of the threshold voltage.

  The above-described embodiment and its modifications are examples of preferred embodiments of the present invention, but the scope thereof is not limited and various modifications can be made without departing from the spirit of the present invention. For example, the procedure, conditions for forming / removing the film, the method, the shape of each layer of the semiconductor device, the constituent material, and the like in the manufacturing method described above can be modified as appropriate without departing from the spirit of the present invention. For example, three or more n-channel MISFETs having different gate lengths and threshold voltages may be provided on the first region 10, and the gate length and threshold voltage may be different from each other on the second region 11. Three or more different p-channel type MISFETs may be provided.

  As described above, the present invention can be used for a semiconductor device having a transistor in which different threshold voltages are set for each application, for example. Furthermore, the semiconductor device according to an example of the present invention is used in various electronic devices.

10 first region 11 second region 100, 200 semiconductor device 101 semiconductor substrate 102 element isolation region 103 p-type well region 104 n-type well regions 105, 105a, 105b, 105c, 105d base gate insulating films 106, 106a, 106b 106c, 106d High dielectric constant films 106A, 106B, 106C, 106D Insulating film 106a High dielectric constant films 107, 107a, 107b, 107c, 107d First gate electrode films 108, 108a, 108b, 108c, 108d Second gate electrode films 109a, 109b, 109c, 109d Gate electrodes 110a, 110b, 110c, 110d Gate insulating films 111, 113 Work function adjusting films
112a, 112b, 112c, 112d Resist 112e, 112f, 112g, 112h Resist 114a, 114b, 115a, 115b Offset spacer 116a, 116b, 136a, 136b Side wall spacer 117a, 117b, 117c, 117d Extension regions 118a, 118b, 118c, 118d Source / drain regions 119, 119a, 119b, 120, 120a, 120b Work function adjusting films 150, 152, 160, 162 n-channel MISFETs
154, 156, 164, 166 p-channel MISFET

Claims (29)

A first gate insulating film formed on a semiconductor substrate; a first gate electrode formed on the first gate insulating film; a side surface of the first gate insulating film; and the first gate. A first conductivity type first MISFET having a first sidewall insulating film formed on a side surface of the electrode;
A semiconductor device, wherein at least part of the first sidewall insulating film includes a first element for inducing positive or negative fixed charges in the first gate insulating film. The semiconductor device according to claim 1,
A second gate insulating film formed on the semiconductor substrate; a second gate electrode formed on the second gate insulating film and having a gate length shorter than that of the first gate electrode; A second conductivity type second MISFET having a second sidewall insulating film formed on a side surface of the gate insulating film and on a side surface of the second gate electrode,
At least a part of the second sidewall insulating film includes a second element for inducing a fixed charge having the same polarity as the first element in the second gate insulating film. A featured semiconductor device. The semiconductor device according to claim 2,
The first sidewall insulating film is provided so as to be in contact with a side surface of the first gate insulating film and a side surface of the first gate electrode, and includes a first offset spacer containing the first element. Have
The second sidewall insulating film is provided in contact with a side surface of the second gate insulating film and a side surface of the second gate electrode, and includes a second offset spacer containing the second element. A semiconductor device including the semiconductor device. The semiconductor device according to claim 2,
The first sidewall insulating film is provided on a side surface of the first gate insulating film and on a side surface of the first gate electrode, and includes a first sidewall spacer containing the first element. Have
The second sidewall insulating film is provided on a side surface of the second gate insulating film and on a side surface of the second gate electrode, and includes a second sidewall spacer containing the second element. A semiconductor device including the semiconductor device. The semiconductor device according to claim 4,
The first sidewall insulating film further includes a first offset spacer provided between a side surface of the first gate insulating film and a side surface of the first gate electrode and the first sidewall spacer. Have
The second sidewall insulating film further includes a second offset spacer provided between a side surface of the second gate insulating film and a side surface of the second gate electrode and the second sidewall spacer. A semiconductor device including the semiconductor device. In the semiconductor device according to any one of claims 2 to 5,
The semiconductor device, wherein the first gate insulating film and the second gate insulating film contain a high dielectric constant material. The semiconductor device according to any one of claims 2 to 6,
The first gate insulating film is formed on the first base gate insulating film formed on the semiconductor substrate and the first base gate insulating film, and includes at least one of Hf oxide and Zr oxide. Including a first high dielectric constant film,
The second gate insulating film is formed on the second base gate insulating film formed on the semiconductor substrate and on the second base gate insulating film, and includes at least one of Hf oxide and Zr oxide. And a second high dielectric constant film. The semiconductor device according to claim 7,
The semiconductor device, wherein the first base gate insulating film and the second base gate insulating film are made of silicon oxide or silicon oxynitride. In the semiconductor device according to any one of claims 2 to 8,
The first gate electrode is formed on the first gate insulating film, and includes a first gate electrode film including at least one of TiN and TaN, and a first gate electrode film formed on the first gate electrode film. A conductive silicon film, and
The second gate electrode is formed on the second gate insulating film, and includes a second gate electrode film including at least one of TiN and TaN, and a second gate electrode film formed on the second gate electrode film. And a conductive silicon film. The semiconductor device according to any one of claims 2 to 9,
A second MISFET and a fourth MISFET of the second conductivity type both formed on the semiconductor substrate;
The first element is an element for inducing a positive fixed charge in the first gate insulating film,
The second element is an element for inducing a positive fixed charge in the second gate insulating film,
The third MISFET includes a third gate insulating film formed on the semiconductor substrate, a third gate electrode formed on the third gate insulating film, and a third gate insulating film. Third sidewall insulation formed on the side surface and the side surface of the third gate electrode and including at least a part of a third element for inducing a negative fixed charge in the third gate insulating film And having a membrane
The fourth MISFET is formed on a fourth gate insulating film formed on the semiconductor substrate and on the fourth gate insulating film, and has a fourth gate length shorter than that of the third gate electrode. A gate element; a fourth element formed on the side surface of the fourth gate insulating film and on the side surface of the fourth gate electrode, for inducing negative fixed charges in the fourth gate insulating film; And a fourth sidewall insulating film including at least a part thereof. The semiconductor device according to claim 10.
The first gate insulating film contains the first element;
The second gate insulating film contains the second element at a concentration higher than the concentration of the first element in the first gate insulating film;
The third gate insulating film contains the third element;
The semiconductor device, wherein the fourth gate insulating film contains the fourth element at a concentration higher than the concentration of the third element in the third gate insulating film. The semiconductor device according to claim 10 or 11,
The first MISFET and the second MISFET are n-channel MISFETs,
The semiconductor device, wherein the first element and the second element are at least one element selected from a rare earth element and Mg. The semiconductor device according to any one of claims 10 to 12,
The third MISFET and the fourth MISFET are p-channel type MISFETs,
The semiconductor device, wherein the third element and the fourth element are at least one element selected from Al, Ti, Ta, and Hf. In the semiconductor device according to any one of claims 10 to 13,
The third sidewall insulating film is provided in contact with the side surface of the third gate insulating film and the side surface of the third gate electrode, and includes a third offset spacer containing the third element. Have
The fourth sidewall insulating film is provided so as to be in contact with a side surface of the fourth gate insulating film and a side surface of the fourth gate electrode, and includes a fourth offset spacer containing the fourth element. A semiconductor device including the semiconductor device. In the semiconductor device according to any one of claims 10 to 13,
The third sidewall insulating film is provided on a side surface of the third gate insulating film and a side surface of the third gate electrode, and includes a third sidewall spacer containing the third element. Have
The fourth sidewall insulating film is provided on a side surface of the fourth gate insulating film and on a side surface of the fourth gate electrode, and includes a fourth sidewall spacer containing the fourth element. A semiconductor device including the semiconductor device. In the semiconductor device according to any one of claims 10 to 15,
The third gate insulating film is formed on the third base gate insulating film formed on the semiconductor substrate and the third base gate insulating film, and includes at least one of Hf oxide and Zr oxide. And a third high dielectric constant film including
The fourth gate insulating film is formed on the fourth base gate insulating film and the fourth base gate insulating film formed on the semiconductor substrate, and includes at least one of Hf oxide and Zr oxide. And a fourth high dielectric constant film. In the semiconductor device according to any one of claims 10 to 16,
The third gate electrode is formed on the third gate insulating film, and includes a third gate electrode film including at least one of TiN and TaN, and a third gate electrode film formed on the third gate electrode film. A conductive silicon film, and
The fourth gate electrode is formed on the fourth gate insulating film, and includes a fourth gate electrode film including at least one of TiN and TaN, and a fourth gate electrode film formed on the fourth gate electrode film. And a conductive silicon film. A method of manufacturing a semiconductor device including a first conductivity type first MISFET having a first gate insulating film, a first gate electrode, and a first sidewall insulating film formed on a semiconductor substrate. ,
(A) forming the first gate insulating film and the first gate electrode provided on the first gate insulating film;
A first element for inducing a positive or negative fixed charge in the first gate insulating film on at least a part of the side surface of the first gate insulating film and the side surface of the first gate electrode. A step (b) of forming the first sidewall insulating film. In the manufacturing method of the semiconductor device according to claim 18,
A method of manufacturing a semiconductor device, further comprising a step (c) of performing a heat treatment to diffuse the first element contained in the first sidewall insulating film into the first gate insulating film. In the manufacturing method of the semiconductor device according to claim 19,
The semiconductor device further includes a first conductivity type second MISFET having a second gate insulating film, a second gate electrode, and a second sidewall insulating film formed on the semiconductor substrate,
In the step (a), the second gate insulating film and the second gate electrode provided on the second gate insulating film and having a gate length shorter than that of the first gate electrode are further formed. And
In the step (b), a second for inducing a positive or negative fixed charge on the second gate insulating film on the side surface of the second gate insulating film and the side surface of the second gate electrode. Further forming the second sidewall insulating film containing at least a part of
In the step (c), the second element contained in the second sidewall insulating film is diffused in the second gate insulating film by a heat treatment, and the method for manufacturing a semiconductor device is characterized in that: In the manufacturing method of the semiconductor device according to claim 20,
The first element is an element for inducing a positive fixed charge in the first gate insulating film,
The method of manufacturing a semiconductor device, wherein the second element is an element for inducing a positive fixed charge in the second gate insulating film. In the manufacturing method of the semiconductor device according to claim 21,
The semiconductor device includes: a third MISFET of a second conductivity type having a third gate insulating film, a third gate electrode, and a third sidewall insulating film formed on the semiconductor substrate; and the semiconductor substrate A second conductivity type fourth MISFET having a fourth gate insulating film, a fourth gate electrode, and a fourth sidewall insulating film formed thereon;
Before the step (b), or after the step (b) and before the step (c), on the side surface of the third gate insulating film and the side surface of the third gate electrode, Forming the third sidewall insulating film including at least part of the third element for inducing negative fixed charges in the third gate insulating film, and on the side surface of the fourth gate insulating film; Forming the fourth sidewall insulating film including at least a part of a fourth element for inducing a negative fixed charge in the fourth gate insulating film on a side surface of the fourth gate electrode; (D) is further provided,
In the step (a), the third gate insulating film and the third gate electrode provided on the third gate insulating film are further formed, and the fourth gate insulating film; Forming the fourth gate electrode provided on the fourth gate insulating film and having a gate electrode shorter than the third gate electrode;
In the step (c), an element for inducing a fixed charge contained in the third sidewall insulating film is diffused in the third gate insulating film by heat treatment, and the fourth sidewall insulating is performed. A method of manufacturing a semiconductor device, wherein an element for inducing a fixed charge contained in a film is diffused in the fourth gate insulating film. In the manufacturing method of the semiconductor device according to claim 22,
In the step (a), a first work function including an element for inducing a positive fixed charge in the first gate insulating film between the first gate insulating film and the first gate electrode. A second work function adjusting film containing an element for inducing a positive fixed charge in the second gate insulating film between the second gate insulating film and the second gate electrode; A third work function adjusting film containing an element for inducing a negative fixed charge in the third gate insulating film between the third gate insulating film and the third gate electrode, A fourth work function adjusting film containing an element for inducing a negative fixed charge in the fourth gate insulating film between the fourth gate insulating film and the fourth gate electrode,
In the step (c), the constituent material of the first work function adjusting film and the constituent material of the first gate insulating film are mixed by heat treatment, and the constituent material of the second work function adjusting film and the The constituent material of the second gate insulating film is mixed, the constituent material of the third work function adjusting film and the constituent material of the third gate insulating film are mixed, and the constituent material of the fourth work function adjusting film is mixed. A manufacturing method of a semiconductor device, wherein a constituent material and a constituent material of the fourth gate insulating film are mixed. 24. The method of manufacturing a semiconductor device according to claim 23,
The first work function adjusting film and the second work function adjusting film both contain at least one element selected from rare earth elements and Mg,
Both of the third work function adjusting film and the fourth work function adjusting film include at least one element selected from Al, Ti, Ta, and Hf. Production method. In the manufacturing method of the semiconductor device according to any one of claims 22 to 24,
The step (b) is a part of the first sidewall insulating film, is in contact with the side surface of the first gate insulating film and the side surface of the first gate electrode, and contains the first element. A first offset spacer and a part of the second sidewall insulating film, in contact with a side surface of the second gate insulating film and a side surface of the second gate electrode, and a second element containing the second element. A step of forming an offset spacer of
The step (d) is a part of the third sidewall insulating film, is in contact with a side surface of the third gate insulating film and a side surface of the third gate electrode, and is formed on the third gate insulating film. A third offset spacer including an element for inducing a negative fixed charge; a part of the fourth sidewall insulating film; and a side surface of the fourth gate insulating film and the fourth gate electrode. A method of manufacturing a semiconductor device, comprising a step of forming a fourth offset spacer in contact with a side surface and including an element for inducing a negative fixed charge in the fourth gate insulating film. In the manufacturing method of the semiconductor device as described in any one of Claims 22-25,
The method for manufacturing a semiconductor device, wherein the first element and the second element are at least one element selected from a rare earth element and Mg. In the manufacturing method of the semiconductor device as described in any one of Claims 22-26,
The method for manufacturing a semiconductor device, wherein the third element and the fourth element are at least one element selected from Al, Ti, Ta, and Hf. In the manufacturing method of the semiconductor device as described in any one of Claims 22-27,
The first gate insulating film, the second gate insulating film, the third gate insulating film, and the fourth gate insulating film formed in the step (a) are Hf oxide and Zr oxide. A method for manufacturing a semiconductor device, comprising at least one of the following. In the manufacturing method of the semiconductor device according to any one of claims 22 to 28,
The first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode formed in the step (a) include at least one of TiN and TaN. A method for manufacturing a semiconductor device.

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