JP2012169348A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can accurately detect a current flowing through a main cell, can improve the linearity of current detection and hardly receives the influence of the use of a high voltage.SOLUTION: A main cell is placed on both sides of a sense cell, and an emitter of the sense cell is sandwiched by an emitter of the main cell. The structure can bring a density of current flowing through the emitter of the sense cell closer to a density of current flowing through the emitter of the main cell to bring a mirror ratio closer to a longitudinal emitter length ratio of the sense cell to the main cell. The density of the current flowing through the emitter of the sense cell can be brought closer to the density of the current flowing through the emitter of the main cell to inhibit a current amount per unit area from increasing to a higher level in the sense cell than in the main cell at switching or high current application. This can suppress a current variation and breakdown capacity can be improved.

Description

  The present invention relates to a semiconductor device in which a lateral IGBT is divided into a main cell and a sense cell, and a current flowing through the main cell is detected by the sense cell.

  Conventionally, Patent Document 1 discloses a semiconductor integrated circuit provided with a current detection unit (sense cell) for detecting a current flowing in an emitter of a lateral IGBT in addition to a main cell in which a lateral IGBT is formed. This semiconductor integrated circuit has the same structure as that of the lateral IGBT formed in the main cell, but has a structure in which a lateral IGBT for current detection with different emitter lengths is formed in the current detection unit and these are connected in a current mirror. . In such a structure, a current obtained by reducing the current flowing through the emitter of the lateral IGBT of the main cell to a predetermined ratio flows through the emitter of the current detection unit, and therefore flows through the emitter of the main cell based on the current flowing through the current detection unit. Current can be detected. Specifically, in this semiconductor integrated circuit, a main cell is formed by arranging a plurality of cells constituting a lateral IGBT in parallel in a semiconductor chip, and a current is applied to an end of the semiconductor chip away from the main cell. The detection unit is arranged.

Japanese Patent Publication No. 08-34709

  However, in the semiconductor integrated circuit disclosed in the above-mentioned conventional publication, since the current detection unit is arranged at the end of the semiconductor chip that is away from the main cell, the current density flowing in the current detection unit and the current cell emitter flow. The current density is greatly different, and the mirror ratio is greatly different from the length ratio of the IGBT emitter of the main cell. That is, in the lateral IGBT, a difference in current density depending on the arrangement location tends to be larger than that of a MOSFET or the like due to the influence of conductivity modulation, and this phenomenon occurs. For this reason, the current flowing through the emitter of the main cell cannot be detected accurately. In addition, since the ratio of the current flowing through the current detection unit varies depending on the current density, the current (sense current) detected by the current detection unit and the current flowing through the emitter of the main cell are not proportional, and current detection linearity is poor. Become.

Further, for example, when the configuration of the semiconductor integrated circuit disclosed in the above-mentioned conventional publication is applied to the circuit configuration having the main cell 100 and the sense cell 101 shown in FIG. 8, an output for detecting the current value flowing through the current detection unit. When the resistance value of the sense resistor Rs is increased so as to increase the voltage across the sense resistor Rs for voltage formation, the emitter potential of the sense cell 101 increases. For this reason, the potential of the p-type body layer electrically connected to the emitter electrode rises, and the PN junction formed between the p-type body layer and the n ⁻ -type drift layer is forward-biased. The output becomes unstable. For this reason, it is necessary to suppress the voltage across the sense resistor Rs, that is, the maximum voltage of the output voltage to about 0.3V. When a high voltage (for example, 200 to 600 V) is applied to the collector, the output voltage is affected by the coupling with the high voltage, and a correct voltage cannot be output.

  In view of the above points, the present invention includes a lateral IGBT that can accurately detect the current flowing through the main cell, can improve the linearity of current detection, and is not easily affected even when a high voltage is used. An object of the present invention is to provide a semiconductor device.

  To achieve the above object, according to the first aspect of the present invention, in the surface layer portion of the first conductivity type drift layer (2) provided in the semiconductor substrate (1) having the first conductivity type drift layer (2). A collector region (4) of the second conductivity type formed with one direction as a longitudinal direction, and a straight line parallel to the collector region (4) in the surface layer portion of the drift layer (2) in the drift layer (2) And a channel layer (6) of the second conductivity type having a shape-like portion and a surface layer portion of the channel layer (6) in the channel layer (6), which is terminated inside the terminal portion of the channel layer (6) Of the first conductivity type emitter region (7) having a linear portion having the same direction as the longitudinal direction of the collector region (4), of the surface of the channel layer (6) , Emitter region (7) and drift layer (2) And a gate insulating film (10) formed on the surface of the channel region, and a gate electrode (11) formed on the surface of the gate insulating film (10). A first electrode (12) electrically connected to the collector region (4) and a second electrode (13) electrically connected to the emitter region (7) and the channel layer (6) In a semiconductor device having a lateral IGBT for controlling on / off of current supply to the load by controlling the current flowing in the load, a lateral IGBT for controlling on / off of current supply to the load by dividing the emitter region (7) And a sense cell having a lateral IGBT having the same structure as that of the main cell as a current detection element, and the main cell is disposed on both sides of the sense cell. Suseru is characterized in that interposed at the main cell.

  Thus, the main cell is arranged on both sides of the sense cell, and the emitter region (7) of the sense cell is sandwiched between the emitter region (7) of the main cell. For this reason, the current density flowing in the emitter region (7) of the main cell and the current density flowing in the emitter region (7) of the sense cell can be made closer, and the mirror ratio is the length of the emitter region (7) of each of the main cell and the sense cell. It becomes close to the ratio of length in the direction. Further, since the current density flowing in the emitter region (7) of the sense cell and the current density flowing in the emitter region (7) of the sense cell can be made closer, the amount of current per unit area flowing when switching or when a large current flows is on the main cell side. As compared with the above, it is possible to suppress an increase on the sense cell side. For this reason, current bias can be suppressed and the breakdown tolerance can be improved.

  Therefore, the current flowing through the main cell can be accurately detected by the sense cell, and the semiconductor device can be improved in the linearity of current detection. In addition, even when a high voltage is used, it is possible to obtain a semiconductor device that is hardly affected by the influence.

  According to the second aspect of the present invention, the channel layer (6) is provided with the second conductivity type body layer (9) having a higher impurity concentration than the channel layer (6). The body layer (9) is divided between the two and the body layer (9) is junction-separated.

  Thus, the junction separation of the body layer (9) can prevent leakage through the body layer (9).

  According to a third aspect of the present invention, the sense cell is arranged at the center position of the main cell on both sides of the sense cell.

  In this way, the sense cell is arranged at the substantially central portion of the straight line portion constituting the emitter region (7) of the main cell. With this arrangement, the amount of carriers flowing into the sense cell becomes a value that reflects the average carrier concentration of the main cell, the mirror ratio can be brought close to the cell length ratio, and the mirror ratio varies with the current value. Can be suppressed.

  According to the fourth aspect of the present invention, the channel layer (6) is provided with a second conductivity type contact layer (8) having a higher impurity concentration than the channel layer (6), and the main cell side of the sense cells. The contact layer (8) is provided with an isolation layer (8a) extending toward the end on the emitter region (7) side at the end of the main cell and the end on the sense cell side of the main cell. It is a feature.

  Thus, by providing the isolation layer (8a), the parasitic transistor constituted by the emitter region (7), the body layer (9), and the drift layer (2) operates on the main cell side and the sense cell side, respectively. Can be prevented.

  In the invention according to claim 5, the linear portions of the channel layer (6) and the emitter region (7) are arranged on both sides of the collector region (4), and the channel layer (6) 4) It has an oval shape by having a corner portion surrounding the tip, and a plurality of cells are arranged in a direction perpendicular to the longitudinal direction of the collector region (4), and the outermost linear shape A sense cell is formed by dividing the emitter region (7).

  In this way, a structure in which a plurality of cells having an oval layout for the channel layer (6) are arranged side by side can be obtained. In this case, for example, the sense cell can be configured by dividing the outermost linear emitter region (7).

  In this case, for example, in the case of including the sense resistor (Rs) electrically connected to the second electrode (13) connected to the emitter region (7) in the sense cell as described in claim 6. The sense wiring (15b) constituted by the first layer wiring formed in the first layer through the interlayer insulating film formed on the surface of the semiconductor substrate (1) is directly electrically connected to the second electrode (13). The sense resistor (Rs) may be directly electrically connected to the sensor resistor.

  With such a structure, the reference potential of the sense resistor (Rs) can be stably obtained, so that the current detection accuracy can be further improved.

  Further, as described in claim 7, by pulling out the sense wiring (15b) to the side opposite to the collector region (4), the first electrode (12) connected to the collector region (4) is electrically connected. It can also be set as the structure which does not overlap with the common wiring (16) connected.

  According to such a structure, the wiring layout can be such that the common wiring (16), the main wiring (15a), and the sense wiring (15b) do not overlap. For this reason, the influence of the coupling current due to the potential fluctuation from the first electrode (12) side where a high potential difference occurs can be reduced, and high current detection accuracy in the sense cell can be ensured. In addition, compared to a structure in which current is extracted to the outside through multilayer wiring through via holes, etc., current can be extracted to the outside through the shortest path, so that the influence of noise can be reduced and higher current detection accuracy can be achieved. Can be secured.

  In the invention according to claim 8, the main wiring (15a) electrically connected to the second electrode (13) connected to the emitter region (7) in the main cell arranged on both sides of the sense cell, The sense resistor (Rs) is connected between the sense wiring (15b) and the main wiring (15a) so that the potential of the second electrode (13) of the main cell arranged on both sides of the sense cell is used as a reference potential. It is characterized by being.

  In this way, the sense resistor (Rs) is connected to the main wiring (15a) of the main cell arranged on both sides of the sense cell, so that the sense resistor (Rs) is connected to the nearest main wiring (15a). In addition to being able to connect, it is possible to stably obtain the reference potential. Therefore, the current detection accuracy can be further improved.

  In the invention described in claim 9, the sense resistor (Rs) is provided both between the sense wiring (15b) in the sense cell and the main wiring (15a) of each of the main cells arranged on both sides of the sense cell. It is characterized by that.

  Thus, if the sense resistor (Rs) is arranged between the main wire (15a) and the sense wire (15b) located on both sides of the sense wire (15b), the sense resistor (Rs) is reduced. They can be arranged with equal resistance values on both sides of the sense cell wiring. Therefore, the operation of the main cell becomes uniform on both sides of the sense cell, and the current detection accuracy in the sense cell can be further improved.

  Such a semiconductor device includes, for example, an SOI substrate including, as a semiconductor substrate, an active layer (1c) on a support substrate (1a) via a buried oxide film (1b) as a semiconductor substrate. This can be applied to the case where a lateral IGBT is formed in the active layer (1c) using (1).

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is the figure which showed the cross-sectional structure of horizontal type IGBT with which the semiconductor device concerning 1st Embodiment of this invention is equipped. It is the figure which showed the cross-sectional structure of horizontal IGBT in a cross section different from FIG. FIG. 3 is a top surface layout diagram of the lateral IGBT shown in FIGS. It is the figure which showed the cross-sectional structure of horizontal IGBT concerning 2nd Embodiment of this invention. FIG. 4 is a top surface layout diagram of the lateral IGBT shown in FIG. 3. FIG. 4 is a wiring layout diagram of the lateral IGBT shown in FIG. 3. It is a top surface layout diagram of a lateral IGBT according to a third embodiment of the present invention. It is a top surface layout diagram of the semiconductor device which constituted the inverter circuit concerning a 4th embodiment of the present invention. It is a circuit diagram when a sense resistor for current detection is connected to a semiconductor integrated circuit having a main cell and a sense cell.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. In this embodiment, a case where the present invention is applied to a semiconductor device provided with an n-channel type lateral IGBT will be described.

  FIGS. 1A and 1B are views showing a cross-sectional configuration of the lateral IGBT according to the present embodiment. FIG. 2 is a top surface layout diagram of the lateral IGBT shown in FIGS. 1A corresponds to the cross section along line A-A ′ in FIG. 2, and FIG. 1B corresponds to the cross section along B-B ′ in FIG. 2. Although FIG. 2 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing. Hereinafter, the structure of the lateral IGBT according to the present embodiment will be described with reference to these drawings.

  As shown in FIGS. 1A and 1B, in this embodiment, a lateral IGBT is formed using the SOI substrate 1, and a lateral IGBT for turning on / off current supply to a load (not shown) is formed. In addition to the main cell thus formed, a sense cell including a lateral IGBT having the same structure as the main cell as a current detection element is also formed.

The SOI substrate 1 is formed by forming an active layer 1c made of silicon on a support substrate 1a made of silicon or the like via a buried oxide film (box) 1b. In this embodiment, the active layer 1c the n ^- is functioning as a type drift layer 2, the the n ^- surface portion of the type drift layer 2, the components constituting the lateral IGBT is formed in the main cell and sensing cell.

The thickness of the buried oxide film 1b in the SOI substrate 1, the thickness of the active layer 1c (n ⁻ type drift layer 2), and the impurity concentration are arbitrary, but are designed to obtain a desired breakdown voltage. For example, the thickness of the buried oxide film 1b is preferably 4 μm or more in order to obtain a high breakdown voltage, and in particular, the thickness is 5 μm or more in order to ensure a stable breakdown voltage of 600 V or more. Is preferable. For the active layer 1c, the n-type impurity concentration is 1 × 10 ^{14 to} 1.2 × 10 ¹⁵ cm ⁻³ when the thickness is 15 μm or less in order to ensure a stable withstand voltage of 600 V or more. When the thickness is 20 μm, the n-type impurity concentration is preferably 1 × 10 ¹⁴ to 8 × 10 ¹⁴ cm ⁻³ .

A LOCOS oxide film 3 is formed on the surface of the n ⁻ -type drift layer 2, and each part constituting the lateral IGBT is separated by the LOCOS oxide film 3. A p ⁺ -type collector region 4 having one direction as a longitudinal direction is formed in a portion of the surface layer portion of the n ⁻ -type drift layer 2 where the LOCOS oxide film 3 is not formed. The periphery of the p ⁺ -type collector region 4 is surrounded by an n-type buffer layer 5 having a higher impurity concentration than the n ⁻ -type drift layer 2.

Further, in the surface layer portion of the n ⁻ -type drift layer 2, a linear channel p-well layer 6 and an n ⁺ -type emitter region 7 parallel to the p ⁺ -type collector region 4 are formed in a portion where the LOCOS oxide film 3 is not formed. , P ⁺ -type contact layer 8 and p-type body layer 9 are formed.

The channel p well layer 6 is a part for forming a channel region on the surface, and has a thickness of 2 μm or less and a width of 6 μm or less, for example. As shown in FIG. 2, the channel p-well layer 6 is formed with the same direction as the p ⁺ -type collector region 4 (and collector electrode 12 described later) as the longitudinal direction.

Further, the n ⁺ -type emitter region 7 is formed in the surface layer portion of the channel p-well layer 6 so as to terminate inside the termination position of the channel p-well layer 6, and the longitudinal direction of the p ⁺ -type collector region 4 And the same direction as the longitudinal direction. In this embodiment, one n ⁺ -type emitter region 7 is arranged on each side of the p-type contact layer 8 and the p-type body layer 9.

The p ⁺ -type contact layer 8 is for fixing the channel p-well layer 6 to the emitter potential, and has a higher impurity concentration than the channel p-well layer 6. The p ⁺ type contact layer 8 is also formed with the same direction as the p ⁺ type collector region 4 (and collector electrode 12 described later) as the longitudinal direction, as shown in FIG.

The p-type body layer 9 serves to reduce a voltage drop caused by a hole current flowing from the collector to the emitter via the surface. The p-type body layer 9 is also formed with the same direction as the p ⁺ -type collector region 4 (and a collector electrode 12 described later) as the longitudinal direction. This p-type body layer 9 makes it difficult for the parasitic npn transistor constituted by the n ⁺ -type emitter region 7, the channel p-well layer 6 and the n ⁻ -type drift layer 2 to operate, and further improves the turn-off time. It becomes possible.

As shown in FIGS. 1A and 1B and FIG. 2, the channel p-well layer 6, the n ⁺ -type emitter region 7, the p ⁺ -type contact layer 8 and the p-type body layer 9 configured as described above are taken as a set. Two sets of these portions are arranged side by side in the direction perpendicular to the longitudinal direction of the p ⁺ -type collector region 4. As shown in FIG. 1B and FIG. 2, each of these parts is divided into two regions at the central position to be divided into three regions. The central part is used as a sense cell, and main cells are arranged on both sides of the sense cell. I try to do it. That is, the emitter of the sense cell is sandwiched between the emitters of the main cell. The p-type body layer 9 is also divided between the sense cell and the main cell, and the p-type body layer 9 of each of the sense cell and the main cell is junction-separated. Thereby, leakage through the p-type body layer 9 can be prevented.

Further, between the divided n ⁺ -type emitter region 7, that is, on the main cell side of the sense cell and on the sense cell side of the main cell, from the end of the p ⁺ -type contact layer 8 to the end of the n ⁺ -type emitter region 7. A p ⁺ type separation layer 8 a extending in the direction perpendicular to the longitudinal direction of the p ⁺ type contact layer 8 is provided. By providing this p ⁺ type isolation layer 8a, a parasitic transistor constituted by the n ⁺ type emitter region 7, the p type body layer 9, and the n − type drift layer 2 operates on the main cell side and the sense cell side, respectively. It is possible to prevent.

  A gate electrode 11 made of doped Poly-Si or the like is disposed on the surface of the channel p well layer 6 with a gate insulating film 10 interposed therebetween. By applying a gate voltage to the gate electrode 11, a channel region is formed on the surface portion of the channel p-well layer 6.

Further, a collector electrode 12 electrically connected to the p ⁺ type collector region 4 is formed on the surface of the p ⁺ type collector region 4, and the n ⁺ type emitter region 7 and the p ⁺ type contact layer are formed. An emitter electrode 13 electrically connected to the n ⁺ -type emitter region 7 and the p ⁺ -type contact layer 8 is formed on the surface of 8. In this embodiment, the emitter electrode 13 has a structure in which two pairs of the p well layer 6, the n ⁺ type emitter region 7, the p ⁺ type contact layer 8 and the p type body layer 9 are provided adjacent to each other. Are formed side by side, and adjacent emitter electrodes 13 are electrically connected to each other.

Further, although not shown in FIGS. 1A and 1B, as shown in FIG. 2, the main emitter wiring (main wiring) 15a to which the emitter electrode 13 of the main cell is electrically connected and the emitter electrode of the sense cell are connected. Sense emitter wiring (sense wiring) 15b electrically connected to 13 is drawn to the opposite side of the collector, and the main emitter wiring 15a further extends in the same direction as the longitudinal direction of the n ⁺ -type emitter region 7. It is installed. The collector wiring (common wiring) 16 electrically connected to the collector electrode 12 extends in the same direction as the longitudinal direction of the collector electrode 12. The main emitter wiring 15a, the sense emitter wiring 15b, and the collector wiring 16 are constituted by a first layer wiring such as a 1stAl wiring formed through an interlayer insulating film (not shown).

  With such a configuration, the wiring layout can be such that the collector wiring 16, the main emitter wiring 15a, and the sense emitter wiring 15b do not overlap. For this reason, it is possible to reduce the influence of the coupling current due to the potential fluctuation from the collector where a high potential difference occurs, and to ensure high current detection accuracy in the sense cell.

The horizontal IGBT according to the present embodiment is configured by the above structure. In the lateral IGBT configured as described above, when a desired gate voltage is applied to the gate electrode 11, the lateral IGBT is positioned below the gate electrode 11 sandwiched between the n ⁺ -type emitter region 7 and the n ⁻ -type drift layer 2. A channel region is formed in the surface layer portion of the channel p-well layer 6 to be operated, and electrons flow into the n ⁻ -type drift layer 2 from the emitter electrode 13 and the n ⁺ -type emitter region 7 through the channel region. Along with this, n through the collector electrode 12 and the p ⁺ -type collector region 4 ^- hole flows into the type drift layer 2, n ^- conductivity modulation occurs in the type drift layer 2. Thereby, an IGBT operation of flowing a large current between the emitter and the collector is performed.

  In this embodiment, the main cell is arranged on both sides of the sense cell so that the emitter of the sense cell is sandwiched between the emitters of the main cell. For this reason, the current density flowing through the emitter of the main cell can be made closer to the current density flowing through the emitter of the sense cell, and the mirror ratio becomes close to the ratio of the lengths of the main cell and the sense cell in the longitudinal direction of the emitter. Also, since the current density flowing through the emitter of the sense cell and the current density flowing through the emitter of the sense cell can be made closer, the amount of current per unit area that flows when switching or when a large current flows is larger on the sense cell side than on the main cell side. Can be suppressed. For this reason, current bias can be suppressed and the breakdown tolerance can be improved.

  Therefore, the current flowing through the main cell can be accurately detected by the sense cell, and the semiconductor device can be improved in the linearity of current detection. In addition, even when a high voltage is used, it is possible to obtain a semiconductor device that is hardly affected by the influence.

(Second Embodiment)
A second embodiment of the present invention will be described. In this embodiment, the configuration of the lateral IGBT, specifically, the top surface layout of the lateral IGBT is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment. Only different parts will be described.

  FIG. 3 is a cross-sectional view of the lateral IGBT according to the present embodiment. FIG. 4 is a top surface layout diagram of the lateral IGBT according to the present embodiment, and FIG. 5 is a wiring layout diagram of the lateral IGBT according to the present embodiment. 3 corresponds to the C-C ′ cross section of FIG. 4. Further, FIG. 5 schematically shows only the channel p-well 6 and the sense cell, omitting each part constituting the lateral IGBT in order to make the wiring layout easy to see.

As shown in FIGS. 3 and 4, also in this embodiment, the p ⁺ type collector region 4 is formed with one direction as the longitudinal direction, and the n type buffer layer 5 is surrounded so as to surround the p ⁺ type collector region 4. Is forming. In this embodiment, the channel p-well layer 6, n ⁺ -type emitter region 7, p ⁺ -type contact layer 8 and p-type body layer 9 are formed around the p ⁺ -type collector region and the n-type buffer layer 5. is doing.

Specifically, the channel p well layer 6, as shown in FIG. 4, around the p ⁺ -type collector region 4, are disposed around the p ⁺ -type collector region 4 to 1 around unnecessarily concentric. The n ⁺ -type emitter region 7 is formed in the surface layer portion of the channel p-well layer 6 with the same direction as the longitudinal direction of the p ⁺ -type collector region 4 as the longitudinal direction. The n ⁺ -type emitter region 7, a corner portion of the p ⁺ -type collector region 4 as shown in FIG. 4, that is not formed at both ends of the p ⁺ -type collector region 4 in which the one-way to the longitudinal direction, The linear layout is arranged in parallel with the p ⁺ -type collector region 4. In this embodiment, one n ⁺ -type emitter region 7 is arranged on each side of the p-type contact layer 8 and the p-type body layer 9. p ⁺ -type contact layer 8 around the p ⁺ -type collector region 4 as shown in FIG. 4, is disposed around the p ⁺ -type collector region 4 to 1 around unnecessarily concentric. p-type body layer 9 is also around the p ⁺ -type collector region 4, are disposed around the p ⁺ -type collector region 4 to 1 around unnecessarily concentric.

Thus, as shown in FIGS. 3 and 4, the channel p-well layer 6, the n ⁺ -type emitter region 7, the p ⁺ -type contact layer 8 and the p-type body layer 9 have p ^{+ + for} each cell. They are arranged on both sides of the mold collector region 4. Therefore, between adjacent cells, as shown in FIG. 4, two sets of channel p-well layer 6, n ⁺ -type emitter region 7, p ⁺ -type contact layer 8 and p-type body layer 9 are arranged. It has become. Corresponding to such a layout, the gate electrode 11, the collector electrode 12, and the emitter electrode 13 are laid out so as to be electrically connected to a desired part.

Furthermore, in the present embodiment, the resistance layer 14 constituting the field plate in which doped Poly-Si is extended is formed on the surface of the LOCOS oxide film 3 formed between the collector and gate, In this way, the bias of the potential gradient is eliminated. Specifically, as shown in FIG. 4, the resistance layer 14 has a structure wound in a spiral around the collector electrode 12, and one end thereof is electrically connected to the collector electrode 12 as shown in FIG. 3. And the other end is connected to the gate electrode 11. For this reason, the portion of the resistance layer 14 connected to the collector electrode 12 is set to the collector potential, and proceeds from the resistance layer 14 to the emitter side while gradually decreasing the voltage due to the internal resistance. Therefore, the potential of the resistance layer 14 becomes a potential gradient corresponding to the distance from the collector electrode 12, and the potential gradient in the n ⁻ type drift layer 2 located below the resistance layer 14 via the LOCOS oxide film 3 is also It can be kept constant. As a result, electric field concentration that can occur when there is a bias in the potential gradient can be suppressed, the withstand voltage can be improved, impact ionization can be suppressed, and an increase in switching time during switching (turn-off) can be suppressed. Is possible.

With such a structure, a lateral IGBT laid out in an oval shape is configured, and the main cell and the sense cell are configured by the lateral IGBT laid out in an oval shape. Specifically, a main cell is formed by a plurality of horizontal IGBTs having an elliptical layout structure, and a plurality of them are arranged side by side in a direction perpendicular to the longitudinal direction of the p ⁺ -type collector region 4. A sense cell is configured by using a linear portion of the outer emitter. Then, both the main cell and the sense cell are surrounded by the trench isolation structure 1d, so that the main cell and the sense cell are arranged in the same trench island.

  The semiconductor device including the lateral IGBT according to the present embodiment is configured by the structure as described above. In the lateral IGBT provided in the semiconductor device configured as described above, a main cell is disposed on both sides of the sense cell, and the emitter of the sense cell is sandwiched between the emitters of the main cell. In such a structure, as shown in FIG. 5, the main emitter wiring 15a electrically connected to the emitter electrode 13 of the main cell located on both sides of the sense cell and the emitter electrode 13 of the sense cell are electrically connected. Both sense emitter wirings 15b are drawn to the opposite side of the collector. Further, the collector wiring 16 electrically connected to the collector electrode 12 is extended in the same direction as the longitudinal direction of the collector electrode 12, and then the collector wiring 16 of each cell is made common and collected. Yes.

  According to such a structure, as in the first embodiment, the wiring layout can be such that the collector wiring 16, the main emitter wiring 15a, and the sense emitter wiring 15b do not overlap. For this reason, it is possible to reduce the influence of the coupling current due to the potential fluctuation from the collector where a high potential difference occurs, and to ensure high current detection accuracy in the sense cell. In addition, according to the structure of the present embodiment, compared to a structure in which current is extracted to the outside via multilayer wiring through via holes or the like, current can be extracted to the outside through the shortest path, thereby reducing the influence of noise. Therefore, higher current detection accuracy can be ensured.

  Further, as shown in FIG. 5, a sense resistor Rs is arranged between the sense emitter wiring 15b and the main emitter wiring 15a adjacent to the sense emitter wiring 15b. That is, as shown in FIG. 8, the current flowing through the emitter of the main cell is detected by detecting the voltage across the sense resistor Rs, but one end of the sense resistor Rs is connected to the emitter of the sense cell. The end is connected to the emitter of the main cell to take a reference potential. For this reason, the reference potential of the sense resistor Rs is obtained by arranging the sense resistor Rs between the sense emitter wire 15b and the main emitter wire 15a. As a result, the sense resistor Rs can be connected to the closest main emitter wiring 15a. The sense resistor Rs can be directly connected to the main emitter wiring 15a constituted by the first layer wiring, and the reference potential can be obtained stably. Therefore, the current detection accuracy can be further improved.

  Note that the sense resistor Rs is not limited to a diffused resistor formed at a position isolated from the trench island where the lateral IGBT is formed, but also a Poly-Si resistor or a thin film resistor formed on the interlayer insulating film. You may be comprised by the resistance of the structure.

  In addition, in this embodiment, since the resistance layer 14 constituting the field plate is provided, it is possible to ensure a withstand voltage, but on the other hand, the potential of the resistance layer 14 also changes during switching, which can be a noise generation source. However, since the sense emitter wiring 15b is drawn out on the side opposite to the collector, the sense emitter wiring 15b is prevented from overlapping with the resistance layer 14, and even if the resistance layer 14 becomes a noise generation source, the current detection accuracy is thereby deteriorated. Can be suppressed.

  Further, in the present embodiment, the sense cell is arranged substantially at the center of the straight line portion constituting the emitter of the main cell. With this arrangement, the amount of holes flowing into the sense cell becomes a value reflecting the average hole concentration of the main cell, and the mirror ratio can be made closer to the cell length ratio. It becomes possible to suppress fluctuations.

  In the present embodiment, a lateral IGBT including only two cells having an oval layout structure is taken as an example, but the number may be larger than that. Even in such a case, the main cell is formed by the lateral IGBTs having a plurality of oval-shaped layout structures, and the sense cell is formed by using the linear portion of the outermost emitter of the main cells. The same effect can be obtained.

(Third embodiment)
A third embodiment of the present invention will be described. This embodiment shows a specific structure of the connection form of the sense resistor Rs with respect to the first embodiment, and the other parts are the same as those of the first embodiment, and therefore different from the first embodiment. Only will be described.

  FIG. 6 is a top surface layout diagram of the lateral IGBT according to the present embodiment. As shown in this figure, in this embodiment, a sense resistor Rs is arranged between both the sense emitter wiring 15b and the main emitter wiring 15a adjacent to both sides thereof.

  Thus, if the sense resistor Rs is arranged between the main emitter line 15a and the sense emitter line 15b located on both sides of the sense emitter line 15b, the sense resistor Rs is equal to both sides of the sense cell line. It can be arranged with a resistance value. Therefore, the operation of the main cell becomes uniform on both sides of the sense cell, and the current detection accuracy in the sense cell can be further improved.

  Although the specific structure of the sense resistor Rs is shown here with respect to the first embodiment, the same structure is provided even when each cell has an elliptical top layout as in the second embodiment. By applying, effects similar to the above can be obtained.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, a case will be described in which the semiconductor device including the lateral IGBT described in the first to third embodiments is applied to a semiconductor device constituting an inverter circuit. Here, the case where the top surface layout of the lateral IGBT shown in the second embodiment is applied will be described as an example, but the top surface layout of the first and third embodiments may be used.

  FIG. 7 is a top surface layout diagram of the semiconductor device constituting the inverter circuit according to the present embodiment. The inverter circuit shown in this figure drives a three-phase motor based on a high voltage (for example, 288 V) applied from a main power source such as a battery. A semiconductor device has a basic configuration of an inverter circuit as an integrated circuit. A chip inverter driver IC is configured. Specifically, the driving of a three-phase motor is controlled by a control microcomputer (not shown) provided outside the semiconductor device, and the control microcomputer supplies alternating current to each phase of the three-phase motor in turn when the motor is driven. Thus, the three-phase motor is driven by controlling the inverter circuit.

  The semiconductor device includes an inverter output circuit 20 in which upper and lower arms 20a to 20f connected in series are connected in parallel for three phases, and a circuit for controlling upper and lower arms 20a to 20f for three phases, that is, six arms 20a to 20f. For example, the control circuit unit 21 including various circuits is provided.

  As shown in FIG. 7, the upper arms 20a, 20c, 20e for the three phases and the lower arms 20b, 20d, 20f for the three phases are alternately laid out in the horizontal direction on the paper. In this embodiment, the lower arm 20b, the upper arm 20a, the upper arm 20c, the lower arm 20d, the lower arm 20f, and the upper arm 20e are alternately arranged in this order from the left in FIG. The control circuit unit 21 is configured by providing various circuits corresponding to the upper and lower arms 20a to 20f. The lateral IGBTs 22a to 22f, the free wheel diodes (hereinafter referred to as FWD) 23a to 23f, and the control circuit unit 21 provided in the arms 20a to 20f are insulated and separated by the trench isolation structure 1d.

  In such a structure, a plurality of horizontal IGBTs 22a to 22f having an elliptical top layout are arranged in one direction (up and down in the drawing), and the sense cell is arranged on the outermost side of the cell on the control circuit unit 21 side. 24a to 24f are arranged. Although not shown, the sense emitter wirings in the sense cells 24a to 24f are arranged so as not to overlap the main emitter wiring in the main cells and the anode wiring and cathode wiring of the FWDs 23a to 23f.

  As described above, the same structure as that of the first to third embodiments can be applied to the sense cell for detecting the current of the lateral IGBT also for the semiconductor device configuring the inverter circuit. In such a structure, the sense cells 24a to 24f are arranged on the outermost side of the cells on the control circuit unit 21 side among the plurality of lateral IGBTs 22a to 22f arranged side by side. For this reason, the sense emitter wirings in the sense cells 24a to 24f can be arranged so as not to overlap the main emitter wiring in the main cell and the anode wiring and cathode wiring of the FWDs 23a to 23f, that is, the high potential wirings of the lateral IGBTs 22a to 22f and FWDs 23a to 23f. Therefore, even if the detection voltage from the sense cell (the output voltage of the sense resistor Rs) is a low voltage of, for example, 300 mV or less, it is detected due to interference with the high potentials of the lateral IGBTs 22a to 22f and FWDs 23a to 23f (for example, about 300V at maximum) It is possible to prevent the voltage from fluctuating.

  Further, by adopting such a configuration, the influence of the recovery current generated in the FWDs 23a to 23f can be reduced, and the length of the wiring connected to the control circuit unit 21 can be minimized, so that the lateral IGBTs 22a to 22f are generated more. The influence of noise can be reduced.

(Other embodiments)
In each of the above embodiments, an example of the configuration of a semiconductor device including a lateral IGBT has been described, but the design can be changed as appropriate.

  For example, in each of the above embodiments, the case where the lateral IGBT is formed on the SOI substrate 1 has been described. However, the lateral IGBT may be formed on a semiconductor substrate such as a simple silicon substrate that does not have an SOI structure. Further, the structure of the lateral IGBT may be changed. For example, in the second embodiment, the resistance layer 14 is formed to make the potential gradient more uniform, but the resistance layer 14 may not be formed. Further, although the other end of the resistance layer 14 is connected to the gate electrode 11, a structure in which it is connected to the emitter electrode 13 may be used.

Furthermore, in each of the above embodiments, the n-channel type lateral IGBT in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example, but the conductivity type of each component is inverted. The present invention can also be applied to a p-channel type lateral IGBT. In other words, the drift layer is composed of the n ⁻ type drift layer 2, the channel layer is composed of the channel p well layer 6, the collector region is composed of the p ⁺ type collector region 4, and the emitter region is composed of the n ⁺ type emitter region 7. Although a channel type lateral IGBT is taken as an example, a p-channel type lateral IGBT can be obtained by inverting these conductivity types.

DESCRIPTION OF SYMBOLS 1 SOI substrate 1a Support substrate 1b Embedded oxide film 1c Active layer 2 n ⁻ type drift layer 4 p ⁺ type collector region 6 channel p well layer 7 n ⁺ type emitter region 8 p ⁺ type contact layer 9 p type body layer 10 gate Insulating film 11 Gate electrode 12 Collector electrode 13 Emitter electrode 14 Resistance layer 20 Arm (upper and lower arms)
21 Control circuit

Claims (10)

A semiconductor substrate (1) having a drift layer (2) of the first conductivity type;
A collector region (4) of a second conductivity type formed with one direction as a longitudinal direction in a surface layer portion of the drift layer (2) in the drift layer (2);
A channel layer (6) of a second conductivity type having a linear portion parallel to the collector region (4) in a surface layer portion of the drift layer (2) in the drift layer (2);
A surface layer portion of the channel layer (6) in the channel layer (6) is formed so as to terminate inside the terminal portion of the channel layer (6), and is the same as the longitudinal direction of the collector region (4). A first conductivity type emitter region (7) having a linear portion with the direction as a longitudinal direction;
A portion of the surface of the channel layer (6) sandwiched between the emitter region (7) and the drift layer (2) is defined as a channel region, and a gate insulating film ( 10) and
A gate electrode (11) formed on the surface of the gate insulating film (10);
A first electrode (12) electrically connected to the collector region (4);
A cell having a second electrode (13) electrically connected to the emitter region (7) and the channel layer (6) is provided, and has a lateral IGBT for controlling on / off of current supply to a load. A semiconductor device,
By dividing the emitter region (7), a main cell having a lateral IGBT for controlling on / off of current supply to the load and a lateral IGBT having the same structure as the main cell are provided as a current detection element. A semiconductor device having a lateral IGBT, characterized in that a sense cell is configured, and the main cell is disposed on both sides of the sense cell so that the sense cell is sandwiched between the main cells.   A second conductivity type body layer (9) having a higher impurity concentration than the channel layer (6) is provided in the channel layer (6), and the body is interposed between the sense cell and the main cell. The semiconductor device having a lateral IGBT according to claim 1, wherein the body layer (9) is junction-separated by dividing the layer (9).   3. The semiconductor device having a lateral IGBT according to claim 1, wherein the sense cell is arranged at a center position of the main cell on both sides of the sense cell. A contact layer (8) of the second conductivity type having a higher impurity concentration than the channel layer (6) is provided in the channel layer (6).
The contact layer (8) extends toward the emitter region (7) side end at the main cell side end of the sense cell and the sense cell side end of the main cell. The semiconductor device having a lateral IGBT according to any one of claims 1 to 3, further comprising a separation layer (8a). Linear portions of the channel layer (6) and the emitter region (7) are disposed on both sides of the collector region (4),
The channel layer (6) has an oval shape by having a corner portion surrounding the tip of the collector region (4),
A plurality of the cells are arranged in a direction perpendicular to the longitudinal direction of the collector region (4), and the outermost linear emitter region (7) is divided to constitute the sense cell. The semiconductor device having a lateral IGBT according to claim 1, wherein the semiconductor device has a lateral IGBT. A sense resistor (Rs) electrically connected to the second electrode (13) connected to the emitter region (7) in the sense cell;
A sense wiring (15b) composed of a first-layer wiring formed as a first layer via an interlayer insulating film formed on the surface of the semiconductor substrate (1) is directly connected to the second electrode (13). 6. The semiconductor device having a lateral IGBT according to claim 1, wherein the semiconductor device is electrically connected and is also directly electrically connected to the sense resistor (Rs). 7.   The sense wiring (15b) is pulled out to the opposite side of the collector region (4), thereby being electrically connected to the first electrode (12) connected to the collector region (4). The semiconductor device having a lateral IGBT according to claim 6, wherein the semiconductor device has a structure that does not overlap with (16). A main wiring (15a) electrically connected to the second electrode (13) connected to the emitter region (7) in the main cell disposed on both sides of the sense cell;
The sense resistor (Rs) is connected between the sense line (15b) and the main line (15a), so that the second electrode (13) of the main cell disposed on both sides of the sense cell. The semiconductor device having a lateral IGBT according to claim 6, wherein the potential is a reference potential.   The sense resistor (Rs) is provided both between the sense wiring (15b) in the sense cell and the main wiring (15a) of each of the main cells arranged on both sides of the sense cell. A semiconductor device having the lateral IGBT according to claim 8.   The semiconductor substrate is an SOI substrate (1) having an active layer (1c) on a support substrate (1a) through a buried oxide film (1b), and the lateral IGBT is formed on the active layer (1c). The semiconductor device having a lateral IGBT according to claim 1, wherein the semiconductor device is formed.

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