JP2012169345A - Multilayer wiring board - Google Patents
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Abstract
Description
この発明は、高速で動作する半導体チップを搭載する多層配線基板に関するものである。 The present invention relates to a multilayer wiring board on which a semiconductor chip that operates at high speed is mounted.
高速動作する半導体チップを搭載する配線基板では、高周波信号の伝搬のため、半導体チップに接続される各信号配線のインピーダンスを揃える必要がある。
また、半導体チップに接続される各信号配線の信号の伝搬速度を揃える必要がある。
In a wiring board on which a semiconductor chip that operates at high speed is mounted, it is necessary to align the impedance of each signal wiring connected to the semiconductor chip in order to propagate high-frequency signals.
Further, it is necessary to make the signal propagation speeds of the respective signal wirings connected to the semiconductor chip uniform.
このような信号配線において、インピーダンスを揃えるための構造として、例えばストリップラインが知られている。
ストリップラインでは、２層の平行した接地層や電源層間に信号配線を設けた構造により、信号配線のインピーダンスを調整する。
In such signal wiring, for example, a strip line is known as a structure for equalizing impedance.
In the strip line, the impedance of the signal wiring is adjusted by a structure in which the signal wiring is provided between two parallel ground layers and power supply layers.
特許文献１には、ストリップライン構造の信号配線を設け、各信号配線のインピーダンスを揃えた多層配線基板が開示されている。
しかし、各信号配線の信号の伝搬速度を揃えるための構造は開示されていない。
Patent Document 1 discloses a multilayer wiring board in which strip line structure signal wirings are provided and the impedance of each signal wiring is made uniform.
However, a structure for aligning the signal propagation speed of each signal wiring is not disclosed.
本発明の目的は、配線基板に配設される信号配線のインピーダンス及び信号伝搬速度を揃え得る多層配線基板を提供することにある。 An object of the present invention is to provide a multilayer wiring board capable of aligning the impedance and signal propagation speed of signal wirings arranged on the wiring board.
本発明の一観点によれば、多数本の信号配線の一端を接続するパッドと他端を接続するパッドを配線基板の表面と裏面に同心円状に配設して前記信号配線を等長とし、前記信号配線の上層及び下層に電源配線を配設した。 According to one aspect of the present invention, a pad for connecting one end of a large number of signal wires and a pad for connecting the other end are arranged concentrically on the front surface and the back surface of the wiring board so that the signal wires have the same length, A power supply wiring is disposed on the upper and lower layers of the signal wiring.
この構成によれば、配線基板に配設される信号配線のインピーダンス及び信号伝搬速度が揃えられる。 According to this configuration, the impedance and signal propagation speed of the signal wiring arranged on the wiring board are made uniform.
本発明の一観点によれば、配線基板に配設される信号配線のインピーダンス及び信号伝搬速度を揃え得る多層配線基板を提供することができる。 According to one aspect of the present invention, it is possible to provide a multilayer wiring board capable of aligning the impedance and signal propagation speed of signal wirings disposed on the wiring board.
（第一の実施形態）
以下、この発明を具体化した第一の実施形態を図面に従って説明する。図１に示す多層配線基板１は、その表面の中央部に形成されたＩＣパッド領域ＰＡに多数のＩＣパッド（半導体チップ搭載用のパッド）２がマトリックス状に配設されている。前記多層配線基板１の裏面には、図３に示すように、ほぼ前面に亘って多数のＩＯパッド（外部接続端子用のパッド）３が配設されている。
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. A multilayer wiring board 1 shown in FIG. 1 has a large number of IC pads (pads for mounting semiconductor chips) 2 arranged in a matrix in an IC pad area PA formed at the center of the surface thereof. On the back surface of the multilayer wiring board 1, as shown in FIG. 3, a large number of IO pads (pads for external connection terminals) 3 are disposed substantially over the front surface.
前記多層配線基板１は、図４に示すように、比誘電率が比較的小さい例えばエポキシ樹脂で形成される絶縁層４内に、高電位側電源配線５と、信号配線６と、低電位側電源配線７がそれぞれ電気的に絶縁された状態で配設されている。 As shown in FIG. 4, the multilayer wiring board 1 includes a high potential side power supply wiring 5, a signal wiring 6, and a low potential side in an insulating layer 4 made of, for example, epoxy resin having a relatively low relative dielectric constant. The power supply wirings 7 are arranged in an electrically insulated state.
この多層配線基板１は、一例として、エポキシ樹脂により絶縁層を形成する工程と、当該絶縁層上にセミアディティブ法により銅からなる配線層を形成する工程を繰り返して多層配線構造を得る、ビルドアップ法により形成される。 As an example, this multilayer wiring board 1 is a build-up in which a multilayer wiring structure is obtained by repeating a process of forming an insulating layer with an epoxy resin and a process of forming a wiring layer made of copper on the insulating layer by a semi-additive method. Formed by law.
前記高電位側電源配線５の一端はビア８を介してＩＣパッド２ａに接続され、前記信号配線６の一端はビア９を介してＩＣパッド２ｂに接続され、前記低電位側電源配線７の一端はビア１０を介してＩＣパッド２ｃに接続されている。 One end of the high potential side power supply wiring 5 is connected to the IC pad 2 a through the via 8, one end of the signal wiring 6 is connected to the IC pad 2 b through the via 9, and one end of the low potential side power supply wiring 7. Is connected to the IC pad 2 c through the via 10.
ＩＣパッド２ａ〜２ｃは、前記ＩＣパッド２の一部であり、前記多層配線基板１の表面に形成されるソルダーレジスト膜１１の開口部１２に露出される。ソルダーレジスト膜１１は、多層配線基板１の表面に形成された後、開口部１２がパターニングされる。 The IC pads 2 a to 2 c are a part of the IC pad 2 and are exposed to the opening 12 of the solder resist film 11 formed on the surface of the multilayer wiring board 1. After the solder resist film 11 is formed on the surface of the multilayer wiring board 1, the opening 12 is patterned.
前記高電位側電源配線５の他端はビア１３を介してＩＯパッド３ａに接続され、前記信号配線６の他端はビア１４を介してＩＯパッド３ｂに接続され、前記低電位側電源配線７の他端はビア１５を介してＩＯパッド３ｃに接続されている。 The other end of the high potential side power supply line 5 is connected to the IO pad 3a through the via 13, the other end of the signal line 6 is connected to the IO pad 3b through the via 14, and the low potential side power supply line 7 is connected. Is connected to the IO pad 3c via the via 15.
ＩＯパッド３ａ〜３ｃは、前記ＩＯパッド３の一部であり、多層配線基板１の裏面に形成されるソルダーレジスト膜１６の開口部１７に露出される。
前記ＩＣパッド２ｂは、図２に示すように、前記ＩＣパッド領域ＰＡの外周近傍においてマトリクス状に配置されたＩＣパッド２の中からほぼ円周上に位置するＩＣパッドがＩＣパッド２ｂとして選択されている。
The IO pads 3 a to 3 c are a part of the IO pad 3 and are exposed to the openings 17 of the solder resist film 16 formed on the back surface of the multilayer wiring board 1.
As shown in FIG. 2, the IC pad 2b is selected as an IC pad 2b that is located on a substantially circumference from the IC pads 2 arranged in a matrix in the vicinity of the outer periphery of the IC pad area PA. ing.
そして、ＩＣパッド２ｂの外周側に近接してほぼ円周上に位置するＩＣパッドが前記ＩＣパッド２ｃとして円形に配置され、ＩＣパッド２ｂの内周側に近接してほぼ円周上に位置するＩＣパッドが前記ＩＣパッド２ａとして円形に配置されている。 Then, an IC pad that is located approximately on the circumference close to the outer peripheral side of the IC pad 2b is arranged in a circle as the IC pad 2c, and is located approximately on the circumference adjacent to the inner peripheral side of the IC pad 2b. IC pads are arranged in a circle as the IC pads 2a.
前記ＩＯパッド３ｂは、図３に示すように、前記多層配線基板１の裏面の外周近傍においてマトリクス状に配置されたＩＯパッド３の中からほぼ円周上に位置するＩＯパッドがＩＯパッド３ｂとして選択されている。また、前記ＩＣパッド２ｂとＩＯパッド３ｂとは同心円状に位置している。 As shown in FIG. 3, the IO pad 3b is an IO pad located almost on the circumference from among the IO pads 3 arranged in a matrix in the vicinity of the outer periphery of the back surface of the multilayer wiring board 1 as an IO pad 3b. Is selected. The IC pad 2b and the IO pad 3b are located concentrically.
そして、ＩＯパッド３ｂの外周側に近接して位置する多数のＩＯパッドが前記ＩＯパッド３ｃとして円周状に配置され、ＩＯパッド３ｂの内周側に近接して位置する多数のＩＯパッドが前記ＩＯパッド３ａとして円周状に配置されている。 A large number of IO pads positioned close to the outer peripheral side of the IO pad 3b are circumferentially arranged as the IO pad 3c, and a large number of IO pads positioned close to the inner peripheral side of the IO pad 3b are The IO pads 3a are arranged circumferentially.
図６〜図１２に示すように、前記高電位側電源配線５は，前記信号配線６及び低電位側電源配線７に接続されされるビア１４，１５を回避しながら、前記多層配線基板１の全域に亘って広面積で形成される配線層（パワープレーン）である。 As shown in FIGS. 6 to 12, the high-potential side power supply line 5 avoids the vias 14 and 15 connected to the signal line 6 and the low-potential side power supply line 7, while avoiding the vias 14 and 15. This is a wiring layer (power plane) formed in a wide area over the entire area.
また、前記低電位側電源配線７は，前記信号配線６及び高電位側電源配線５に接続されされるビア８，９を回避しながら、前記多層配線基板１の全域に亘って広面積で形成される配線層（グランドプレーン）である。 The low potential side power supply wiring 7 is formed in a wide area over the entire area of the multilayer wiring board 1 while avoiding the vias 8 and 9 connected to the signal wiring 6 and the high potential side power supply wiring 5. This is a wiring layer (ground plane).
前記信号配線６は、図５に示すように、前記ＩＣパッド２ｂとＩＯパッド３ｂとを接続するように、前記各ＩＣパッド２ｂからＩＯパッド３ｂに向かって放射状にパターニングされる多数本の配線である。そして、前記各信号配線６はほぼ同一の長さの配線であり、絶縁層４を介して高電位側電源配線５と低電位側電源配線７に対し等間隔を隔てて挟まれるストリップライン構造となっている。 As shown in FIG. 5, the signal wiring 6 is a plurality of wirings that are radially patterned from each IC pad 2b toward the IO pad 3b so as to connect the IC pad 2b and the IO pad 3b. is there. Each signal wiring 6 is a wiring having substantially the same length, and has a stripline structure sandwiched at an equal interval from the high potential side power supply wiring 5 and the low potential side power supply wiring 7 via the insulating layer 4. It has become.
次に、上記のように構成された多層配線基板１の作用を説明する。図４に示すように、多層配線基板１のＩＣパッド領域ＰＡ上の各ＩＣパッド２に、バンプ１８を介してチップ１９を接合する。 Next, the operation of the multilayer wiring board 1 configured as described above will be described. As shown in FIG. 4, a chip 19 is bonded to each IC pad 2 on the IC pad area PA of the multilayer wiring board 1 through bumps 18.
そして、ＩＯパッド３ａに供給される電源電圧が高電位側電源配線５及びＩＣパッド２ａを介してチップ１９に供給される。また、ＩＯパッド３ｃに供給されるグランド電位が低電位側電源配線７及びＩＣパッド２ｃを介してチップ１９に供給される。 Then, the power supply voltage supplied to the IO pad 3a is supplied to the chip 19 via the high potential side power supply wiring 5 and the IC pad 2a. The ground potential supplied to the IO pad 3c is supplied to the chip 19 via the low potential side power supply wiring 7 and the IC pad 2c.
また、ＩＯパッド３ｂに入力される信号が信号配線６及びＩＣパッド２ｂを介してチップ１９に供給され、あるいはチップ１９から出力される信号がＩＣパッド２ｂ及び信号配線６を介してＩＯパッド３ｂから出力される。 A signal input to the IO pad 3b is supplied to the chip 19 via the signal wiring 6 and the IC pad 2b, or a signal output from the chip 19 is output from the IO pad 3b via the IC pad 2b and the signal wiring 6. Is output.
このとき、各ＩＣパッド２ｂとＩＯパッド３ｂとを接続する各信号配線６の長さがほぼ均等であり、かつすべての信号配線６が高電位側電源配線５と低電位側電源配線７との間に均等間隔で挟まれた状態であるので、各信号配線６のインピーダンス及び信号の伝搬速度がほぼ均等となる。 At this time, the lengths of the signal lines 6 connecting the IC pads 2b and the IO pads 3b are substantially equal, and all the signal lines 6 are connected to the high potential side power supply lines 5 and the low potential side power supply lines 7. Since they are sandwiched between them at equal intervals, the impedance of each signal line 6 and the signal propagation speed are substantially equal.
そして、各信号配線６とチップ１９の入出力回路との間でインピーダンスの不整合が発生しないように、各信号配線６のインピーダンスとチップ１９の入出力インピーダンスが設定されている。 The impedance of each signal wiring 6 and the input / output impedance of the chip 19 are set so that impedance mismatch does not occur between each signal wiring 6 and the input / output circuit of the chip 19.
上記のような多層配線基板１では、次に示す効果を得ることができる。
（１）ＩＣパッド２ｂとＩＯパッド３ｂとを同心円状に配置して、ＩＣパッド２ｂとＩＯパッド３ｂとを接続する多数本の信号配線６をほぼ等長とすることができる。また、各信号配線６が高電位側電源配線５と低電位側電源配線７との間に挟まれるストリップライン構造としたので、各信号配線６に寄生する容量及びインダクタンスを揃えて、各信号配線６のインピーダンス及び信号の伝搬速度を揃えることができる。
（２）多数本の信号配線６をほぼ等長としたので、各信号配線６での信号伝搬遅延のばらつきを抑制し、信号の伝搬速度をほぼ均等とすることができる。
（３）ＩＣパッド２ｂとＩＯパッド３ｂとの間の各信号配線６を、ビア９，１４を含めてほぼ等長としたので、ＩＣパッド２ｂとＩＯパッド３ｂとの間での信号伝搬遅延のばらつきを抑制し、信号の伝搬速度をほぼ均等とすることができる。
（４）各信号配線６のインピーダンスと、チップ１９の入出力インピーダンスを整合させることができる。
（５）多層配線基板１の表面にマトリックス状に配設されるＩＣパッド２の中から円周状に位置するＩＣパッド２ｂと、多層配線基板１の裏面にマトリックス状に配設されるＩＯパッド３の中から円周状に位置するＩＯパッド３ｂとを信号配線６で接続した。多層配線基板１の表裏面にマトリックス状に配設されるＩＣパッド及びＩＯパッドを使用して、多数本の等長の信号配線６を形成することができる。
（第二の実施形態）
図１３〜図１５は、第二の実施形態を示す。この実施形態は、前記第一の実施形態の各信号配線６の間に低電位側電源配線７を配設して各信号配線６間に発生するクロストークノイズの低減を図るようにしたものである。
In the multilayer wiring board 1 as described above, the following effects can be obtained.
(1) The IC pad 2b and the IO pad 3b are concentrically arranged, and a large number of signal wirings 6 connecting the IC pad 2b and the IO pad 3b can be made substantially equal in length. Further, since each signal wiring 6 has a stripline structure sandwiched between the high-potential-side power supply wiring 5 and the low-potential-side power supply wiring 7, the parasitic capacitance and inductance of each signal wiring 6 are aligned and each signal wiring is arranged. 6 impedance and signal propagation speed can be made uniform.
(2) Since a large number of the signal wirings 6 are substantially equal in length, variation in signal propagation delay in each signal wiring 6 can be suppressed, and the signal propagation speed can be made substantially uniform.
(3) Since each signal wiring 6 between the IC pad 2b and the IO pad 3b is made substantially equal in length including the vias 9 and 14, the signal propagation delay between the IC pad 2b and the IO pad 3b is reduced. Variations can be suppressed and signal propagation speeds can be made substantially uniform.
(4) The impedance of each signal line 6 and the input / output impedance of the chip 19 can be matched.
(5) IC pads 2b located circumferentially among the IC pads 2 arranged in a matrix on the surface of the multilayer wiring board 1, and IO pads arranged in a matrix on the back surface of the multilayer wiring board 1 The IO pad 3 b located in a circumferential shape from among the three is connected by the signal wiring 6. A large number of equal-length signal wirings 6 can be formed using IC pads and IO pads arranged in a matrix on the front and back surfaces of the multilayer wiring board 1.
(Second embodiment)
13 to 15 show a second embodiment. In this embodiment, a low potential side power supply wiring 7 is provided between the signal wirings 6 of the first embodiment so as to reduce crosstalk noise generated between the signal wirings 6. is there.
図１４に示すように、低電位側電源配線７は信号配線６と同一層で前記ビア１５から延設され、図１３及び図１５に示すように、放射状に延びる各信号配線６間を埋めるように、かつ信号配線６と低電位側電源配線７との間隔が一定となるようにレイアウトされている。 As shown in FIG. 14, the low-potential-side power supply wiring 7 extends from the via 15 in the same layer as the signal wiring 6, and fills between the radially extending signal wirings 6 as shown in FIGS. In addition, the layout is made such that the distance between the signal wiring 6 and the low potential side power supply wiring 7 is constant.
上記のような多層配線基板では、第一の実施形態で得られた効果に加えて、次に示す作用効果を得ることができる。
（１）隣り合う信号配線６間でクロストークノイズの発生を抑制することができる。
In the multilayer wiring board as described above, the following operational effects can be obtained in addition to the effects obtained in the first embodiment.
(1) Generation of crosstalk noise between adjacent signal wirings 6 can be suppressed.
上記実施形態は、以下の態様で実施してもよい。
・第一及び第二の実施形態において、高電位側電源配線５と低電位側電源配線７を上下方向に入れ替えてもよい。
・第一及び第二の実施形態において、信号配線６の上層及び下層に設ける電源配線をともに低電位側電源配線、あるいはともに高電位側電源配線としてもよい。
・ＩＣパッド２ｂを、ＩＣパッド領域ＰＡの外周近傍以外の位置に設けてもよい。同様に、ＩＯパッド３ｂを、多層配線基板の裏面の外周近傍以外の位置に設けてもよい。例えば、ＩＣパッド領域ＰＡの中央部近傍に位置するＩＣパッドから、円周上に位置するパッドをＩＣパッド２ｂとしてもよい。また、多層配線基板１の裏面中央部近傍に位置するＩＯパッドから円周上に位置するパッドをＩＯパッド３ｂとしてもよい。
・第二の実施形態において、各信号配線６間に高電位側電源配線を配設してもよい。
You may implement the said embodiment in the following aspects.
In the first and second embodiments, the high potential side power supply wiring 5 and the low potential side power supply wiring 7 may be interchanged in the vertical direction.
-In 1st and 2nd embodiment, it is good also considering the power supply wiring provided in the upper layer and lower layer of the signal wiring 6 as a low potential side power supply wiring, or both high potential side power supply wiring.
The IC pad 2b may be provided at a position other than the vicinity of the outer periphery of the IC pad area PA. Similarly, the IO pad 3b may be provided at a position other than the vicinity of the outer periphery of the back surface of the multilayer wiring board. For example, the IC pad 2b may be a pad located on the circumference from an IC pad located near the center of the IC pad area PA. Alternatively, the IO pad 3b may be a pad located on the circumference from the IO pad located near the center of the back surface of the multilayer wiring board 1.
In the second embodiment, a high potential side power supply wiring may be disposed between the signal wirings 6.
１…多層配線基板、２，２ａ，２ｂ，２ｃ…ＩＣパッド、３，３ａ，３ｂ，３ｃ…ＩＯパッド、５…電源配線（高電位側電源配線）、６…信号配線、７…電源配線（低電位側電源配線）。 DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board, 2, 2a, 2b, 2c ... IC pad, 3, 3a, 3b, 3c ... IO pad, 5 ... Power supply wiring (high potential side power supply wiring), 6 ... Signal wiring, 7 ... Power supply wiring ( Low potential side power supply wiring).
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011027359A JP5872773B2 (en) | 2011-02-10 | 2011-02-10 | Multilayer wiring board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011027359A JP5872773B2 (en) | 2011-02-10 | 2011-02-10 | Multilayer wiring board |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012169345A true JP2012169345A (en) | 2012-09-06 |
| JP2012169345A5 JP2012169345A5 (en) | 2014-02-13 |
| JP5872773B2 JP5872773B2 (en) | 2016-03-01 |
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| JP2011027359A Active JP5872773B2 (en) | 2011-02-10 | 2011-02-10 | Multilayer wiring board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017050560A (en) * | 2016-11-16 | 2017-03-09 | 株式会社村田製作所 | High frequency module |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06236939A (en) * | 1993-02-08 | 1994-08-23 | Sumitomo Kinzoku Ceramics:Kk | Ic package and its wiring connecting method |
| JP2001274279A (en) * | 2000-03-27 | 2001-10-05 | Kyocera Corp | Multilayer wiring board |
| JP2005191172A (en) * | 2003-12-25 | 2005-07-14 | Elpida Memory Inc | Semiconductor integrated circuit |
| US20060065433A1 (en) * | 2004-09-29 | 2006-03-30 | Endicott Interconnect Technologies, Inc. | Circuitized substrate with improved impedance contol circuitry, method of making same, electrical assembly and information handling system utilizing same |
| JP2006147676A (en) * | 2004-11-17 | 2006-06-08 | Nec Corp | Wiring circuit board for semiconductor integrated circuit package and semiconductor integrated circuit device using the same |
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2011
- 2011-02-10 JP JP2011027359A patent/JP5872773B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06236939A (en) * | 1993-02-08 | 1994-08-23 | Sumitomo Kinzoku Ceramics:Kk | Ic package and its wiring connecting method |
| JP2001274279A (en) * | 2000-03-27 | 2001-10-05 | Kyocera Corp | Multilayer wiring board |
| JP2005191172A (en) * | 2003-12-25 | 2005-07-14 | Elpida Memory Inc | Semiconductor integrated circuit |
| US20060065433A1 (en) * | 2004-09-29 | 2006-03-30 | Endicott Interconnect Technologies, Inc. | Circuitized substrate with improved impedance contol circuitry, method of making same, electrical assembly and information handling system utilizing same |
| JP2006147676A (en) * | 2004-11-17 | 2006-06-08 | Nec Corp | Wiring circuit board for semiconductor integrated circuit package and semiconductor integrated circuit device using the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017050560A (en) * | 2016-11-16 | 2017-03-09 | 株式会社村田製作所 | High frequency module |
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| JP5872773B2 (en) | 2016-03-01 |
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