JP2012168650A - Information processor, and operation method of information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To switch core I/O devices for use without restarting partitions.SOLUTION: An information processor comprises: a map unit for mapping a currently used core I/O space and a standby core I/O space in a memory space of respective processor nodes; an inhibition unit for inhibiting the plurality of processor nodes from issuing a new transaction according to a change instruction of a use core I/O device; a copy unit for, after the inhibition, copying data stored in a copy source register included in the currently used core I/O device to a copy destination register included in the standby core I/O device; a routing setting change unit for, after the copying is completed, changing a routing setting so that a transaction related to the currently used core I/O device is transferred to the standby core I/O device; and a cancellation unit for, after the aforementioned changing, cancelling the inhibition of issuance of a new transaction.

Description

  The present invention relates to an information processing apparatus and an operation method of the information processing apparatus.

  In an information processing apparatus having a plurality of processor nodes and a plurality of I / O nodes, a plurality of partitions may be configured by arbitrarily combining processor nodes and I / O nodes. In each partition, the OS operates independently. Each I / O node is provided with a core I / O device. When each partition includes a plurality of I / O nodes, only the core I / O device included in any of the I / O nodes is used. Here, there is a request to switch the core I / O device used in the partition.

  As a related technique, there is a dynamic degeneration device described in Patent Document 1 (Japanese Patent Laid-Open No. 2008-225534). This dynamic degeneration apparatus is a dynamic degeneration apparatus of an I / O device that is duplicated by a master device and a slave device, and a transaction routing controller that receives, routes, and sends a transaction, and duplication of an I / O device. Valid information indicating validity, two identification information associated with the validity information, master device identification information indicating a route to the master device, and slave device identification information indicating a route to the slave device And a service processor that controls the transaction routing controller and the routing table.

  As another related technique, there is a system board described in Patent Document 2 (Japanese Patent No. 4165423). This system board has a plurality of PCI buses with the core I / O card. One identical core I / O card is mounted on each PCI bus. Furthermore, the same input / output device is connected to each core I / O card. Each core I / O card has storage means for storing information on input / output devices and a program for controlling the input / output devices, and input / output device control means for controlling the input / output devices. The storage means is connected to the input / output device control means, and the input / output device control means is connected to the PCI bus. This makes it possible to duplicate the core I / O card, and even when the core I / O card used due to a failure or the like is disconnected, it is possible to reboot using the other core I / O card. It becomes possible.

  Still another related technique is a system control apparatus described in Patent Document 3 (Japanese Patent Laid-Open No. 2006-72492). This system control apparatus is a system control apparatus that controls a plurality of devices included in a computer system. A system control apparatus includes a system information acquisition unit that acquires system information including BIOS and system configuration information stored in a device connected under the operating core device bridge, and a system that holds the acquired system information An information holding unit and a switching processing unit for storing system information in a device connected under the substitute bus bridge and switching the operation device bridge to the substitute device bridge when the operation device bridge fails.

  Still another related technique is a dynamic switching device described in Patent Document 4 (Japanese Unexamined Patent Application Publication No. 2009-193469). This dynamic switching device receives a routing table storing information related to a valid bit indicating that routing to an I / O device is valid, and routing path information to the I / O device, and a transaction. When the valid bit is false, the sending of the transaction is suppressed. When the valid bit is true, the transaction is sent to the I / O device according to the routing path information, and the I / O device is switched. When it occurs, the transaction routing controller temporarily suppresses the transmission of the transaction, waits for a predetermined time, updates the valid bit, and resumes the transmission of the transaction.

JP 2008-225534 A Japanese Patent No. 4165423 JP 2006-72492 A JP 2009-193469 A

  In each partition, when switching the core I / O device in use, it is necessary to restart the partition. For this reason, the availability of the information processing apparatus is impaired.

  In the dynamic degeneration apparatus described in Patent Document 1, one I / O device can be degenerated during operation. However, spare core I / O devices must always be running.

  Patent Documents 2 and 3 describe that the core I / O used when a failure occurs is switched by duplicating the core I / O. However, switching requires a restart of the system, and there is no description about switching the core I / O used during system operation.

  Further, Patent Document 4 describes processing when I / O device switching occurs, but describes how to switch core I / O to be used during system operation. Not.

  Accordingly, an object of the present invention is to provide an information processing apparatus and an operation method of an information apparatus that can switch a core I / O device to be used without restarting a partition.

  An information processing apparatus according to the present invention includes a plurality of processor nodes, a plurality of I / O nodes each having a core I / O device, and node control for connecting the plurality of processor nodes and the plurality of I / O nodes. An information processing apparatus including the apparatus. Each of the processor nodes includes a used core I / O space corresponding to the used core I / O device and a reserved core I / O corresponding to the reserved core I / O device in the memory space of each processor node. A map unit that maps a space, a deterrence unit that deters the issuance of a new transaction by the plurality of processor nodes according to a use core I / O change instruction, and the use after the issuance of the new transaction is deterred A copy unit that copies data stored in a copy source register included in the middle core I / O device to a copy destination register included in the spare core I / O device, and the used core after the copy is completed Change routing settings so that transactions for I / O devices are forwarded to the spare core I / O device And routing setting change unit, after the routing configuration is changed to release the suppression of the issuance of the new transaction, and a release portion. The node control device includes a spare core I / O access control circuit. The copy unit reads data stored in a copy source register included in the used core I / O device as copy target data by accessing a copy source address in the used core I / O space, A write transaction indicating that the copy target data is to be stored is issued with an address corresponding to the copy source address in the spare core I / O space as an access destination address. When the reserve core I / O access control circuit acquires the write transaction, the access address of the write transaction is the same as the address assigned to the copy source register in the in-use core I / O device. The address is converted to become an address, and the converted write transaction is notified to the spare core I / O device.

  An operation method of an information processing apparatus according to the present invention includes a plurality of processor nodes, a plurality of I / O nodes each having a core I / O device, and the plurality of processor nodes and the plurality of I / O nodes. The operation method of the information processing apparatus provided with the node control apparatus which performs. In this operation method, each processor node has a memory space in each processor node, a used core I / O space corresponding to the used core I / O device, and a spare corresponding to the spare core I / O device. Mapping the space for core I / O, a step in which each of the processor nodes suppresses the issuance of a new transaction by the plurality of processor nodes according to a use core I / O change instruction, Copying the data stored in the copy source register included in the in-use core I / O device to the copy destination register included in the spare core I / O device after issuance is suppressed; After the node completes the copy, the transaction for the in-use core I / O device And changing routing settings to be transferred to the spare core I / O devices, wherein each processor node, after the routing configuration is changed, and a step of releasing the suppression of the issuance of the new transaction. In the copying step, the processor node accesses the copy source address in the used core I / O space, whereby the data stored in the copy source register included in the used core I / O device is stored. A step of issuing a write transaction indicating that the copy target data is to be stored, with the address corresponding to the copy source address in the spare core I / O space as an access destination address read as copy target data; When the device acquires the write transaction, the access destination address of the write transaction is converted to the same address as the address assigned to the copy source register in the in-use core I / O device, Light tiger after conversion The-transactions and a step of notifying the preliminary core I / O devices.

  According to the present invention, it is possible to provide an information processing apparatus and an operation method of an information apparatus that can change an I / O node to be used without restarting a partition.

1 is a schematic diagram showing an information processing apparatus 1. FIG. It is the schematic which shows a partition. It is a figure which shows an example of a structure of each I / O node. It is a figure which shows an example of a structure of a core I / O device. It is the schematic which shows the function structure of each processor node. It is a conceptual diagram which shows the memory space when it sees from each processor node. It is a conceptual diagram which shows a configuration space. It is a conceptual diagram which shows the transfer format of a flit. It is a figure which shows an example of the format of the address field in the case of accessing a configuration space. It is a figure which shows an example of a structure of a node control apparatus. It is a figure which shows the detail of a port input part. It is a flowchart which shows the operation method of information processing apparatus. It is a flowchart which shows operation | movement of a backup core I / O access control circuit. It is a flowchart which shows operation | movement of a backup core I / O access control circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram illustrating an information processing apparatus 1 according to the present embodiment. As illustrated in FIG. 1, the information processing apparatus 1 includes a plurality (16) of processor nodes 100 to 115, a plurality (8) of I / O nodes 120 to 127, and a plurality (4) of node control devices. 130-133. Each node controller is connected to four processor nodes and two I / O nodes. The four node control devices 130 to 133 are connected to each other at 1: 1. Note that the number of processor nodes and the like is merely an example. That is, the present invention can be applied to a configuration smaller than the information processing apparatus 1 shown in FIG. 1 (for example, a configuration having two processor nodes, one node control device, and two I / O nodes). It is also applicable to a larger scale configuration (for example, a configuration of 64 processor nodes, 32 I / O nodes, and 16 node control devices).

  Although not shown in FIG. 1, each of the processor nodes 100 to 115 includes at least one processor and a main storage device.

  As shown in FIG. 1, each I / O node includes a core I / O device. When a plurality of I / O nodes are included in the same partition, only the core I / O device included in any I / O node is used.

  Each node control device has a function of performing communication control between nodes. Each node control device is provided with a spare core I / O access control circuit 620.

  In the information processing apparatus 1 according to the present embodiment, one or more partitions can be configured by combining an arbitrary processor node and an arbitrary I / O node. In each partition, the OS operates independently. FIG. 2 is a diagram illustrating an example of a plurality of partitions. In the example shown in FIG. 2, the information processing apparatus 1 is divided into a partition 200 and a partition 201. The partition 200 includes processor nodes 100, 101, 104, and 105, and I / O nodes 120 and 122. The partition 201 includes processor nodes 102, 103, 106, 107, 108 to 115, and I / O nodes 121, 123, and 124 to 127.

  Here, in the present embodiment, the core I / O device (used core I / O device) being used is replaced with another core I / O device (spare core I / O device) without restarting the partition. A device has been devised so that it can be switched to. Specifically, when an instruction to switch the core I / O device (used core I / O device change instruction) is given, any of the plurality of processor nodes becomes the used core I / O device. The data stored in the included register (copy source register) is copied to the register (copy destination register) included in the spare core I / O device. At this time, the data is copied so that the address given to the copy source register in the used core I / O device is the same as the address given to the copy destination register in the spare core I / O device.

  Specifically, the used core IO / device and the spare core I / O device are mapped separately in the memory space as viewed from each processor node. That is, in each processor node, the copy source register and the copy destination register are assigned to different addresses. After reading data from the copy source register, each processor node issues a write transaction indicating that the read data is written to the copy destination register. The write transaction is supplied to the node control device. In the node controller, the spare core I / O access control circuit 620 converts the access destination address described in the write transaction so as to be the same as the address given to the copy source register in the used core I / O. . The converted write transaction is notified to the standby core I / O device. As a result, in the spare core I / O device, data is written to a register to which the same address as the copy source register is assigned. That is, the same data is stored at the same address between the used core I / O device and the spare core I / O device. If the used core I / O device and the spare core I / O device are industry standard core I / O devices, the spare core I / O device is accessed with the same address as the access address for the used core I / O device. It becomes possible to switch the core I / O device to be used without restarting.

  Hereinafter, the information processing apparatus 1 according to the present embodiment will be described in detail.

  First, each I / O node will be described.

  FIG. 3 is a diagram illustrating an example of the configuration of each I / O node 120. Each I / O node 120 includes an I / O control device 300, four I / O devices 310 to 313, and a core I / O device 314. The I / O control device 300 is connected to the node control device 130 via the interface 160. Further, the I / O devices 310 to 313 are connected to the I / O control device 300 via interfaces 320 to 323, respectively. Similarly, the core I / O device 314 is connected to the I / O control device 300 via the interface 324. The interfaces 320 to 323 comply with PCI specifications such as PCI-Express. The interface 324 conforms to the use of PCI such as PCI-Express or has a unique protocol.

  FIG. 4 is a diagram illustrating an example of the configuration of the core I / O device 314. The core I / O device 314 includes one control LSI 400, one BMC (Baseboard Management Controller) 410, one Super I / O 411, and one BIOS ROM 412. The control LSI 400 is connected to the I / O control device 300 via the interface 324. The BMC 410, Super I / O 411, and BIOS ROM 412 are connected to the control LSI 400 via interfaces 420 to 422, respectively.

  Although not shown, the control LSI 400 includes a USB control unit, an HDD control unit, a BMC interface control unit, a Super I / O interface control unit, and a BIOS ROM interface control unit. A plurality of control registers are provided.

  Next, each processor node will be described.

  FIG. 5 is a schematic diagram showing a functional configuration of each processor node. As described above, each processor node has at least one processor and a main storage device. An OS is operating on each processor node. Also, as shown in FIG. 5, in each processor node, a core I / O changing unit is realized by system firmware. The core I / O changing unit has a function of switching the core I / O device being used. The core I / O change unit includes a map unit 10, a suppression unit 11, a copy unit 12, a routing setting change unit 13, and a release unit 14.

  The map unit 10 preliminarily (for example, at the time of starting a partition, etc.), an address space (memory space when viewed from the entire partition) as viewed from each processor node (address space corresponding to the used core I / O device). It has a function of mapping a used core I / O space) and an address space (spare core I / O space) corresponding to a spare core I / O device.

  FIG. 6 is a conceptual diagram showing a memory space when viewed from each processor node. As shown in FIG. 6, the memory space includes an IO space of the used core I / O device, an MMIO (Memory Mapped Input Output) space of the used core I / O device, an IO space of the spare core I / O device, The MMIO space of the spare core I / O device is mapped. In this embodiment, the MMIO space of the spare core I / O device has a size of 4 GB and is mapped to addresses 200000000000000 to 2000FFFFFFFF (hexadecimal number). The IO space of the spare core IO has a size of 4 Kbytes, and is mapped to addresses 200200000000 to 2002000000FFF (hexadecimal number). The base address and size of the map destination may be fixedly set or may be set to be changeable.

  The map unit 10 has a function of mapping the configuration space of each I / O node to the memory space. FIG. 7 is a conceptual diagram showing a mapped configuration space. As shown in FIG. 7, a configuration space of a plurality of I / O nodes is continuously mapped in the memory space. Each configuration space is assigned a segment number and a bus number (maximum bus number and minimum bus number). The bus numbers are assigned so that they do not overlap among a plurality of configuration spaces.

  Refer to FIG. 5 again. The suppression unit 11 is a part that suppresses the issuance of a new transaction. The suppression unit 11 is activated when a use core I / O change instruction is given, and suppresses the issuance of a new transaction.

  The copy unit 12 has a function of copying the data stored in the copy source register of the used core I / O device to the copy destination register of the spare core I / O device after the issue of a new transaction is suppressed. Yes. The copy unit 12 accesses the used core I / O device at the address (copy source address) in the in-use core I / O space, and reads the data stored in the copy source register. Then, the copy unit 12 selects an address corresponding to the copy source address from the spare core I / O space, and issues a write transaction for writing the read data using the selected address as the access destination address.

  The routing setting changing unit 13 has a function of changing the routing setting related to the core I / O for the plurality of processor nodes 100 to 115 and the plurality of I / O nodes 120 to 127. The routing setting changing unit 13 changes the routing setting after the copying by the copying unit 12 is completed.

  The canceling unit 14 is a part that cancels transaction issuance suppression for the plurality of processors 101 to 115. The canceling unit 14 cancels the issuance of new transactions after the routing setting changing unit 13 completes the change of the routing setting.

  Here, a transfer format of information in the information processing apparatus 1 according to the present embodiment will be described.

  In the present embodiment, transactions issued at each node are transmitted and received in packet units. A packet is a logical information transfer unit and is defined as one or more flits. The frit has a fixed bit width, and in this embodiment, the bit width is 90 bits. There are two types of flits: header flits and data flits.

  FIG. 8 shows the transfer format of each flit. Bits 89:88 of each frit are strobes, indicating that the frit is valid and the type of frit. When the strobe is 00 (binary number), the flit is invalid. When 01 (binary number), the header flit is indicated. When the strobe is 10 (binary number), the data flit is indicated. . This code definition is an example. A packet is composed of one header flit and zero, one, two, four or eight data flits. Therefore, in the present embodiment, the packet is composed of one flit at the minimum and nine flits at the maximum. An ECC and parity are added to the flit for the purpose of error detection and correction, but the details are omitted because they are not directly related to the present invention. The header flit bits 87: 0 define five 8-bit fields and 48-bit address fields, respectively. These field definitions are examples, and are determined depending on the resource, protocol, and topology of the information processing apparatus.

  The command code is a field in which a code for specifying an operation for the target device is stored. Examples of the designated operation include memory read, memory write, I / O read, I / O write, configuration read, configuration write, reply, and completion.

  The source node ID is a field in which a unique number (referred to as a node ID) for identifying a processor node or an I / O node that is a packet transfer source is stored. The target node ID is a field in which a node ID for identifying a processor node, an I / O node, or a node control device as a packet transfer destination is stored.

  The data length is a field for designating the target data length in bytes when the packet is a read request. In the case of 00 (hexadecimal number) to 40 (hexadecimal number), 0 to 64 bytes are designated. Other values are undefined.

  The address is a field for storing the access destination address of the request.

  Byte enable is defined in bits 71:64 of the data flit, and valid or invalid of each byte defined in bits 63: 0 is designated.

  FIG. 9 is a diagram showing an example of the format of the address field when accessing the configuration space. Bits 47:32 are base addresses when the configuration space is mapped to the memory space. Bits 31:28 are segment numbers when a plurality of configuration spaces are used in one partition. In this embodiment, since the segment number is 4 bits, a maximum of 16 segments can be used. Bits 27: 0 are fields conforming to the PCI specification, and indicate a bus number, a device number, a function number, an extension register number, and a register address, respectively.

  Next, the node control device 130 will be described.

  FIG. 10 is a diagram illustrating an example of the configuration of the node control device 130. In the present embodiment, the node control device 130 includes nine port input units 500 to 508, nine port output units 510 to 518, and a crossbar switch 520. Here, a port is defined by a set of port input unit and port output unit. For example, a port connected to the processor node 100 includes a port input unit 500 and a port output unit 510. Nine ports included in the node control device 130 are connected to the processor nodes 100 to 103, the I / O nodes 120 to 121, and the node control devices 131 to 133, respectively.

  FIG. 11 is a diagram illustrating details of the port input unit 500. The port input units 500 to 503 have the same configuration. As shown in FIG. 11, the port input unit 500 includes a spare core I / O access control circuit 620. The spare core I / O access control circuit 620 includes a register 600, a spare core I / O access detection circuit 601, a spare core I / O access flit generation circuit 602, and a selector 603.

  The register 600 holds values (segment number, maximum bus number, and minimum bus number) assigned to the configuration space of the spare core I / O device in each processor node 100. The register 600 is a 20-bit register. In this embodiment, bits 19:16 hold the segment number, bits 15: 8 hold the maximum bus number, and bits 7: 0 hold the minimum bus number. For example, when the segment number of the configuration space allocated to the spare core I / O device is 3 and the range of the bus number is F0 to F2 (hexadecimal number), the setting value of the register 600 is 3F2F0 (hexadecimal number). Become. The register 600 is set by the system firmware or the BMC firmware when the information processing apparatus 1 is initialized or when a dynamic configuration change is performed during the operation of the information processing apparatus. However, details regarding the setting of the register 600 are well known to those skilled in the art and are not directly related to the present invention, and thus detailed description thereof is omitted.

  The spare core I / O access detection circuit 601 is a circuit that detects whether or not the access destination address of a transaction issued by the processor node 100 is a spare core I / O device. The spare core I / O access detection circuit 601 acquires the flit signal 530 included in the transaction issued by the processor node 100, and determines whether or not the flit signal 530 is a header flit. When the flit signal 530 is a header flit, that is, when the strobe field is 01 (binary number), the spare core I / O access detection circuit 601 sets values of the command code field and address field to predetermined fixed values. And the detection result signal 611 and the address signal 612 are generated based on the comparison result. The detection result signal 611 is a 1-bit signal and becomes 1 when the access destination address is a spare core I / O device. The address signal 612 is a signal indicating a value used in the address field of the header flit sent to the spare core I / O device.

  When the flit signal 530 is a header flit, the spare core I / O access flit generation circuit 602 replaces the address field with a value indicated by the address signal 612 and outputs the converted header flit signal 613.

  The selector 603 selects the flit signal 530 if the detection result signal 611 is 0, and selects the converted header frit signal 613 if the detection result signal 611 is 1, and outputs it to the crossbar switch 520 as the flit signal 540. .

  Subsequently, an operation method of the information processing apparatus 1 according to the present embodiment will be described. In this embodiment, it is assumed that one partition is constituted by all the processor nodes 100 to 115 and the I / O nodes 120 to 127 (see FIG. 1). Here, it is assumed that the core I / O device in use is a core I / O device included in the I / O node 120. When it is desired to disconnect the I / O node 120 while the partition is operating, it is necessary to change the core I / O device to be used before disconnecting. In the present embodiment, an operation when the core I / O device to be used is switched from the core I / O device of the I / O node 120 to the core I / O device of the I / O node 127 will be described.

  FIG. 12 is a flowchart illustrating an operation method of the information processing apparatus according to the present embodiment.

Step S1: Core I / O Device Change Instruction First, the operator instructs the information processing apparatus 1 to change the core I / O device via the BMC (see FIG. 4). Although the user interface between the operator and the BMC is performed by WEBUI or the like, the description is omitted because it is not directly related to the present invention.

Step S2: System Firmware Activation When an instruction to change the core I / O device is issued, the core I / O device is interrupted from one of the plurality of processors 100 to 115 from the BMC firmware operating on the BMC. Change instructions are sent. In this embodiment, it is assumed that a core I / O device change instruction is sent to the processor 100 (see FIG. 1). In the processor 100, system firmware is activated and a core I / O device changing unit is realized.

Step S3: Suppression of Issuance of New Transaction In the processor 100, the suppression unit 11 (see FIG. 5) suppresses the issuance of a new transaction to the other processors 101 to 115 in the partition.

Step S4: Waiting for completion of transaction being executed Further, the suppression unit 11 waits for completion of a transaction being executed in all the processors 100 to 115. The method for suppressing issuance of a new transaction and the method for confirming completion of a transaction being executed depends on the implementation of the processor and is not directly related to the present invention.

Step S5: Copy Next, the copy unit 12 (see FIG. 5) of the processor 100 stores the contents of the register in the core I / O device (used core I / O device) of the I / O node 120 as the I / O node Copy to 127 spare core I / O devices (spare core I / O devices).

Step S6: Routing Setting Change Next, the routing setting changing unit 13 (see FIG. 5) of the processor 100 relates to the core I / O device for the plurality of processor nodes 100 to 115 and the plurality of I / O nodes 120 to 127. Change the routing settings. As a result, the transaction that has been transferred to the used core I / O device in the I / O node 120 is transferred to the backup core I / O device in the I / O node 127.

Step S7: Cancellation of Transaction Issuance Suppression Next, the cancellation unit 14 of the processor 100 cancels transaction issuance suppression for the other processors 101 to 115, and returns the control of the processor 100 to the OS.

  Through the operations in steps S1 to S7, the core I / O device used in the partition is changed from the core I / O device in the I / O node 120 to the core I / O device in the I / O node 127. Is done.

  Next, the operation in step S5 will be described in more detail using a specific example. Registers in each core I / O device are mapped to any one of a memory space, an I / O space, and a configuration space in each core I / O device. Therefore, in this embodiment, specific examples in each case will be described using specific examples 1 to 3. It is assumed that each space is mapped to the memory space when viewed from the processor 100 in the state shown in FIGS.

<Specific example 1>
Specific Example 1 describes a case where the copy source register is a register mapped to a memory space in the core I / O device. It is assumed that the address assigned to the copy source register in the used core I / O device is FED00040 (hexadecimal number), and 4 bytes of data are stored in the copy source register.

  First, in the processor 100, the copy unit 12 issues a memory read transaction to the address FED000040 (hexadecimal number) using the MMIO space (see FIG. 6) of the used core I / O device. The memory read transaction is transferred to the I / O node 120 via the node control device 130. In the I / O node 120, the memory read transaction is transferred to the core I / O device 314 via the I / O control device 300 (see FIG. 3). The used core I / O device 314 reads the data stored in the register (copy source register) mapped to the FED00040 (hexadecimal number) in the memory space. The read data is returned as a reply to the I / O control device 300 and transferred to the processor 100 via the node control device 130.

  In the processor 100, the copy unit 12 issues a write transaction for writing the read data. Here, the copy unit 12 sets an address corresponding to the address of the copy source register, which is an address in the MMIO space (see FIG. 6) of the spare core I / O device, as the access destination address. That is, the copy unit 12 sets an address obtained by adding the base address 200000000000000 of the MMIO space of the spare core I / O device to the address FED00040 of the copy source register allocated in the used core I / O device. . That is, the copy unit 12 issues a write transaction using the address 2000FED00040 (hexadecimal number) as the access destination address. The issued write transaction is transferred to the node control device 130.

  In the node control apparatus 103, the port input unit 500 (see FIG. 11) acquires a write transaction. In the port input unit 500, the backup core I / O access control circuit 620 converts the access destination address of the write transaction. Hereinafter, the operation of the spare core I / O access control circuit 620 will be described in detail. 13A and 13B are flowcharts showing the operation of the backup core I / O access control circuit 620.

Step S11:
In the spare core I / O access control circuit 620, the spare core I / O access detection circuit 601 checks whether the transaction access destination is the memory space of the spare core I / O device. That is, the backup core I / O access detection circuit 601 confirms the header flit of the transaction packet. The spare core I / O access detection circuit 601 checks whether the command field (see FIG. 8) is a command indicating memory space access (memory write). Further, the spare core I / O access detection circuit 601 checks whether bits 47:32 of the address field are 2000 (hexadecimal number). As shown in FIG. 6, when bits 47:32 are 2000 (hexadecimal), the access destination address is the memory space of the spare core I / O device. If the access destination of the transaction is the memory space of the spare core I / O device, the process of the next step S12 is performed. If the transaction access destination is not the memory space of the spare core I / O device, the process of step S14 is performed.

  In this specific example, the command field is a memory space access command (memory write), and bits 47:32 of the address field are 2000 (hexadecimal). Therefore, the backup core I / O access detection circuit 601 determines that the transaction access destination is the memory space of the backup core I / O device, and performs the process of step S12. The operation when the process of step S14 is performed will be described in specific examples 2 and 3.

Step S12:
The spare core I / O access detection circuit 601 replaces the value of the address field with the value assigned to the copy destination register in the used core I / O device, and outputs it as an address signal 612 (see FIG. 11). Specifically, the spare core I / O access detection circuit 601 replaces bits 47:32 of the address field with 0000 (hexadecimal number) and outputs it as an address signal 612. That is, in this specific example, as the address signal 612, a signal indicating 0000FED00040 (hexadecimal number) is output. That is, as the address signal 612, an address obtained by subtracting the base address 200000000000000 (see FIG. 6) of the MMIO space of the spare core I / O device from the access destination address 2000FED00040 (hexadecimal number) is output.

Step S13:
Further, the spare core I / O access detection circuit 601 outputs a value indicating 1 as the detection result signal 611 (see FIG. 11).

  Thereafter, the spare core I / O access flit generation circuit 602 acquires the address signal 612. The spare core I / O access flit generation circuit 602 replaces the address field of the header flit 530 with a value indicated by the address signal 612 and generates a converted header flit signal 613. The converted header flit signal 613 is notified to the selector 603.

  As described above, the selector 603 is configured to select the converted header frit signal 613 when the detection result signal 611 is 1, and to output the frit signal 530 when the detection result signal 611 is 0. Yes. In this specific example, a signal indicating 1 is supplied as the detection result signal 611. Therefore, the selector 603 selects the header frit signal 613 after conversion, and outputs it to the crossbar switch 520 as the flit signal 540. As a result, the access destination address of the write transaction issued by the processor node 100 is changed from 2000 FED00040 (hexadecimal number) to FED00040 (hexadecimal number).

  The converted write transaction is transferred to the I / O node 127 via the node control device 133 (see FIG. 1). In the I / O node 127, the converted write transaction is transferred to the core I / O device 314 via the I / O control device 300. In the core I / O device 314, a 4-byte value is written to a register (copy destination register) mapped to an address FED000040 (hexadecimal number) in the memory space. When the writing is completed, the completion is returned to the I / O control device 300 and is returned to the processor 100 via the node control device 133 and the node control device 130.

  As described above, data is transferred from the register mapped to the memory space address FED000040 (hexadecimal number) in the used core I / O device to the register mapped to the memory space address FED00004 (hexadecimal number) in the spare core I / O device. Is copied.

<Specific example 2>
Next, specific example 2 will be described. In specific example 2, a case where the copy source register is a register mapped to the I / O space in the used core I / O device will be described. The copy source register is mapped to the address 00C0 of the I / O space and holds 1-byte data.

  In the processor 100, the copy unit 12 issues a read transaction at the address 00C0 (hexadecimal number) using the I / O space (see FIG. 6) of the used core IO device. The read transaction is transferred to the I / O node 120 via the node control device 130. In the I / O node 120, a transaction is transferred to the core I / O 314 via the I / O control device 300, and a register value mapped to 00C0 (hexadecimal number) in the I / O space is read. The read value is returned as a reply to the I / O control device 300 and transferred to the processor 100 via the node control device 130.

  Next, the copy unit 12 issues a write transaction for writing the read 1-byte value. Here, the copy unit 12 sets an address corresponding to the address of the copy source register, which is an address in the IO space (see FIG. 6) of the spare core I / O device, as the access destination address. That is, the copy unit 12 sets an address obtained by adding the base address 2000200000000 of the IO space of the spare core I / O device to the address 00C0 of the copy source register allocated in the used core I / O device. . That is, the copy unit 12 issues a write transaction using the address 2002000000000C0 (hexadecimal number) as the access destination address. The write transaction is transferred to the node control device 130 and input to the port input unit 500 of the node control device 130.

  In the port input unit 500, the backup core I / O access control circuit 620 converts the access destination address of the write transaction. In the spare core I / O access control circuit 620, processing is performed according to the flowcharts shown in FIGS. 13A and 13B. That is, the backup core I / O access detection circuit 601 checks whether the transaction access destination is the memory space of the backup core I / O device (step S11). In this specific example, since it is not the memory space of the spare core I / O device for the transaction, the process of step S14 is executed. The processing after step S14 will be described in detail below.

Step S14:
The backup core I / O access detection circuit 601 determines whether the transaction access destination is the I / O space in the backup core I / O. That is, the spare core I / O access detection circuit 601 determines whether or not the command field of the header flit is an I / O space access command. Also, it is confirmed whether or not bits 47:12 of the address field are 200200000 (hexadecimal number). If bits 47:12 are 200200000 (hexadecimal), the access destination is a spare core I / O device (see FIG. 6). When the access destination of the transaction is the I / O space in the standby core I / O device, the process of the next step S15 is executed. If the access destination is not the I / O space in the spare core I / O device, the process of step S16 is executed.

  In this specific example, the command field is an I / O space access command, and bits 47:12 of the address field are 200200000 (hexadecimal). Accordingly, the backup core I / O access detection circuit 601 determines that the transaction access destination is the I / O space of the backup core I / O device, and performs the process of step S15. The operation when the process of step S16 is performed will be described in a specific example 3.

Step S15:
The spare core I / O access detection circuit 601 replaces bits 47:12 of the address field with 000000000000 (hexadecimal number) and outputs it as an address signal 612. That is, a signal indicating 0000000000000C0 is output as the address signal 612. That is, as the address signal 612, an address obtained by subtracting the base address 200200000000 (see FIG. 6) of the IO space of the spare core I / O device from the access address 2002000000000C0 (hexadecimal number) is output.

  Further, the backup core I / O access detection circuit 601 outputs a signal indicating 1 as the detection result signal 611 (step S13). The spare core I / O access flit generation circuit replaces the address field of the header flit with the address signal 612 and outputs it as the header flit signal 613. Since the detection result signal 611 is 1, the selector 603 selects the header flit signal 613 and outputs it to the crossbar switch 520 as the flit signal 540. As a result, the access destination address of the transaction is changed from 2002000000000C0 (hexadecimal number) to 00C0 (hexadecimal number).

  The write transaction output from the node control device 130 is transferred to the I / O node 127 via the node control device 133. Within the I / O node 127, a transaction is transferred to the core I / O 314 via the I / O control device 300, and a 1-byte value is stored in the register mapped to 00C0 (hexadecimal) in the I / O space. Written. When the writing is completed, the completion is returned to the I / O control device 300 and is returned to the processor 100 via the node control device 133 and the node control device 130.

  With the above operation, the register mapped to the address 00C0 (hexadecimal) of the I / O space in the used core I / O device is changed to the register mapped to the address 00C0 of the I / O space in the spare core I / O device. The data is copied.

<Specific example 3>
Next, specific example 3 will be described. Specific Example 3 describes a case where the copy source register is a register mapped to the configuration space (see FIG. 7). The copy source register includes segment number 0 (hexadecimal number), bus number 00 (hexadecimal number), device number 00000 (binary number), function number 000 (binary number), extension register number 0 (hexadecimal number) in the configuration space, Assume that this is a 4-byte register mapped to register address A0 (hexadecimal). Further, the base address of the configuration space is assumed to be 1000. In this case, the address of the copy source register is 1000000000A0. The configuration space allocated to the spare core I / O device is assumed to have a segment number of 3 (hexadecimal number) and a bus number of F0 to F2 (hexadecimal number). That is, it is assumed that 3F2F0 (hexadecimal number) is set in the register 600 (see FIG. 11).

  In the processor 100, the copy unit 12 reads 4-byte data from the configuration space address 1000000000A0 (hexadecimal number). When a configuration read from the processor 100 to the address 1000000000A0 (hexadecimal number) is issued, the transaction is transferred to the I / O node 120 via the node control device 130. Within the I / O node 120, the transaction is transferred to the core I / O device 314 via the I / O control device 300. In the core I / O device 314, the bus number 00 (hexadecimal number), device number 00000 (binary number), function number 000 (binary number), extension register number 0 (hexadecimal number), register address A0 (16) in the configuration space The value of the register mapped to (hexadecimal) is read. The read value is returned as a reply to the I / O control device 300 and transferred to the processor 100 via the node control device 130.

  Next, the copy unit 12 issues a write transaction indicating that the read 4-byte value is to be written in the configuration space address 10003F0000A0 (hexadecimal number). The address indicated by 10003F0000A0 (hexadecimal number) is segment number 3 (hexadecimal number), bus number F0 (hexadecimal number), device number 00000 (binary number), function number 000 (binary number), and extension register number 0 (hexadecimal number). ), Register address A0 (hexadecimal). The write transaction is transferred to the node control device 130 and input to the port input unit 500 of the node control device 130.

  In the port input unit 500, the backup core I / O access control circuit 620 converts the access destination address of the write transaction. In the spare core I / O access control circuit 620, processing is performed according to the flowcharts shown in FIGS. 13A and 13B. That is, the backup core I / O access detection circuit 601 checks whether the transaction access destination is the memory space of the backup core I / O device (step S11). In this specific example, since the access destination is not the memory space of the spare core I / O device of the transaction, the process of step S14 is executed. In step S14, the spare core I / O access detection circuit checks whether the transaction access destination is the I / O space of the spare core I / O device. In this specific example, since the access destination is not the I / O space, the process of step S16 is executed. The processing after step S16 will be described in detail below.

Step S16:
The backup core I / O access detection circuit 601 determines whether or not the transaction targets the configuration space of the backup core I / O device. Specifically, the spare core I / O access detection circuit checks the header flit of the transaction and confirms whether or not the command field is a configuration space access command. The spare core I / O access detection circuit 601 checks whether the segment number and bus number in the address field are included in the range specified by the register 600.

  If the transaction is targeted for the configuration space of the standby core I / O device, the process of the next step S17 is performed. When the transaction does not target the configuration space of the spare core I / O device, the spare core I / O access detection circuit 601 outputs a signal indicating 0 as the address signal 612 (step S18) and detects it. A signal indicating 0 is output as the result signal 611 (step S19).

  In this specific example, the command field is a configuration space access command. The segment number in the address field is 3 (hexadecimal number), which matches bits 19:16 of the register 600. Further, the bus number in the address field is F0 (hexadecimal number), which is 15: 8 or less of the register 600 and 7: 0 or more of the bit. Therefore, the backup core I / O access detection circuit 601 determines that the transaction is targeted for the configuration space of the backup core I / O device, and the process of the next step S17 is performed.

Step S17:
The spare core I / O access detection circuit 601 subtracts the minimum bus number written in the register 600 for the address filled rule bus number, and outputs a signal indicating the value of the address field after the subtraction as the address signal 612. . That is, a signal indicating 1000300000A0 (hexadecimal number) is output as the address signal 612.

  Further, the spare core I / O access detection circuit 601 outputs a signal indicating 1 as the detection result signal 611. The spare core I / O access flit generation circuit 602 replaces the address field of the header flit with the address signal 612 to generate a converted header flit signal 613. Since the detection result signal 611 indicates 1, the selector 603 selects the converted header frit signal 613 and outputs it to the crossbar switch 520 as the flit signal 540. As a result, the address of the transaction is changed from 10003F0000A0 (hexadecimal number) to 1000300000A0 (hexadecimal number).

  The transaction output from the node control device 130 is transferred to the I / O node 127 via the node control device 133. Within the I / O node 127, the transaction is transferred to the core I / O device 314 via the I / O control device 300. In the core I / O device 314, the bus number 00 (hexadecimal number), device number 00000 (binary number), function number 000 (binary number), extension register number 0 (hexadecimal number), register address A0 (configuration number) in the configuration space A 4-byte value is written to a register mapped to (hexadecimal). When the writing is completed, the completion is returned to the I / O control device 300 and is returned to the processor 100 via the node control device 133 and the node control device 130.

  Through the above processing, the configuration space segment number 0 (hexadecimal number), bus number 00 (hexadecimal number), device number 00000 (binary number), function number 000 (binary number), extension register in the core I / O device The register mapped to number 0 (hexadecimal) and register address A0 (hexadecimal) is copied.

  As described above, according to the present embodiment, the address of the copy source register in the used core I / O device and the address of the copy destination register in the spare core I / O device can be made the same. As a result, even when an I / O node including a core I / O device in use is disconnected, the core I / O device to be used is changed to a spare core I / O device without restarting the partition. The availability of the information processing apparatus can be improved.

10: Map unit 11: Suppression unit 12: Copy unit 13: Routing setting change unit 14: Release unit 100-115: Processor node 120-127: I / O node 130-133: Node control device 160: Interface 200-201: Partition 300: I / O control device 310-313: I / O device 314: Core I / O
320 to 324: Interface 400: Control LSI
410: BMC
411: Super I / O
412: BIOS ROM
420 to 422: interface 500 to 508: port input unit 510 to 518: port output unit 520: crossbar switch 530: flit signal 540: flit signal 600: register 601: spare core I / O access detection circuit 602: spare core I / O access flit generation circuit 603: selector 611: detection result signal 612: address signal 613: header flit signal 620: spare core I / O access control circuit

Claims (7)

Multiple processor nodes;
A plurality of I / O nodes each having a core I / O device;
An information processing apparatus comprising: a node control device that connects the plurality of processor nodes and the plurality of I / O nodes;
Each of the processor nodes is
A map for mapping the used core I / O space corresponding to the used core I / O device and the reserved core I / O space corresponding to the reserved core I / O device to the memory space in each processor node And
A deterrence unit for deterring issuance of new transactions by the plurality of processor nodes in response to a use core I / O device change instruction;
A copy that copies data stored in a copy source register included in the in-use core I / O device to a copy destination register included in the spare core I / O device after issuance of the new transaction is suppressed And
A routing setting changing unit for changing a routing setting so that a transaction for the in-use core I / O device is transferred to the spare core I / O device after copying is completed;
A release unit for releasing the suppression of the issuance of the new transaction after the routing setting is changed,
The node control device includes a spare core I / O access control circuit,
The copy unit reads data stored in a copy source register included in the used core I / O device as copy target data by accessing a copy source address in the used core I / O space, Issuing a write transaction indicating that the copy target data is to be stored, with an address corresponding to the copy source address in the spare core I / O space as an access destination address,
When the reserve core I / O access control circuit acquires the write transaction, the access address of the write transaction is the same as the address assigned to the copy source register in the in-use core I / O device. An information processing apparatus that converts an address into an address and notifies the spare core I / O device of the converted write transaction. An information processing apparatus according to claim 1,
The write transaction is issued as a packet,
The packet is
A header frit having an address field indicating an access destination address;
Including a data frit indicating data,
The spare core I / O access control circuit includes:
When the write transaction is acquired, by referring to the address field of the header flit, it is determined whether or not the write transaction is destined for the spare core I / O device, and detection indicating the determination result A spare core I / O access detection circuit for generating a result signal and an address signal indicating the value of the converted address field;
A spare core I / O access flit generation circuit that obtains the address signal, replaces the value of the address field in the header flit with a value indicated by the address signal, and generates a converted header flit;
When the signal indicating that the write transaction is addressed to the spare core I / O device is acquired as the detection result signal, the converted header frit is selected and transmitted to the spare core I / O device. An information processing apparatus comprising a selector. An information processing apparatus according to claim 1 or 2,
The in-use core I / O space and the spare core I / O space each have an IO space and a MMIO (Memory Mapped Input Output) space. An information processing apparatus according to claim 3,
When the copy source register is a register assigned to the I / O space, the spare core I / O access control circuit calculates the spare core I / O from a value indicating an access destination address of the write transaction. An information processing apparatus that sets a value obtained by subtracting a value indicating a base address of an I / O space in a work space as an access destination address of the converted write transaction. An information processing apparatus according to claim 3 or 4, wherein
When the copy source register is a register assigned to the MMI / O space, the spare core I / O access control circuit determines the spare core I / O from a value indicating an access destination address of the write transaction. An information processing apparatus that sets a value obtained by subtracting a value indicating the base address of the MMI / O space in the O space as an access destination address of the converted write transaction. An information processing apparatus according to any one of claims 3 to 5,
The map unit further maps a configuration space to the memory space,
In the configuration space, a maximum bus number and a minimum bus number are assigned to the plurality of core I / O devices so as not to overlap each other.
When the copy source register is a register assigned to the configuration space, the spare core I / O access control circuit uses the value of the bus number part included in the access destination address of the write transaction as the spare core I / O access control circuit. An information processing apparatus that replaces a value obtained by subtracting the value of the minimum bus number assigned to a core I / O device, and sets the replaced access destination address as the access destination address of the converted write transaction. An information processing apparatus comprising: a plurality of processor nodes; a plurality of I / O nodes each having a core I / O device; and a node control device connecting the plurality of processor nodes and the plurality of I / O nodes. A method of operation,
Each of the processor nodes includes a used core I / O space corresponding to the used core I / O device and a reserved core I / O corresponding to the reserved core I / O device in the memory space of each processor node. A step of mapping the space;
Each processor node, in response to a use core I / O device change instruction, suppressing the issuance of new transactions by the plurality of processor nodes;
Copying the data stored in the copy source register included in the in-use core I / O device to the copy destination register included in the spare core I / O device after the issue of the new transaction is suppressed; ,
Each processor node changing a routing setting so that a transaction for the in-use core I / O device is transferred to the spare core I / O device after copying is completed;
Each processor node, after the routing setting is changed, canceling the suppression of the issuance of the new transaction;
Comprising
The copying step includes
The processor node reads the data stored in the copy source register included in the used core I / O device as copy target data by accessing the copy source address in the used core I / O space, Issuing a write transaction indicating that the copy target data is stored, with an address corresponding to the copy source address in the spare core I / O space as an access destination address;
When the node controller acquires the write transaction, the access destination address of the write transaction is the same as the address assigned to the copy source register in the in-use core I / O device. And a step of notifying the spare core I / O device of the converted write transaction.

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