JP2009193469A - Device, method and program for dynamic switching - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a function for dynamically switching a master device to a slave device during a system operation in a configuration where a multifunction PCI device is duplicated. <P>SOLUTION: A transaction routing controller receives a transaction from an FSB interface on a processor side and an I/O interface on an I/O device side, determines a target device for the transaction by referring to a routing table, when the transaction is a memory access transaction, and transmits the transaction to the interface for the target device. At this time, when the device to which the transaction is transmitted is found to be a duplicated I/O device as the result of referring to the routing information, the transaction is transmitted to either one or both of the master device and the slave device, depending on the duplication status of the device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a dynamic switching apparatus, and more particularly to a dynamic switching apparatus for duplexed I / O devices.

  In order to improve the fault tolerance of a system by duplicating an input / output (I / O) controller device (hereinafter referred to as I / O device) represented by a PCI device, an ordinary fault tolerant (FT) is used. In a computer or the like, access to the duplicated I / O device is absorbed by the device driver layer of the software so that it can be seen as a single I / O device from the upper layer operating system (OS) and application. This technique is adopted. The problem with this method is that a complex device driver is required to realize duplication.

  In order to solve this problem, there is a method for realizing duplication of I / O devices in the hardware layer. In this method, a transaction from the processor to the I / O device is copied and routed to both the master device and the slave device, and the transaction from the I / O device to the processor is performed by either the master device or the slave device. A mechanism for routing only from one of the devices is implemented in the chipset. By this method, when a failure occurs in the path from the chipset to the I / O device by mirroring the I / O device, it is possible to dynamically degenerate the path while continuing the operation of the system. .

  However, this method has a limitation that the type of I / O device that can be applied is limited to a static device such as a non-volatile random access memory (NvRAM). The reason for this is that, for example, a device having an internal state such as a real time clock (RTC) or a timer will completely synchronize both devices to the internal state even if a duplicate transaction is sent to both sides. This is because it is difficult to operate. Generally, an external interface (I / F: interface) such as a network card (NIC: Network Interface Card) also adopts a redundant configuration by cold standby.

As a related technique, a routing control method is disclosed in Japanese Patent Application Laid-Open No. 07-123109 (Patent Document 1).
In this related technology, the routing of information related to the active system and information related to the standby system is managed with reference to the routing table.

Japanese Patent Laid-Open No. 10-207815 (Patent Document 2) discloses a dynamic switching device.
In this related technology, the dynamic switching device has a predetermined number of ports corresponding to the number of channel devices and input / output devices, and switches the route for each predetermined number of ports when switching the route accompanying normal data transfer. Destination information stored in the destination storage means when a failure is detected in the interface connected between the channel device and the input / output device. And a failure notification means for transmitting failure notification information to the corresponding counterpart based on the above.

Japanese Patent Application Publication No. 2005-516478 (Patent Document 3) discloses a system that provides a fault tolerant routing database.
In this related art, the system includes a router that exchanges routing table update information in a network environment. In the system, the primary process is involved in communication with a remote process, and this communication includes transfer of data contents and communication status. In the system, the primary process stores the data content and the communication state in the data storage device. If the primary process fails, communication with the remote process is transferred to a backup process that mirrors the primary process by retrieving data content and communication status from the data store. Thus, the backup process continues to communicate with the remote process using the communication state retrieved from the data storage device.

JP 07-123109 A Japanese Patent Laid-Open No. 10-207815 JP 2005-516478 A

  An object of the present invention is to dynamically switch a master device and a slave device of a duplexed I / O device to any one of the master device valid, the slave device valid, and the mirrored state of both devices during system operation. , A dynamic switching method, and a dynamic switching program.

  In the present invention, in the routing table implemented in the memory controller, when duplicating an I / O device, the transaction information to the master device is sent as it is to the master device as it is by the transaction routing controller, and the transaction is copied to the slave device. It also has instruction information to be sent to. By combining these two pieces of instruction information, it is possible to realize any operation of sending a transaction addressed to the master device only to the master device, sending only to the slave device, and sending to both the master device and the slave device. Also, the transaction from the I / O interface in the memory controller to the I / O device is temporarily suppressed under the control of the service processor (SP: Service Processor) 21, and the end of the previous transaction in progress is waited for. Thereafter, the routing information in the routing table is updated, and the operation of the I / O interface is restarted, thereby switching the operation mode of the duplexed I / O device.

  The dynamic switching device of the present invention receives a routing table storing information related to a valid bit indicating that routing to an I / O device is valid, and routing path information to the I / O device, and a transaction, and performs routing. If the valid bit is false with reference to the table, the sending of the transaction is suppressed. If the valid bit is true, the transaction is sent to the I / O device according to the routing path information. When switching occurs, the transaction routing controller temporarily suppresses the transmission of a transaction, waits for a certain period of time, updates the valid bit, and resumes the transmission of the transaction.

  In the dynamic switching method of the present invention, when a transaction is received, information related to a valid bit indicating that routing to the I / O device is valid, and a routing table storing routing path information to the I / O device are referred to. A step of suppressing the sending of a transaction if the valid bit is false, a step of sending a transaction to the I / O device according to the routing path information if the valid bit is true, A step of temporarily stopping the transmission of a transaction when the O device is switched, waiting for a predetermined time, updating a valid bit, and restarting the transmission of the transaction.

  When the dynamic switching program of the present invention receives a transaction, the dynamic switching program refers to a routing table storing information related to a valid bit indicating that routing to the I / O device is valid, and routing path information to the I / O device. A step of suppressing the sending of a transaction if the valid bit is false, a step of sending a transaction to the I / O device according to the routing path information if the valid bit is true, A program for causing a computer to execute the steps of temporarily suppressing the sending of a transaction, waiting for a fixed time, updating a valid bit, and restarting the sending of a transaction when O device switching occurs. .

  I / O device mirroring and cold standby can be realized arbitrarily. In addition, the I / O device can be degenerated or switched dynamically.

Hereinafter, a first embodiment of the present invention will be described with reference to the accompanying drawings.
Referring to FIG. 1, a computer system as an example of the dynamic switching device of the present invention includes a processor (CPU: Central Processing Unit) 11, a processor (CPU) 12, and a front side bus (FSB: Front Side Bus) 13. A memory controller (MEMCTL: Memory Controller) 14, a memory (MEM: Memory) 15, an I / O controller (IOCTL: Input / Output Controller) 16, and an I / O controller (IOCTL) 17.

  In FIG. 1, a processor (CPU) 11 and a processor (CPU) 12 are connected to the same front side bus (FSB) 13 to form a symmetric multiprocessor (SMP) configuration. A memory controller (MEMCTL) 14 is connected to the front side bus (FSB) 13. Here, the memory controller (MEMCTL) 14 manages the routing of transactions among the CPU, memory, and I / O device.

  Further, a memory (MEM) 15, an I / O controller (IOCTL) 16, and an I / O controller (IOCTL) 17 are connected to the memory controller (MEMCTL) 14. An I / O controller (IOCTL) 16 and an I / O controller (IOCTL) 17 are connected to a PCI bus (PCI-Bus) 18 or a PCI bus (PCI-Bus) 19 on the opposite side of the transaction from the memory controller (MEMCTL) 14. A bus bridge to be connected. An I / O device (Master Device) 30 is connected to the PCI bus (PCI-Bus) 18. An I / O device (Slave Device) 40 is connected to the PCI bus (PCI-Bus) 19.

  In the present embodiment, the I / O device (Master Device) 30 is assumed to be a multifunction I / O device equipped with a nonvolatile memory (NvRAM), a real-time clock (RTC) external I / O interface, etc. In FIG. 1, functions 31 to 33 are indicated. The I / O device (Slave Device) 40 is also an I / O device having the same configuration as the I / O device (Master Device) 30.

  Further, the computer system of this embodiment is equipped with a service processor (SP: Service Processor) 21 that controls the operation of the system, and initializes and modes each element in the system including the memory controller (MEMCTL) 14. Control such as setting and resetting can be performed. Note that FIG. 1 does not show communication paths that are not directly related to the description of the present embodiment. However, in practice, there may be communication paths that are not directly related.

  In the present embodiment, the number of processors and memories connected to the computer system is not directly related to the requirements of the present invention, and it is apparent that the present invention can be implemented in any configuration. Similarly, the number of I / O controllers and the number of PCI buses connected to the I / O controller are not related to the present invention. In addition to the PCI bus, any I / O bus can be used in addition to the PCI-X bus and the PCI Express bus. Further, the function / configuration of the I / O device is not limited to the function / configuration of the present embodiment.

Next, referring to FIG. 2, a logic block diagram of the memory controller (MEMCTL) 14 is shown.
The memory controller (MEMCTL) 14 includes an FSB interface (FBS I / F) 141, a routing table 142, a transaction routing controller (Txn Routing CTL) 143, a memory interface (MEM I / F) 144, An I / O interface (I / O I / F) 145, an I / O interface (I / O I / F) 146, and an SP interface (SP I / F) 147 are provided.

  In FIG. 2, the connection interface between the memory controller (MEMCTL) 14 and each element in the computer system includes an FSB interface (FBS I / F) 141, a memory interface (MEM I / F) 144, and an I / O interface (I / O I / F) 145 and I / O interface (I / O I / F) 146.

  The FSB interface (FBS I / F) 141 is a connection interface with the front side bus (FSB) 13. The memory interface (MEM I / F) 144 is a connection interface with the memory (MEM) 15. The I / O interface (I / O I / F) 145 is a connection interface with the I / O controller (IOCTL) 16. The I / O interface (I / O I / F) 146 is a connection interface with the I / O controller (IOCTL) 17.

  A block indicated as an SP interface (SP I / F) 147 is an interface block that provides a communication path between software operating on the CPU and the SP. Here, the SP interface (SP I / F) 147 provides a communication path between the software operating on the processor (CPU) 11 and the processor (CPU) 12 and the service processor (SP) 21.

  A transaction routing controller (Txn Routing CTL) 143 exists at a position connecting each interface block, and various types of memory read (memory read), reply (response), memory write (memory write), interrupt, etc. input from each interface block. Route the transaction and output it to the appropriate interface block. Examples of information included in these various transactions include a memory access target address, reply data, a reply or interrupt source device ID, a target device ID, and the like. Further, the transaction routing controller (Txn Routing CTL) 143 refers to the routing table 142 to determine a routing route.

Next, the format of the routing information stored in the routing table 142 will be described with reference to FIG.
The routing table 142 is a table having a plurality of records including a series of information as illustrated, and registers one record for each function of the I / O device. The computer system according to the present embodiment maps registers and memory devices on the I / O device in addition to the memory (MEM) 15 as memory mapped I / O (MMIO: Memory Mapped I / O) on the physical storage space. Since the configuration is adopted, the information stored in one record of the table is routing path information to any device mapped on the physical storage space.

  Looking at the individual fields in one record of the routing table 142, the record of the routing table 142 has a Vm bit (Vm) 51, a master device ID (Master DID) 52, and a Vs bit (Vs). ) 53, a slave device ID (Slave DID) 54, an address offset (Addr. Offset) 55, and an address range (Addr. Range) 56.

  A Vm bit (Vm) 51 indicates a valid bit indicating that routing to a duplicated master I / O device is valid. A master device ID (Master DID) 52 indicates routing path information to the master I / O device mapped on the physical storage space. The Vs bit (Vs) 53 indicates a valid bit indicating that routing to the slave I / O device is valid. A slave device ID (Slave DID) 54 indicates routing path information to the slave I / O device mapped on the physical storage space. An address offset (Addr. Offset) 55 is used to map each function (Function) from the start address of the entire memory area when mapping each function (Function) of the I / O device to a continuous memory area for each I / O device. ) Is used as an offset to the area. The address range (Addr. Range) 56 indicates the size of the area of each function (Function).

Next, the operation of the memory controller (MEMCTL) 14 in FIG. 2 will be described.
First, an initial setting method when starting up the system will be described.

  In the configuration set in FIG. 1 as the system configuration of the present embodiment, the I / O device (Master Device) 30 is operated as a master device of the duplexed I / O device, and the I / O device (Slave Device) 40 is the slave device. Must be set to operate as This setting is realized by setting information as shown in FIG. 4 from the service processor (SP) 21 to the routing table (routing table) 142 at the time of starting the system.

The table in FIG. 4 is an example of a table format (data format) of the routing table 142.
The setting contents in the table of FIG. 4 will be described in detail. With respect to the setting items for the I / O device (Master Device) 30, three records are defined above the table of FIG. In this embodiment, the I / O device (Master Device) 30 is a multi-function I / O card equipped with three types of functions, and the address of the MMIO space corresponding to each function (Function) is 1 Define each record. Here, individual function names are described as a, b, and c, respectively.

  In this embodiment, as shown in FIG. 1, the I / O device (Master Device) 30 includes a function (Function) a: 31, a function (Function) b: 32, and a function (Function) c: 33. including. Further, the I / O device (Slave Device) 40 includes a function (function) a ': 41, a function (Function) b': 42, and a function (Function) c ': 43.

  In the present embodiment, if the mirroring is set for the function a among the three types of functions a, b, and c, the function of the I / O device (Master Device) 30 is set. (Function) a: The Vm bit (Vm) 51 and the Vs bit (Vs) 53 for 31 are both set to true (T: True). At this time, in the record corresponding to the I / O device (Slave Device) 40, the Vm bit (Vm) 51 and the Vs bit (Vs) 53 are both set to false (F: False). This prevents the CPU from accessing the I / O device (Slave Device) 40 directly.

  A function (Function) b: 32 is an example of setting a cold standby. Here, the Vm bit (Vm) 51 of the I / O device (Master Device) 30 is expressed as true (T), and the Vs bit (Vs) 53 is expressed as false (F). The Vm bit (Vm) 51 and the Vs bit (Vs) 53 of the record corresponding to the I / O device (Slave Device) 40 are both set to false (F) as in the case of the function a: 31. Yes.

  Furthermore, since the function (Function) c: 33 operates the function (Function) of the I / O device (Master Device) 30 and the I / O device (Slave Device) 40 separately, the Vm bit ( Vm) 51 is set to true (T), and Vs bit (Vs) 53 is set to false (F).

  As a result of such setting, the MMIO space of each device and function mapped on the physical storage space has a layout as shown in FIG. The functions (Functions) a, b, and c of the I / O device (Master Device) 30 are individually mapped on the physical storage space, and the function (Function) a of the I / O device (Slave Device) 40 ', B' is mapped to the same address as the functions a, b of the I / O device (Master Device) 30, and it can be seen from the software as a single device.

Next, the operation of the memory controller (MEMCTL) 14 during system operation will be described.
With reference to FIG. 6, an operation for a memory access transaction from the processor will be described.
(1) Step S101
The transaction routing controller (Txn Routing CTL) 143 performs memory access transactions such as memory read and memory write from the processor (CPU) 11 and the processor (CPU) 12 via the FSB interface (FBS I / F) 141. receive.
(2) Step S102
The transaction routing controller (Txn Routing CTL) 143 refers to the routing table (Routing Table) 142 and searches for routing information corresponding to the address range specified by the transaction.
(3) Step S103
When a corresponding routing information record is found, the transaction routing controller (Txn Routing CTL) 143 refers to the Vm bit (Vm) 51. If the Vm bit (Vm) 51 is true (T), the record is recorded. A master device ID (Master DID) 52 is taken out from the memory interface, and a memory interface (MEM I / F) 144, an I / O interface (I / O I / F) 145, and an I / O are followed in accordance with a routing path to the target device of the transaction. A transaction is sent to one of the O interfaces (I / O I / F) 146.
(4) Step S104
Further, the transaction routing controller (Txn Routing CTL) 143 refers to the Vs bit (Vs) 53 and extracts the slave device ID (Slave DID) 54 when the Vs bit (Vs) 53 is true (T). The memory interface (MEM I / F) 144, the I / O interface (I / O I / F) 145, and the I / O interface (I / O I / F) 146 are in accordance with the routing path to the target device. Send the transaction to either.

With reference to FIG. 7, an operation for a memory access transaction from the I / O controller will be described.
(1) Step S201
The transaction routing controller (Txn Routing CTL) 143 is transferred from the I / O controller (IOCTL) 16 or the I / O controller (IOCTL) 17 to the I / O interface (I / O I / F) 145 or the I / O interface (I / O I / F) 146 receives a memory access transaction such as memory read or memory write.
(2) Step S202
The transaction routing controller (Txn Routing CTL) 143 refers to the routing table (routing table) 142 and searches for routing information corresponding to the address range specified in the transaction, as in the previous case (FIG. 6). .
(3) Step S203
When the corresponding routing information record is found, the transaction routing controller (Txn Routing CTL) 143 first refers to the Vm bit (Vm) 51, and if the Vm bit (Vm) 51 is true (T), A master device ID (Master DID) 52 is taken out from the memory device, and a memory interface (MEM I / F) 144, an I / O interface (I / O I / F) 145, A transaction is sent to one of the / O interfaces (I / O I / F) 146.
(4) Step S204
Further, the transaction routing controller (Txn Routing CTL) 143 searches the Vs bit (Vs) 53, and if the Vs bit (Vs) 53 is true (T), extracts the slave device ID (Slave DID) 54. The memory interface (MEM I / F) 144, the I / O interface (I / O I / F) 145, and the I / O interface (I / O I / F) 146 are in accordance with the routing path to the target device. Send the transaction to either.

With reference to FIG. 8, operations for reply and interrupt for a transaction will be described.
(1) Step S301
The transaction routing controller (Txn Routing CTL) 143 receives a reply to a transaction such as a memory read or an interrupt from any interface block. That is, the transaction routing controller (Txn Routing CTL) 143 includes an FSB interface (FBS I / F) 141, a memory interface (MEM I / F) 144, an I / O interface (I / O I / F) 145, and an I / O. From any interface block of the interface (I / O I / F) 146, a reply to a transaction such as a memory read or an interrupt is received.
(2) Step S302
The transaction routing controller (Txn Routing CTL) 143 refers to the routing table 142 and searches for a record that matches the condition for specifying the transaction transmission source. Here, the transaction routing controller (Txn Routing CTL) 143 refers to the routing table 142, and Vm is true (T) and the master device ID (Master DID) 52 matches the device ID of the transaction sending source. Alternatively, a record in which Vm is false (F), Vs is true (T), and the slave device ID (Slave DID) 54 matches the device ID of the transaction transmission source is searched.
(3) Step S303
The transaction routing controller (Txn Routing CTL) 143 determines whether the transaction transmission source device is a master device of the duplexed I / O devices when there is a record that matches the condition for specifying the transaction transmission source. It is determined that the slave device is an active slave device in the cold standby state.
(4) Step S304
The transaction routing controller (Txn Routing CTL) 143 determines a routing path according to the target device ID of the transaction, and sends the transaction to an appropriate interface block. That is, the transaction routing controller (Txn Routing CTL) 143 includes an FSB interface (FBS I / F) 141, a memory interface (MEM I / F) 144, an I / O interface (I / O I / F) 145, and an I / O. The transaction is sent to one of the interfaces (I / O I / F) 146.
(5) Step S305
The transaction routing controller (Txn Routing CTL) 143 does not perform routing when a record that matches a condition for specifying a transaction transmission source is not found, for example, when a transaction from a mirroring slave device is received. Discard the transaction.

Next, a procedure for initializing a duplexed I / O device at the time of system startup and setting the cold standby state will be described with reference to FIG.
(1) Step S401
First, at the start of system startup, as an initial setting, when the service processor (SP) 21 registers the routing information of the I / O device in the routing table 142, the function (Function) of the target I / O device is registered. ) Is set for the above-described mirroring. In a series of sequences in which the operating system is activated, initial setting of the I / O device is performed by a device driver (not shown) of the operating system. At this time, since the duplexed I / O device is mirrored, the same initial setting is performed for both the master and the slave. Here, the service processor (SP) 21 performs the same initial setting for both the I / O device (Master Device) 30 and the I / O device (Slave Device) 40.
(2) Step S402
When the initial setting is completed, the device driver notifies the service processor (SP) 21 of an instruction to disconnect the slave I / O device and operate in parallel in the cold standby state. As a more specific example, this notification is performed by mapping the communication register of the service processor (SP) 21 to the MMIO as in the case of the I / O device, and from the transaction routing controller (Txn Routing CTL) 143 of FIG. Implementation that notifies the service processor (SP) 21 via (I / F) 147 is conceivable.
(3) Step S403
Upon receiving the notification, the service processor (SP) 21 dynamically disconnects the slave device of the I / O device and shifts to the cold standby. Here, the service processor (SP) 21 dynamically disconnects the I / O device (Slave Device) 40 and shifts to a cold standby.

With reference to FIG. 10, the operation procedure for setting the cold standby state will be described.
The following procedure is realized by controlling the operation of each element in the system including the transaction routing controller (Txn Routing CTL) 143 from the service processor (SP) 21. The control procedure is the service processor (SP) 21. It is implemented as an internal program.
(1) Step S501
First, the service processor (SP) 21 inhibits transaction transmission from each I / O interface in the memory controller (MEMCTL) 14 to the I / O controller. As a result, the inhibited transaction temporarily stays in a buffer or the like (not shown) existing in the transaction routing controller (Txn Routing CTL) 143. Depending on the mounting method, the transaction for suppressing transmission from the I / O interface may be limited to only those directed to the duplexed I / O device. In this case, the service processor (SP) 21 refers to the target device ID of the transaction and determines whether to send or inhibit the transaction. At this time, the service processor (SP) 21 does not suppress the transaction transmission from the I / O controller to the I / O interface, and continues the operation for the transaction transmission from the I / O device.
(2) Step S502
The service processor (SP) 21 waits for a certain time in this state. This completes the reply process for the in-process transaction that has been sent from each processor, memory, and other I / O device via the I / O interface. It is necessary to define an appropriate value for the waiting time depending on the implementation of the computer system. That is, the service processor (SP) 21 waits until all reply processing for the current transaction is completed.
(3) Step S503
After the preceding transaction for the I / O device is completed, the service processor (SP) 21 updates the record in the routing table 142. Specifically, the Vs bit (Vs) 53 described in the record in which the target mirrored device is defined is rewritten to false (F).
(4) Step S504
Subsequently, the service processor (SP) 21 resumes the transaction transmission from the I / O interface to the I / O controller. As a result, the transaction staying in the transaction routing controller (Txn Routing CTL) 143 is routed only to the master device and sent from the I / O interface according to the updated routing information.

  This completes the operation for setting the I / O device in the cold standby state. At this time, the state of the slave device may be held in a state in which the initial setting by the device driver at the time of starting the operating system is completed. Recognize.

Next, a procedure for switching a slave device in a cold standby state to operate as a new master device will be described with reference to FIG.
(1) Step S601
When it becomes necessary to switch between the master device and the slave device for some reason, such as the occurrence of a failure, the service processor (SP) 21 receives each I / O as in the case of the transition from the mirroring to the cold standby described above. Transaction transmission from the interface to the I / O controller is temporarily suppressed.
(2) Step S602
The service processor (SP) 21 waits for a fixed time.
(3) Step S603
The service processor (SP) 21 updates the Vm bit (Vm) 51 of the record corresponding to the device in the routing table (routing table) 142 to false (F), and sets the Vs bit (Vs) 53 to true (T). Update to That is, the service processor (SP) 21 switches the slave device in the cold standby state to become a new master device.
(4) Step S604
The service processor (SP) 21 resumes the transaction transmission from the I / O interface. At this time, the service processor (SP) 21 sends a transaction to the new master device.

  As a result, the transaction staying in the transaction routing controller (Txn Routing CTL) 143 is sent to the new master device according to the updated routing information. At this time, since the state of the original master device and the new master device (original slave device) is generally not the same, it should be noted that continuity of operation as viewed from the operating system and application software is not guaranteed before and after switching. There is. For this reason, it is considered that devices such as device drivers and application software require contrivances such as retrying input / output to the I / O device.

  Further, instead of the service processor (SP) 21 starting switching of the I / O device when a hardware failure is detected, the device driver that detects the abnormality of the I / O device is the SP interface (SP I / F). A method of instructing the service processor (SP) 21 to switch the I / O device through 147 can also be considered. In this case, since it is possible to appropriately select the I / O device switching timing by the device driver, it is considered that the above-described problem of continuity of operation before and after switching can be easily handled.

  Finally, a procedure for dynamically degenerating one of the I / O devices in the mirroring state will be described. Needless to say, according to the configuration of the embodiment of the present invention, the duplexed I / O device can be operated while being mirrored even after the initial setting by the device driver at the time of starting the operating system.

  As in the above example, when it becomes necessary to degenerate one of the mirrored I / O devices due to a failure or the like, the service processor (SP) 21 shifts from the above-described mirroring to cold standby. Similarly to the time, the transaction transmission from each I / O interface to the I / O controller is temporarily suppressed, the waiting for a certain time is performed, and the Vm of the record corresponding to the device in the routing table 142 is displayed. The bit or Vs bit, whichever corresponds to the device to be degenerated, is updated to false (F).

  Here, before restarting the transaction transmission from the I / O interface, the service processor (SP) 21 stops the operation of the degenerated I / O device. The method for stopping the I / O device is beyond the scope of the present invention and will not be described in detail. However, if it is a PCI device, depending on the function of the device, the device configuration register is operated to stop the device operation. A method of resetting the PCI bus by operating the bus bridge if there is a bus bridge to which the device is connected, a method of masking from receiving a transaction from the device depending on the function of the I / O interface Etc. are considered. If the device is a passive device such as a memory device, it may be left as it is without doing anything. In any case, the I / O device that is degenerated by these operations is logically disconnected so that its operation does not affect the system.

  When the operations so far are completed, the service processor (SP) 21 resumes the transaction transmission from the I / O interface, and the transaction staying in the transaction routing controller (Txn Routing CTL) 143 is updated to the updated routing. According to the information, it is sent to the remaining I / O device.

  As described above, the present invention provides transaction routing information to the master device and slave device provided in the routing table implemented in the memory controller, a control program implemented in the service processor, a device driver operating on the CPU, During operation of the system in a configuration in which I / O devices duplicated in a computer system by software such as BIOS (Basic Input / Output System) are duplicated, especially a multifunction PCI device having a plurality of functions in one device. It is characterized by the dynamic switching function from the master device to the slave device.

  In FIG. 2, a routing table 142 stores information in the format shown in FIG. The information stored in the routing table 142 is a table having a plurality of records storing transaction routing information for each range of the physical main storage space. Each record has Vm bits (Vm) 51. A master device ID (Master DID) 52, a Vs bit (Vs) 53, a slave device ID (Slave DID) 54, an address offset (Addr. Offset) 55, and an address range (Addr. Range) 56.

  The Vm bit (Vm) 51 indicates a valid bit indicating that the routing to the duplicated master device is valid for the memory access from the processor and the I / O device. A master device ID (Master DID) 52 indicates routing path information to the master device mapped to the address on the physical storage space. The Vs bit (Vs) 53 indicates a valid bit indicating that routing to the slave device is valid. The slave device ID (Slave DID) 54 indicates routing path information to the slave device mapped to the address on the physical storage space. An address offset (Addr. Offset) 55 indicates an address offset at which the transaction is to be routed. An address range (Addr. Range) 56 indicates an address range corresponding to the address offset.

  In FIG. 2, a transaction routing controller (Txn Routing CTL) 143 includes an FSB interface (FBS I / F) 141 on the processor side, an I / O interface (I / O I / F) 145 on the I / O device side, When a transaction from the O interface (I / O I / F) 146 is received and the transaction is a memory access transaction, the target device of the transaction is determined by referring to the routing table 142 and the target Send the transaction to the interface for the device. At this time, when the destination device of the transaction is a duplexed I / O device as a result of referring to the routing information, depending on the duplexed state of the device, the transaction of the transaction to one or both of the master device and the slave device is performed. Send it out. Duplex status is any of “only the master device is functioning effectively”, “only the slave device is functioning effectively”, or “both devices are functioning effectively and mirrored” It is.

  Further, the transaction routing controller (Txn Routing CTL) 143 includes an FSB interface (FBS I / F) 141, an I / O interface (I / O I / F) 145, and an I / O interface (I / O I / F) 146. Alternatively, when a reply transaction for a memory access is received from the memory interface (MEM I / F) 144, the routing information is referred to. The transaction routing controller (Txn Routing CTL) 143 is an I / O device in which the device that sent the reply transaction with reference to the routing information is duplicated, and either the master device or the slave device depending on the duplication status of the device If only the function is valid, routing is performed to the target device indicated by the reply transaction. At this time, if the transaction routing controller (Txn Routing CTL) 143 is in the mirrored state, the transaction routing from the master device is performed and the transaction from the slave device is discarded.

  In this way, in the present invention, memory access to the duplexed I / O device is performed by the transaction routing controller (Txn Routing CTL) 143 according to the duplexed state of the I / O device. Since the data is sent to both I / O devices, the software device driver can achieve memory access to both the master and slave devices with a single memory access to the master device.

  Next, in FIG. 2, a service processor (SP) 21 (not shown; described in FIG. 1) controls each functional block in the memory controller (MEMCTL) 14 during system operation, and performs transactions to the I / O interface. The transmission is temporarily stopped, the routing information in the routing table is updated, the duplexing state of the duplexed I / O device is changed, and the operation of the I / O interface is resumed.

  In this way, according to the present invention, the master device and slave device of the duplexed I / O device can be switched to any of the master device valid, the slave device valid, and the mirrored state of both devices during system operation.

In addition, in this invention, there exists an effect as described below.
The first effect is that the Vm bit, master device ID, Vs bit, and slave device ID are added to the routing information stored in the routing table, and the transaction routing controller refers to the routing information to determine the I / O of the transaction destination. By providing a mechanism capable of sending a transaction to a duplicated master device and / or a slave device when the O device is duplicated, I / O device mirroring and cold standby can be realized arbitrarily. .

  The second effect is that the mapping of the MMIO space defined by the routing information stored in the routing table can be defined for each function of the I / O device, so that there are multiple I / O devices to be duplicated. In the case of a multi-function device having a function, it is possible to determine whether to operate in either mirroring or cold standby by selecting an appropriate duplexing method for each function (Function) or to operate as an individual device.

  The third effect is to control the operation of each functional block in the memory controller from the service processor, stop the transaction to the temporary I / O device, degenerate or switch the I / O device, change the routing route of the transaction, By resuming transaction routing, I / O devices can be degenerated or switched dynamically.

  Here, the master device and slave device of the duplexed I / O device are described as an example, but actually, the device is not limited to the duplexed I / O device. For example, a case where there are a plurality of slave devices is also conceivable. That is, the present invention can be applied not only to duplex but also to multiplexed I / O devices.

FIG. 1 is a block diagram showing a configuration example of a dynamic switching device according to the present invention. FIG. 2 is a logic block diagram of the memory controller (MEMCTL). FIG. 3 is a diagram showing a format of routing information. FIG. 4 is a diagram illustrating an example of a table format (data format) of a routing table (routing table). FIG. 5 is a diagram illustrating an example of the layout of the MMIO space. FIG. 6 is a flowchart showing an operation for a memory access transaction from the processor. FIG. 7 is a flowchart showing an operation for a memory access transaction from the I / O controller. FIG. 8 is a flowchart showing an operation for a reply or interrupt for a transaction. FIG. 9 is a flowchart showing a procedure for initializing a duplexed I / O device at the time of system startup and setting it to a cold standby state. FIG. 10 is a flowchart showing an operation procedure for setting a cold standby state. FIG. 11 is a flowchart showing a procedure for switching a slave device in a cold standby state to operate as a new master device.

Explanation of symbols

11 ... Processor (CPU: Central Processing Unit)
12 ... Processor (CPU)
13 ... Front Side Bus (FSB: Front Side Bus)
14 ... Memory controller (MEMCTL: Memory Controller)
141 ... FSB interface (FBS I / F)
142 ... Routing Table
143 ... Transaction routing controller (Txn Routing CTL)
144 ... Memory interface (MEM I / F)
145 ... I / O interface (I / O I / F)
146 ... I / O interface (I / O I / F)
147 ... SP interface (SP I / F)
15 ... Memory (MEM: Memory)
16 ... I / O controller (IOCTL: Input / Output Controller)
17 ... I / O controller (IOCTL)
18 ... PCI bus (PCI-Bus)
19 ... PCI bus (PCI-Bus)
21 ... Service processor (SP: Service Processor)
30 ... I / O device (Master Device)
31 ... Function a
32 ... Function b
33 ... Function c
40 ... I / O device (Slave Device)
41 ... Function (a)
42 ... Function b '
43 ... Function c '
51 ... Vm bit (Vm)
52 ... Master Device ID (Master DID)
53 ... Vs bit (Vs)
54 ... Slave device ID (Slave DID)
55 ... Address offset (Addr. Offset)
56 ... Address range (Addr. Range)

Claims (18)

A routing table storing information about valid bits indicating that routing to the I / O device is valid, and routing path information to the I / O device;
A transaction is received, the routing table is referenced, and if the valid bit is false, the sending of the transaction is suppressed, and if the valid bit is true, the I / O device is sent according to the routing path information. When the I / O device is switched, the transaction is temporarily prevented from being transmitted, the transaction is waited for a certain time, the valid bit is updated, and the transaction is resumed. And a transaction switching controller. The dynamic switching device according to claim 1,
The routing table further stores information on an address range indicating the size of the function (Function) area of the I / O device in association with the valid bit and the routing route information.
The transaction routing controller receives the transaction, refers to the routing table, and if the valid bit is true and the address range is specified in the transaction, the transaction routing controller follows the routing route information corresponding to the address range. A dynamic switching device that sends the transaction to the I / O device. The dynamic switching device according to claim 1 or 2,
The transaction routing controller receives a reply (response) or interrupt to the transaction, refers to the routing table, the valid bit is true, and the I / O device in the routing path information is the source of the transaction If there is, a dynamic switching device that sends the transaction to an appropriate destination according to the routing route information. The dynamic switching device according to any one of claims 1 to 3,
The routing table is
A Vm bit which is a valid bit indicating that routing to the master device is valid among the I / O devices;
A dynamic switching device including a Vs bit which is a valid bit indicating that routing to a slave device is valid among the I / O devices. The dynamic switching device according to claim 4,
The transaction routing controller sends the transaction to both the master device and the slave device when both the Vm bit and the Vs bit are true. The dynamic switching device according to claim 4 or 5,
The transaction routing controller sends the transaction to the slave device when the Vm bit is false and the Vs bit is true. Receiving a transaction, referring to a routing table storing information about valid bits indicating that routing to the I / O device is valid, and routing path information to the I / O device;
If the valid bit is false, inhibiting sending the transaction;
Sending the transaction to the I / O device according to the routing path information if the valid bit is true;
A step of temporarily stopping the transmission of the transaction when the I / O device is switched, waiting for a predetermined time, updating the valid bit, and restarting the transmission of the transaction. Switching method. The dynamic switching method according to claim 7,
Associating information on an address range indicating a size of a function (Function) area of the I / O device with the effective bit and the routing route information in the routing table;
When the transaction is received, the I / O is referenced according to the routing route information corresponding to the address range when the valid bit is true and the address range is specified in the transaction by referring to the routing table. Sending the transaction to a device. A dynamic switching method. The dynamic switching method according to claim 7 or 8,
Upon receipt of a reply or response to the transaction, referencing the routing table;
When the valid bit is true and the I / O device is the source of the transaction in the routing path information, sending the transaction to an appropriate destination according to the routing path information; Further including a dynamic switching method. A dynamic switching method according to any one of claims 7 to 9,
The routing table is
A Vm bit which is a valid bit indicating that routing to the master device is valid among the I / O devices;
A dynamic switching method including a Vs bit that is a valid bit indicating that routing to a slave device is valid among the I / O devices. The dynamic switching method according to claim 10,
The method of dynamic switching further comprising the step of sending the transaction to both the master device and the slave device if both the Vm bit and the Vs bit are true. The dynamic switching method according to claim 10 or 11,
The method of dynamic switching further comprising the step of sending the transaction to the slave device if the Vm bit is false and the Vs bit is true. Receiving a transaction, referring to a routing table storing information about valid bits indicating that routing to the I / O device is valid, and routing path information to the I / O device;
If the valid bit is false, inhibiting sending the transaction;
Sending the transaction to the I / O device according to the routing path information if the valid bit is true;
When switching of the I / O device occurs, the computer temporarily stops sending the transaction, waits for a predetermined time, updates the valid bit, and resumes sending the transaction. Dynamic switching program for The dynamic switching program according to claim 13,
Associating information on an address range indicating a size of a function (Function) area of the I / O device with the effective bit and the routing route information in the routing table;
When the transaction is received, the I / O is referenced according to the routing route information corresponding to the address range when the valid bit is true and the address range is specified in the transaction by referring to the routing table. A dynamic switching program for causing a computer to further execute the step of sending the transaction to a device. The dynamic switching program according to claim 13 or 14,
Upon receipt of a reply or response to the transaction, referencing the routing table;
When the valid bit is true and the I / O device is the source of the transaction in the routing path information, sending the transaction to an appropriate destination according to the routing path information; Furthermore, a dynamic switching program for causing a computer to execute. A dynamic switching program according to any one of claims 13 to 15,
The routing table is
A Vm bit which is a valid bit indicating that routing to the master device is valid among the I / O devices;
A dynamic switching program including a Vs bit which is a valid bit indicating that routing to a slave device is valid among the I / O devices. The dynamic switching program according to claim 16, wherein
A dynamic switching program for causing a computer to further execute a step of sending the transaction to both the master device and the slave device when both the Vm bit and the Vs bit are true. The dynamic switching program according to claim 16 or 17,
A dynamic switching program for causing a computer to further execute a step of sending the transaction to the slave device when the Vm bit is false and the Vs bit is true.

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