JP2012165209A - Flip-flop device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that when noise enters, with data, a conventional flip-flop device, which has an input terminal 2 receiving a clock C and an input terminal 3 receiving data D and acquires data in synchronized with a rising edge or a falling edge of the clock, the flip-flop device misidentifies the noise as true data to malfunction.SOLUTION: A flip-flop device 1 is constituted from a first edge-data acquisition circuit 110 acquiring data at a first edge of a clock; a second edge-data acquisition circuit 111 acquiring the data at a second edge of the clock; a temporary holding circuit 112 temporary holding the output from the first edge-data acquisition circuit; a comparison and output determination circuit 113 comparing the output from the temporary holding circuit and the output from the second edge-data acquisition circuit and outputting the acquired data; and an alarm output circuit 114 outputting an alarm signal when the two outputs are different.

Description

  The present invention relates to a flip-flop device that captures data in synchronization with a clock signal.

There is a flip-flop device as a device that captures data in synchronization with a clock signal. As a typical method for acquiring the data, there are a method of acquiring data at the time of the rising edge of the clock and a method of acquiring data at the time of the falling edge of the clock.
(1) What is Captured at the Rising Point FIG. 5 shows a conventional flip-flop device that captures data at the rising edge. FIG. 5A shows the configuration. In FIG. 5A, 61 is a flip-flop device, 62 and 63 are input terminals, and 68 and 69 are output terminals.

A clock C is input to the input terminal 62, and data D is input to the input terminal 63. The flip-flop device 61 is configured such that when the value of the data D is high at the rising edge of the clock C, the output Q _P of the output terminal 68 is high and the output Q _P B of the output terminal 69 is low. It shall be. When the value of the data D is low at the rising edge of the clock C, the output Q _P of the output terminal 68 is low and the output Q _P B of the output terminal 69 is high.
The subscript _P means positive edge (rising edge), and B means a bar (Bar) which is a symbol that is drawn on the head of the character and represents its inverted output (in the following description). The same applies to _P and B attached to other characters).

FIG. 5B is a diagram for explaining the operation of the flip-flop device 61. In FIG. 5B, t _{1 to} t ₁₂ are time, C is clock, D is data, Q _P and Q _P B are outputs of the flip-flop device 61, 70 is genuine data, 71 and 72 are noise, 73 Is authentic data, and 74 to 79 are waveforms of outputs Q _P and Q _P B.
Here, “authentic data” refers to normal data, and is used particularly when it is distinguished from noise.

The operation of the flip-flop device 61 is performed as follows. Note the first rise time t ₁ of clock C. It is assumed that the data value D ₁ at this time is high. Then, this high is input, and the output Q _P of the flip-flop device 61 becomes high (Q _P B of the inverted output becomes low).

It is assumed that the data value D ₃ is low at the next rising time t ₃ of the clock C. Then, this low is inputted, and the output Q _P of the flip-flop device 61 becomes low (Q _P B of the inverted output becomes high).
Output Q _P high waveform 74 and the output Q _P waveform 77 of B rows between time t ₁ ~t ₃ is formed as described above.

(2) What is Captured at the Falling Point FIG. 6 shows a conventional flip-flop device that captures data at the falling edge. FIG. 6 (1) shows the configuration. In FIG. 6A, 81 is a flip-flop device, 82 and 83 are input terminals, and 88 and 89 are output terminals.

A clock C is input to the input terminal 82, and data D is input to the input terminal 83. The flip-flop device 81 is configured such that when the value of the data D is high at the falling edge of the clock C, the output Q _N of the output terminal 88 is high and the output Q _N B of the output terminal 89 is low. It is assumed that When the value of data D is low at the falling edge of clock C, output Q _{N at} output terminal 88 is low and output Q _N B at output terminal 89 is high.
The subscript _N means Negative edge (falling edge) (the same applies to _N attached to other characters in the following description).

FIG. 6 (2) is a diagram for explaining the operation of the flip-flop device 81. The reference numerals correspond to those in FIG. 5B, Q _N and Q _N B are the outputs of the flip-flop device 81, and 90 to 95 are the waveforms thereof.
The operation of the flip-flop device 81 is performed as follows. Note the first fall time t ₂ of clock C. The value D ₂ data at this time and at the high. Then, this high is input, and the output Q _N of the flip-flop device 61 becomes high (Q _{NB of the} inverted output becomes low).

It is assumed that the data value D ₄ is low at the next falling time t ₄ of the clock C. Then, this low is inputted, and the output Q _N of the flip-flop device 61 becomes low (Q _{NB of the} inverted output becomes high).
Time t ₂ ~t output Q _N high waveform 90 and the output of the Q _N rows of the waveform 93 of the B between ₄ is formed as described above.

JP-A-5-37306

(problem)
There is a case where noise is mixed in a terminal for inputting data for some reason. However, in the above-described flip-flop device of FIG. 5, if the noise is present at the rising edge of the clock, it is misunderstood as being genuine data, and the value of the noise is output and held. Therefore, there was a problem of causing a malfunction.
In the flip-flop device of FIG. 6, if noise is present just at the falling edge of the clock, it is also mistakenly recognized as genuine data and taken in.

(Explanation of problem)
(1) First, the flip-flop device of FIG. 5 will be described. Noise 71 in FIG. 5 (2) is a noise occurring at the rise time t ₅ clock C, the value D ₅ is high. Accordingly, the flip-flop device 61 in FIG. 5A operates in the same manner as when high genuine data is input, outputs high as the output Q _P (generates a high waveform 75), and outputs Q _P B As low (generates a low waveform 78). Since these are outputs generated by the noise 71, they are incorrect outputs.

Since the data value D _{7 at the} next rise time t ₇ is low, the output Q _P of the flip-flop device 61 is low (lowering the high waveform 75 low) and the output Q _P B is high ( Raise the low waveform 78 high).
Since the noise 72 is not a noise generated at the rising time of the clock C, the output of the flip-flop device 61 does not change. That is, at this time, the flip-flop device 61 does not operate as if high genuine data has been input.

(2) Next, the flip-flop device of FIG. 6 will be described. Figure 6 Noise 72 (2) is a noise occurring at the falling time t ₈ the clock C, the value D ₈ is high. Accordingly, the flip-flop device 81 in FIG. 6A operates in the same manner as when high genuine data is input, outputs high as the output Q _N (generates a high waveform 91), and outputs Q _N B As low (generates a low waveform 94). Since these are outputs generated by the noise 72, they are incorrect outputs.

Since the data value D _{10 at the} next falling time t ₁₀ is high, the flip-flop device 81 takes it in and outputs high as the output Q _N (generates a high waveform 92 and continues high). Low is output as output Q _N B (low waveform 95 is generated and low continues).
Since the noise 71 is not a noise generated at the falling time of the clock C, the output of the flip-flop device 81 does not change. That is, at this time, the flip-flop device 81 does not operate as if high genuine data has been input.
An object of the present invention is to solve the above problems.

In order to solve the above problems, in the flip-flop device of the present invention, in the flip-flop device having a clock input terminal and a data input terminal, the data at the clock rising and the data at the clock falling are taken in and compared, and the same If so, the operation is performed so as to output the output corresponding to the authentic data, and if the data is different, the operation is not performed and the previous output is maintained.
Note that a circuit that outputs a warning signal when data is different between rising and falling may be added to the above configuration.

Specifically, in the flip-flop device of the present invention as described above, a positive pulse (a pulse in the order of rising first and then falling) is used as a clock signal, and a negative pulse (first falling and then falling). It can be configured corresponding to the case of using pulses in the order of ascending).
When corresponding to a positive pulse, at the rising edge comprising a rising edge data fetching circuit for fetching data at the data input terminal at the clock rise and a first data temporary holding unit for holding the output of the rising edge data fetching circuit A data processing circuit, a falling edge data capturing circuit for capturing data at a data input terminal at the time of clock falling, an output of the falling edge data capturing circuit, and an output of the first data temporary holding unit A data value difference determination unit for determining whether the data at the rise and the data at the fall are the same, and a second data temporary holding unit for holding the output of the data value difference determination unit, The output of the second temporary data holding unit and its inverted output can be taken out as outputs.

  In the case of dealing with a negative pulse, a falling edge data capturing circuit that captures data at the data input terminal at the falling edge of the clock and a first data temporary retaining unit that retains the output of the falling edge data capturing circuit are provided. A data processing circuit at the time of falling, a rising edge data capturing circuit for capturing data at the data input terminal at the time of clock rising, an output of the rising edge data capturing circuit, and an output of the first data temporary holding unit A data value difference determination unit for determining whether the data at the fall and the data at the rise are the same, and a second data temporary holding unit for holding the output of the data value difference determination unit, The output of the second data temporary holding unit and its inverted output can be taken out as outputs.

In addition, the above-described flip-flop device uses the output from the rising edge data capturing circuit and the output from the falling edge data capturing circuit when noise is input at the rising edge or falling edge of the clock. Conductive, otherwise it is non-conductive during noise detection and conductive when there is no noise in the data (authentic data is input), otherwise it is non-conductive It is possible to add a noise detection circuit that is configured to connect in series with the noise non-detection conduction unit and extract the noise detection output from the series connection point.
Note that the noise detection conduction section described above is specifically connected to a noise detection conduction section at the time of rising, which is conductive when noise is input at the rising edge of the clock, and is otherwise nonconductive. It can be configured to be connected in parallel with a falling-edge noise detection conduction unit that is conductive when noise is input from time to time, and is otherwise non-conductive.

According to the flip-flop device of the present invention, it is first determined whether or not the data values (logical values high and low) at the rising and falling time points forming one clock signal are the same, and if they are the same In the case of high and high, or in the case of low and low, it is taken as genuine data, and when it is different, it is not taken as not being genuine data. For this reason, it is no longer possible to operate by misidentifying noise as genuine data.
When a noise detection circuit is added, it can be detected that noise has been input.

Flip-flop device according to first embodiment of the present invention The figure which shows the specific example of 1st Embodiment Flip-flop device according to second embodiment of the present invention The figure which shows the specific example of 2nd Embodiment Conventional flip-flop device that captures data at the rising edge Conventional flip-flop device that captures data at the falling edge Flip-flop device according to the third embodiment of the present invention The figure explaining operation | movement of 3rd Embodiment Flip-flop device according to the fourth embodiment of the present invention The figure which shows the invention concept of this invention The figure which shows an example of the rising edge data acquisition circuit The figure which shows an example of the falling edge data acquisition circuit

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
FIG. 1 shows a flip-flop device according to a first embodiment of the present invention. Reference numerals correspond to those in FIG. 5, 1 is a flip-flop device, 2 and 3 are input terminals, and 4 and 5 are output terminals. Q and QB are outputs of the flip-flop device 1, and 100 to 103 are their waveforms.
A clock C is input to the input terminal 2, and data D is input to the input terminal 3. The flip-flop device 1 is a circuit that determines whether or not the input data is genuine data, treats it as a formal input only when it is genuine data, and outputs Q and QB to the output terminals 4 and 5, respectively. (QB is the inverted output of Q). A specific example of the configuration is shown in FIG. 2 (which will be described in detail later).

FIG. 1B is a diagram for explaining the operation of the flip-flop device 1. Here, an outline of the operation will be described (the details of the operation will be described with reference to FIG. 2).
In the present invention, data at both the rise time and fall time forming one clock signal is read, and it is determined whether or not their values (logical values high and low) are the same. The example in FIG. 1 is an example in which a positive pulse signal (a pulse signal that changes in order of rising first and then falling) is used as a clock, as shown in FIG. Hereinafter, the description will be given in the order of clocks.

(1) Clock C ₁ ... T _{1 to} t ₂
First, focus on the clock C ₁ rising at time t ₁ and falling at time t ₂ . It is assumed that high genuine data 70 is input at this clock. Data value D ₁ of the rising time t ₁ is high, the data value D ₂ falling time t ₂ also high. Both are the same because they are both high.
If both are the same, the flip-flop device 1 operates as if authentic data has been input. In this case, since high is input, high is output as the output Q (generating a high waveform 100), and low is output as the output QB (generating a low waveform 102).

(2) Clock C ₂ ... T _{3 to} t ₄
At the time of the clock C ₂ is the authentic data of the low has come to input. Data value D ₃ of the rising time t ₃ is low, the data value D ₄ falling time t ₄ is also low. Both are the same because they are both low.
If both are the same, the flip-flop device 1 operates as if authentic data has been input. In this case, since low is input, low is output as the output Q (the waveform 100 is lowered to low), and high is output as the output QB (the waveform 102 is raised to high).

(3) Clock C ₃ ... T _{5 to} t ₆
And just noise 71 to the rise time t ₅ of the clock C ₃ has come to input. Data values D ₅ at that time is high. And the falling time t ₆ is already noise 71 disappears. The data value D ₆ at that time is low. Comparing the two is different because one is high and the other is low.
If the two are different, the flip-flop device 1 does not operate as if the genuine data was input (that is, responds that there was no input (no change in input)). Accordingly, the outputs Q and QB maintain the previous values.

(4) clock C ₄ ... t ₇ ~t ₈
It is assumed that the data value D _{7 at} the rising time t ₇ of the clock C ₄ is low. However, the just noise 72 in the fall time t ₈ has come to input. The data value D ₈ at that time is high. Comparing the two is different because one is low and the other is high.
If the two are different, the flip-flop device 1 does not operate as if the genuine data was input (that is, responds that there was no input (no change in input)). Accordingly, the outputs Q and QB maintain the previous values.
The case of the clock C ₅ is the same as the case of the clock C ₁ , and the case of the clock C ₆ is the same as the case of the clock C ₂ , so the description is omitted.
As is clear from the above description, even if the noises 71 and 72 are input, the flip-flop device 1 does not operate erroneously.

In the description so far, for the sake of convenience of explanation, the clock signal is assumed to be a positive pulse signal (pulses in the order of rising first and then falling) and a positive pulse noise signal (a “high” level noise signal). I came. However, the present invention is similarly described when the clock signal is a negative pulse signal (pulses in the order of falling first and then rising) or a negative pulse noise signal ("low" level noise signal). I can do it.
The following description will be made assuming the case of a positive pulse clock signal and a positive pulse noise signal, but the same applies to the case of a negative pulse.

  The present invention is essentially different from a double edge trigger (or also called a dual edge trigger) flip-flop. In the double edge trigger flip-flop, data (two data in total) is taken in independently at each rising edge and falling edge of the clock signal, whereas in the present invention, each of the rising edge and falling edge of the clock signal is one by one. This is because the authenticity of data is determined in pairs, and when it is determined as authentic data, the data (a total of one data) is taken in and output.

If data is read by the double edge trigger flip-flop at the same time (t ₁ , t ₃ , t ₅ ,...) As shown in FIG. 5 (2), the clock waveform of the double edge trigger is as follows. The In other words, to maintain a high from the rising time t ₁ to time t ₃ to a high at time t _1, falling to low at time t _3, it maintains the low from time t ₃ to t _5, also high at time t ₅ Is a waveform that repeats rising to low and falling to low at time t ₇ (compared to the clock shown in FIG. 5 (2), the waveform is considerably wider and the frequency of the clock is half. ). Then, the data D ₁ in the rising time t ₁ of the waveform is captured, the rise time t ₃ the data D ₃ are taken.

In the first place, the main purpose of the double edge trigger is to halve the frequency of the clock and to almost halve the power consumption of the CMOS semiconductor circuit. The reason why it can be halved is as follows. The power consumption P of the CMOS semiconductor circuit is expressed by P = C _L × V _DD ² × f (C _L is a load capacitance, V _DD is a power supply voltage, and f is a clock frequency). Electricity is consumed.
Therefore, if data is acquired using only one of the rising and falling edges, but if both the rising and falling edges are used, the clock can be used to perform the same operation. The frequency may be halved. Then, the number of times of charging / discharging is halved, and the power consumption can be almost halved.

Next, the configuration and operation of the contents of the flip-flop device 1 in FIG. 1 will be described.
(1) Configuration of Flip-Flop Device 1 FIG. 2 is a diagram illustrating a specific example of the first embodiment, and is a diagram illustrating an example of the flip-flop device 1 in FIG. Reference numerals correspond to those in FIG. 1, 11 is a data processing circuit at the time of rising, 12 is a rising edge data fetching circuit, 13 is an inverter, 14 is an output confirmation unit, 15 to 18 are MOS transistors, 19 is an output terminal, 20 Is a data temporary holding unit, 21 and 22 are inverters, 23 is a falling edge data fetch circuit, 24 is an inverter, 25 is a data value difference determination unit, 26 to 31 are MOS transistors, 32 is an output terminal, and 33 is data temporary The holding units 34 to 36 are inverters.

The rising edge data processing circuit 11 is a circuit for reading data at the rising edge of the clock signal and performing predetermined processing. The rising edge data processing circuit 11 includes a rising edge data capturing circuit 12, an inverter 13, an output confirmation unit 14, and a data temporary holding unit 20.
The rising edge data take-in circuit 12 takes in the data D from the input terminal 3 when the rising edge of the clock C is inputted from the input terminal 2 and outputs outputs E _P and E _P B according to the value. Circuit.
FIG. 11 shows an example of the rising edge data fetch circuit 12. This is an example in which four NAND circuits are used. The rising edge data fetch circuit 12 can be realized by using a first stage edge detection and data fetch circuit of a known rising edge trigger flip-flop. When the value of data D is high at the moment of the rising edge of clock C, output E _P is high and output E _P B is low. When the value of the data D is low at the moment of the rising edge of the clock C, the output E _P becomes low and the output E _P B becomes high.
During the period when the clock C is high after the rising edge, the values of the outputs E _P and E _P B do not change. That is, the data D is not taken in.
In other periods of the clock C, that is, the instant of the falling edge of the clock C and the period when the clock C is low, the outputs E _P and E _P B are both high. In the circuit of FIG. 11, both outputs E _P and E _P B do not go low.
As described above, the rising edge data fetch circuit 12 newly fetches and holds the data signal at the rising edge time of the clock signal.

The output confirmation unit 14 is a part for confirming whether or not the captured value is a value captured at a rising edge. Here, for example, four MOS transistors 15 to 18 are connected in series, the upper end thereof is connected to the power source + V _DD , the lower end is connected to the ground, and the output is taken out from the central connection point (the C element circuit is connected). Use).
As can be seen from the fact that the upper two MOS transistors 15 and 16 have a state indication symbol (small ◯) attached to the gate, they are activated (turned on) when a low is applied to the gate. (PMOS transistor). Since the lower two MOS transistors 17 and 18 are not attached with a state indication symbol, they are activated when high is applied to the gate (NMOS transistor).

The aforementioned output E _P is applied to the gates of the MOS transistors 15 and 18, and the output E _P B is inverted by the inverter 13 and applied to the gates of the MOS transistors 16 and 17.
The output of the output confirmation unit 14 is taken out from the central connection point (connection point of the MOS transistors 16 and 17) of the series connection to the output terminal 19.
The output value of the output terminal 19 becomes high when the upper two MOS transistors 15 and 16 are turned on and the lower two MOS transistors 17 and 18 are turned off.
The output value of the output terminal 19 becomes low when the upper two MOS transistors 15 and 16 are turned off and the lower two MOS transistors 17 and 18 are turned on.
When the input of these MOS transistors is other than the above, the output terminal 19 is in a floating state (a state that is neither high nor low).

The data temporary holding unit 20 is a part that takes in the output data (logical value) of the output confirmation unit 14 and holds the data. Here, for example, inverters 21 and 22 are connected in a loop. When configured in this way, the data that has been input from the output terminal 19 is held in an inverted form and continuously output (if the data at the output terminal 19 is high, the data temporary holding unit 20 inverts it) Are kept in a form that continues to output).
Thereafter, the data held by the temporary data holding unit 20 does not change until data having a logical value different from that of the previous time comes from the output terminal 19.

The falling edge data take-in circuit 23 takes in the data D from the input terminal 3 when the falling edge of the clock C is inputted from the input terminal 2 and outputs the outputs E _N and E _N B according to the value. It is a circuit to output.
FIG. 12 shows an example of the falling edge data fetch circuit 23. This is an example in which four NOR circuits are used. The falling edge data fetch circuit 23 can be realized by using a first-stage edge detection / data fetch circuit of a known falling edge trigger flip-flop. When the value of data D is high at the moment of the falling edge of clock C, output E _N is high and output E _N B is low. Further, when the value of the data D at the moment of the falling edge of the clock C is low, the output E _N becomes low, the output E _N B becomes high.
While the clock C is low after the falling edge, the values of the outputs E _N and E _N B do not change. That is, the data D is not taken in.
In other periods of the clock C, that is, the instant of the rising edge of the clock C and the period in which the clock C is high, the outputs E _N and E _N B are both low. In the circuit of FIG. 12, the outputs E _N and E _N B are not both high.
In this way, the falling edge data fetch circuit 23 newly fetches and holds the data signal at the time of the falling edge of the clock signal.

The data value difference determination unit 25 is a part that determines whether or not the values (logical values) of the data D captured at the rising and falling of the clock C are different. Here, for example, six MOS transistors 26 to 31 are connected in series, the upper end thereof is connected to the power source + V _DD , the lower end is connected to the ground, and the output is taken out from the central connection point (the C element circuit is connected). Use).
Since the upper three MOS transistors 26 to 28 have state indication symbols (small ◯) attached to their gates, they are activated (turned on) when a low is applied to the gate. Since the lower three MOS transistors 29 to 31 are not provided with a state indication symbol, they are activated when high is applied to the gate.

The output of the temporary data holding unit 20 is applied to the gates of the MOS transistors 26 and 31, the output E _{N of the} falling edge data fetch circuit 23 is applied to the gates of the MOS transistors 27 and 30, and the output E _N B is converted to the inverter 24. The output inverted at is applied to the MOS transistors 28 and 29.
The output of the data value difference determination unit 25 is taken out from the central connection point (connection point of the MOS transistors 28 and 29) in series connection to the output terminal 32.
The output value of the output terminal 32 becomes high when the upper three MOS transistors 26 to 28 are turned on and the lower three MOS transistors 29 to 30 are turned off.
The output value of the output terminal 32 becomes low when the upper three MOS transistors 26 to 28 are turned off and the lower three MOS transistors 29 to 30 are turned on.
When the input of these MOS transistors is other than the above, the output terminal 32 is in a floating state (a state that is neither high nor low).

The data temporary holding unit 33 is a part that takes in the output data (logical value) of the data value difference determination unit 25 and holds the data. Similar to the temporary data storage unit 20, two inverters 34 and 35 can be connected in a loop.
The output terminal of the temporary data holding unit 33 is connected to the terminal 4 and is connected to the terminal 5 through the inverter 36. The output taken out at the terminal 4 is taken as an output Q, and the output taken out at the terminal 5 is taken as an output QB. These are the outputs of the flip-flop device 1.

(2) the operation when the operation is first clock C ₁ when the flip-flop device 1 of the operation (2-1) clock C _1, will be described with reference to FIG. 1 (2). Since the data values D ₁ of the rising time t ₁ is high, the output E _P rising edge data acquisition circuit 12 is high, the output E _P B becomes low. At this time, the inputs to the gates of the MOS transistors of the output confirmation unit 14 are all high (E _P is high, and the value obtained by inverting low E _P B by the inverter 13 is high). Accordingly, the MOS transistors 15 and 16 are turned off and the MOS transistors 17 and 18 are turned on. Since the output terminal 19 is connected to the ground and disconnected from the power source + V _DD , the output of the output terminal 19 becomes low.
This is input to the data temporary holding unit 20 and inverted high is output (this value is held). This is applied to the gates of the MOS transistors 26 and 31 of the data value difference determination unit 25.

Next, the fall time t ₂ is reached. Since the data value D ₂ at this time is also high, the output E _N of the falling edge data fetch circuit 23 is high and the output E _N B is low. The output E _N (high) is applied to the gates of the MOS transistors 27 and 30 of the data value difference determination unit 25. The output E _N B (low) is inverted by the inverter 24 to be high and applied to the gates of the MOS transistors 28 and 29.

By the way, the output (high) of the temporary data holding unit 20 is continuously held from the rising time t ₁ and is still applied to the gates of the MOS transistors 26 and 31, so at the falling time t ₂ . Is applied to the gates of all the MOS transistors of the data value difference determination unit 25. Accordingly, the MOS transistors 26 to 28 are turned off, the MOS transistors 29 to 30 are turned on, and low is output to the output terminal 32. Since the low level is inverted to high by the data temporary holding unit 33, a high output is output as the output Q from the terminal 4, and a low output is output as the output QB from the terminal 5.

(2-2) Since the data values D ₃ of the rising time t ₃ of the operation clock C ₂ when the clock C ₂ is low, the output E _P is low rising edge data acquisition circuit 12, the output E _P B is Become high. At this time, the inputs to the gates of the MOS transistors of the output confirmation unit 14 are all low (since E _P is low and the value obtained by inverting high E _P B by the inverter 13 is low). Accordingly, the MOS transistors 15 and 16 are turned on, and the MOS transistors 17 and 18 are turned off. Since the output terminal 19 is connected to the power source + V _DD and is disconnected from the ground, the output of the output terminal 19 becomes high.
This is input to the data temporary holding unit 20 and an inverted low is output (this value is held). This is applied to the gates of the MOS transistors 26 and 31 of the data value difference determination unit 25.

Next, the fall time t ₄ is reached. Since the data value D ₄ at this time is also low, the output E _N of the falling edge data fetch circuit 23 is low and the output E _N B is high. The output E _N (low) is applied to the gates of the MOS transistors 27 and 30 of the data value difference determination unit 25. The output E _N B (high) is inverted by the inverter 24 to be low and applied to the gates of the MOS transistors 28 and 29.
Therefore, at the falling time t ₄ , low is applied to the gates of all the MOS transistors of the data value difference determination unit 25. Accordingly, the MOS transistors 26 to 28 are turned on, the MOS transistors 29 to 30 are turned off, and high is output to the output terminal 32. Since the high is inverted to low by the data temporary holding unit 33, a low output is output as the output Q from the terminal 4, and a high output is output as the output QB from the terminal 5.

(2-3) Data value D ₅ of the rising time t ₅ of the operation clock C ₃ when the clock C ₃ is just high because high noise is out. Accordingly, the output E _P of the rising edge data fetch circuit 12 is high and the output E _P B is low. At this time, the inputs to the gates of the MOS transistors of the output confirmation unit 14 are all high (E _P is high, and the value obtained by inverting low E _P B by the inverter 13 is high). Accordingly, the MOS transistors 15 and 16 are turned off and the MOS transistors 17 and 18 are turned on. Since the output terminal 19 is connected to ground and disconnected from the power supply + V _DD , the output of the output terminal 19 becomes low.
This is input to the data temporary holding unit 20 and inverted high is output (this value is held). This is applied to the gates of the MOS transistors 26 and 31 of the data value difference determination unit 25.

Next, the fall time t ₆ is reached. Since the data value D ₆ at this time is low (noise has disappeared), the output E _N of the falling edge data capturing circuit 23 is low, and the output E _N B is high. The output E _N (low) is applied to the gates of the MOS transistors 27 and 30 of the data value difference determination unit 25. The output E _N B (high) is inverted by the inverter 24 to be low and applied to the gates of the MOS transistors 28 and 29.
Therefore, at the falling time t ₄ , high, low, and low are applied to the gates of the three MOS transistors 26, 27, and 28 above the data value difference determination unit 25, respectively, and the lower three MOS transistors 29 , 30 and 31 are applied with low, low and high, respectively.

Of the MOS transistors 26, 27, and 28 between the output terminal 32 and the power source + V _DD , a gate input (low) that can turn them on is applied to the transistors 27 and 28. The gate input (high) to be applied is applied. Therefore, the output terminal 32 and the power source + V _DD are disconnected.
Of the MOS transistors 29, 30, and 31 between the output terminal 32 and the ground, 31 is applied with a gate input (high) that can turn it on, but 29 and 30 have gates that turn them off. Input (low) is applied. Accordingly, the output terminal 32 and the ground are also disconnected.
That is, since the output terminal 32 is in a floating state, the output of the data temporary holding unit 33 is not changed, and the previous value low (it was low at the time of the clock C ₂ ) is maintained. Therefore, the output Q of the terminal 4 is also kept low, and the output QB of the terminal 5 is also kept high.

(2-4) Operation at the time of clock C ₄ The difference from the case of clock C ₃ is only that the time when noise is occurring is not rising but falling. Therefore, the operation of the flip-flop device 1 at the time of the clock C ₄ can be followed as in the case of the clock C ₃ . Although a detailed description is omitted, the output terminal 32 is also in a floating state at this time.
Eventually, even in the case of the clock C ₄ , the output Q and output QB from the flip-flop device 1 do not change, and the previous values (output Q low, output QB high) are maintained.
Thus, when the data from the terminal D is genuine data, the flip-flop device 1 outputs an output corresponding to the data. However, if the data is noise, the flip-flop device 1 is not affected by the output. To maintain.

(Second Embodiment)
FIG. 3 shows a flip-flop device according to the second embodiment of the present invention. The reference numerals correspond to those in FIG. 1, 37 is a noise detecting conduction part, 37A is a rising noise detection conduction part, 37B is a falling noise detection conduction part, 38 is a noise non-detecting conduction part, and 40 is a noise detection. A circuit 54 is a detection output terminal.
In this embodiment, when noise is input at one of the rising and falling edges of the clock, as in the case of the clocks C ₃ and C ₄ in FIG. 1 (2), this is detected. The noise detection circuit 40 is added.

The noise detection circuit 40 includes a noise detecting conduction unit 37 and a noise non-detecting conduction unit 38 connected in series, and a detection output terminal 54 is taken out from a connection point between the two. The upper end of the noise detecting conduction unit 37 is connected to the power source + V _DD, and the lower end of the noise non-detecting conduction unit 38 is connected to the ground. These have a circuit configuration using, for example, a CMOS transistor.
When normal data is input as in the case of clocks C ₁ and C ₂ in FIG. 1 (2) (when the clock rise and fall values are the same), the conduction section when no noise is detected 38 is conductive, and when noise is detected, the conductive portion 37 is non-conductive, and a low output is output to the detection output terminal 54.
On the other hand, when noise is input as in the case of clocks C ₃ and C ₄ (when the clock rise and fall values are different), the noise detecting conduction unit 37 is turned on and no noise is received. At the time of detection, the conducting portion 38 becomes non-conductive, and a high output is output to the detection output terminal 54. As a result, noise can be detected.

The noise detection conduction unit 37 can be configured, for example, by connecting a rising noise detection conduction unit 37A and a falling noise detection conduction unit 37B in parallel. Rise time noise sensing conductive portion 37A, as in the case of the clock C _3, which conducts when noise is present at the time of rise (at that time, towards the falling time of the noise detecting conductive portion 37B is non-conductive). Falling during noise sensing conductive portion 37B, as in the case of the clock C _4, conducts when the noise at the time of falling is present (at that time, towards the rising time of the noise detecting conductive portion 37A is non-conductive).

  FIG. 4 is a diagram illustrating a specific example of the second embodiment, and illustrates a specific configuration example of the flip-flop device 1 and the noise detection circuit 40. Reference numerals correspond to those in FIGS. 2 and 3, 41 to 45 are MOS transistors, 46 is an inverter, and 47 to 53 are MOS transistors. This circuit is an example configured using a CMOS transistor circuit (a circuit configuration method in which a PMOS transistor and an NMOS transistor are paired). Since the configuration and operation of the flip-flop device 1 are the same as those in FIGS. 1 and 2, the description thereof will be omitted, and only the configuration and operation of the noise detection circuit 40 will be described below.

(Configuration of noise detection circuit 40)
The rising-edge noise detection conduction section 37A is configured by connecting three PMOS transistors 41 to 43 in series, and the falling-edge noise detection conduction section 37B is also configured by connecting three PMOS transistors 49 to 51 in series. When no noise is detected, the conducting section 38 is configured by connecting two NMOS transistors in parallel (first group... 44, 47, 52, second group... 45, 48, 53) connected in series. To do.
Then, the gates are connected so that they are inputted as follows (in order to avoid complication of text, MOS transistors will be described only with reference numerals).

Output E _N → 42 of → 44, 49 to the gate falling edge data acquisition circuit 23 (the inverted output value of the output terminal 19) the output value → data temporary holding section 20 to the gate of 41 and 45 of the output terminal 19 , the output E _N B output E _N to 48 of the gate to the gate of the output E _N B → 51 and 52 to the inverted output → 47, 50 of the gate by the inverter 46 falling edge data acquisition circuit 23 by the inverter 24 Inverted output → To gates 43 and 53

As a result of this connection, inverted values are input to the gates of the MOS transistors connected to the corresponding positions of the rising-edge noise detection conduction portion 37A and the falling-time noise detection conduction portion 37B. become. For example, when high is input to the gate 41, low is input to the gate 49, and conversely, when low is input to the gate 41, high is input to the gate 49.
The three MOS transistors connected in series are used as gate inputs of “output terminal 19 output”, “output E _N ”, “output E _N B” and these three inverted outputs.
When no noise is detected, the gates of the second set of three MOS transistors (45, 48, 53) connected in parallel to the conducting portion 38 are connected to "output of output terminal 19", "output E _N ", “Inverted output of output E _N B” is applied, and the three inverted outputs are applied to the gates of the first three MOS transistors (44, 47, 52).

(Operation of the noise detection circuit 40)
(1) When the input data has no noise (authentic data) In this case, in the rising-edge noise detection conducting section 37A, at least one of the MOS transistors is non-conducting and the falling-edge noise Even in the detection conduction portion 37B, at least one of the MOS transistors is non-conduction. Therefore, the noise detecting conduction part 37 is non-conductive as a whole.
The case of the clock C _{1 in} FIG. 1 (2) will be described as an example. MOS transistors 42 and 43 are non-conductive in the rising-edge noise detection conducting portion 37A, and 49 is non-conducting in the falling-time noise detection conducting portion 37B. . This is because E _P and E _N are both high at clock C ₁ , E _N is input to 42 and becomes non-conducting, and 43 is input high that is obtained by inverting E _N B (low) by inverter 24. , Become non-conductive. This is also because 49 is inputted with high obtained as E _P (high) → output terminal 19 (low) → output (high) of the data temporary holding unit 20 and becomes non-conductive.

On the other hand, in the noise non-detection conduction unit 38, at least one MOS transistor in the first set is turned on, and at least one MOS transistor in the second set is turned on. Therefore, when no noise is detected, the conducting unit 38 is in a conducting state as a whole.
The case of the clock C ₁ will be described as an example. In the first set, the MOS transistor 44 is turned on, and in the second set, 48 and 53 are turned on. This is because, becomes conductive is entered high output of the data temporary storage unit 20 to 44, a conducting high E _N is input to the 48, E _N B (low) is inverted by the inverter 24 to 53 This is because a high level is input and becomes conductive.
Therefore, the detection output terminal 54 is connected to the ground, and the detection output becomes low.
(If the clock C ₂ is considered in the same way, the detection output becomes low.)

(2) When there is noise in the input data In this case, in the noise detection conduction unit 37, the rising noise detection conduction unit 37A or the falling noise detection conduction unit 37B becomes conductive and noise detection is performed. The hour conduction portion 37 as a whole becomes conductive.
On the other hand, in the noise non-detection conduction unit 38, all the MOS transistors in the first set are turned off or all the MOS transistors in the second set are turned off, so that the noise is not detected. The conduction part 38 as a whole becomes non-conductive.
As a result, the detection output terminal 54 is connected to the power supply (+ V _DD ), and the detection output becomes high. Hereinafter, the case of rising noise and falling noise will be described separately.

(2-1) The noise detection at conduit 37 when noise came entered during the rise (in the case of the clock C ₃ in FIG. 1 (2)) when noise was achieved during the rise, the rise time of the noise All the MOS transistors of the detection conduction part 37A become conductive.
This is because E _P is high and E _N is low in the case of the clock C ₃ , and the low of the output terminal 19 (E _P high → output terminal 19 low) is input to 41 and becomes conductive. The 42 becomes conductive entered the low E _N is the, in 43 because E _N B High becomes conductive been entered inverted low by inverter 24.

On the other hand, the noise not detected when conducting portion 38 (in the case of the clock C ₃₎ noise if it was intended at the time of rising, the second set of MOS transistors 45,48,53 are all nonconductive.
This is because, in the case of the clock C ₃ , E _P is high and E _N is low, and the low of the output terminal 19 (E _P high → output terminal 19 low) is input to 45 and becomes non-conductive. This is because a low E _N is input to 48 and becomes non-conductive, and a low signal obtained by inverting the high E _N B by the inverter 24 is input to 53 and becomes non-conductive.
Therefore, the detection output from the detection output terminal 54 is high.

(2-2) The noise detection at conduit 37 when noise came entered during the fall (for clock C ₄₎ when the noise was intended at the time of fall, when the falling noise sensing conductive portion All the MOS transistors of 37B become conductive.
This is because, in the case of the clock C ₄ , E _P is low and E _N is high, and 49 is the output low of the data temporary holding unit 20 (E _P low → output terminal 19 high → output low of the data temporary holding unit 20). It is input and becomes conductive. Also the 50 becomes conductive to high E _N are inverted row input in the inverter 46, the 51 because E _N B rows are conductive entered.

On the other hand, the noise not detected when conducting portion 38 (in the case of the clock C ₄₎ when the noise was intended at the time of falling, the first set of MOS transistors 44,47,52 are all nonconductive.
This is because in the case of the clock C ₄ , E _P is low and E _N is high, and 44 is the output low of the data temporary holding unit 20 (E _P low → output terminal 19 high → output low of the data temporary holding unit 20). It is input and becomes non-conductive. This is because the low EN obtained by inverting the high _EN by the inverter 46 is input to 47 and becomes non-conductive, and the low _EN B is input to 52 and becomes non-conductive.
Therefore, the detection output from the detection output terminal 54 is high.

FIG. 7 is a diagram showing a flip-flop device according to a third embodiment of the present invention. This is an embodiment in the case where a negative pulse signal (a pulse in the order of falling first and then rising) is used as a clock signal (the first and second embodiments are positive pulse signals ( In this case, a pulse in the order of rising first and then falling) is used.
In FIG. 7, the reference numerals correspond to those in FIG. 2, and 96 is a data processing circuit at the time of falling. In the case of a negative pulse signal, there is a fall first, followed by a rise. Therefore, the circuit of FIG. 2 is modified to cope with this.

That is, the position where the rising edge data capturing circuit 12 is connected in FIG. 2 is a position where a circuit for capturing data at the time of occurrence first is connected between the rising edge and the falling edge of the clock signal. In FIG. 2, a positive pulse signal is used as the clock signal, and the rising edge occurs first. Therefore, the rising edge data capturing circuit 12 is connected to capture data at that time.
However, in the third embodiment shown in FIG. 7, since a negative pulse is to be used as the clock signal, the falling edge occurs first. Therefore, the falling edge data capturing circuit 23 may be connected to the position where the rising edge data capturing circuit 12 is connected in FIG. Since the next rise occurs, the rising edge data capturing circuit 12 may be connected to the position where the falling edge data capturing circuit 23 is connected in FIG.
In FIG. 2, the portion that is named the rising edge data processing circuit 11 surrounded by a dotted line is not suitable for the reason that the falling edge data capturing circuit 23 is brought into FIG. The data processing circuit 96 has been changed.

FIG. 8 is a diagram for explaining the operation of the third embodiment described above. The reference numerals correspond to those in FIG. The only difference is that the waveform of the clock C is a negative pulse (a pulse in the order of falling first and then rising), and the rest is the same as FIG.
Since the operation description is almost the same, the description is omitted.

FIG. 9 is a diagram showing a flip-flop device according to a fourth embodiment of the present invention. The reference numerals correspond to those in FIGS.
In this embodiment, a noise detection circuit 40 is added to that of the third embodiment. The only difference is that a negative pulse signal is used as the clock signal, and the rest is the same. Since the configuration and operation are substantially the same as those in FIG. 4, description thereof will be omitted.

FIG. 10 is a diagram showing the inventive concept of the present invention, and is a diagram summarizing various embodiments described so far. Reference numerals correspond to those in FIG. 1, 110 is a first edge data capturing circuit, 111 is a second edge data capturing circuit, 112 is a temporary holding circuit, 113 is a comparison / output determination circuit, 114 is a warning output circuit, Reference numeral 115 denotes a warning output terminal.
The data flip-flop device 1 of the present invention includes a first edge data capturing circuit 110, a second edge data capturing circuit 111, a temporary holding circuit 112, a comparison / output determination circuit 113, a warning output circuit 114, and a warning as shown in the figure. The output circuit 114 is configured. However, the warning output circuit 114 is a circuit added as necessary.

The clock signal has a first edge and a second edge. When a positive pulse is used as the clock signal, the first edge is a rising edge and the second edge is a falling edge. When a negative pulse is used, the first edge is a falling edge and the second edge is a rising edge.
The first edge data capturing circuit 110 is a circuit that captures data D at the first edge of the clock C input from the input terminal 2. This output is sent to the temporary holding circuit 112 where it is temporarily held.
The second edge data capturing circuit 111 is a circuit that captures data D at the second edge of the clock C input from the input terminal 2.

The comparison / output determination circuit 113 compares the data held in the temporary holding circuit 112 (data read at the first edge) with the data read by the second edge data fetch circuit 111 and fetches the data. This is a circuit for determining whether to output data or to retain the previous output value (determining whether noise has been mixed in).
The warning output circuit 114 is a circuit that outputs a warning signal that noise is mixed when the data captured at the first edge is different from the data captured at the second edge.

As is clear from the above description, according to the present invention, in a flip-flop device that captures data in synchronization with a clock, even if data is mixed with noise, it is mistaken for genuine data. Will not be captured.
As can be seen from the observation and comparison of the pulse width of the clock C ₃ and the noise 71 in FIG. 1, the clock pulse width is smaller than that shown in the figure, and the noise pulse width is larger than that shown in the figure. In this case, the noise value becomes high at the rising and falling edges of the clock, and theoretically, it becomes the same as that of the genuine data 70. Therefore, it is necessary to adjust the pulse width of the clock to be larger than the pulse width of noise. However, the pulse width of a clock that is normally used is almost extremely larger than the pulse width of noise.
When a noise detection circuit is added, it is possible to detect that noise has been input.

  DESCRIPTION OF SYMBOLS 1 ... Flip-flop apparatus, 2, 3 ... Input terminal, 4, 5 ... Output terminal, 11 ... Rising edge data processing circuit, 12 ... Rising edge data acquisition circuit, 13 ... Inverter, 14 ... Output confirmation part, 15-18 DESCRIPTION OF SYMBOLS MOS transistor, 19 ... Output terminal, 20 ... Data temporary holding part, 21, 22 ... Inverter, 23 ... Falling edge data fetch circuit, 24 ... Inverter, 25 ... Data value difference determination part, 26-31 ... MOS transistor 32 ... Output terminal, 33 ... Data temporary holding unit, 34, 35 ... Inverter, 36 ... Inverter, 37 ... Noise detection conduction unit, 37A ... Rising noise detection conduction unit, 37B ... Falling noise detection conduction unit, 38 ... Conducting part when no noise is detected, 40 ... Noise detection circuit, 41-45 ... MOS transistor, 46 ... Inverter, 47-53 ... MOS transistor Jister, 54 ... Detection output terminal, 61 ... Flip-flop device, 62, 63 ... Input terminal, 68, 69 ... Output terminal, 70 ... True data, 71, 72 ... Noise, 73 ... True data, 74 to 79 ... Output waveform , 81, flip-flop device, 82, 83, input terminal, 88, 89, output terminal, 90 to 95, output waveform, 96, falling data processing circuit, 100 to 103, output waveform, 110, first edge Data fetch circuit, 111 ... second edge data fetch circuit, 112 ... temporary holding circuit, 113 ... comparison / output determination circuit, 114 ... warning output circuit, 115 ... warning output terminal

Claims (6)

In a flip-flop device having a clock input terminal and a data input terminal,
The data at the rising edge of the clock and the data at the falling edge of the clock are taken in and compared. If they are the same, the data is judged to be genuine data and an operation corresponding to the genuine data is output. A flip-flop device configured to maintain a conventional output. In a flip-flop device having a clock input terminal and a data input terminal,
The data at the rising edge of the clock and the data at the falling edge of the clock are taken in and compared. If they are the same, the data is judged to be genuine data and an operation corresponding to the genuine data is output. It is configured to maintain the previous output,
A flip-flop device having a circuit for outputting a warning signal when data is different between rising and falling. A rising edge data processing circuit comprising a rising edge data capturing circuit for capturing data at a data input terminal at the time of a clock rising; and a first data temporary holding unit for retaining an output of the rising edge data capturing circuit;
A falling edge data fetch circuit for fetching data at the data input terminal at the clock fall;
A data value difference determination unit for determining whether the data at the rising edge and the data at the falling edge are the same by using the output of the falling edge data fetching circuit and the output of the first data temporary holding unit And a second data temporary holding unit for holding the output of the data value difference determination unit,
A flip-flop device configured to take out an output of the second temporary data holding unit and its inverted output as an output. Falling-edge data processing circuit comprising a falling-edge data fetching circuit that fetches data at the data input terminal when the clock falls, and a first data temporary holding unit that holds the output of the falling-edge data fetching circuit When,
A rising edge data capturing circuit for capturing data at the data input terminal at the rising edge of the clock;
A data value difference determination unit for determining whether the data at the fall and the data at the rise are the same by using the output of the rising edge data capturing circuit and the output of the first data temporary holding unit; A second data temporary holding unit for holding the output of the data value difference determination unit,
A flip-flop device configured to take out an output of the second temporary data holding unit and its inverted output as an output. The flip-flop device according to claim 3 or 4,
Using the output from the rising edge data capture circuit and the output from the falling edge data capture circuit, it conducts when noise is input at the rising or falling edge of the clock, otherwise it is non-conducting The noise detection conduction part that is
Connected in series with a noise non-detection conducting part that conducts when there is no noise in the data (authentic data is input), and is otherwise non-conducting,
A flip-flop device to which a noise detection circuit configured to take out a noise detection output from the series connection point is added. The noise detecting conduction part in the flip-flop device according to claim 5,
The noise detection conduction part at the time of rising, which becomes conductive when noise is input at the rising edge of the clock, and is otherwise non-conductive,
A flip-flop device comprising a parallel connection of a falling-edge noise detection conducting portion that conducts when noise is inputted at the time of falling, and is otherwise non-conducting.

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