JP2012164704A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device and the semiconductor device capable of suppressing deposition of a copper compound on an isolated pattern.SOLUTION: In a semiconductor device, alignment marks AM and superposition inspection marks KM, which are formed to respective openings of a low dielectric constant film LOW1 of an element and substrate layer ESL, an ultra low dielectric constant film ELK1 and the like of a fine layer FL, and a low dielectric constant film LOW2 and the like of a semiglobal layer SGL, are electrically connected to a predetermined conductivity type impurity region IR formed on a semiconductor substrate SUB. The alignment marks AM and the superposition inspection marks KM are fixed to the ground potential.

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device to which a copper wiring and a low dielectric constant film are applied, and such a semiconductor device.

  In a semiconductor device, a copper film having a low specific resistance is applied as wiring in order to cope with miniaturization and high speed of the semiconductor device, and a low dielectric constant film (Low-k) having a relatively low dielectric constant is used as an inter-wiring material. Has been applied.

  In this type of semiconductor device, the copper wiring and the like are formed by a so-called damascene method. There are two damascene methods, a single damascene method and a dual damascene method. The single damascene method is a method used when forming a copper wiring alone or when forming a via or the like alone. In this method, first, a wiring groove (via hole or the like) is formed in a low dielectric constant film, and a copper film is formed on the surface of the low dielectric constant film so as to fill the wiring groove (via hole or the like). Next, the part of the copper film that is left in the wiring trench (via hole, etc.) is removed by performing chemical mechanical polishing to remove the part of the copper film located on the surface of the low dielectric constant film. (Via etc.) will be formed.

  On the other hand, the dual damascene method is a method used when copper wiring and vias are formed simultaneously. In this method, first, a wiring groove and a via hole are formed in a low dielectric constant film, and a copper film is formed on the surface of the low dielectric constant film so as to fill the wiring groove and the via hole. Next, by performing a chemical mechanical polishing process to remove the portion of the copper film located on the surface of the low dielectric constant film, the portion of the copper film remaining in the wiring trench is formed as a wiring, The portion of the copper film left in the via hole is formed as a via or the like for connecting the wirings. In a semiconductor device, a multilayer wiring structure is formed by repeating the process of forming such wiring and vias.

  By the way, in the process of forming a wiring groove (via hole or the like) in the low dielectric constant film, a photoengraving process for transferring the mask pattern to the resist applied on the surface of the low dielectric constant film is performed, and then the patterning is performed. The low dielectric constant film is etched using the resist thus formed as a mask. In the photoengraving process, the alignment of the mask pattern with respect to the underlying pattern of the wafer is performed by the alignment mark. Further, the positional deviation between the patterned resist pattern after development and the base pattern is inspected by the overlay inspection mark. In general, the alignment mark and the overlay inspection mark are formed in a dicing line region.

  In order to ensure alignment accuracy, a certain area located around the alignment mark is provided with a pattern prohibited area in which other patterns such as dummy patterns should not be formed, and also in an area immediately below the alignment mark, It is required not to form other patterns such as other alignment marks. In addition, in order to ensure overlay inspection accuracy, a certain area located around the overlay inspection mark is provided with a pattern prohibited area in which other patterns such as dummy patterns should not be formed, and overlay It is required not to form other patterns such as other overlay inspection marks in the region immediately below the inspection marks.

  That is, each of the alignment mark and the overlay inspection mark is formed in a different area in the dicing line area for each corresponding photoengraving process as an isolated pattern separated from other patterns. In particular, alignment marks and overlay inspection marks for patterning wiring grooves, via holes, etc. are formed in a predetermined area in the dicing line area in conjunction with the formation of wirings or vias having a multilayer wiring structure. Will be formed.

  In the manufacture of a semiconductor device, for example, a semiconductor device having a magnetic memory element or the like is formed by repeating a step of forming a predetermined film and a step of patterning the predetermined film including the multilayer wiring structure. It will be. Patent Document 1 is an example of a document disclosing a technique for forming a copper wiring in a low dielectric constant film.

JP 2009-4408 A

  As described above, the alignment mark and the overlay inspection mark are formed by leaving a portion of the copper film located in the opening of the low dielectric constant film or the like by the chemical mechanical polishing process simultaneously with the process of forming the wiring or the via. , By removing a portion of the copper film located on the upper surface of the low dielectric constant film.

  However, it has been found that after the chemical mechanical polishing treatment, a defect occurs in which a copper compound is deposited on the surface of the copper film. As a result of confirmation by the inventors, it has been found that a copper compound grows in proportion to the elapsed time after the chemical mechanical polishing treatment. Further, it was found that the copper compound grows particularly remarkably at the edge of the alignment mark or overlay inspection mark formed as an isolated pattern with a pattern prohibition region provided around the copper compound. Furthermore, as a result of confirmation by the inventors, it has been found that, as an isolated pattern, a defect in which a copper compound is deposited after the chemical mechanical polishing treatment occurs on the surface of a via or the like formed by a single damascene method.

  If copper is deposited at the edge of the alignment mark or overlay inspection mark, the boundary between the alignment mark or overlay inspection mark and the low dielectric constant film becomes unclear, which may adversely affect alignment accuracy and overlay inspection accuracy. Further, when copper is deposited on the surface of a via or the like, there is a possibility of adversely affecting the reliability evaluation of the wiring represented by TDDB (Time Dependent Dielectric Breakdown).

  The present invention has been made to solve the above problems, and its purpose is specific to an isolated pattern of a copper film, such as an alignment mark, an overlay inspection mark, or a via by a single damascene method. Another object is to provide a semiconductor device that solves the problems peculiar to the isolated pattern of the copper film.

  A manufacturing method of a semiconductor device according to an embodiment of the present invention includes the following steps. An insulating film having a predetermined dielectric constant is formed on the main surface of the semiconductor substrate. A recess for forming an alignment mark is formed in a predetermined region on the surface of the insulating film. A copper film is formed so as to cover the insulating film so as to fill the recess. By removing the portion of the copper film located on the upper surface of the insulating film by chemical mechanical polishing, the portion of the copper film remaining in the recess is formed as an alignment mark. The step of forming the alignment mark includes a step of electrically connecting the alignment mark to the ground potential.

  A semiconductor device according to another embodiment of the present invention includes an insulating film having a predetermined dielectric constant and an alignment pattern including a copper film. An insulating film having a predetermined dielectric constant is formed on the main surface of the semiconductor substrate. The alignment mark including the copper film is formed in a predetermined recess on the surface of the insulating film. The alignment mark is electrically connected to the ground potential.

  A method for manufacturing a semiconductor device according to still another embodiment of the present invention includes the following steps. An insulating film having a predetermined dielectric constant is formed on the main surface of the semiconductor substrate. When the ratio of the area occupied by the opening to the unit area is defined as the opening occupation ratio, a plurality of first openings penetrating the insulating film are formed in a predetermined first region on the surface of the insulating film with the first opening occupation ratio. At the same time, a plurality of second openings penetrating the insulating film are formed in the second region adjacent to the first region with a second opening occupancy ratio higher than the first opening occupancy ratio. A copper film is formed so as to cover the insulating film in such a manner as to fill the plurality of first openings and the plurality of second openings. When the ratio of the occupied area of the via to the unit area is defined as the via occupation ratio, the portion of the copper film located in the first opening and the portion of the copper film located in the second opening are left by the chemical mechanical polishing process. By removing a portion of the copper film located on the upper surface of the insulating film, vias are formed in the first region with a first via occupancy corresponding to the first opening occupancy, and in the second region, A dummy via is formed with a second via occupation ratio corresponding to the second opening occupation ratio.

  A semiconductor device according to still another embodiment of the present invention includes an insulating film having a predetermined dielectric constant, a plurality of vias including a copper film, and a plurality of dummy vias including a copper film. An insulating film having a predetermined dielectric constant is formed on the main surface of the semiconductor substrate. The plurality of vias including the copper film penetrate the insulating film with a first via occupation ratio in a predetermined first region on the surface of the insulating film, where the via occupation area per unit area is a via occupation ratio. Is formed. The plurality of dummy vias including the copper film are formed in the second region adjacent to the first region so as to penetrate the insulating film with a second via occupation ratio higher than the first via occupation ratio.

  In the method of manufacturing a semiconductor device according to one embodiment of the present invention and the semiconductor device according to another embodiment, the alignment mark is electrically connected to the ground potential, so that the chemical mechanical polishing process is performed. It is possible to suppress the copper compound from being deposited on the surface of the alignment mark.

  In the method of manufacturing a semiconductor device according to still another embodiment of the present invention and the semiconductor device according to still another embodiment, the first region in which a plurality of vias are formed with the first via occupation ratio is By adjoining a second region where a plurality of dummy vias are formed with a second via occupancy rate higher than one via occupancy rate, a copper compound is sacrificially deposited on the surface of the dummy via, thereby It can suppress that a copper compound precipitates in the via.

FIG. 3 is a partial plan view showing a part of a planar layout of the semiconductor device according to the first embodiment of the present invention. In the same embodiment, it is a fragmentary sectional view of the semiconductor device formed in a chip formation field. FIG. 4 is a partially enlarged plan view showing an alignment mark formation region and a TEG region arranged in a dicing line region in the same embodiment. In the embodiment, it is a partial enlarged plan view showing an example of an alignment mark. FIG. 5 is a partial cross-sectional view taken along a cross-sectional line VV shown in FIG. 4 in the same embodiment. 4 is a partially enlarged plan view showing an example of an overlay inspection mark in the embodiment. FIG. FIG. 7 is a partial cross-sectional view taken along a cross-sectional line VII-VII shown in FIG. 6 in the same embodiment. 4 is a partial cross-sectional view schematically showing a relationship between a wiring structure of a semiconductor device in a chip formation region and a structure such as an alignment mark in a dicing line region in the embodiment. FIG. In the same embodiment, it is sectional drawing of the chip formation area which shows 1 process of the manufacturing method of a semiconductor device. FIG. 10 is a partial plan view of a dicing line region in the step shown in FIG. 9 in the embodiment. FIG. 11 is a partial plan view of a dicing line region showing a step performed after the step shown in FIG. 10 in the same embodiment. FIG. 12 is a partial cross-sectional view taken along a cross-sectional line XII-XII shown in FIG. 11 in the same embodiment. FIG. 12 is a partial cross-sectional view taken along a cross-sectional line XIII-XIII shown in FIG. 11 in the same embodiment. FIG. 14 is a first partial cross-sectional view of a dicing line region showing a process performed after the process shown in FIGS. 11 to 13 in the embodiment. FIG. 15 is a second partial cross-sectional view of a dicing line region in the step shown in FIG. 14 in the embodiment. FIG. 16 is a partial plan view of a dicing line region showing a process performed after the process shown in FIGS. 14 to 15 in the embodiment. FIG. 17 is a partial cross-sectional view taken along a cross-sectional line XVII-XVII shown in FIG. 16 in the same embodiment. FIG. 17 is a partial cross-sectional view taken along a cross-sectional line XVIII-XVIII shown in FIG. 16 in the same embodiment. FIG. 17 is a partial cross-sectional view of the chip formation region in the step shown in FIG. 16 in the same embodiment. FIG. 19 is a partial plan view of a dicing line region showing a process performed after the process shown in FIGS. 16 to 18 in the embodiment. FIG. 21 is a partial cross-sectional view taken along a cross-sectional line XXI-XXI shown in FIG. 20 in the same embodiment. FIG. 21 is a partial cross-sectional view taken along a cross-sectional line XXII-XXII shown in FIG. 20 in the same embodiment. FIG. 23 is a partial plan view of a dicing line region showing a process performed after the process shown in FIGS. 20 to 22 in the embodiment. FIG. 24 is a partial cross sectional view taken along a cross sectional line XXIV-XXIV shown in FIG. 23 in the same embodiment. FIG. 24 is a partial cross-sectional view taken along a cross-sectional line XXV-XXV shown in FIG. 23 in the same embodiment. FIG. 26 is a partial plan view of a dicing line region showing a process performed after the process shown in FIGS. 23 to 25 in the embodiment. FIG. 27 is a partial sectional view taken along a sectional line XXVII-XXVII shown in FIG. 26 in the embodiment. FIG. 27 is a partial cross-sectional view taken along a cross-sectional line XXVIII-XXVIII shown in FIG. 26 in the same embodiment. FIG. 29 is a partial plan view of a dicing line region showing a process performed after the process shown in FIGS. 26 to 28 in the embodiment. FIG. 30 is a partial cross sectional view taken along a cross sectional line XXX-XXX shown in FIG. 29 in the same embodiment. FIG. 30 is a partial cross sectional view taken along a cross sectional line XXXI-XXXI shown in FIG. 29 in the same embodiment. FIG. 32 is a partial plan view of a dicing line region showing a step performed after the step shown in FIGS. 29 to 31 in the embodiment. FIG. 33 is a partial cross sectional view taken along a cross sectional line XXXIII-XXXIII shown in FIG. 32 in the same embodiment. FIG. 33 is a partial cross sectional view taken along a cross sectional line XXXIV-XXXIV shown in FIG. 32 in the same embodiment. FIG. 35 is a partial plan view of a dicing line region showing a process performed after the process shown in FIGS. 32 to 34 in the embodiment. FIG. 36 is a partial cross sectional view taken along a cross sectional line XXXVI-XXXVI shown in FIG. 35 in the same embodiment. FIG. 36 is a partial cross sectional view taken along a cross sectional line XXXVII-XXXVII shown in FIG. 35 in the same embodiment. FIG. 38 is a partial plan view of a dicing line region showing a step performed after the step shown in FIGS. 35 to 37 in the same embodiment. FIG. 39 is a partial cross sectional view taken along a cross sectional line XXXIX-XXXIX shown in FIG. 38 in the same embodiment. FIG. 39 is a partial cross sectional view taken along a cross sectional line XL-XL shown in FIG. 38 in the same embodiment. FIG. 41 is a partial plan view of a dicing line region showing a step performed after the step shown in FIGS. 38 to 40 in the embodiment. FIG. 42 is a partial cross sectional view taken along a cross sectional line XLII-XLII shown in FIG. 41 in the same embodiment. FIG. 42 is a partial cross sectional view taken along a cross sectional line XLIII-XLIII shown in FIG. 41 in the same embodiment. FIG. 44 is a partial plan view of a dicing line region showing a step performed after the step shown in FIGS. 41 to 43 in the same embodiment. FIG. 45 is a partial cross sectional view taken along a cross sectional line XLV-XLV shown in FIG. 44 in the same embodiment. FIG. 45 is a partial cross sectional view taken along a cross sectional line XLVI-XLVI shown in FIG. 44 in the same embodiment. FIG. 47 is a partial cross-sectional view of the chip formation region in the steps shown in FIGS. 44 to 46 in the embodiment. FIG. 47 is a partial plan view of a chip formation region in the process shown in FIGS. 44 to 46 in the embodiment. FIG. 47 is a partial plan view of a dicing line region showing a step performed after the step shown in FIGS. 44 to 46 in the same embodiment. FIG. 50 is a partial cross sectional view taken along a cross sectional line LL shown in FIG. 49 in the same embodiment. FIG. 50 is a partial cross sectional view taken along a cross sectional line LI-LI shown in FIG. 49 in the same embodiment. FIG. 52 is a partial plan view of a dicing line region showing a process performed after the process shown in FIGS. 49 to 51 in the embodiment. FIG. 53 is a partial cross sectional view taken along a cross sectional line LIII-LIII shown in FIG. 52 in the same embodiment. FIG. 53 is a partial cross sectional view taken along a cross sectional line LIV-LIV shown in FIG. 52 in the same embodiment. In the same embodiment, it is a top view which shows the alignment mark which concerns on a 1st modification. FIG. 56 is a cross sectional view taken along a cross sectional line LVI-LVI shown in FIG. 55 in the same embodiment. In the same embodiment, it is a top view showing the alignment mark concerning the 2nd modification. FIG. 58 is a cross sectional view taken along a cross sectional line LVIII-LVIII shown in FIG. 57 in the same embodiment. FIG. 58 is a cross sectional view taken along a cross sectional line LIX-LIX shown in FIG. 57 in the embodiment. FIG. 58 is a cross sectional view taken along a cross sectional line LX-LX shown in FIG. 57 in the same embodiment. In the same embodiment, it is a top view which shows the alignment mark which concerns on a 3rd modification. FIG. 62 is a cross sectional view taken along a cross sectional line LXII-LXII shown in FIG. 61 in the embodiment. FIG. 6 is a perspective view schematically showing a positional relationship among magnetoresistive elements, digit lines, and bit lines in a memory cell of a semiconductor magnetic memory device according to a second embodiment of the present invention. 2 is a diagram showing a circuit configuration of a semiconductor magnetic memory device in the same embodiment. FIG. 4 is a partial cross-sectional view showing a cross-sectional structure of each of a memory cell region and a dummy memory cell region in the same embodiment. FIG. 4 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing one step in the method of manufacturing the semiconductor magnetic memory device in the same embodiment. FIG. FIG. 67 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 66 in the embodiment. FIG. 68 is a partial cross-sectional perspective view of the memory cell region and the dummy memory cell region, showing a step performed after the step shown in FIG. 67 in the same Example; FIG. 69 is a partial plan view showing the arrangement of local vias in the memory cell region in the step shown in FIG. 68 in the embodiment. FIG. 69 is a partial plan view showing the arrangement of dummy local vias in the dummy memory cell region in the step shown in FIG. 68 in the embodiment. FIG. 69 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 68 in the embodiment. FIG. 72 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 71 in the same Example; FIG. 73 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 72 in the embodiment. FIG. 74 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 73 in the embodiment. FIG. 75 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 74 in the embodiment. FIG. 76 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 75 in the embodiment. FIG. 77 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 76 in the embodiment. FIG. 78 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 77 in the same Example; FIG. 79 is a partial plan view showing the arrangement of local vias in the memory cell region in the step shown in FIG. 78 in the embodiment. FIG. 79 is a partial plan view showing the arrangement of dummy local vias in the dummy memory cell region in the step shown in FIG. 78 in the embodiment. FIG. 79 is a partial cross-sectional perspective view of a memory cell region and a dummy memory cell region, showing a step performed after the step shown in FIG. 78 in the embodiment. In each embodiment, it is a figure which shows the tendency of various patterns and corrosion.

Embodiment 1
Here, a semiconductor device provided with alignment marks and overlay inspection marks formed by subjecting a copper film to chemical mechanical polishing will be described. As shown in FIG. 1, on a semiconductor substrate (wafer) SUB, chip formation regions CPR where semiconductor elements and the like are formed are arranged in a matrix, and between adjacent chip formation regions CPR and chip formation regions CPR. A dicing line region DL is disposed.

  In the chip formation region CPR, as shown in FIG. 2, a semiconductor device having a multilayer wiring structure is formed. As the multilayer wiring structure, an element / substrate layer ESL, a fine layer FL, a semi-global layer SGL, a global layer GL, and the like are formed. As will be described later, in the element / substrate layer ESL, a TEOS film and a low dielectric constant film are laminated as an interlayer insulating film, and in the fine layer FL, an extremely low dielectric constant film or the like is laminated. In addition, a low dielectric constant film or the like is laminated in the semi-global layer SGL, and a non-low dielectric constant film or the like is laminated in the global layer GL.

  On the other hand, as shown in FIG. 1, an alignment mark formation region AMR in which alignment marks are formed and an overlay inspection mark formation region KMR in which overlay inspection marks are formed are arranged in the dicing line region DL. . The alignment mark formation area AMR and the overlay inspection mark formation area KMR are arranged in predetermined areas for each corresponding photoengraving process. The relationship between the structure of the alignment mark and overlay inspection mark and the wiring structure of the chip formation region CPR will be described later. In the dicing line region DL, in addition to the alignment mark formation region AMR and the overlay inspection mark formation region KMR, for example, a TEG region TR in which a TEG (Test Element Group) for evaluating electrical characteristics and the like is formed is arranged. Has been.

  As shown in FIG. 3, in the alignment mark formation area AMR, in order to ensure alignment accuracy in the photoengraving process, a pattern prohibition area AFP that prohibits the formation of patterns other than the alignment mark AM including the dummy pattern is provided. It arrange | positions so that the alignment mark AM may be surrounded. As an example of the alignment mark, FIG. 4 and FIG. 5 show the structure of the alignment mark used when forming a wiring groove or the like of the fine layer FL (see FIG. 2). As shown in FIG. 4, the alignment mark AM is, for example, a pattern in which strip-like linear patterns having a predetermined width are arranged at intervals. In this semiconductor device, each of the strip-shaped patterns forming the alignment mark AM is fixed to the ground potential by being electrically connected to a predetermined impurity region in the semiconductor substrate SUB as shown in FIG.

  Next, as an example of the overlay inspection mark, FIGS. 6 and 7 show the structure of the overlay inspection mark used when forming a wiring groove or the like of the fine layer FL (see FIG. 2). As shown in FIGS. 6 and 7, in the overlay inspection mark formation region KMR, a pattern other than the overlay inspection mark KM is formed including a dummy pattern in order to ensure overlay inspection accuracy of the patterned resist PR. A prohibited pattern area KFP is arranged so as to surround the overlay inspection mark KM.

  The overlay inspection mark KM is a pattern in which a strip-like linear pattern having a predetermined width is arranged in a rectangular shape. The overlay inspection mark KM is also fixed to the ground potential by being electrically connected to a predetermined impurity region in the semiconductor substrate SUB. As shown in FIG. 6, the overlay inspection is performed by measuring the relative positional relationship of the blank pattern NP formed on the developed resist PR with respect to the overlay inspection mark KM.

  In contrast to the alignment mark formation area AMR and overlay inspection mark formation area KMR where the pattern prohibition areas AFP and KFP are arranged, in the TEG area TR, as shown in FIG. A dummy pattern DPL having a large size and a dummy pattern DPS having a relatively small size are arranged. The dummy patterns DPL and DPS are provided in order to ensure the flatness of the base after the polishing process during the chemical mechanical polishing process.

  Next, the relationship between the wiring structure of the chip formation region CPR and the structure of the alignment mark AM and the overlay inspection mark KM will be described. As shown in FIG. 8, in the chip formation region CPR, the fine layer FL is formed so as to be in contact with the element / substrate layer ESL, and the semi-global layer SGL is formed so as to be in contact with the fine layer FL. A global layer GL or the like is formed so as to be in contact with the semi-global layer SGL.

  In the element / substrate layer ESL, for example, a TEOS film TE is formed so as to cover the semiconductor substrate SUB, and a low dielectric constant film LOW1 having a low dielectric constant is formed so as to be in contact with the TEOS film TE. In the wiring groove formed in the low dielectric constant film LOW1, the wiring M1 is formed as the lowermost wiring by a chemical mechanical polishing process. In the fine layer FL, a liner film FLL1 such as a silicon nitride film and an extremely low dielectric constant film ELK1 having a lower dielectric constant are alternately laminated. In the via hole and the wiring groove formed in the extremely low dielectric constant film ELK1, for example, the via V1 and the wiring M2 are formed by chemical mechanical polishing.

  In the semi-global layer SGL, a liner film SLL such as a silicon nitride film and a low dielectric constant film LOW2 having a low dielectric constant are alternately stacked. In the via hole and the wiring groove formed in the low dielectric constant film LOW2, for example, a via V5 and a wiring M6 are formed by a chemical mechanical polishing process. In the global layer GL, for example, liner films GLL such as silicon nitride films and insulating films GTE such as TEOS films or plasma silicon oxide films are alternately stacked. For example, a via V7 and a wiring M8 are formed in the via hole and the wiring groove formed in the insulating film GTE by a chemical mechanical polishing process.

  On the other hand, in the dicing line region DL, alignment marks AM and overlay inspection marks KM used in each photoengraving process when forming a multilayer wiring structure or the like are formed in predetermined regions. In FIG. 8, for simplification of the drawing, the alignment mark AM and the overlay inspection mark KM are represented by one cross-sectional pattern. The alignment mark AM and the overlay inspection mark KM are sequentially formed in accordance with the process of forming the multilayer wiring structure.

  In particular, in this semiconductor device, the opening as a concave portion of each of the low dielectric constant film LOW1 of the element / substrate layer ESL, the extremely low dielectric constant film ELK1 of the fine layer FL, and the low dielectric constant film LOW2 of the semiglobal layer SGL, etc. The alignment mark AM and the overlay inspection mark KM formed on the part are fixed to the ground potential by being electrically connected to an impurity region IR of a predetermined conductivity type formed on the semiconductor substrate SUB.

  Since these alignment mark AM and overlay inspection mark KM are fixed to the ground potential, the deposition of copper on the alignment mark AM and overlay inspection mark KM is suppressed after the chemical mechanical polishing process is performed. be able to. On the other hand, the alignment mark AM and the overlay inspection mark KM formed in the opening of the insulating film GTE such as the TEOS film or the plasma silicon oxide film are not necessarily fixed to the ground potential. These will be described in detail later.

  Next, an example of a method for manufacturing the semiconductor device described above will be described. First, as shown in FIG. 9, a predetermined semiconductor element such as a transistor such as NMOS (Negative-channel Metal Oxide Semiconductor) or PMOS (Positive-channel Metal Oxide Semiconductor) is formed in the chip formation region on the main surface of the semiconductor substrate. For example, a TEOS film TE is formed so as to cover the semiconductor element. By subjecting the TEOS film TE to predetermined photolithography and etching, a contact hole CH is formed in the chip formation region CPR. On the other hand, as shown in FIG. 10, in the alignment mark formation region AMRM1 in the dicing line region DL, an opening AHM1 in which an alignment mark for patterning the wiring groove of the wiring M1 is formed. In the overlay inspection mark formation region KMRM1, an opening KHM1 in which the overlay inspection mark is to be formed is formed.

  Next, a barrier metal layer and a tungsten film (both not shown) are formed so as to cover the TEOS film TE so as to fill the contact hole CH and the openings AHM1 and KHM1. Next, by etching the entire surface of the tungsten film or the like to remove the tungsten film or the like located on the upper surface of the TEOS film, the plug PG is formed in the contact hole CH in the chip formation region CPR. On the other hand, the alignment mark AMM1 is formed in the alignment mark formation area AMRM1 in the dicing line area DL, and the overlay inspection mark KMM1 is formed in the overlay inspection mark formation area KMRM1.

  At this time, in the alignment mark formation region AMRV1, a conductor portion that electrically connects an alignment mark formed in a later process and the impurity region of the semiconductor substrate is formed, and in the overlay inspection mark formation region KMRV1 A conductor portion for electrically connecting the overlay inspection mark and the impurity region of the semiconductor substrate is formed.

  Next, a low dielectric constant film LOW1 having a low dielectric constant is formed so as to be in contact with the TEOS film TE (see FIG. 12 and the like). Examples of the material for the low dielectric constant film LOW1 (LOW2) include SiOCH, MSQ (Methyl Silsesquioxane), and HSQ (Hydrogen Silsesquioxane). Next, a resist is applied so as to be in contact with the low dielectric constant film LOW1. Next, the resist is subjected to a photoengraving process for forming a wiring groove (wiring M1) based on the alignment mark AMM1 (see FIG. 10). Next, by developing the resist, an opening pattern (not shown) corresponding to the wiring groove (wiring M1) is formed in the resist in the chip formation region.

  On the other hand, as shown in FIGS. 11, 12, and 13, in the alignment mark formation region AMRV1 in the dicing line region DL, an opening pattern corresponding to the alignment mark (for via V1 formation) is formed in the resist RM1 and overlapped. In the inspection mark formation region KMRV1, an opening pattern corresponding to the overlay inspection mark (via V1) is formed. At this time, an opening pattern NRM1 is formed in the overlay inspection mark formation region KMRM1. The overlay inspection is performed by measuring the amount of deviation between the opening pattern NRM1 and the overlay inspection mark. If the amount of deviation is within a predetermined range, it is determined that the mask pattern is satisfactorily photoengraved on the resist. On the other hand, if the amount of deviation is outside the predetermined range, the resist is removed and the photoengraving process is performed again.

  Next, by etching the low dielectric constant film LOW1 using the resist RM1 as a mask, a wiring groove (not shown) is formed in the low dielectric constant film LOW1 in the chip formation region. On the other hand, in the alignment mark formation area AMVR1 in the dicing line area DL, an opening AHV1 in which an alignment mark (for via V1 formation) is to be formed is formed, and in the overlay inspection mark formation area KMRV1, an overlay inspection mark ( An opening KHV1 in which the via V1) is to be formed is formed (see FIG. 14 and the like).

  Next, as shown in FIGS. 14 and 15, a barrier metal layer BM1 is formed so as to be in contact with the low dielectric constant film LOW1, and further, the barrier metal layer BM1 is covered in such a manner as to fill the openings AHV1 and KHV1. Thus, for example, the copper film CUM1 is formed by a plating method or the like. Next, a portion of the copper film CUM1 located on the upper surface of the low dielectric constant film LOW1 is left by chemical mechanical polishing, leaving the portions of the barrier metal layer BM1 and the copper film CUM1 located in the openings AHV1 and KHV1. The portion of the barrier metal layer BM1 is removed.

  At this time, the polishing pressure is set to about 0.5 kPa to 45 kPa, for example, and the rotation speed of the table or polishing head on which the wafer is placed is set to about 50 to 150 rpm, for example. Further, when polishing the copper film CUM1 as an abrasive (slurry), acidic (ph <7.0) general abrasive grains are used, and when polishing the barrier metal layer BM1, it is acidic. A general abrasive grain (ph <7.0) is used. When the polishing process is completed, for example, a cleaning process combining cleaning with an acidic cleaning liquid and rinsing with pure water is performed on the surface of the wafer.

  Thus, as shown in FIGS. 16, 17, and 18, the alignment mark AMV1 (for via V1 formation) is formed in the alignment mark formation region AMRV1 in the dicing line region DL, and the overlay inspection mark formation region KMRV1 is overlaid. The alignment inspection mark KMV1 (for forming the via V1) is formed. On the other hand, as shown in FIG. 19, the wiring M1 and the like are formed in the chip formation region CPR.

  At this time, as shown in FIG. 20, FIG. 21, and FIG. 22, in alignment mark formation region AMRM2, there is a conductor portion that electrically connects the alignment mark formed in a later step and the impurity region of the semiconductor substrate. In the overlay inspection mark formation region KMRM2 formed, a conductor portion that electrically connects the overlay inspection mark and the impurity region of the semiconductor substrate is formed.

  Next, as shown in FIGS. 23, 24, and 25, a liner film FLL1 such as a silicon nitride film is formed so as to be in contact with the low dielectric constant film LOW1 (see FIG. 24 and the like). Next, an extremely low dielectric constant film ELK1 having a lower dielectric constant is formed so as to be in contact with the liner film FLL1. Examples of the material for the extremely low dielectric constant film ELK1 include porous SiOCH, porous MSQ, and porous HSQ. Porous materials are deposited by depositing a film-forming material containing porogen by chemical vapor deposition or coating, and then performing a curing process using heat, ultraviolet (UV), electron beam (EB), or plasma treatment. The porogen is desorbed from the film forming material, and a large number of holes are formed in the film forming material. The pore diameter of the pores formed by desorption of the porogen is larger than the pore diameter of the pores of the material itself such as SiOCH, MSQ, or HSQ. Porous SiOCH is a material for a low dielectric constant film. The dielectric constant is lower than that of SiOCH or the like.

  Next, a resist is applied so as to be in contact with the extremely low dielectric constant film ELK1. Next, the resist is subjected to a photoengraving process for forming a via hole (via V1) based on the alignment mark AMV1 (see FIG. 20). Next, by performing development processing on the resist, an opening pattern (not shown) corresponding to the via hole (via V1) is formed in the resist in the chip formation region.

  On the other hand, in the alignment mark formation area AMRM2 in the dicing line area DL, an opening pattern corresponding to the alignment mark (for forming the wiring M2) is formed in the resist RV1, and in the overlay inspection mark formation area KMRM2, the overlay is formed on the resist RV1. An opening pattern corresponding to the inspection mark (for forming the wiring M2) is formed. At this time, an opening pattern NRV1 is formed in the overlay inspection mark formation region KMRV1. As described above, overlay inspection is performed by measuring the amount of deviation between the opening pattern NRV1 and overlay inspection mark KMV1 (see FIG. 20).

  Next, by etching the ultra-low dielectric constant film ELK1 using the resist RV1 as a mask and removing the resist RV1, a part of the via exposing the liner film FLL1 to the ultra-low dielectric constant film ELK1 in the chip formation region (Not shown) is formed. Further, as shown in FIGS. 26, 27, and 28, in the alignment mark formation region AMRM2 in the dicing line region DL, an opening AHM2 in which the alignment mark (for forming the wiring M2) is formed is formed and overlapped. In the alignment inspection mark formation region KMRM2, an opening KHM2 where the overlay inspection mark (for forming the wiring M2) is to be formed is formed. At this time, the openings AHM2 and KHM2 are formed so as to expose the liner film FLL1.

  Next, a resist (not shown) is applied so as to be in contact with the extremely low dielectric constant film ELK in such a manner that a part of the via in the chip formation region and the openings AHM2 and KHM2 in the dicing line region DL are filled. Next, by applying an etch back process to the applied resist, in the chip formation region, the portion of the resist filled in a part of the via is left, and the resist located on the upper surface of the extremely low dielectric constant film ELK1 is left. Part is removed. In addition, as shown in FIGS. 29, 30 and 31, in the dicing line region DL, the resist portions (resist VR) filled in the openings AHM2 and KHM2 are left on the upper surface of the extremely low dielectric constant film ELK1. The portion of the resist located at is removed.

  At this time, as shown in FIG. 32, FIG. 33 and FIG. 34, in alignment mark formation region AMRV2, there is a conductor portion that electrically connects the alignment mark formed in the subsequent step and the impurity region of the semiconductor substrate. The opening to be formed is filled with the resist VR. In the overlay inspection mark formation region KMRV2, the resist VR is formed in the opening in which the conductor portion that electrically connects the overlay inspection mark and the impurity region of the semiconductor substrate is formed. Will be filled. Next, a resist is applied so as to be in contact with the extremely low dielectric constant film ELK1. Next, the resist is subjected to a photoengraving process for forming a wiring groove (for forming the wiring M2) based on the alignment mark AMM2 (see FIG. 30).

  Next, by developing the resist, an opening pattern (not shown) corresponding to the wiring groove (for forming the wiring M2) is formed in the resist in the chip formation region. As shown in FIGS. 35, 36, and 37, in the alignment mark formation region AMRV2 in the dicing line region DL, an opening pattern corresponding to the alignment mark (via V2) is formed in the resist RM2, and an overlay inspection mark is formed. In the formation region KMRV2, an opening pattern corresponding to the overlay inspection mark (via V2) is formed in the resist RM2. At this time, an opening pattern NRM2 is formed in the overlay inspection mark formation region KMRM2. As described above, overlay inspection is performed by measuring the amount of deviation between the opening pattern NRM2 and the overlay inspection mark.

  Next, the extremely low dielectric constant film ELK1 is etched using the resist RM2 as a mask, and the resist RM2 is removed, whereby a wiring groove (not shown) is formed in the extremely low dielectric constant film ELK1 in the chip formation region. The On the other hand, as shown in FIGS. 38, 39 and 40, in the alignment mark formation region AMRV2 in the dicing line region DL, an opening AHV2 in which the alignment mark (for via V2 formation) is to be formed is formed and overlapped. In the alignment inspection mark formation region KMRV2, an opening KHV2 in which an overlay inspection mark (for via V2 formation) is to be formed is formed. By this etching, the exposed portion of the liner film FLL1 is removed, and the conductor portion of the copper film formed on the low dielectric constant film LOW1 is exposed.

  Next, as shown in FIGS. 41, 42, and 43, a barrier metal layer BM2 is formed so as to be in contact with the extremely low dielectric constant film ELK1, and the barrier metal is filled with the openings AHV2 and KHV2. For example, a copper film CUM2 is formed by a plating method or the like so as to cover layer BM2. Next, a portion of the copper film CUM2 located on the upper surface of the ultra-low dielectric constant film ELK1, leaving the portions of the barrier metal layer BM2 and the copper film CUM2 located in the openings AHV2 and KHV2 by chemical mechanical polishing. And the portion of the barrier metal layer BM2 are removed. The polishing conditions at this time are set to substantially the same conditions as those described above.

  Thus, as shown in FIGS. 44, 45 and 46, the alignment mark AMV2 (for via V2 formation) is formed in the alignment mark formation region AMRV2 in the dicing line region DL, and the overlay inspection mark formation region KMRV2 is overlaid. An alignment inspection mark KMV2 (for forming via V2) is formed. On the other hand, as shown in FIG. 47, the via V1, the wiring M2, and the like are formed in the chip formation region CPR.

  At this time, as shown in FIG. 48, in the chip formation region CPR, for example, the power supply wiring PL, the signal line SL, and the like are formed as the wiring M2, and the TEG pattern TP is formed in a predetermined region. Further, a relatively small dummy pattern DPS and a relatively large dummy pattern DPL are formed around the TEG pattern TP. Dummy patterns DPS and DPL are also formed between the wirings M2. These dummy patterns DPS and DPL are electrically floating. In the chip formation region CPR, a large number of such electrically floating dummy patterns DSP and DPL are arranged, so that corrosion after the chemical mechanical polishing process is suppressed. FIG. 82 shows a summary regarding corrosion.

  Next, as shown in FIGS. 49, 50 and 51, for example, a liner film FLL2 such as a silicon nitride film is formed so as to be in contact with the extremely low dielectric constant film ELK1. Next, an extremely low dielectric constant film ELK2 is formed so as to be in contact with the liner film FLL2. Next, a resist is applied so as to be in contact with the extremely low dielectric constant film ELK2. Next, the resist is subjected to a photoengraving process for forming a via hole (via V2) based on the alignment mark AMV2 (see FIG. 44). Next, by developing the resist, an opening pattern (not shown) corresponding to the via hole (via V2) is formed in the resist in the chip formation region.

  On the other hand, as shown in FIGS. 52, 53, and 54, in the alignment mark formation region AMRM3 in the dicing line region DL, an opening pattern corresponding to the alignment mark (for forming the wiring M3) is formed in the resist RV2, and the overlapping is performed. In the inspection mark formation region KMRM3, an opening pattern corresponding to the overlay inspection mark (for forming the wiring M3) is formed in the resist RV2. Thereafter, by repeating the same process as the process of forming the via V1 and the wiring M2, a semiconductor device having the multilayer wiring structure shown in FIG. 2 and the like is formed.

  In the semiconductor device described above, among alignment marks and overlay inspection marks that are isolated patterns, in particular, alignment marks AM and overlay inspection marks KM formed on fine layer FL and semi-global layer SGL are fixed to the ground potential. As a result, it is possible to prevent the copper compound (copper hydroxide) from being deposited on the alignment mark AM and the overlay inspection mark KM after the chemical mechanical polishing treatment.

  This will be described. As described above, in the alignment mark AM and the overlay inspection mark KM, an opening corresponding to the alignment mark or the overlay inspection mark is formed in the very low dielectric constant film ELK or the low dielectric constant film LOW2, etc. It is formed by performing a chemical mechanical polishing process on a copper film or the like formed so as to cover the film in a mode of filling the opening.

An insulating film such as porous SiOCH, porous MSQ, or porous HSQ, which is a material such as an extremely low dielectric constant film ELK1, or a material such as SiOCH, MSQ or HSQ, which is a material such as a low dielectric constant film LOW2. All the insulating films have a methyl group (—CH ₃ ) and exhibit water repellency. The extremely low dielectric constant film ELK1 and the like having more methyl groups than the low dielectric constant film LOW2 and the like exhibit stronger water repellency. On the other hand, the surface of the copper film that has been subjected to the chemical mechanical polishing treatment is hydrophilic.

  Then, in the alignment mark or overlay inspection mark formed by performing chemical mechanical polishing, a low dielectric constant film that exhibits water repellency so as to surround the periphery of the isolated hydrophilic alignment mark or overlay inspection mark Or an extremely low dielectric constant film. For this reason, in the hydrophilic alignment mark or overlay inspection mark, the adsorption of moisture to the end thereof is promoted, and there is a possibility that it is strongly influenced by oxygen (oxidant) contained in the moisture. In addition, the oxygen constituting the low dielectric constant film or the ultra low dielectric constant film becomes an oxidizing agent, and the end portion of the alignment mark or overlay inspection mark in contact with the low dielectric constant film or the ultra low dielectric constant film is May be strongly affected.

  Furthermore, the cleanliness of the surface of low-permittivity and ultra-low-permittivity films that are water-repellent can be reduced to the cleanliness of the surface of alignment marks and overlay inspection marks that are hydrophilic by cleaning in chemical mechanical polishing. It is difficult to increase the concentration, and the concentration of impurities remaining after the chemical mechanical polishing treatment tends to increase on the surface of the low dielectric constant film or the extremely low dielectric constant film. For this reason, the edge part of the alignment mark or overlay inspection mark that is in contact with the low dielectric constant film or extremely low dielectric constant film can be strongly influenced by impurities remaining in the low dielectric constant film or extremely low dielectric constant film. There is sex.

  For these reasons, the inventors have found that in the precipitation of the copper compound, oxygen in the atmosphere (factor 1) contained in the moisture adsorbed on the wafer, the very low dielectric constant film ELK, the low dielectric constant film LOW2, etc. It was considered that oxygen (factor 2) and impurities remaining on the surface of the wafer after the chemical mechanical polishing process (factor 3) were involved in combination.

  According to the knowledge obtained by the inventors, the phenomenon (reaction) in which copper precipitates is represented by the following chemical reaction formula.

^{Cu (s) → Cu 2+ +} 2e (aq.) - ··········· ( Formula 1)
O ₂ (aq.) + H ₂ O + 2e ⁻ → 2OH ⁻ (aq.) (Chemical formula 2)
^{Cu 2+ + 2OH (aq.)} - (. Aq) → Cu (OH) 2 (s) ↓ ·· ( of 3)
The chemical reaction formula (Chemical Formula 1) is a reaction at the anode where copper (Cu) is oxidized by adsorbed water (H ₂ O). At the anode, solid copper (Cu (s)) emits electrons and becomes divalent Cu ²⁺ ions (Cu ²⁺ (aq.)) And diffuses in water. The chemical reaction formulas (Chemical Formula 2, Chemical Formula 3) are reactions at the cathode where copper (Cu) is deposited. Electrons (e ⁻ ) emitted in the oxidation process shown in the chemical reaction formula (Chemical Formula 1) are copper (Cu ₂ ) in which dissolved oxygen (O ₂ (aq.)) In water and water (H ₂ O) are in contact with each other. ) To the site (cathode) of (), and a reduction (OH ⁻ (aq.)) Reaction of dissolved oxygen (O ₂ (aq.)) To hydroxide ions occurs. When Cu ²⁺ ions (Cu ²⁺ (aq.)) Diffused in water reach the cathode, they react with hydroxide ions (OH ⁻ (aq.)) To form a copper compound (Cu (OH ) ₂ ) precipitates and will precipitate.

  In the semiconductor device described above, the alignment mark and overlay inspection mark formed on the fine layer FL and the semi-global layer SGL are fixed to the ground potential. Thereby, electrons are supplied to the alignment mark and overlay inspection mark formed from copper, and copper oxidation (Chemical Formula 1) among the chemical reaction formulas (Chemical Formula 1) to (Chemical Formula 3) is suppressed. Become. As a result, the reaction (Chemical Formula 3) in which a copper compound (copper hydroxide) precipitates on the surfaces of the alignment mark and overlay inspection mark can be suppressed.

  By suppressing the precipitation of the copper compound on the surface of the alignment mark AM, it is possible to prevent the alignment accuracy in the photolithography process from deteriorating. Further, since the copper compound is prevented from being deposited on the surface of the overlay inspection mark KM, it is possible to prevent the overlay inspection accuracy of the patterned resist from being deteriorated.

  On the other hand, in the global layer GL, a TEOS film or a plasma silicon oxide film is formed as an interlayer insulating film. The water repellency of this type of interlayer insulating film is not as high as the water repellency of the low dielectric constant film LOW1 or the like or the extremely low dielectric constant film ELK1. For this reason, a copper compound hardly deposits on the alignment mark or overlay inspection mark of the global layer GL, and it is considered that it is not always necessary to fix the alignment mark or the like to the ground potential.

  In the semiconductor device manufacturing method described above, the case where the alignment mark (AMRM2, AMM2) for forming the wiring M2 is formed in the step of forming the via hole for the via V1 has been described as an example. In the step of forming the wiring M1, both an alignment mark for forming a via hole for the via V1 and an alignment mark for forming the wiring M2 may be formed.

  In the above-described embodiment, it has been described that the TEG region TR and the like are arranged in the dicing line region DL in addition to the alignment mark formation region AMR. When the TEG area is arranged next to the alignment mark formation area, assuming that a TEG area in which no dummy pattern is arranged around the TEG pattern is assumed, the pattern inhibition area and the TEG area in the alignment mark formation area are assumed. Are adjacent to the TEG pattern.

  At this time, since the alignment mark itself is at the ground potential, the precipitation of the copper compound is suppressed. On the other hand, in the TEG pattern, a copper compound is precipitated by the reactions (Chemical Formula 1) to (Chemical Formula 3). Therefore, when arranging the TEG region next to the alignment mark formation region, for example, as shown in FIG. 3, between the pattern inhibition region AFP in the alignment mark formation region AMR and the TEG pattern TP in the TEG region TR, The dummy patterns DPS and DPL should be arranged to suppress copper compound precipitation.

  The semiconductor device having the multilayer wiring structure described above is divided into a plurality of semiconductor chips by cutting the wafer using a dicing blade or the like in the dicing line region. In the finished semiconductor chip (semiconductor device), a part of the dicing line region remains. For this reason, a part of the alignment mark formation region, the TEG region, the dummy pattern, and the like may remain in a part of the dicing line region left on the semiconductor chip. Conversely, some or all of the alignment mark formation region, TEG region, dummy pattern, etc. may not remain.

  Further, in the above-described embodiment, the case where the alignment mark for forming both the wiring layer using the low dielectric constant film and the wiring layer using the extremely low dielectric constant film is connected to the ground potential is described. However, in particular, only an alignment mark for forming a wiring layer using an extremely low dielectric constant film, in which copper deposition is a greater problem, may be connected to the ground potential. In this case, a conventional alignment mark can be used for the wiring layer using the low dielectric constant film, and the design cost can be reduced and the period can be shortened.

Alignment mark modification 1
In the above-described semiconductor device, the structure of the alignment mark fixed to the ground potential has been described by taking as an example a structure in which conductor portions electrically connected to the impurity regions of the semiconductor substrate are sequentially formed. The structure for fixing the alignment mark to the ground potential is not limited to this structure. For example, as shown in FIGS. 55 and 56, an alignment mark AMH1 that is electrically connected to the guard ring GR may be formed.

  The guard ring GR is a conductor that is sequentially formed according to the manufacturing process so as to surround the chip formation region CPR, and is fixed to the ground potential. Also by electrically connecting the alignment mark AMH1 to such a guard ring GR, it is possible to suppress the deposition of copper on the surface of the alignment mark AMH1.

Alignment mark modification 2
Also, in order to prevent burrs during dicing in the dicing line region, it is not electrically connected to the guard ring portion located in the layer where the alignment mark is formed, but below the layer where the alignment mark is located. You may make it electrically connect to the part of the guard ring located in a layer.

  For example, as shown in FIG. 57, FIG. 58, FIG. 59, and FIG. 60, the alignment mark AMH2 formed on the extremely low dielectric constant film ELK is placed on the guard ring portion (GR ( M1)) may be electrically connected. By using such an alignment mark AMH2, it is possible to prevent copper from being deposited on the surface of the alignment mark AMH2, and to take measures against burrs during dicing.

Modification 3 of alignment mark
Further, as the alignment marks, a plurality of patterns each extending in a strip shape are described as examples in which both the width and the length are set to the same dimension. The alignment mark is not limited to this. For example, as shown in FIG. 61 and FIG. 62, the patterns extending in a strip shape have different widths and lengths (widths W1, W2, length). An alignment mark AMH3 including a pattern set in (L1, L2) may be used.

Embodiment 2
Here, a semiconductor magnetic memory device having a magnetoresistive element will be described as an example of a semiconductor device having vias formed by a single damascene method.

  As shown in FIG. 63, in the memory cell MC of the semiconductor magnetic memory device, the magnetoresistive element TMR includes a digit line DIL extending in one direction and a bit line BL extending in a direction substantially orthogonal thereto. It is formed in an array shape in such a manner that it is arranged in the portion to be. As shown in FIG. 64, around the memory cell region MR in which the memory cell MC is formed, a dummy memory cell region DMR in which the dummy memory cell DMC is formed is arranged so as to surround the memory cell region MR. . In the region outside the dummy memory cell region DMR, a column decoder region CDR, a sense amplifier region SA, a row decoder region LDR, and the like are arranged as peripheral circuit regions.

  Next, the structures of the memory cell region MR and the dummy memory cell region DMR will be described respectively. As shown in FIG. 65, in the memory cell region MR, a digit line DIL is disposed below the magnetoresistive element TMR, and a bit line BL is disposed above the magnetoresistive element TMR. One end side of the magnetoresistive element TMR is electrically connected to the bit line BL via a top via TV formed by a single damascene method. The other end side of the magnetoresistive element TMR is electrically connected to one end side of the strap wiring STL. The other end side of the strap wiring STL is electrically connected to the read line REL via a local via LV formed by a single damascene method. The read line REL is electrically connected to the drain region of the element selection transistor TM through a plurality of vias or the like in the multilayer wiring structure.

  In each magnetoresistive element TMR, two magnetic layers are laminated with a tunnel insulating film interposed therebetween. The resistance value of the magnetoresistive element varies depending on whether the magnetization directions of the two magnetic layers are the same or opposite to each other. The direction of magnetization of the magnetoresistive element can be changed by a magnetic field generated by passing a predetermined current through the bit line BL and the digit line DIL. In the semiconductor magnetic memory device, this difference in resistance value is used as information corresponding to “0” or “1”.

  On the other hand, in the dummy memory cell region DMR, dummy magnetoresistive elements DTMR are arranged on one end side and the other end side of one dummy strap wiring DSTL. A dummy top via DTV formed by a single damascene method is formed immediately above each dummy magnetoresistive element DTMR. A dummy bit line DBL is formed above the dummy top via DTV.

  A dummy local via DLV formed by a single damascene method is formed immediately below each dummy magnetoresistive element DTMR. A dummy digit line DDIL is formed immediately below one dummy local via DLV, and a dummy read line DREL is formed immediately below the other dummy local via DLV. The dummy read line DREL is not electrically connected to the element selection transistor. For this reason, the dummy local via DLV and the dummy top via DTV are electrically floating.

  Thus, in this semiconductor magnetic memory device, one memory cell MC in the memory cell region MR is formed with one magnetoresistive element TMR, one local via LV, and one top via TV. Thus, two dummy magnetoresistive elements DTMR, two dummy local vias DLV, and two dummy top vias DTV are formed in one dummy memory cell DMC in the dummy memory cell region DMR.

  That is, in the present semiconductor magnetic memory device, when the ratio of the via occupation area to the unit area is the via occupation ratio, the via occupation ratio is higher than the via occupation ratio in the memory cell region MR so as to surround the memory cell region MR. A dummy memory cell region DMR is arranged. By forming a dummy via having a via occupation ratio higher than the via occupation ratio for the via in the memory cell region MR, a copper compound is formed on the surface of the via of the memory cell that is required to function as a memory cell. Precipitation can be suppressed. This will be described later.

  Next, an example of a manufacturing method of the above-described semiconductor magnetic memory device will be described. As shown in FIG. 65, predetermined semiconductor elements including element selection transistors TM and the like are formed on the surface of the semiconductor substrate SUB, and a multilayer wiring structure is formed so as to cover the semiconductor elements. For example, the manufacturing method described in the first embodiment may be applied to the multilayer wiring structure.

Thereafter, as shown in FIG. 66, silicon oxide film 2 is formed so as to cover semiconductor substrate SUB. Wiring grooves 2 a and 2 b are formed in predetermined regions in the silicon oxide film 2.
In the memory cell region MR, a read line REL composed of the cladding layer 4a and the copper film 4b is formed in the wiring groove 2a. A digit line DIL composed of the cladding layer 3a and the copper film 3b is formed in the wiring groove 2b. On the other hand, in the dummy memory cell region DMR, a dummy read line DREL composed of the cladding layer 4a and the copper film 4b is formed in the wiring trench 2a. A dummy digit line DDIL composed of the cladding layer 3a and the copper film 3b is formed in the wiring groove 2b.

  Next, a liner film LL such as a silicon nitride film is formed in contact with the silicon oxide film 2 so as to cover the digit line DIL, the read line REL, the dummy digit line DDIL, and the dummy read line DREL. A low dielectric constant film LOWA is formed in contact with the liner film LL. In the drawings showing the subsequent steps, the semiconductor substrate SUB is omitted for simplification of the drawing.

  Next, as shown in FIG. 67, in the memory cell region MR, a local via hole LVH that penetrates the low dielectric constant film LOWA and the liner film LL and exposes the read line REL is formed. On the other hand, in the dummy memory cell region DMR, a dummy local via hole DLVH that exposes the read line REL and a dummy local via hole DLVH that exposes the dummy digit line DDIL are formed through the low dielectric constant film LOWA and the liner film LL. Is done. Next, a barrier metal layer BMA is formed so as to be in contact with the low dielectric constant film LOWA so as to cover the bottom and side walls of the local via hole LVH and the dummy local via hole DLVH. Next, a copper film CUA is formed by plating or the like so as to contact the barrier metal layer BMA.

  Next, the copper located on the upper surface of the low dielectric constant film LOWA is left by the chemical mechanical polishing process, leaving portions of the barrier metal layer BMA and the copper film CUA located in the local via hole LVH and the dummy local via hole DLVH. The part of the film CUA and the part of the barrier metal layer BMA are removed. At this time, the polishing pressure is set to about 0.5 kPa to 45 kPa, for example, and the rotation speed of the table or polishing head on which the wafer is placed is set to about 50 to 150 rpm, for example. Further, when polishing the copper film CUM1 as an abrasive (slurry), acidic (ph <7.0) general abrasive grains are used, and when polishing the barrier metal layer BM1, it is acidic. A general abrasive grain (ph <7.0) is used. When the polishing process is completed, for example, a cleaning process combining cleaning with an acidic cleaning liquid and rinsing with pure water is performed on the surface of the wafer.

  Thus, as shown in FIG. 68, in the memory cell region MR, a local via LV composed of the barrier metal layer BMA and the copper film CUA is formed in the local via hole LVH. On the other hand, in the dummy memory cell region DMR, a dummy local via DLV composed of the barrier metal layer BMA and the copper film CUA is formed in the dummy local via hole DLVH.

  In this case, as shown in FIGS. 69 and 70, the via occupancy of the dummy local via DLV in the dummy memory cell region DMR is higher than the via occupancy of the local via LV in the memory cell region MR, and is about twice as high. Become. Thus, after the chemical mechanical polishing process is performed, a copper compound is sacrificially deposited on the surface of the dummy local via DLV having a higher via occupancy rate, so that a memory cell region is required to function as a memory cell. Precipitation of copper compounds on the surface of the local via LV in MR can be suppressed.

  Next, as shown in FIG. 71, for example, a tantalum (Ta) film 12 serving as a strap wiring is formed so as to be in contact with the low dielectric constant film LOWA. Next, a predetermined film (not shown) to be a pinned layer is formed on the tantalum film 12. As the predetermined film, for example, a laminated film containing platinum (Pt), manganese (Mn), nickel (Ni), ruthenium (Ru), cobalt (Co), iron (Fe), and boron (B) is formed. . Next, a tunnel insulating film (not shown) is formed on the predetermined film that becomes the pinned layer. As the tunnel insulating film, for example, an aluminum oxide (AlOx) film or a magnesium oxide (MgO) film is formed.

  Next, a predetermined film to be a free layer is formed on the tunnel insulating film. As the predetermined film, for example, an alloy film containing at least two metals among nickel (Ni), iron (Fe), cobalt (Co), and boron (B) is formed. Next, a predetermined film (not shown) serving as a cap layer is formed on the predetermined film serving as a free layer. For example, a ruthenium (Ru) film is formed as the predetermined film to be the cap layer. A tantalum (Ta) film (not shown) is formed on a predetermined film serving as the cap layer. Next, a resist pattern (not shown) for patterning the magnetoresistive element is formed on the tantalum (Ta) film.

  Next, using the resist pattern as a mask, a tantalum (Ta) film, a predetermined film serving as a cap layer, a predetermined film serving as a free layer, a tunnel insulating film, and a predetermined film serving as a pinned layer are subjected to predetermined conditions. As shown in FIG. 72, the pinned layer 13, the tunnel insulating film 14, the free layer 15, the cap layer 16, and the tantalum (Ta) film 17 are patterned, and in the memory cell region MR, as shown in FIG. Element TMR is formed, and dummy magnetoresistive element DTMR is formed in dummy memory cell region DMR.

  Next, as shown in FIG. 73, a silicon nitride film 19 is formed as a liner film so as to be in contact with the tantalum (Ta) film 12 so as to cover the magnetoresistive element TMR and the dummy magnetoresistive element DTMR. Next, a resist pattern (not shown) for patterning the strap wiring is formed on the silicon nitride film 19. Next, by using the resist pattern as a mask, the silicon nitride film 19 and the tantalum (Ta) film 12 are etched under predetermined conditions, so that the strap wiring is formed in the memory cell region MR as shown in FIG. An STL is formed, and a dummy strap wiring DSTL is formed in the dummy memory cell region DMR. Next, as shown in FIG. 75, a low dielectric constant film LOWB is formed so as to cover the silicon nitride film 19.

  Next, a resist pattern (not shown) for forming a top via hole is formed on the low dielectric constant film LOWB. Next, using the resist pattern as a mask, the low dielectric constant film LOWB and the silicon nitride film 19 are etched under a predetermined condition, so that a magnetoresistive element is formed in the memory cell region MR as shown in FIG. A top via hole TVH that exposes the TMR is formed, and a dummy top via hole DTVH that exposes the dummy magnetoresistive element DTMR is formed in the dummy memory cell region DMR.

  Next, as shown in FIG. 77, a barrier metal layer BMB is formed so as to be in contact with the low dielectric constant film LOWB in such a manner as to cover the bottom and side walls of the top via hole TVH and the dummy top via hole DTVH. A copper film CUB is formed by plating or the like so as to be in contact with the barrier metal layer BMB.

  Next, the copper located on the upper surface of the low dielectric constant film LOWB is left by chemical mechanical polishing, leaving the portions of the barrier metal layer BMB and the copper film CUB located in the top via hole TVH and the dummy top via hole DTVH. The part of the film CUB and the part of the barrier metal layer BMB are removed. At this time, the polishing conditions are preferably substantially the same as the polishing conditions for forming the local via LV and the like.

  Thus, as shown in FIG. 78, in the memory cell region MR, a top via TV composed of the barrier metal layer BMB and the copper film CUB is formed in the top via hole TVH. On the other hand, in the dummy memory cell region DMR, a dummy top via DTV including a barrier metal layer BMB and a copper film CUB is formed in the dummy top via hole DTVH.

  In this case, as shown in FIGS. 79 and 80, the via occupancy of the dummy top via DTV in the dummy memory cell region DMR is higher than the via occupancy of the top via TV in the memory cell region MR, and is about double. Become. Thus, after performing chemical mechanical polishing, a copper compound is sacrificed on the surface of the dummy top via DTV having a higher via occupancy rate, so that a memory cell region is required to function as a memory cell. Precipitation of copper compounds on the surface of the top via TV in MR can be suppressed.

  Next, as shown in FIG. 81, the bit line BL is formed in the memory cell region MR, and the dummy bit line DBL is formed in the dummy memory cell region DMR. Thereafter, a predetermined insulating film or the like is formed so as to cover bit line BL and dummy bit line DBL, and the semiconductor magnetic memory device shown in FIG. 65 is completed.

  In the above-described semiconductor magnetic memory device, the dummy memory cell region DMR is disposed so as to surround the memory cell region MR, so that after the chemical mechanical polishing process is performed, a copper compound ( Precipitation of copper hydroxide) can be suppressed.

  As described above, an isolated pattern of a copper film such as a via formed by subjecting a copper film to a chemical mechanical polishing process is strongly influenced by an oxidizing agent (oxygen) or the like. Also, in the cleaning after the chemical mechanical polishing process, the surface of the hydrophilic via surrounded by the low dielectric constant film or the extremely low dielectric constant film exhibiting water repellency is accompanied by the chemical mechanical polishing process. Easily corroded by residual impurities. As the occupation area (pattern occupation ratio) per unit area of an isolated pattern surrounded by a low dielectric constant film or the like increases, the degree of corrosion of the isolated pattern tends to increase.

  In the above-described semiconductor magnetic memory device, the dummy memory cell region DMR is disposed so as to surround the vias (local via LV and top via TV) of the memory cell region MR, and the vias of the memory cell region are disposed in the dummy memory cell region DMR. Dummy vias (dummy local via DLV and dummy top via DTV) having a via occupation ratio higher than the occupation ratio are formed. As a result, after the chemical mechanical polishing treatment, the copper compound can be positively deposited on the surface of the dummy via at a sacrificial effect, and as a result, the copper compound is deposited on the surface of the via in the memory cell region. Can be suppressed.

  Note that, as in this embodiment, in the chemical mechanical polishing process performed after the copper film is embedded in the single damascene via and the dummy via, the dummy memory cell should be in an electrically floating state. . This is because when the dummy memory cell is electrically connected to the ground potential at the time of the chemical mechanical polishing process, the above-described reaction of (Chemical Formula 1) is suppressed, so that the dummy memory cell is not corroded by the dummy via. As a result, a substance that causes copper oxidation or the like during the chemical mechanical polishing process is not consumed in the dummy via of the dummy memory cell. This is because the possibility of causing corrosion increases.

  In this embodiment, the dummy read line is not electrically connected to the element selection transistor, but the dummy memory cell is in a floating state during the chemical mechanical polishing process because the other part is not connected. For example, the contact formed of tungsten connected to the element selection transistor may be left floating by removing it from the dummy memory cell, or another form may be adopted.

  It should be noted that there is no problem that the dummy memory cell is connected to the ground potential via the dummy bit line or the like when the semiconductor magnetic memory device is completed, and is applied after the copper film is embedded in the single damascene via and the dummy via. It is only necessary that the dummy memory cell be in a floating state during the chemical mechanical polishing process.

  Furthermore, in the present embodiment, a case where a dummy memory cell region having a via occupancy higher than the via occupancy in the memory cell region has been described, but the same or lower than the via occupancy in the memory cell region. Even if a dummy memory cell region DMR having a via occupancy ratio (not 0) is arranged, the effect is somewhat reduced as compared with the case of the present embodiment, but it has a certain degree of effectiveness.

  In this embodiment, the vias (local vias and top vias) of the memory cells of the semiconductor magnetic memory device have been described as examples. However, any conductor portion formed by a single damascene method can be used. For example, it can be applied to a contact plug. Further, the semiconductor device is not limited to a semiconductor magnetic memory device, and can be applied to a semiconductor device provided with a via or a contact plug.

  FIG. 82 shows a summary of the relationship between isolated patterns and corrosion (precipitation of copper compounds). As shown in FIG. 82, and in particular, as described in the first embodiment, the precipitation of the copper compound involves three factors (factor 1, factor 2, and factor 3) in combination. Conceivable. The inventors fixed the isolated pattern to the ground potential (Embodiment 1) or provided a dummy pattern for sacrificial deposition of a copper compound (Embodiment 2). It was found that the precipitation of the compound can be suppressed. The above-described embodiments and modifications can be applied in combination as long as there is no particular problem.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is effectively used for a semiconductor device in which a low dielectric constant film or an extremely low dielectric constant film is applied as an interlayer insulating film and a copper film or the like is applied as a wiring or via material.

  ESL element / substrate layer, SUB semiconductor substrate, TE TEOS film, CH contact hole, PG plug, LOW1, LOW2 low dielectric constant film, M1 wiring, FL fine layer, FLL1, FLL2 liner film, ELK1, ELK2 Ultra low dielectric constant film , M2 wiring, V1 via, SGL semi-global layer, SLL liner film, M6 wiring, V5 via, GL global layer, GLL liner film, GTE insulating film, VH7 via hole, M8 wiring, V7 via, CPR chip formation region, DLR Dicing line area, TR TEG area, TP TEG pattern, DPL dummy pattern, DPS dummy pattern, SL signal line, PL power line, AMR alignment mark formation area, AM alignment mark, AFP pattern prohibited area, K R Overlay inspection mark formation area, KM Overlay inspection mark, KFP pattern inhibition area, AHM1, KHM1 opening, AMRM1 alignment mark formation area, AMM1 alignment mark, KMRM1 Overlay inspection mark formation area, KMM1 Overlay inspection mark, AHV1 , KHV1 opening, AMVR1 alignment mark formation area, AMV1 alignment mark, KMRV1 overlay inspection mark formation area, KMV1 overlay inspection mark, AMRM2 alignment mark formation area, AMM2 alignment mark, KMRM2 overlay inspection mark formation area, KMM2 overlay Inspection mark, AMRV2 alignment mark formation area, AMV2 alignment mark, KMRV2 overlay inspection mark Formation region, KMV2 overlay inspection mark, BM1 barrier metal layer, CUM1 copper film, BM2 barrier metal layer, CUM2 copper film, RM1 resist, RV1 resist, VR resist, RM2 resist, RV2 resist, AMH1 alignment mark, GR guard ring, AMH2 alignment mark, IR impurity region, AMH3 alignment mark, MR memory cell region, DMR dummy memory cell region, CDR column decoder region, RDR row decoder region, SAR sense amplifier region, SUB semiconductor substrate, TMR magnetoresistive element, DTMR dummy magnetic Resistance element, STL strap wiring, DSTL dummy strap wiring, REL readout line, DREL dummy readout line, DIL digit line, DDIL dummy device Jitter line, BL bit line, DBL dummy bit line, LVH local via hole, DLVH dummy local via hole, LV local via, DLV dummy local via, TVH top via hole, DTVH dummy top via hole, TV top via, DTV dummy top via 2 silicon oxide film, 2a, 2b, 2c wiring groove, 3a cladding layer, 3b copper film, 4a cladding layer, 4b copper film, LL liner film, LOWA low dielectric constant film, BMA barrier metal layer, CUA copper film, 12 Tantalum film, 13 pin layer, 14 tunnel insulating film, 15 free layer, 16 Ru film, 17 tantalum film, 19 silicon nitride film, LOWB low dielectric constant film, BMB barrier metal layer, CUB copper film.

Claims (15)

Forming an insulating film having a predetermined dielectric constant on the main surface of the semiconductor substrate;
Forming a recess for forming an alignment mark in a predetermined region on the surface of the insulating film;
Forming the copper film so as to cover the insulating film in a manner of filling the concave portion;
Forming a portion of the copper film left in the recess as an alignment mark by removing a portion of the copper film located on the upper surface of the insulating film by a chemical mechanical polishing process. ,
The method of manufacturing a semiconductor device, wherein the step of forming the alignment mark comprises a step of electrically connecting the alignment mark to a ground potential. Forming an impurity region of a predetermined conductivity type in the region of the semiconductor substrate;
The method of manufacturing a semiconductor device according to claim 1, wherein the step of electrically connecting the alignment mark to a ground potential includes a step of electrically connecting the alignment mark to the impurity region of the predetermined conductivity type. Forming a guard ring that is electrically connected to a ground potential so as to surround a region for forming a predetermined semiconductor element;
The method of manufacturing a semiconductor device according to claim 1, wherein the step of electrically connecting the alignment mark to a ground potential includes a step of electrically connecting to the guard ring.   The method of manufacturing a semiconductor device according to claim 1, wherein the alignment marks are alignment marks and overlay inspection marks in photolithography. An insulating film having a predetermined dielectric constant formed on the main surface of the semiconductor substrate;
An alignment mark including a copper film formed in a predetermined recess on the surface of the insulating film,
The semiconductor device, wherein the alignment mark is electrically connected to a ground potential. Including an impurity region of a predetermined conductivity type formed in the region of the semiconductor substrate;
The semiconductor device according to claim 5, wherein the alignment mark is electrically connected to the impurity region of the predetermined conductivity type. A guard ring formed so as to surround a region for forming a predetermined semiconductor element and electrically connected to a ground potential;
The semiconductor device according to claim 5, wherein the alignment mark is electrically connected to the guard ring.   The semiconductor device according to claim 5, wherein the alignment mark is an alignment mark or an overlay inspection mark in photolithography. Around the alignment mark, there is provided a pattern prohibited area where a pattern should not be formed,
The semiconductor device according to claim 8, wherein a dummy pattern is formed in a region located between the pattern prohibited region and a region where a pattern other than the alignment mark is formed. Forming an insulating film having a predetermined dielectric constant on the main surface of the semiconductor substrate;
When the ratio of the area occupied by the opening to the unit area is defined as the opening occupancy ratio, a plurality of first openings that penetrate the insulating film with a first opening occupancy ratio are provided in a predetermined first region on the surface of the insulating film. Forming a plurality of second openings penetrating the insulating film in a second region adjacent to the first region with a second opening occupancy higher than the first opening occupancy;
Forming a copper film so as to cover the insulating film in a manner of filling the plurality of first openings and the plurality of second openings;
When the ratio of the occupied area of the via to the unit area is the via occupation ratio, the portion of the copper film located in the first opening and the portion of the copper film located in the second opening by chemical mechanical polishing processing By removing the portion of the copper film located on the upper surface of the insulating film, vias are formed in the first region with a first via occupancy corresponding to the first opening occupancy. And forming a dummy via in the second region with a second via occupancy corresponding to the second opening occupancy. Forming a plurality of magnetoresistive element portions in a matrix shape in a region corresponding to the first region in the semiconductor substrate, and forming a plurality of dummy magnetoresistive element portions in a region corresponding to the second region; With
Forming the plurality of first openings and the second openings, respectively,
Before forming each of the plurality of magnetoresistive element portions and the dummy magnetoresistive element portion, in a predetermined position corresponding to each of the plurality of magnetoresistive element portions in the first insulating film as the insulating film, Forming a lower first opening, and forming a lower second opening at a predetermined position corresponding to each of the plurality of dummy magnetoresistive elements in the first insulating film;
After each of the plurality of magnetoresistive element portions and the dummy magnetoresistive element portions are formed, the second insulating film as the insulating film is placed at a predetermined position corresponding to each of the plurality of magnetoresistive element portions. Forming a first opening, and forming an upper second opening at a predetermined position corresponding to each of the plurality of dummy magnetoresistive elements in the second insulating film,
Forming the via and the dummy via,
Forming a lower via electrically connected to one end of the magnetoresistive element in the lower first opening, and forming a lower dummy via in the lower second opening;
Forming an upper via electrically connected to the other end side of the magnetoresistive element portion in the upper first opening, and forming an upper dummy via in the upper second opening. Item 11. A method for manufacturing a semiconductor device according to Item 10.   The method of manufacturing a semiconductor device according to claim 10, wherein the second region is arranged so as to take in the first region from the periphery. An insulating film having a predetermined dielectric constant formed on the main surface of the semiconductor substrate;
When a via occupation area per unit area is defined as a via occupation ratio, a predetermined first region on the surface of the insulating film includes a copper film formed so as to penetrate the insulating film with a first via occupation ratio. With multiple vias,
The second region adjacent to the first region includes a plurality of dummy vias including a copper film formed so as to penetrate the insulating film with a second via occupation ratio higher than the first via occupation ratio. Semiconductor devices. The insulating film is
A first insulating film;
A second insulating film formed on the first insulating film,
The via
A lower via formed in a region corresponding to the first region in the first insulating film;
An upper via formed in a region corresponding to the first region in the second insulating film,
The dummy via is
A lower dummy via formed in a region corresponding to the second region in the first insulating film;
An upper dummy via formed in a region corresponding to the second region in the second insulating film,
A matrix is formed in a region corresponding to the first region in a region between the first insulating film and the second insulating film, and is electrically connected to the corresponding lower via and upper via, respectively. A plurality of magnetoresistive element portions,
14. A plurality of dummy magnetoresistive element portions formed in a matrix in a region corresponding to the second region in a region between the first insulating film and the second insulating film. Semiconductor device.   15. The semiconductor device according to claim 13, wherein the second region is arranged so as to take in the first region from the periphery.

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