JP2012164050A - Information processing device, task management method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce overhead required to maintain cache coherency while keeping a real-time property.SOLUTION: An information processing device performs following steps; reading processor information of a task executable on a plurality of processors from a storage device in which priority information of a task is stored in association with processor information showing a processor which has executed a task lately, executes one immediately or is executing one, for each task; and determining whether or not the read processor information matches the processor information showing one processor according to the priority information, and if it is determined to match, a task associated with the processor information determined to match is determined as the task to be executed by the one processor next among the plurality of processors.

Description

  The present invention relates to an information processing apparatus, a task management method, and a program.

In recent years, mounting of multiprocessors is increasing as a method for simultaneously satisfying improvement in performance and suppression of power consumption in embedded systems. The suppression of power consumption in an embedded system is directly related to the operating time of the embedded system. In order to improve the performance of the embedded system while satisfying this, it is more advantageous to increase the number of processors than to increase the clock frequency of the embedded system. For this reason, there is an increasing demand for an embedded real-time operating system (real-time OS) that supports multiprocessors.
Even in conventional embedded systems, an embedded system in which a plurality of different or similar processors are mounted is not uncommon. However, most of them have a sparse relationship between processors, and the demand for an embedded system having a close relationship between processors has increased in recent years.

In fact, even if you look at the embedded OS that controls such processors, TOPPERS / FMP (so-called TOPPERS project, see Non-Patent Document 1) and SMP / AMP T-Kernel (T-Engine Forum) Recently, discussions have become active.
On the other hand, the OS corresponding to the multiprocessor corresponding to the tight coupling is not a story started in recent years, but has been studied since the dawn of computer science. Even in today's general-purpose computers, anyone can easily use a general-purpose OS (for example, Linux (registered trademark) or Windows (registered trademark)) compatible with multiprocessors. Also, a technique related to a multiprocessor is disclosed (see Patent Document 1 and Patent Document 2).

Japanese Patent No. 3444505 JP-A-9-305553

Junya Honda, Hiroaki Takada “Functional Distributed Multiprocessor Extension of ITRON Specification OS”, “Electronic Information and Communication Society Transactions D Vol.

However, the embedded real-time OS has a proposition that the real-time property of the entire embedded system must be guaranteed.
Here, strictly speaking, real time indicates that all execution times can be predicted, and therefore the OS guarantees the worst-case execution time required for its own processing. In addition, with the introduction of technology that makes it difficult to predict execution time, such as caches, the meaning of real-time is becoming loose in recent years, but strict execution according to priority and minimization of the occupation time in the OS, etc. An OS with a high real-time property is required.

Due to such a requirement for real-time property, there is a problem that the inventions described in Patent Document 1 and Patent Document 2 that have been cultivated in general-purpose OSs cannot be used in an embedded real-time OS.
Actually, the invention described in Patent Document 1 does not consider the real-time property and cannot reduce the overhead for maintaining the cache coherency in the embedded real-time OS while maintaining the real-time property.

  The present invention has been made in view of such problems, and an object thereof is to reduce the overhead required for maintaining cache coherency while maintaining real-time performance.

  Therefore, an information processing apparatus according to the present invention is an information processing apparatus having a storage device and a plurality of processors, and the task priority information and the task are executed most recently, or are most recently executed or executed. Reading means for reading processor information of a task executable by the plurality of processors from the storage device in which processor information indicating the processor is stored in association with each task, and one processor of the plurality of processors Then, as a task to be executed next, it is determined according to priority information whether the processor information read by the reading means matches the processor information indicating the one processor. And determining means for determining a task associated with the processor information.

  According to the present invention, it is possible to reduce overhead associated with maintaining cache coherency while maintaining real-time performance.

It is a figure which shows an example of a structure of real-time OS. It is a figure which shows an example of the hardware constitutions of information processing apparatus. It is a figure which shows an example of a table. It is a figure which shows an example of the relationship of the task in an executable task group. It is a figure which shows an example of the flowchart which concerns on a task switch process. It is a figure which shows an example of the flowchart which concerns on a task switch process. It is a figure which shows an example of a table. It is a figure which shows an example of the relationship of the task in an executable task group. It is a figure which shows an example of the flowchart which concerns on a task switch process. It is a figure which shows an example of a table. It is a figure which shows an example of the relationship of the task in an executable task group.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention, and all the configurations described in the embodiments are not necessarily essential to the means for solving the problems of the present invention.

<First Embodiment>
FIG. 1 is a diagram showing an example (OS 101) of a configuration of an embedded real-time OS corresponding to the multiprocessor according to the present embodiment.
The OS 101 is a real-time OS based on a priority based preemptive scheduling method (preemptive multitasking), and manages the processor 102 by distributing a load to each processor in units of tasks. The processor 102 includes a plurality of processor units such as processor units “PU0”, “PU1”, and “PU2”. Each processor unit performs processing by switching the processing target to a task determined (selected) by the task execution determination unit 105 after necessary initialization is performed or for each scheduling point.

The OS 101 manages the executable task group 103 according to the specification information of the OS 101. An executable task is a task that is executed on a processor unless interrupt processing occurs when the task has the highest priority at that time. Here, all the executable tasks are collectively referred to as an executable task group 103.
Here, the general embedded real-time OS manages the tasks in the order of priority of the executable task group, and the first-come-first-served order (the order in which the tasks arrived at the real-time OS) within the same priority order. In addition, a general embedded real-time OS realizes one part of real-time performance by extracting one task with the highest priority and the top task for each scheduling point and operating it on the processor.

The execution hint information 104 is an example of processor information indicating in which processor unit of the processor 102 the task in the executable task group 103 was executed at the previous execution.
The task execution determination unit 105 determines a task to be executed (operated) next time in the processor unit of the processor 102. In the present embodiment, the task execution determination unit 105 targets only the task having the highest priority of the executable task group 103 at this time point at each scheduling point. Then, the task execution determination unit 105 refers to the execution hint information 104 in the order of arrival of the target tasks.

For example, the task execution determination unit 105 determines whether the target processor unit in the processor 102 matches the processor unit that previously executed the target task based on the execution hint information 104. .
If the task execution determination unit 105 determines that they match, the task execution determination unit 105 determines the task of the execution hint information 104 determined to match as the task to be executed next by the target processor unit. On the other hand, if the task execution determination unit 105 determines that they do not match, the task execution determination unit 105 sequentially determines the target task execution hint information 104 until it determines that they match.
Further, it is assumed that the task execution determination unit 105 determines that the target task in the executable task group 103 does not have a task executed previously in the target processor unit. In this case, the task execution determination unit 105 determines the first task (the task that has arrived at the OS 101 first) among the tasks with the highest priority as the task to be executed next time.

The configuration of the OS 101 not shown in detail is the same as the configuration of a general embedded OS.
In the present embodiment, in order to realize real-time performance, as in a general embedded OS, a task being executed transitions to a state of another task, and a task having a higher priority transitions to a state where it can be executed. A task to be executed next time is determined by using a timing such as the end of the interrupt processing as a scheduling point.
The number of processor units is not limited, and two or more processor units are preferable.

Further, although the execution hint information 104 is shown as task information of the executable task group 103, it is not limited to this. That is, a configuration capable of managing task information of the executable task group 103 can be adopted as appropriate. For example, the execution hint information 104 may manage tasks including the tasks of the executable task group 103 such as all tasks existing in the OS 101 or all tasks that are not suspended. .
Further, for convenience of explanation, the execution hint information 104 is shown as single information, but is not limited thereto. For example, the execution hint information 104 may be part of task management information for managing all tasks. For example, the execution hint information 104 may be in a list format instead of a table format.
Further, the execution hint information 104 may be added or deleted each time the executable task group 103 is changed. Further, the execution hint information 104 may be configured by appropriately combining the above-described configurations.

FIG. 2 is a diagram illustrating an example of a hardware configuration of an information processing apparatus (computer) having the OS 101 included in the embedded system.
The information processing apparatus includes a processor unit 201, a processor unit 202, a cache coherent mechanism 203, a ROM (Read Only Memory) 204, a RAM (Random Access Memory) 205, a bus 206, and the like. The processor unit 201 is a processor unit having a processor number “PU0”, and the processor unit 202 is a processor unit having a processor number “PU1”.
The OS 101 operates on the hardware of a plurality of processor units (processor unit 201, processor unit 202, etc.), cache coherent mechanism 203, ROM 204, RAM 205, and bus 206. Further, the data operation performed via the cache in each of the plurality of processor units is kept unique by the cache coherent mechanism 203 in the case of data operation on the same address.

The OS 101 program (code) and data used for the operation of the OS 101 are arranged in either the ROM 204 or the RAM 205 and are executed by the processor unit 201 or the processor unit 202. By executing the program of the OS 101, the function of the OS 101 and processing according to a flowchart described later are realized.
Note that the hardware configuration of the information processing apparatus according to the present embodiment is not limited to the hardware configuration described above.
For example, the connection method between the processor unit and the cache coherent mechanism 203 may be different. For example, the processor unit and the cache coherent mechanism 203 may be connected via the bus 206.
Further, another device (hard disk or the like) different from the above-described devices may be connected to the bus 206 to freely combine other devices.

Next, the execution hint information 104 will be described with reference to FIG.
FIG. 3 shows an example of a table in which tasks at a certain point in time, priority of the tasks, and information (execution hint information 104) indicating the processor unit in which the task was executed last time are associated for each task. FIG. The table is stored in a storage device such as the RAM 205.
For taskA, the priority is “1”, and the execution hint information 104 is “PU1”. Similarly, it is indicated that priority is “1” and execution hint information 104 “PU1” for taskB, and priority “1” and execution hint information 104 “PU0” are for taskC. Similarly, it is indicated that taskD has priority “3” and execution hint information 104 “PU1”, and taskE has priority “3” and execution hint information 104 “PU0”.

Here, the initial value of the execution hint information 104, that is, information when the task is first executable is not described in detail. This is because the present embodiment can be implemented with any initial value.
For example, in the case where information indicating a specific processor unit is used as an initial value although no actual operation is performed, there is a high possibility that it will be executed first by that processor unit. Further, for example, when information that is not an actual processor unit is set as an initial value, it is only undefined which processor unit is executed.
The data structure of the table is not limited to that shown in FIG.

Next, the executable task group 103 will be described with reference to FIG.
FIG. 4 is a diagram illustrating an example of a task relationship in the executable task group 103 at a certain point in time. Information on tasks that can be executed (task information) is registered and managed in the list as an executable task group 103 in the order of priority in the order of arrival within the same priority. The list is provided for each priority order and is stored in a storage device such as the RAM 205.
Here, the list 401 includes task information indicating executable tasks having a priority “1”, and the list 402 includes task information indicating executable tasks having a priority “2”. Includes task information indicating an executable task having a priority “3”.

For example, when all of the tasks shown in FIG. 3 can be executed, the relationship of the tasks in the executable task group 103 is as shown in FIG.
At this time, the maximum priority of the executable task group 103 is “1”, and the tasks taskA, taskB, and taskC registered (connected) in the list 401 are the targets of the task to be executed next time. Thus, the suitability of the task to be executed next time is determined. That is, the priority order and the connection order (equivalent to the first-come-first-served basis) are examples of priority information indicating the priority of task assignment.
The data structure of the executable task group 103 is not limited to that shown in FIG.

Next, the operation of the task execution determination unit 105 will be described with reference to FIG. The behavior of the task execution determination unit 105 when the execution hint information 104 is as shown in FIG. 3 and the executable task group 103 is as shown in FIG. 4 will be described together.
FIG. 5 is a diagram illustrating an example of a flowchart relating to task switching processing in the task execution determination unit 105. Task switch processing is started at a scheduling point in each processor unit. A processor unit on which task switch processing is executed is referred to as an execution processor unit.

In step S <b> 501, the task execution determination unit 105 is task information of a task having the highest priority among tasks registered as the executable task group 103 (an example representing priority information higher than prescribed priority information). Is stored in a variable tmp.
In step S502, the task execution determination unit 105 determines whether task information exists in tmp. At this time, if the task execution determination unit 105 determines that the task information does not exist, the task execution determination unit 105 performs the process of S507. If the task execution determination unit 105 determines that the task information exists, the task execution determination unit 105 performs the process of S503.

In step S503, the task execution determination unit 105 reads the execution hint information 104 corresponding to the task information of tmp from the table, and determines whether or not the read execution hint information 104 and the processor number indicating the execution processor unit are the same (match). Or not). At this time, if the task execution determination unit 105 determines that they are the same, the task execution determination unit 105 performs the process of S504.
In S504, the task execution determining unit 105 stores information indicating that the task of the task information of tmp is determined as the task to be executed next by the execution processor unit in the storage device such as the RAM 205, and performs the process of S505.

In step S505, the task execution determination unit 105 corrects the execution hint information 104 corresponding to the task information of tmp to the processor number indicating the execution processor unit, and ends the task switch process.
In S506, the task execution determination unit 105 changes the task information of tmp to the next task information in the corresponding list of the executable task group 103, and performs the process of S502.
In step S <b> 507, the task execution determination unit 105 stores in the storage device such as the RAM 205 information indicating that the task of the top task information in the list of the highest priority of the executable task group 103 has been determined as the next task to be executed. Remember. Further, the task execution determination unit 105 holds the task information in tmp, and performs the process of S505.

In the following, the task switching process is started by the processor unit 201, the execution hint information 104 is as shown in FIG. 3, and the executable task group 103 is as shown in FIG. This will be described in more detail.
First, in S501, the list 401 is specified as a list including task information with the highest priority, and the first task information “taskA” of the list 401 is held in tmp. Next, in S502, since “taskA” exists in tmp, the processing in S503 is subsequently performed.
In S503, since the execution hint information 104 corresponding to “taskA” is “PU1” and is different from the processor number “PU0” indicating the processor unit 201, the processing of S506 is subsequently performed. In S506, the task information of tmp is changed to “taskB” (second) after “taskA”, and the process of S502 is performed.

When “taskB” is held in tmp, the processes of S502, S503, and S506 are similarly performed. In step S506, “taskC” next to “taskB” is held in tmp.
When the task information of tmp is “taskC”, the process of S502 is performed in the same manner. In S503, since the execution hint information 104 corresponding to “taskC” is “PU0”, it matches the processor number “PU0” indicating the execution processor unit, and the process of S504 is performed.
In S504, the task to be executed next time is determined as “taskC”, and the processing in S505 is performed. In S505, since the execution hint information 104 corresponding to “taskC” is “PU0”, the value is not changed.

Here, in the task switching process, the task execution hint information 104 determined to be executed next time is rewritten in S505. This rewriting can be performed at the time of other processing, and does not have to be performed with the task information held in tmp.
For example, when a scheduling point occurs during task execution and task switch processing may be performed (or when it is surely performed), the processor number of the processor unit that is executing the task is set. The execution hint information 104 may be used. That is, the execution hint information 104 includes any of the processor number of the processor unit in which the task is executed most recently, the processor number of the processor unit in which the task is executed, and the processor number of the processor unit in which the task is executed most recently. It may be stored.
According to the configuration described above, it is possible to reduce overhead due to maintenance of cache coherency while maintaining real-time performance in a real-time OS compatible with a multiprocessor.

<Second Embodiment>
The second embodiment makes it possible to relatively reduce the overhead for maintaining cache coherency as compared with the first embodiment. Therefore, the real-time property of the present embodiment may be inferior to the real-time property of the first embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

The operation of the task execution determination unit 105 of this embodiment will be described with reference to FIG.
FIG. 6 is a diagram illustrating an example of a flowchart relating to task switching processing in the task execution determination unit 105.
In step S <b> 601, the task execution determination unit 105 holds the task information at the head of the list including the task information of the task with the highest priority among the tasks registered as the executable task group 103 in tmp. Further, the task execution determination unit 105 sets the value of the variable cnt that holds the number of processed tasks to “0”, and performs the process of S602.

In step S602, the task execution determination unit 105 determines whether task information exists in tmp and whether the value of cnt is smaller than the number of processor units, which is an example of a specified number. At this time, if the task execution determination unit 105 determines that both conditions are satisfied, the task execution determination unit 105 performs the process of S603. If the task execution determination unit 105 determines that at least one of both conditions is not satisfied, the task execution determination unit 105 performs the process of S607.
In step S603, the task execution determination unit 105 reads the execution hint information 104 corresponding to the task information of tmp from the table, and determines whether or not the read execution hint information 104 and the processor number indicating the execution processor unit are the same. To do. At this time, if the task execution determination unit 105 determines that they are the same, the task execution determination unit 105 performs the process of S604. If determined different, the task execution determination unit 105 performs the process of S606.

In S604, the task execution determination unit 105 stores information indicating that the task of the task information of tmp is determined as the task to be executed next by the execution processor unit in a storage device such as the RAM 205, and performs the process of S605.
In step S605, the task execution determination unit 105 corrects the execution hint information 104 corresponding to the task information of tmp to the processor number indicating the execution processor unit, and ends the task switch process.

In step S <b> 606, the task execution determination unit 105 changes the task information of tmp to the next task information in the corresponding list of the executable task group 103. However, if it is the end of the priority list, the task execution determination unit 105 changes the task information to the head of the next highest priority list. Further, the task execution determination unit 105 adds “1” to the value of cnt and performs the process of S602.
In step S <b> 607, the task execution determination unit 105 stores information indicating that the task of the top task information in the list of the highest priority of the executable task group 103 is determined as a task to be executed next in a storage device such as the RAM 205. Remember. Further, the task execution determination unit 105 holds the task information in tmp, and performs the process of S605.

In the following, the task switching process is started by the processor unit 201, the execution hint information 104 is as shown in FIG. 7, and the executable task group 103 is as shown in FIG. This will be described in more detail. It is assumed that the information processing apparatus includes a processor unit 201 and a processor unit 202, and the total number of processor units is “2”.
First, in S601, the list 801 is specified as a list including task information with the highest priority, task information “taskA” of the list 801 is held in tmp, and “0” is held in cnt. Next, in S602, since “taskA” exists in tmp and cnt is “0”, both conditions are satisfied, and then the processing in S603 is performed.

In S603, since the execution hint information 104 corresponding to “taskA” is “PU1” and is different from the processor number “PU0” indicating the processor unit 201, the processing of S606 is subsequently performed. In S606, since “taskA” in the list 801 is the end (end of the list 801), the next priority list 802 is targeted, and the first “taskB” in the list 802 is held in tmp. Then, “1” is held in cnt, and the process of S602 is performed.
When “taskB” is held in tmp, the process of S602 is performed in the same manner. In S603, since the execution hint information 104 corresponding to “taskB” is “PU0”, it matches the processor number “PU0” indicating the execution processor unit, and the process of S604 is performed. In S604, the task to be executed next time is determined to be taskB, and the process of S605 is performed. In S605, since the execution hint information 104 corresponding to “taskB” is “PU0”, the value is not changed.

Here, although detailed fitting is omitted, when the above example is performed in the task switching process of the first embodiment, taskA is determined as a task to be executed next time.
When the first embodiment and the second embodiment are compared based on the above-described contents, it can be said that the first embodiment has higher real-time performance because execution in the priority order is protected. However, in the first embodiment, the processor unit on which taskA is executed is different from the processor unit that was executed last time, and thus there is a possibility that the overhead for maintaining cache coherency during data operations may increase.

Note that when the task switch processing of this embodiment is performed under the conditions of FIGS. 3 and 4 shown in the first embodiment, taskA is determined as the task to be executed next time.
According to the configuration described above, it is possible to realize a real-time OS corresponding to a multiprocessor that reduces the overhead required for maintaining cache coherency, although it is inferior to real-time performance compared to the first embodiment.
In other words, other configurations and operations according to the present embodiment are the same as those of the first embodiment.

<Third Embodiment>
The third embodiment has a configuration that improves the real-time property relative to the first and second embodiments. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

The operation of the task execution determination unit 105 of this embodiment will be described with reference to FIG.
FIG. 9 is a diagram illustrating an example of a flowchart relating to task switching processing in the task execution determination unit 105.
In step S <b> 901, the task execution determination unit 105 holds the task information at the head of the list including the task information of the task with the highest priority among the tasks registered as the executable task group 103 in tmp. Further, the task execution determination unit 105 sets the value of the variable cnt that holds the number of processed tasks to “0”, and performs the process of S902.

In step S902, the task execution determination unit 105 determines whether task information exists in tmp and whether the value of cnt is smaller than the number of processor units. At this time, if the task execution determining unit 105 determines that both conditions are satisfied, the process of S903 is performed, and if it is determined that both conditions are not satisfied, the process of S907 is performed.
In step S903, the task execution determination unit 105 reads the execution hint information 104 corresponding to the task information of tmp from the table, and determines whether or not the read execution hint information 104 and the processor number indicating the execution processor unit are the same (match). Or not). At this time, if the task execution determination unit 105 determines that they are the same, the task execution determination unit 105 performs the process of S904, and if determined to be different, performs the process of S906.

In step S904, the task execution determination unit 105 stores information indicating that the task in the task information of tmp is determined as a task to be executed next by the execution processor unit in a storage device such as the RAM 205, and performs the processing in step S905.
In step S905, the task execution determination unit 105 corrects the execution hint information 104 corresponding to the task information of tmp to the processor number indicating the execution processor unit, and ends the task switch process.

In S906, the task execution determination unit 105 changes the task of tmp to the next task information in the corresponding list of the executable task group 103, adds “1” to the value of cnt, and performs the process of S902.
In step S907, the task execution determination unit 105 stores information indicating that the task of the top task information in the list of the highest priority of the executable task group 103 is determined as a task to be executed next in a storage device such as the RAM 205. Remember. Further, the task execution determination unit 105 holds the task information in tmp, and performs the process of S905.

In the following, the task switching process is started by the processor unit 201, the execution hint information 104 is as shown in FIG. 10, and the executable task group 103 is as shown in FIG. This will be described in more detail. It is assumed that the information processing apparatus includes a processor unit 201 and a processor unit 202, and the total number of processor units is “2”.
First, in S901, the list 1101 is specified as a list including task information with the highest priority, task information “taskA” of the list 1101 is held in tmp, and “0” is held in cnt. Next, in S902, since “taskA” exists in tmp and cnt is “0”, both conditions are satisfied, and the processing in S903 is performed.

In S903, since the execution hint information 104 corresponding to “taskA” is “PU1” and is different from the processor number “PU0” indicating the processor unit 201, the processing of S906 is subsequently performed. In S906, “taskB” is held in tmp, “1” is held in cnt, and then the processing in S902 is performed.
When “taskB” is held in tmp, the process of S902 is performed in the same manner. In S903, since the execution hint information 104 corresponding to “taskB” is “PU0”, it matches the processor number indicating the execution processor unit, and the process of S904 is performed. In S904, the task to be executed next time is taskB, and the processing in S905 is performed. In S905, since the execution hint information 104 corresponding to “taskB” is “PU0”, the value is not changed.

Here, although detailed fitting is omitted, when the above example is performed in the task switch process of the first embodiment, taskB is determined as the task to be executed next time, and the task switch process of the second embodiment is performed. If done, taskB is determined as the task to be executed next time.
Further, when the task switch processing of the present embodiment is performed under the conditions shown in FIGS. 3 and 4 shown in the first embodiment, the task to be executed next is determined as taskA, which is shown in the second embodiment. When performed under the conditions of FIGS. 7 and 8, the task to be executed next time is determined as taskA.
According to the configuration described above, it is possible to realize a real-time OS corresponding to a multiprocessor that improves the real-time property as compared with the first and second embodiments.
In other words, other configurations and operations according to the present embodiment are the same as those of the first embodiment.

<Other embodiments>
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

  According to the configuration of the above-described embodiment, it is possible to reduce overhead for maintaining cache coherency while maintaining real-time performance.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

101 OS, 102 processor, 103 executable task group, 104 execution hint information, 105 task execution determination unit

Claims (8)

An information processing apparatus having a storage device and a plurality of processors,
From the storage device in which the priority information of the task and the processor information indicating the processor which has executed the task most recently, or which has been executed or is being executed are associated and stored for each task, the plurality of processors Reading means for reading processor information of executable tasks;
As a task to be executed next by one of the plurality of processors, it is determined according to priority information whether or not the processor information read by the reading means matches the processor information indicating the one processor. Determining means for determining a task associated with the processor information determined to match when determined to match;
An information processing apparatus comprising:   When the determining unit determines that all of the processor information read by the reading unit does not match, the task having the highest priority information among the tasks associated with the read processor information is executed next. The information processing apparatus according to claim 1, wherein the information processing apparatus is determined as a task.   The information processing apparatus according to claim 2, wherein the reading unit reads processor information of a task having priority information higher than prescribed priority information among tasks executable by the plurality of processors. The task priority information stored in the storage device is information indicating the priority order of the tasks and the first-come-first-served order of the tasks,
Priority information higher than the prescribed priority information is priority information with the highest priority,
The reading means reads processor information of a task having the highest priority among tasks that can be executed by the plurality of processors,
The determining means determines whether the processor information read by the reading means matches the processor information indicating the one processor according to the first-come-first-served basis as the next task to be executed, and determines that they match. When determining the task associated with the processor information that is determined to match,
When the determination unit determines that all of the processor information read by the reading unit does not match, the task in the first-come-first-served basis among the tasks associated with the read processor information is executed next. The information processing apparatus according to claim 3, wherein the information processing apparatus is determined as a task.   3. The information processing apparatus according to claim 2, wherein the reading unit reads processor information of a task included in a prescribed number from tasks having high priority information among tasks executable by the plurality of processors.   The reading means reads processor information of a task included in a specified number from a task having priority information higher than specified priority information and having higher priority information among tasks executable by the plurality of processors. The information processing apparatus according to claim 2. A task management method for managing a task to be executed next in one of the plurality of processors in an information processing apparatus having a storage device and a plurality of processors,
In the storage device, priority information of a task and processor information indicating a processor that has executed the task most recently, or that has been executed recently, or an executing processor are stored in association with each task,
Determining whether processor information of a task having the highest priority information among a plurality of tasks executable by the plurality of processors stored in the storage device matches processor information indicating the one processor; ,
Determining the task with the highest priority information as the next task to be executed when it is determined to match in the step;
A step of determining whether or not processor information of a task having the second highest priority information among the plurality of tasks matches processor information indicating the one processor when it is determined not to match in the step;
A task management method characterized by comprising: A computer having a storage device and a plurality of processors,
From the storage device in which the priority information of the task and the processor information indicating the processor which has executed the task most recently, or which has been executed or is being executed are associated and stored for each task, the plurality of processors Reading means for reading processor information of executable tasks;
As a task to be executed next by one of the plurality of processors, it is determined according to priority information whether or not the processor information read by the reading means matches the processor information indicating the one processor. Determining means for determining a task associated with the processor information determined to match when determined to match;
Program to make it work.

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