JP2012160492A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device excellent in performance characteristics of a logical circuit.SOLUTION: A semiconductor device comprises: a semiconductor substrate 1; a multilayer wiring layer; a storage circuit 200 including a first active element 3a, a capacitive element 19 and peripheral circuits; a logical circuit 100 including a second active element 3b; a capacitance contact 13c formed in a region of the storage circuit 200 and electrically connecting the active element 3a and the capacitive element 19; and a connection contact 13a formed in a region of the logical circuit 100 and electrically connecting the active element 3b and first wiring 8a. The first wiring 8a is located in an interlayer insulation film 7a of an undermost wiring layer among wiring layers in which the capacitive element 19 is embedded. The connection contact 13a is provided in the same layer as the capacitance contact 13c. The first wiring 8a and the connection contact 13a have a dual damascene structure.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In the manufacturing technology in the field of integrated circuits in the electronics industry, there is an increasing demand for higher integration and higher speed. Further, with the progress of integration, the scale of the circuit has increased and the difficulty of design has increased.

  In an integrated circuit in which a logic circuit and a memory circuit are mounted on the same semiconductor substrate, that is, a so-called mixed circuit, the logic circuit and the memory circuit exist on the same substrate, so that the layout can be simply performed at a short distance. In addition to the improvement, the operation speed can be improved by shortening the wiring between circuits.

For example, Patent Documents 1 and 2 describe a semiconductor device having an integrated circuit on which such a logic circuit and a memory circuit are mounted. For example, in the semiconductor device described in Patent Document 1, a logic contact is formed in an insulating film in which a capacitor contact is embedded. This capacitive contact electrically connects the DRAM transistor and the capacitive element. The logic contact electrically connects the logic transistor and the logic wiring. It is described that such a logic contact and a logic wiring are made of tungsten (W), respectively (FIG. 16 described in Patent Document 1).
In the semiconductor device described in Patent Document 2, the lower electrode contact plug and the capacitor element are formed in the first interlayer insulating film and the second interlayer insulating film, respectively, in the DRAM region. On the other hand, in the logic region, contact plugs penetrating these first interlayer insulating film and second interlayer insulating film are formed. The contact plug electrically connects the logic transistor and the upper layer wiring. It is described that such a contact plug is composed of W (FIG. 7 described in Patent Document 2).
As described above, a semiconductor device having a conventional integrated circuit has a contact plug made of W. A contact plug made of W is generally used because it has a stable interface with the silicon diffusion layer and has low leakage, and thus has good compatibility with a memory circuit using a capacitor.

JP 2007-201101 A JP 2004-342787 A JP 2005-101647 A JP-A-11-186518

International Electron Device Meeting Digest of Technical Papers IEEE pages 619-622 2008

  However, the conventional semiconductor device has room for improvement in terms of reducing the resistance of the contact plug.

According to the present invention,
A substrate,
A multilayer wiring layer provided on the substrate, in which a plurality of wiring layers composed of wiring and insulating layers are laminated;
In plan view, formed in a memory circuit region in the substrate, and a first active element, at least one capacitive element provided in the multilayer wiring layer and electrically connected to the first active element, And a memory circuit having a peripheral circuit;
In plan view, formed in a logic circuit region that is different from the memory circuit region in the substrate, and a logic circuit having a second active element;
A capacitor contact formed in the memory circuit region and electrically connecting the first active element and the capacitor;
A connection contact which is formed in the logic circuit region and electrically connects the second active element and the first wiring;
The first wiring is located in the lowermost wiring layer of the wiring layer in which the capacitive element is embedded;
The connection contact is provided in the same layer as the capacitor contact,
A semiconductor device is provided in which the first wiring and the connection contact have a dual damascene structure.

  According to the above configuration, the first wiring of the logic circuit provided in the lowermost layer of the wiring layer in which the capacitive element is embedded and the connection contact provided in the contact insulating layer in which the capacitive contact is formed have a dual damascene structure. have. For this reason, since no interface is formed between the wiring and the connection contact, generation of interface resistance can be suppressed. Therefore, as compared with the conventional case, wiring and connection contacts having lower resistance can be formed, so that a decrease in operation speed of the logic circuit can be suppressed.

Moreover, according to the present invention,
A substrate,
A multilayer wiring layer provided on the substrate, in which a plurality of wiring layers composed of wiring and insulating layers are laminated;
In plan view, formed in a memory circuit region in the substrate, and a first active element, at least one capacitive element provided in the multilayer wiring layer and electrically connected to the first active element, And a memory circuit having a peripheral circuit;
In plan view, formed in a logic circuit region that is different from the memory circuit region in the substrate, and a logic circuit having a second active element;
A capacitor contact formed in the memory circuit region and electrically connecting the first active element and the capacitor;
A connection contact which is formed in the logic circuit region and electrically connects the second active element and the first wiring;
The first wiring is located in the lowermost wiring layer of the wiring layer in which the capacitive element is embedded;
The connection contact is provided in the same layer as the capacitor contact,
There is provided a semiconductor device in which the first wiring and the connection contact have a single machine structure and are each made of a metal material containing copper.

  According to the above configuration, the first wiring of the logic circuit provided in the lowermost layer of the wiring layer in which the capacitive element is embedded, and the connection contact provided in the contact insulating layer in which the capacitive contact is formed have a single machine structure. And a metal material containing copper. For this reason, the resistance value of the connection contact can be reduced as compared with the case where the connection contact is made of W. Therefore, as compared with the conventional case, wiring and connection contacts having lower resistance can be formed, so that a decrease in operation speed of the logic circuit can be suppressed.

Moreover, according to the present invention,
A method for manufacturing a semiconductor device having a memory circuit and a logic circuit on the same substrate,
Forming a contact insulating layer on the substrate;
Forming a first contact hole penetrating the contact insulating layer in the memory circuit formation region, and embedding the first contact hole with a first metal material, thereby forming a capacitor contact;
Forming an insulating layer on the contact insulating layer;
In the logic circuit formation region, by selectively removing the contact insulating layer and the insulating layer, a second through hole penetrating the contact insulating layer is formed, and the insulating layer is selectively removed. Forming a wiring groove continuous with the second through hole in the insulating layer, and forming a connection contact and a wiring by embedding the second through hole and the wiring groove with a second metal material; ,
Forming a recess reaching the capacitor contact in the insulating layer in which the wiring is formed, and embedding a capacitor element in the recess. .

Moreover, according to the present invention,
A method for manufacturing a semiconductor device having a memory circuit and a logic circuit on the same substrate,
Forming a contact insulating layer on the substrate;
Forming a first contact hole penetrating the contact insulating layer in the memory circuit formation region, and embedding the first contact hole with a first metal material, thereby forming a capacitor contact;
Forming an insulating layer on the contact insulating layer;
In the logic circuit formation region, by selectively removing the contact insulating layer and the insulating layer, a second through hole penetrating the contact insulating layer is formed, and the second through hole includes a second copper containing copper. A connection contact is formed by embedding with a metal material, and by selectively removing the insulating layer, a wiring groove continuing to the second through hole is formed in the insulating layer, and the wiring groove is formed. Forming a wiring by embedding with the second metal material including copper;
Forming a recess reaching the capacitor contact in the insulating layer in which the wiring is formed, and embedding a capacitor element in the recess. .

  According to the present invention, a semiconductor device excellent in operating characteristics of a logic circuit is provided.

1 is a top view schematically showing a semiconductor device according to a first embodiment. It is sectional drawing which shows typically the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 1st Embodiment. It is sectional drawing which shows typically the semiconductor device in 2nd Embodiment. It is sectional drawing which shows typically the semiconductor device in 3rd Embodiment. It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in 3rd Embodiment. It is sectional drawing which shows typically the semiconductor device in 4th Embodiment. It is sectional drawing which shows typically the semiconductor device in 5th Embodiment. It is sectional drawing which shows typically the semiconductor device in 6th Embodiment. It is sectional drawing which shows typically the semiconductor device in 7th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
A semiconductor device according to the first embodiment will be described.
FIG. 1 is a top view schematically showing the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view schematically showing the semiconductor device according to the first embodiment.

  The semiconductor device according to the present embodiment includes a substrate (semiconductor substrate 1), a multilayer wiring layer formed on the semiconductor substrate 1, in which a plurality of wiring layers composed of wiring and insulating layers are stacked, and in plan view The first active element (active element 3a) formed in the memory circuit region in the semiconductor substrate 1, and at least one capacitive element 19 embedded in the multilayer wiring layer and electrically connected to the active element 3a. And a memory circuit 200 having a peripheral circuit, and a logic circuit formed in a logic circuit region that is a region different from the memory circuit region in the semiconductor substrate 1 in plan view and having a second active element (active element 3b) 100, formed in the memory circuit region, and electrically connected to the active element 3a and the capacitor element 19c, and formed in the logic circuit region, the active element 3b A connection contact 13a for electrically connecting one wiring (wiring 8a), and the first wiring (wiring 8a) is the lowermost wiring layer (interlayer insulating film) of the wiring layers in which the capacitive element 19 is embedded. 7a), the connection contact 13a is provided in the same layer as the capacitor contact 13c, and the first wiring (wiring 8a) and the connection contact 13a have a dual damascene structure.

  In the semiconductor device according to the first embodiment, the wiring (wiring 8b) constituting the logic circuit 100 formed on the upper surface of the upper connecting wiring 18 and the same wiring layer (interlayer insulating film 7b) as the upper connecting wiring 18 is used. In this embodiment, the same surface is the maximum value of the unevenness of the unevenness with respect to the average height of the surface when measured by the following measurement method. The plane is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less, for example, using SEM (Scanning Electron Microscope) or TEM (Transmission Electron Microscope). Cross-sectional image including the upper surface of the upper connection wiring 18 and the upper surface of the wiring 8b The method of acquiring and measuring the height difference of the step from this cross-sectional image, the method of measuring the profile of the height in the planar direction by the step meter widely used in the inspection process in the manufacturing process of the semiconductor device, etc. Is mentioned.

  As shown in FIG. 1, the semiconductor device of this embodiment has a structure in which a memory circuit 200 including a capacitor 210 and a logic circuit 100 in which a semiconductor element is formed are mixedly mounted on a semiconductor substrate 110. The logic circuit 100 is formed not in the peripheral circuit 220 of the capacitor 210 in the memory circuit 200 but in a region different from the memory circuit 200. For example, the logic circuit 100 region can be a region where a high-speed logic circuit such as a CPU (Central Processing Unit) is formed.

  Referring to FIG. 2, the logic circuit 100 and the memory circuit 200 are formed on the semiconductor substrate 1. Note that the constituent elements in the drawings of the logic circuit 100 and the memory circuit 200 are only partly shown of elements constituting each circuit, and are not directly related to the embodiment according to this embodiment. The scope of rights of the present invention is not limited by the connection method of the active element and the multilayer wiring.

  Further, as shown in FIG. 2, the logic circuit region is formed on the surface of the semiconductor substrate 1, the active element 3 b constituting the logic circuit 100, the memory circuit region, and the memory circuit 200. Each of the active elements 3a constituting the memory cell is formed. An element isolation film 2 is formed on the surface of the semiconductor substrate 1 in the space between the active element 3a and the active element 3b. The element isolation film 2 (silicon oxide film, etc.) and the active elements 3a, 3b (transistors, etc.) may be those according to a commonly used method for manufacturing a semiconductor device, and the scope of rights of the present invention depends on their structure or material. It is not limited.

  In the actual memory circuit 200, the longitudinal directions of the bit lines 12 and the gates of the active elements 3a constituting the memory cells are arranged in a substantially perpendicular relationship with each other, but for simplification of the drawing. In addition, the longitudinal direction of the gate of the active element 3a is illustrated as extending in the direction perpendicular to the paper surface, like the bit line 12. Regarding the positional relationship between the bit line 12 and the gate longitudinal direction of the active element 3b constituting the logic circuit 100, the same notation is used for the cross-sectional views in this specification unless otherwise specified. In this figure, an arrow indicates a surface, a hole, or a wiring groove.

  Next, the structure and materials of members constituting the semiconductor device of the first embodiment will be described in detail.

  As shown in FIG. 2, the contact interlayer insulating films 4, 5a are formed on the semiconductor substrate 1 on the element isolation film 2, the active element 3a (first active element), and the active element 3b (second active element). 5b are formed. A first cell contact (cell contact 10a, cell contact 10b) and a second cell contact (cell contact 10) are embedded in the contact interlayer insulating film 4 (cell contact insulating layer). On the other hand, a bit contact 11, a bit line 12, a capacitor contact 13c, and a connection contact 13a are buried in the contact interlayer insulating film 5 (contact insulating layer) constituted by the contact interlayer insulating films 5a and 5b. The capacitive contact 13c electrically connects the active element 3a and the capacitive element 19. The connection contact 13a electrically connects the active element 3b and the wiring 8a of the logic circuit 100. The cell contact 10a electrically connects the active element 3a and the bit contact 11. The cell contact 10b is formed between the semiconductor substrate 1 and the capacitor contact 13c, and electrically connects the active element 3a and the capacitor contact 13c. The cell contact 10 is formed between the semiconductor substrate 1 and the connection contact 13a, and electrically connects the active element 3b and the connection contact 13a. The lower surface of the connection contact 13a is in direct contact with the upper surface of the cell contact 10 (for example, when a barrier metal film is formed around the connection contact 13a, the barrier metal film on the lower surface of the connection contact 13a The upper surface of the cell contact 10 is in contact). The lower surface of the capacitor contact 13c is in direct contact with the upper surface of the cell contact 10b. The names of the contacts are defined in the specification of the present invention in order to clarify the names of the respective contacts, and the names of the contacts in the specification are based on the names described above.

  Further, the contact interlayer insulating films 4, 5 a, and 5 b (the contact insulating layer (contact interlayer insulating film 5) in which the capacitor contact 13 c and the connection contact 13 a are embedded, or between the contact insulating layer and the substrate, A silicon oxide film may be used for at least one of the cell contact insulating layer (contact interlayer insulating film 4) in which the one cell contact (cell contact 10b) and the second cell contact (cell contact 10) are embedded. It is more preferable that the insulating film has a relative dielectric constant lower than that of the silicon oxide film. As such an insulating film, for example, an insulating film generally referred to as a low dielectric constant film in which oxygen atoms of a silicon oxide film are substituted with fluorine, carbon atoms, and hydrocarbon groups, or at least silicon, oxygen, and carbon are used. Furthermore, a so-called porous film having fine pores having a diameter of several nanometers or less in the insulating film may be used. The dielectric constant of these insulating films is preferably 3.1 or less in the case of an insulating film having no fine vacancies in the film, and more preferably an insulating film having fine vacancies in the film. In the case of a film, it is preferably 2.6 or less. With such a structure, the parasitic capacitance of the contact can be reduced. As a result, the delay of the memory circuit and the logic circuit can be reduced, and the operation speed of the semiconductor element can be improved.

  In the memory circuit 200, one diffusion layer of the active element 3a and the bit line 12 are electrically connected by the bit contact 11 and the cell contact 10a. The other diffusion layer of the active element 3a and the capacitive element 19 are electrically connected by a cell contact 10b and a capacitive contact 13c. With such a structure, the active element 3a, the bit line 12, and the capacitive element 19 are connected to each other, and are a general memory cell of a DRAM (Dynamic Random Access Memory) circuit. Is configured.

  On the contact interlayer insulating film 5b, cap films 6a, 6b, 6c, 6d and interlayer insulating films 7a, 7b, 7c are alternately and sequentially stacked. In the logic circuit 100 region, wirings 8a, 8b and 8c are formed in the respective interlayer films. Thus, in the present embodiment, a multilayer wiring layer is formed. The wirings 8a, 8b, and 8c are more preferably formed by a dual damascene method that is usually used as a method for forming a multilayer wiring of a semiconductor device. Thereby, the manufacturing cost of the wiring can be reduced, and the via resistance connecting the wiring and the wiring existing in a different layer can be reduced. Note that the wirings 8b and 8c shown in FIG. 2 are labeled as wirings including vias for connection to the respective lower wirings 8a and 8b. That is, in this embodiment, unless otherwise specified, the wiring formed by the damascene method includes a via. A barrier metal film is formed around each of the wirings 8a to 8c. Note that all the wirings in this embodiment preferably have a dual damascene structure.

  In the present embodiment, as the metal wiring material, an alloy containing Cu, W, Al or the like, an alloy containing these as a main component (for example, containing 95% by mass or more), or a metal such as a metal made of these elements You can choose from materials. All of the wirings included in the logic circuit 100 may have a dual damascene structure and may be formed of a metal material containing Cu or containing Cu as a main component. Thereby, the operation speed of the semiconductor device can be improved. On the other hand, as the contact plug material (cell contact 10, cell contact 10a, cell contact 10b, bit contact 11, connection contact 13a, capacitance contact 13c, etc.), the same kind of material as the metal wiring material can be used. Although the same material or different materials may be used, a metal material containing W or containing W as a main component is preferable from the viewpoints of embedding characteristics and thermal stability. However, in this embodiment, the dual damascene structure is formed on the lowermost wiring 8a in the wiring layer in which the capacitive element 19 is embedded, and the contact interlayer insulating film 5b in which the capacitive contact 13c is embedded. The connection contact 13a is made of a single and the same kind of metal material (for example, a metal material containing Cu or containing Cu as a main component).

  The material of the interlayer insulating film may be a silicon oxide film or an insulating film having a low dielectric constant, which contains fluorine or carbon in the silicon oxide film, or a fine void is formed in the insulating film. A so-called porous film may be used. As the interlayer insulating film, an insulating material containing Si and containing at least one element out of C, O, and H, and using these constituent elements and containing voids in the film Use materials. It is desirable that the insulating material used here has a small pore size so that a vapor phase raw material used for forming a metal electrode or a capacitor insulating film in a capacitor element forming process to be formed later does not penetrate into the film. . In view of the fact that most of the gas phase raw material has a size of 0.5 to 1 nm, the pore size needs to be 1 nm or less, and desirably 0.5 nm or less. The dielectric constant of the interlayer insulating film is more preferably lower than that of the silicon oxide film in order to reduce the parasitic capacitance between the wirings, not limited to the logic circuit 100 and the memory circuit 200. Thereby, the parasitic capacitance between wirings can be reduced and the delay of circuit operation can be reduced. Further, the plurality of insulating films corresponding to the cap films 6a to 6d located on the metal material constituting the multilayer wiring are made of an insulating film made of silicon, carbon, nitrogen, or a laminated structure of films having them. More preferably, it is a film having diffusion resistance to metal (metal diffusion preventing film).

  In the logic circuit 100, the active element 3b and the wiring 8a of the lowermost layer (interlayer insulating film 7a) among the wirings constituting the multilayer wiring layer are connected in series by two contacts of the cell contact 10 and the connection contact 13a. Electrically connected. In the present embodiment, these wiring 8a and connection contact 13a have a dual damascene structure. With such a structure, there is no interface between the wiring 8a and the connection contact 13a. Therefore, the resistance values of the wiring 8a and the connection contact 13a are compared with the case where each is formed in a separate process (single damascene structure). Can be lowered. Therefore, in the semiconductor device of this embodiment, the operation speed of the logic circuit can be improved. In the present embodiment, the connection contact 13a is formed in the contact interlayer insulating film 5 in which the capacitor contact 13c is buried. However, the present invention is not limited to this mode, and the lowermost layer of the wirings constituting the multilayer wiring layer is not limited thereto. As long as the dual damascene structure is formed with the wiring 8a of the (interlayer insulating film 7a), the capacitor element 19 may be extended to the embedded interlayer insulating film.

Subsequently, the structure of the capacitive element 19 according to the present embodiment will be described.
The capacitive element 19 according to the present embodiment is formed as a memory element that constitutes the memory circuit 200. The capacitive element 19 is provided in a recess 40 provided in a two-layered multilayer composed of a cap film 6a, an interlayer insulating film 7a, a cap film 6b, an interlayer insulating film 7b, a cap film 6c, and wirings 8a and 8b. It is buried in. The recess 40 is composed of a hole 23 and a wiring groove 28 provided continuously outside the hole 23 in plan view. The wiring groove 28 is provided so as to extend in a predetermined direction from the periphery of the hole 23 in which the capacitive element 19 is embedded. The upper connection wiring 18 is embedded in the wiring groove 28. The opening surface of the recess 40 is formed so as to be in contact with the lower surface of the cap film 6c that is in contact with the upper surface of the uppermost wiring 8b in the wiring layer in which the capacitive element 19 is embedded. In other words, in the present embodiment, the upper connection wiring 18 and the upper surface of the wiring 8b constitute the same surface.

  In the hole 23, the capacitive element 19 formed by laminating is formed in a concave shape along the side wall, and an embedded electrode 18c is provided so as to fill the concave portion. An upper connection wiring 18 is formed on the buried electrode 18c. In the present embodiment, the upper connection wiring 18 and the buried electrode 18c are formed seamlessly because they are made of the same material and in the same process. That is, the upper connection wiring 18 is embedded in a recess formed by the lower electrode 14, the capacitor insulating film 15, and the upper electrode 16 constituting the capacitive element 19, and also functions as a buried electrode. The upper connection wiring 18 and the buried electrode can be formed in the same process.

  Further, the upper connection wiring 18 is embedded in the wiring groove 28 and has a lead-out wiring portion 18a connected to the upper layer wiring. A lead-out wiring portion 18 a is formed outside the side wall of the lower electrode 14. The bottom and side walls of the lead wiring portion 18 a are covered with the upper electrode 16. In particular, the upper electrode 16 and the capacitive insulating film 15 are formed immediately below the lead wiring portion 18a. A barrier metal film may be formed between the upper electrode 16 and the upper connection wiring 18.

  The lower electrode 14 and the upper electrode 16 function as electrodes for sandwiching the capacitive insulating film 15 to form parallel plate capacitive elements. The material of the lower electrode 14 and the upper electrode 16 is preferably formed of, for example, a refractory metal such as titanium or tantalum, or a nitride thereof, and the crystallinity of the capacitive insulating film 15 is improved. Preferably, a material that can be used is used.

Examples of the material of the capacitive insulating film 15 include silicon nitride films such as zirconium dioxide (ZrO ₂ ), zirconium aluminate (ZrAlO _x ), and a film obtained by adding lanthanoids such as Tb, Er, and Yb to zirconium dioxide. A material having a higher relative dielectric constant, an oxide containing any one of Zr, Ta, Hf, Al, Nb, and Si, or an oxide mainly containing any of these, and SrTiO ₃ It is more preferable to use a high dielectric material having a perovskite structure. By increasing the relative dielectric constant of the capacitive insulating film 15, the capacitance of the capacitive element 19 can be increased.

  In the present embodiment, as the upper connection wiring 18 (lead wiring part 18a, embedded electrode 18c), for example, a material containing W, TiN, Cu, and Al, or any one of these metal elements as a main component (for example, 95% by mass or more) or a material composed of these metal elements. In any case, inevitable atoms mixed in in the manufacturing process are allowed. In the embodiment, the reliability of the capacitor element 19 can be improved by using a metal material such as W or TiN as a metal material that is more stable in embedment and chemically. In addition, when using Cu, the upper connection wiring 18 and the wiring 8b may be comprised by the same process.

  Further, a common metal diffusion prevention film (cap film 6c) is formed on the upper surface of the upper connection wiring 18 and the upper surface of the wiring 8b constituting the logic circuit 100 formed in the same wiring layer as the upper connection wiring 18. ing. The cap film 6c formed in common here is a metal diffusion prevention film formed in the same process and continuously formed over the logic circuit 100 formation region and the memory circuit 200 formation region.

  The lower limit of the height in the layer thickness direction of the multilayer wiring layer of the capacitive element 19 (hereinafter sometimes simply referred to as the layer thickness direction) is one layer or more, more preferably two layers or more. The upper limit value of the height of the capacitive element 19 in the layer thickness direction is not particularly limited. Here, one layer is composed of one wiring layer (interlayer insulating films 7a, 7b) in the multilayer wiring layer and one cap film 6a, 6b, 6c formed between the wiring layers. The capacitive element 19 of the present embodiment is formed over two layers of multilayer wiring layers, but is not limited to this, and may be formed over multilayer wirings of any number of layers. However, if a large number of wiring layers are occupied in the memory circuit formation region, a situation where wiring resources are insufficient may occur, so that about two layers are preferable.

Further, in the upper connection wiring 18 constituting the capacitive element 19 according to the present embodiment, the height in the layer thickness direction of the extraction wiring portion 18a drawn for external connection is the layer thickness of the wiring 8b of the logic circuit 100. It is preferably equal to or less than the height in the direction, and more preferably lower than the height of the wiring 8b. As a result, the height of the lower electrode 14 occupying the predetermined wiring layer thickness can be increased, so that the capacitance of the capacitive element 19 can be improved. In general, the layer structure of a semiconductor device is determined so as to satisfy a design parameter. Therefore, for example, the thickness of a wiring layer cannot be changed in order to form a capacitive element. Therefore, when a capacitive element is formed in the wiring layer, the contact area of the lower electrode 14, the capacitive insulating film 15, and the upper electrode 16, which functions as an electromagnetic capacitance, is increased. It is necessary to increase the height of the lower electrode 14.
In the present embodiment, since the upper connection wiring 18 is made of the same material as that of the embedded electrode and is integrally formed, the height of the upper connection wiring 18 is formed low in order to increase the height of the lower electrode 14. Can do.

  In the present embodiment, the upper connection wiring 18 has a lead-out wiring portion 18a extending outward from the region where the lower electrode 14 is provided in a top view, and the capacitor element 19 is Connection to a fixed potential for causing the memory circuit 200 to function as a memory cell may be performed by connecting a wiring 201 having a fixed potential to the lead wiring portion 18a. For this reason, the designer of the semiconductor device can realize a free wiring layout by using the wiring layer in the region where the lower electrode 14 exists in the upper wiring layer of the capacitive element 19, for example, The signal wiring 202 can be used as a backing wiring for a word line or a bit line of the memory circuit 200.

  Further, at least one or more wirings 8 a and 8 b constituting the logic circuit 100 are formed in the same wiring layer of the capacitive element 19. More preferably, wirings (wirings 8a and 8b) constituting the logic circuit 100 are necessarily formed in the same wiring layer (interlayer insulating film 7a to interlayer insulating film 7b) of the capacitive element 19. In other words, the height of the capacitive element 19 in the layer thickness direction can be configured to be the same as the total value of the heights of the plurality of wirings formed in the same layer as the capacitive element 19 in the layer thickness direction. Further, the same wiring layer of the capacitive element 19 may be configured such that there is no layer in which only contacts are formed.

  The shape of the capacitive element 19 is not particularly limited, but may be, for example, a cylinder shape, a T shape, or the like. The capacitive element 19 is formed in an interlayer insulating film that is the same material as the interlayer insulating film material constituting the logic circuit 100. In the present embodiment, a plurality of capacitive elements 19 are formed. The plurality of capacitive elements 19 may be electrically independent of the lower electrode 14 or may be electrically connected to the common lower electrode 14 of each capacitive element 19.

  As shown in FIG. 2, in the memory circuit 200 of the semiconductor device, a plurality of capacitive elements 19 are arranged in parallel in the substrate horizontal direction. The plurality of capacitive elements 19 are collectively formed. The upper surface of any of the upper connection wirings 18 of the plurality of capacitive elements 19 forms the same surface as the upper surface of the wiring 8b. The semiconductor device of this embodiment has the scale of the logic circuit 100 corresponding to the scale. For this reason, the memory circuit 200 needs to include as many capacitive elements 19 as are necessary to configure the semiconductor device. In FIG. 2, a wiring 201 having a fixed potential is connected to the lead wiring part 18 a of the capacitive element 19. The potential of the fixed potential wiring 201 can be arbitrarily set by the designer of the memory circuit. Furthermore, according to the first embodiment, a plurality of signal wirings 202 may be arranged above the capacitive element 19.

  Note that a wiring layer including a wiring and an interlayer insulating layer is further provided above the wiring 201 having a fixed potential, the signal wiring 202, and the wiring 8c forming the logic circuit 100, which constitute the memory circuit 200 shown in FIG. May be formed. As a result, a semiconductor device can be configured by forming a multilayer wiring structure of a commonly used semiconductor device. Since it is obvious to the business operator that such a semiconductor device can be configured, in the present invention, the wiring layer 201 having the fixed potential, the signal wiring 202, and the wiring layer on which the wiring 8c is formed are further layered. The structure diagram of the wiring located in FIG.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described in detail with reference to the drawings.
3 to 23 are process diagrams showing the method of manufacturing the semiconductor device according to the first embodiment.

  The method for manufacturing a semiconductor device according to the present embodiment is a method for manufacturing a semiconductor device having a memory circuit 200 and a logic circuit 100 on the same substrate (semiconductor substrate 1). Forming the contact interlayer insulating film 5) and forming a first through hole penetrating the contact interlayer insulating film 5 in the circuit forming region and filling the first through hole with the first metal material, thereby forming the capacitor contact 13c. Forming the insulating layer (interlayer insulating film 7a) on the contact interlayer insulating film 5, and selectively removing the contact interlayer insulating film 5 and the interlayer insulating film 7a in the logic circuit formation region. Thus, the second through-hole (opening 9b) penetrating the contact interlayer insulating film 5 is formed, and the opening 9b is selectively removed by removing the interlayer insulating film 7a. A continuous wiring groove is formed in the interlayer insulating film 7a, and the second through hole and the wiring groove (opening 9d) are filled with the second metal material, thereby forming the connection contact 13a and the wiring (wiring 8a). And a step of forming a recess 40 reaching the capacitor contact 13c in the interlayer insulating film 7a in which the wiring 8a is formed and embedding the capacitor element 19 in the recess 40 in the circuit formation region.

  First, as shown in FIG. 3, an element isolation film 2 and active elements 3a and 3b are formed on a semiconductor substrate 1 by a commonly used method. Further, the contact interlayer insulating film 4, the cell contacts 10, 10a and 10b, the contact interlayer insulating films 5a and 5b, the bit contact 11, the bit line 12 and the capacitor contact 13c are formed on these. In the method for manufacturing a semiconductor device of the present embodiment, the steps up to the formation of the capacitor contact may be performed by a commonly used method for manufacturing a semiconductor device. For example, although not shown, after the contact interlayer insulating film 4 is deposited after the active elements 3a and 3b are formed, an opening serving as a cell contact is opened by a photolithography method, and then a contact material is formed by a CVD (Chemical Vapor Deposition) method. The cell contacts 10, 10a, and 10b are formed by embedding and removing the surplus contact material by CMP (Chemical Mechanical Polishing). Thereafter, after depositing a contact interlayer insulating film 5a for bit contact, an opening of the bit contact 11 is formed by photolithography and reactive ion etching. Thereafter, a metal material containing W, containing W as a main component, or made of W is deposited by a CVD method, and then the bit contact 11 and the bit line 12 are formed by a photolithography method and a reactive ion etching method. Thereafter, a contact interlayer insulating film 5b is deposited, planarized by CMP, and then a capacitor contact 13c is formed by a method similar to the method for forming the cell contact 10. Through the above steps, the structure shown in FIG. 3 can be realized.

  In FIG. 3, an alloy of silicon and a metal such as cobalt, nickel, or platinum, generally called silicide 20, is formed on the surface of the diffusion layer region. As the gate electrodes of the active elements 3a and 3b, a commonly used polysilicon electrode, a partially silicided polysilicon electrode, or a metal gate electrode that has been developed in recent years may be used. Furthermore, as a method for forming a metal gate electrode, a gate first method, a gate last method, and the like are known, and both of them are applied to both the memory circuit and the logic circuit according to this embodiment. Is possible. For this reason, in FIG. 3, a more general polysilicon gate is assumed in the drawing. In addition, according to a normally used method for manufacturing a semiconductor device, the cell contacts 10, 10a and 10b, the bit contact 11 and the bit line 12, and the capacitor contact 13c are often formed of tungsten. The material of the bit line does not impair the scope of the present invention. For example, the contact and the bit line may be made of copper or an alloy containing copper as a main component. Furthermore, when the contact is formed, when the contact material is embedded in the opening, a barrier metal made of titanium, nitride thereof, or the like is generally formed on the bottom surface. This is not particularly shown because it does not affect the configuration and effects of the embodiment. That is, the structure and the manufacturing method according to the present embodiment are characterized by the structure and the formation method of the capacitor and the logic circuit wiring located substantially in the same layer as the capacitor. With respect to the other parts to be configured, these do not impair the structure and effects of the present embodiment, and therefore, a structure and a manufacturing method of a semiconductor device that are usually used may be used.

  In addition, the low dielectric constant film may be used for at least one of the contact interlayer insulating films 4, 5a, 5b. Further, these contact interlayer insulating layers may be formed by stacking different types of low dielectric constant films. In addition, by depositing a low dielectric constant film (for example, an insulating film deposited by a surface reaction using a plasma polymerization method) having an excellent step burying property on the lower layer, the burying property between narrow pitch gates is improved, and the semiconductor device Reliability can be improved.

  Next, in FIG. 4, a cap film 6a and an interlayer insulating film 7a are deposited on the contact interlayer insulating film 5b having the capacitor contact 13c. The cap film 6a is more preferably an insulating film that functions as an etching stopper having a high selectivity with respect to the interlayer insulating film 7a when the interlayer insulating film 7a is subjected to reactive ion etching. However, in the structure of the present embodiment, Is not always necessary. Subsequently, after forming a hard mask 21a on the interlayer insulating film 7a, a multilayer resist layer including a lower layer resist 24a (flat film), a low-temperature oxide film 25a, an antireflection film 26a, and a photoresist 27a is further formed. A photoresist 27a is formed by a method such as a coating method, and a via pattern of a desired logic circuit wiring is transferred by a photolithography method to form an opening 9a.

  Next, as shown in FIG. 5, via openings 9b are formed by a method such as reactive ion etching using the photoresist 27a as a mask. Then, these multilayer resist layers are removed. For example, after the photoresist 27a and the like are removed by ashing, the hard mask 21a is left on the interlayer insulating film 7a.

  Next, as shown in FIG. 6, a multilayer resist layer including a lower layer resist 24b (flat film), a low temperature oxide film 25b, an antireflection film 26b, and a photoresist 27b is formed on the hard mask 21a. Then, an opening 9c having a desired logic circuit pattern is formed in the photoresist 27b by photolithography.

  Next, as shown in FIG. 7, an opening 9d of the logic circuit wiring is formed by a method such as reactive ion etching using the photoresist 27b as a mask. The opening 9d has a dual damascene shape. After the opening 9d of the wiring is formed, the interlayer insulating film 7a is etched using an etching condition in which the etching rate with respect to the cap film 6a is higher than the etching rate with respect to the interlayer insulating film 7a, and the connection with the cell contact 10 of the logic circuit. An opening is formed. Then, the multilayer resist layer is removed. Although not shown, the hard mask 21a may be removed by reactive ion etching after forming the wiring opening 9d.

  Next, as shown in FIG. 8, a barrier metal film and a conductive film are buried in the opening 9d of the logic circuit wiring at a time. As a material constituting the barrier metal film, titanium, tantalum, ruthenium, or a nitride thereof, or a laminated film thereof may be used. The barrier metal film is preferably configured so that the conductive film does not diffuse. The conductive film may be made of a material that forms wiring of a semiconductor device that is usually used, such as copper or an alloy containing copper as a main component. Subsequently, the conductive film, the barrier metal film, and the hard mask 21a are removed by a method such as a CMP method, and a wiring 8a that forms a logic circuit is formed. In this way, the wiring 8a of the logic circuit 100 provided in the interlayer insulating film 7a and the connection contact 13a provided in the contact insulating layer (contact interlayer insulating films 5a and 5b) in which the capacitor contact 13c is formed are dually provided. It can be configured with a damascene structure.

  Subsequently, as shown in FIG. 9, a cap film 6b is deposited so as to cover at least the upper surface of the wiring 8a. Like the cap film 6a, the cap film 6b is preferably an insulating film from which the material constituting the wiring 8a does not diffuse. For example, the cap film 6b is an insulating film containing an element such as silicon, carbon, nitrogen, or the like. A laminated structure may also be used. Subsequently, after an interlayer insulating film 7b is deposited on the cap film 6b, an insulating film to be a hard mask 21b for cylinder type capacitive element processing is deposited on the interlayer insulating film 7b. The hard mask 21b is preferably an insulating film having a high selection ratio with respect to the interlayer insulating film 7b when the interlayer insulating film 7b is processed. For example, a silicon oxide film is preferable. A photoresist 22 is deposited on the hard mask 21b. Then, a desired wiring groove pattern of the upper connection wiring is formed in the photoresist 22 by a method such as photolithography. In FIG. 9, the photoresist 22 is illustrated as a single-layer photoresist, but for example, a multi-layer photoresist such as a planarized organic film, a silicon oxide film, an antireflection film, or a photosensitive resist that has been recently used. A resist layer may be used.

  Next, as shown in FIG. 9, using the photoresist 22 as a mask, a wiring groove 28 of the upper connection wiring is formed in the interlayer insulating film 7b to form the upper connection wiring of the capacitive element. As a processing method, for example, a fine processing method such as reactive ion etching may be used. The height of the wiring trench 28 can be controlled by appropriately adjusting such etching conditions (selection ratio, etc.). Thereafter, the photoresist 22 is removed.

  Subsequently, as shown in FIG. 10, a multilayer resist layer composed of a lower layer resist 24c, a low temperature oxide film 25c, an antireflection film 26c, and a photoresist 27c is formed on the interlayer insulating film 7b and the hard mask 21b in the wiring trench 28. Form. A hole pattern in which a desired capacitor element is embedded is formed in the photoresist 27c by a method such as photolithography.

  Subsequently, as shown in FIG. 11, in order to form a cylinder-type capacitive element, the hole 23 is formed by a fine processing method such as reactive ion etching using the photoresist 27c as a mask. The multilayer resist layer such as the photoresist 27 c is removed by ashing during the processing of the hole 23. The hole 23 may be processed using the hard mask 21b. FIG. 11 is a sectional view showing a state in which a multilayer resist layer such as the photoresist 27c is completely removed.

Note that the lower layer resist 24c (planarization film) deposited outside the cylindrical hole 23 is removed during the reactive ion etching process or after the interlayer insulating film 7b is processed by the reactive ion etching. Next, the cap film 6 a is processed by reactive ion etching to form an opening for connection with the capacitor contact 13 c located further below the hole 23. As a method for removing the lower layer resist 24c, for example, when an ashing process using CO ₂ or O ₂ plasma is used, it is more preferable to use a low dielectric constant film having excellent processing damage resistance as the interlayer insulating films 7a and 7b. For example, as described in Non-Patent Document 1, a film having high resistance to process damage due to reactive ion etching is more preferable. For example, as a preferable example of the low dielectric constant interlayer insulating film, an organic silica film having a high carbon composition will be briefly described below. For example, as a raw material of the organic silica film, a film is formed using an organic siloxane having a six-membered cyclic siloxane as a main skeleton and an organic group as a functional group. The organic functional group bonded to the silicon atom is preferably an unsaturated hydrocarbon group and an alkyl group. Examples of the unsaturated hydrocarbon group include a vinyl group, a propenyl group, an isopropenyl group, a 1-methyl-propenyl group, a 2-methyl-propenyl group, and a 1,2-dimethyl-propenyl group. A particularly preferred unsaturated hydrocarbon group is a vinyl group. The alkyl group is preferably a functional group that is spatially bulky and functions as a steric hindrance group, such as an isopropyl group, an isobutyl group, and a tert-butyl group. By using these raw materials, a very fine (mainly 0.5 nm or less) independent pore structure can be introduced into the organic silica film. Further, the SCC film is a kind of SiOCH film, but has copper diffusion resistance, and has a carbon composition higher than that of a generally known SiOCH film. In other words, when compared with the carbon / silicon ratio, about four times as much carbon as a general SiOCH film is contained. On the other hand, the oxygen element ratio is relatively smaller than that of a general SiOCH film and is about ½. This is because the SCC film is formed by plasma polymerization instead of plasma CVD, which dissociates and activates the raw material in plasma, and unsaturated hydrocarbons are activated preferentially while retaining the silica skeleton. This is realized because it is easy to control the chemical structure of the insulating film. Thus, by obtaining an organic silica film having a high carbon composition, a film having high resistance against process damage can be obtained.

  In this embodiment, the manufacturing method is shown in which the wiring groove 28 of the upper connection wiring is formed first, and the hole 23 for embedding the capacitor element is formed later. However, the hole 23 for embedding the capacitor element is formed first. Then, it may be performed later by a method of forming the wiring groove 28 of the upper connection wiring.

  Next, as shown in FIG. 12, the lower electrode 14 is deposited in the hole 23 and the wiring groove 28 formed by the manufacturing method shown up to FIG. As a method for forming the lower electrode 14, a method usually used for forming a semiconductor device, such as a CVD method, a sputtering method, an ALD (Atomic Layer Deposition) method, or the like may be used. Before the lower electrode 14 is deposited, for example, the surface may be etched by RF sputtering or the like in order to improve the contact with the capacitor contact 13c. Details will not be described because they are not damaged. As a material constituting the lower electrode 14, for example, refractory metals and their nitrides such as titanium and titanium nitride, tantalum and tantalum nitride, ruthenium, or a laminated structure thereof may be used. . According to the manufacturing method of the present embodiment, the lower electrode 14 is formed using a TiN film.

  Next, as shown in FIG. 13, a photoresist 29 is embedded in the hole 23 of the cylinder type capacitor in which the lower electrode 14 is deposited, for example, by a coating method. The photoresist 29 is preferably formed at a height that remains only inside the hole 23 and does not reach the upper end of the hole 23. If necessary, the photoresist 29 is exposed and developed. By performing, unnecessary photoresist may be removed.

  Next, as shown in FIG. 14, the lower electrode 14 is etched back by a method such as a reactive ion etching method. As shown in FIG. 13, by performing etch back with the photoresist 29 remaining only in the hole 23, the lower electrode having a height that does not reach the uppermost layer of the opening 23, such as the capacitive element 19. 14 can be formed.

Next, as shown in FIG. 15, a capacitive insulating film 15 is deposited on the lower electrode 14. That is, the capacitor insulating film 15 is formed so as to cover at least the bottom surface of the hole 23, the sidewall, the bottom surface of the wiring groove 28, and the sidewall. As a method for forming the capacitor insulating film 15, a method usually used for forming a semiconductor device, such as a CVD method, a sputtering method, or an ALD method, may be used, but in order to improve the capacitance of the capacitor element, a few nm. It is more preferable to use the ALD method capable of depositing the thin film with good uniformity. As the capacitor insulating film 15, for example, zirconium dioxide (ZrO ₂ ), zirconium aluminate (ZrAlO _x ), or a film obtained by adding a lanthanoid such as Tb, Er, Yb to zirconium dioxide, or the like may be used. According to the manufacturing method of the present embodiment, the capacitor insulating film 15 is formed using ZrO ₂ . Although not shown, after the capacitor insulating film 15 is deposited, sintering for improving crystallinity may be performed.

  Next, as shown in FIG. 16, the upper electrode 16 is deposited on the capacitive insulating film 15. That is, the upper electrode 16 is formed so as to cover at least the hole 23, the wiring groove 28, and the hard mask 21b. At this time, the entire upper surface of the semiconductor substrate 1 may be covered with the upper electrode 16. As a material constituting the upper electrode 16, for example, refractory metals such as titanium and nitride of titanium, tantalum and nitride of tantalum, ruthenium, and nitrides thereof, or a laminated structure thereof may be used. . As a method for forming the upper electrode 16, a method usually used for forming a semiconductor device, such as a CVD method, a sputtering method, or an ALD method, may be used. According to the manufacturing method of the present embodiment, the upper electrode 16 is formed using a TiN film.

  Next, as shown in FIG. 17, a conductive film 39 is formed so as to fill the hole 23 and the wiring groove 28 and on the hard mask 21b of the logic circuit. The conductive film 39 can be formed using a metal material containing W, TiN, Cu, Al, or an alloy containing these metal materials as a main component.

  Next, as shown in FIG. 18, the conductive film 39 is left in the wiring trench 28 by selectively removing the conductive film 39 by a method such as CMP. Thereby, the upper connection wiring 18 can be embedded in the wiring groove 28.

  Next, as shown in FIG. 19, a hard mask 21c is formed so as to cover the upper surface of the upper connection wiring 18 and the upper surface of the hard mask 21b.

  Next, as shown in FIG. 20, the interlayer insulating film 7b and the cap film 6b are selectively removed by the same formation method as that of the wiring 8a (for example, by the method shown in FIGS. 4 to 7). An opening 37 that reaches the upper surface of 8a and is formed of a wiring pattern and a via pattern of a logic circuit is formed.

  Next, as shown in FIG. 21, a barrier metal film and a conductive film 38 are buried at once in the opening 37 of the logic circuit wiring. As a material constituting the barrier metal film, titanium, tantalum, ruthenium, or a nitride thereof, or a laminated film thereof may be used. The barrier metal film is preferably configured such that the conductive film 38 does not diffuse. The conductive film 38 may be made of a material for forming a wiring of a commonly used semiconductor device, such as copper or an alloy containing copper as a main component.

  Next, as shown in FIG. 22, the conductive film 38, the barrier metal film, and the hard masks 21b and 21c are removed by a method such as a CMP method, and a wiring 8b that forms a logic circuit is formed. At this time, CMP can be performed so that the upper surface of the upper connection wiring 18 and the upper surface of the wiring 8b constitute the same surface.

Next, as shown in FIG. 23, after forming the cap film 6c on the upper surface of the upper connection wiring 18 and the upper surface of the wiring 8b, the capacitive element 19 constituting the memory circuit and the upper connection wiring of the capacitive element 19 are formed. The interlayer insulating film 7c, the wiring 201 having a fixed potential, the signal wiring 202, the wiring 8c, and the cap film 6d are formed on the upper layer of the wiring 8b located in the same layer as that 18 by a commonly used semiconductor device manufacturing method. .
As described above, the semiconductor device of the present embodiment is obtained.

Next, the function and effect of the first embodiment will be described.
In the present embodiment, the capacitive element 19 is embedded in the multilayer wiring layer, and at least one wiring layer (the wiring 8a and the interlayer insulating film 7a constituting the logic circuit 100) is interposed between the capacitive elements 19. Is provided. With such a structure, it is possible to prevent the multilayer wiring layer from becoming thick while securing the capacitance of the capacitive element 19. As a result, the contact height of the logic circuit 100 can be kept low, and an increase in parasitic resistance and parasitic capacitance due to insertion of the capacitive element 19 can be suppressed.

As a result of investigations by the inventors, in the semiconductor device described in Patent Document 1, when the logic contact and the logic wiring are formed in two steps, an interface resistance is generated between them, which decreases the operation speed of the logic circuit. Was found to cause.
On the other hand, in the present embodiment, the wiring 8a of the logic circuit 100 provided in the lowermost layer (interlayer insulating film 7a) of the wiring layer in which the capacitive element 19 is embedded, and the contact in which the capacitive contact 13c is formed. The connection contact 13a provided in the insulating layer (contact interlayer insulating films 5a and 5b) has a dual damascene structure. Since no interface is formed between the wiring 8a having such a dual damascene structure and the connection contact 13a, generation of interface resistance can be suppressed. Therefore, according to the present embodiment, since the parasitic resistance of the wiring 8a and the connection contact 13a can be significantly reduced as compared with the conventional case, it is possible to suppress a decrease in the operating speed of the logic circuit 100.

  For example, as a result of the study by the present inventors, as a wiring 8a and a connection contact 13a, a 45 nm node (70 nm diameter contact), a Cu wiring / W contact plug structure (single damascene) and a Cu wiring / Cu contact plug dual damascene structure As a result of the comparison, it was found that the latter reduced the resistance by about 75%. A more remarkable effect can be expected after the 28 nm node. Further, the parasitic capacitance of the contact interlayer insulating film 5 can be reduced by forming at least a part of the contact interlayer films (contact interlayer insulating films 4 and 5) (for example, the contact interlayer insulating film 5) with a low dielectric constant film. Therefore, according to the present embodiment, it is possible to realize a device with low parasitic resistance and low parasitic capacitance regardless of the presence or absence of the capacitive element 19, and to reduce signal delay and power consumption during operation of the semiconductor device. Become.

As described above, in this embodiment, the connection contact 13a of the logic circuit 100 is made of a low-resistance material such as Cu (low resistance due to the material) and dual damascene (low resistance due to the structure). As a result, the parasitic resistance of the connection contact 13a is significantly reduced, and the contact interlayer insulating film 5 in which the connection contact 13a is embedded is formed of a low dielectric constant film (low parasitic capacitance due to the material). By adopting such a configuration, it is possible to reduce delay during operation of the semiconductor device, improve the processing speed of the semiconductor device, and reduce power consumption. In addition, the embodiment employing such a structure can reduce the difference in design parameters from a pure-logic chip formed using a contact interlayer insulating film 5 made of, for example, SiO ₂ .

In the present embodiment, the upper surface of the upper connection wiring 18 and the upper surface of the wiring 8b constituting the logic circuit 100 constitute the same surface. For this reason, the variation in the etching amount between the upper surface of the upper connection wiring 18 and the upper surface of the wiring 8b is suppressed. For example, when the wiring 201 having a fixed potential connected to the upper connection wiring 18 and the wiring 8c connected to the wiring 8b are simultaneously formed, the respective etching amounts of the upper surface of the upper connection wiring 18 and the upper surface of the wiring 8b are The same level. For this reason, reliability improves and it is excellent in a yield.

  Further, the CMP process for the upper connection wiring 18 of the capacitor 19 and the wiring 8b of the logic circuit 100 can be performed separately. For this reason, a metal material such as low resistance copper is used as the wiring 8b constituting the logic circuit 100, and a metal material such as tungsten having excellent embedding property and chemically stable as the metal electrode of the capacitor element 19 is used as the electrode material. As a result, the reliability of the capacitive element can be further improved.

  Further, since the upper connection wiring 18 and the buried electrode 18c are made of the same material, they are formed in the same process. That is, when the upper connection wiring 18 is formed, it is not necessary to etch back the embedded electrode in order to secure a space for forming the upper connection wiring as shown in Patent Document 1. For this reason, it is suppressed that an embedded electrode is etched excessively. For this reason, reliability improves and it is excellent in a yield. In addition, the production cost is reduced by using the same material. Since the upper connection wiring 18 and the buried electrode 18c are formed of the same material at the same time, they are configured seamlessly. For this reason, since there is no interface, the contact resistance of the semiconductor device can be reduced.

  Further, in the upper connection wiring 18 constituting the capacitive element 19, the height of the extraction wiring portion 18a drawn for external connection can be made lower than the wiring height of the wiring 8b of the logic circuit 100. Thereby, the height of the capacitive insulating film 15 constituting the capacitive element 19 can be increased. Therefore, the effective capacitance value of the capacitive element 19 can be improved, and the operation margin of the memory circuit 200 can be widened.

  The capacitive element 19 is formed in an interlayer insulating film that is the same material as the interlayer insulating film material constituting the logic circuit 100. That is, the interlayer insulating layer 7a of the multilayer wiring layer in which the capacitor element 19 is embedded has the same material as the interlayer insulating film 7a in which the wiring 8b formed in the same layer as the capacitor element 19 is provided. In addition, since the interlayer insulating film 7a has a dielectric constant lower than that of the silicon oxide film, the parasitic capacitance of the capacitive element 19 can be reduced.

  Furthermore, it becomes possible to share design parameters for designing a logic circuit and design parameters for designing a semiconductor device in which a memory circuit and a logic circuit are mixedly mounted on the same semiconductor substrate. The design cost of the semiconductor device can be reduced.

  Further, at least one layer of the insulating film material including the connection portion connecting the active element and the bit line can be a low dielectric constant film. By using a low dielectric constant film for the contact interlayer film, the delay due to the contact interlayer film parasitic capacitance can be further reduced, and the performance of the semiconductor device can be improved. Furthermore, since the difference between the design parameter of the Pure-Logic chip and the design parameter of the Logic portion of the embedded DRAM can be reduced, it is necessary to redesign when using the IP designed by the Pure-Logic product in the embedded DRAM. Man-hours can be compressed. Further, by using a low dielectric constant film for the bit line layer, the bit line parasitic capacitance is reduced, and the signal voltage margin at the time of DRAM reading is widened, so that the operation reliability can be improved.

  Which of the contact interlayer insulating films 4, 5 a, and 5 b uses the low dielectric constant film depends on the circuit performance of the logic circuit of the semiconductor device in which the memory circuit is embedded and the logic circuit of the semiconductor device in which the memory circuit is not embedded. It may be determined by a semiconductor device manufacturer or a designer so that the range of performance deterioration due to the mixed mounting of the memory circuit is within an allowable range by comparing the circuit performance with the circuit performance. In the present embodiment, the capacitive element is formed so as to be embedded in the interlayer insulating film constituting the logic circuit wiring. As a result, it is possible to suppress the increase in the height of the contact, which increases the parasitic resistance and parasitic capacitance of the active element in the logic circuit, causing a decrease in the operation speed of the logic circuit.

  As described above, this embodiment can be applied to a semiconductor device having a transistor and a multilayer wiring. By suitably applying this embodiment mode, a memory circuit and a logic circuit can be mounted on the same semiconductor substrate at a low cost and with a high yield.

(Second Embodiment)
Next, a semiconductor device according to a second embodiment will be described with reference to the drawings.
FIG. 24 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment. In the second embodiment, the (first wiring) wiring 8a of the logic circuit 100 provided in the lowermost layer (interlayer insulating film 7a) of the wiring layer in which the capacitive element 19 is embedded, and the capacitive contact 13c are formed. The connection contact 13a provided in the contact interlayer insulating film 5 has a single machine structure and is made of a metal material containing copper, and is different from that of the first embodiment. It is the same.

  In the method of manufacturing the semiconductor device according to the second embodiment, in the contact interlayer insulating film 5, a metal material is embedded in the via opening of the connection contact 13a, and then the interlayer insulating film 7a is formed on the contact interlayer insulating film 5. Then, a wiring groove pattern of the wiring 8a is formed in the interlayer insulating film 7a. Then, a metal wiring material is embedded in this wiring groove pattern. As described above, the wiring 8a and the connection contact 13a having the single damascene structure described above can be formed.

  That is, in the method of manufacturing the semiconductor device of the second embodiment, a contact insulating layer (contact interlayer insulating film 5) is formed on the semiconductor substrate 1, and the contact interlayer insulating film 5 is penetrated in the memory circuit formation region. Forming a first contact hole, and embedding the first through hole with a first metal material, thereby forming a capacitor contact 13c and forming an insulating layer (interlayer insulating film 7a) on the contact interlayer insulating film 5. In the process and the logic circuit formation region, by selectively removing the contact interlayer insulating film 5 and the interlayer insulating film 7a, a second through hole (opening 9b) penetrating the contact interlayer insulating film 5 is formed. By forming the connection contact 13a by embedding the second metal material containing copper in the opening 9b and selectively removing the interlayer insulating film 7a, A wiring groove (opening 9d) continuous with the opening 9b is formed in the interlayer insulating film 7a, and the wiring groove (opening 9d) is filled with a second metal material containing copper, thereby wiring (wiring 8a). And forming a recess 40 reaching the capacitor contact 13c in the interlayer insulating film 7a on which the wiring 8a is formed, and embedding the capacitor element 19 in the recess 40 in the memory circuit formation region. It is.

As a result of the study by the present inventors, in the semiconductor device described in Patent Document 1, the logic contact and the logic wiring are made of W, which is a material having a relatively high resistance value. As a result, it has been found that the operation speed of the logic circuit is lowered.
On the other hand, in the second embodiment, the wiring 8a and the capacitor contact 13c are made of a material having a lower resistance value than W, for example, an alloy containing copper and containing copper as a main component or a metal material made of copper. It is configured. Such a connection contact 13a has a resistance value lower than that of W. Therefore, according to the present embodiment, since the parasitic capacitance of the wiring 8a and the connection contact 13a can be reduced as compared with the conventional case, a decrease in the operation speed of the logic circuit 100 can be suppressed. Note that the second embodiment can provide the same effects as those of the first embodiment.

(Third embodiment)
Next, a semiconductor device according to a third embodiment will be described with reference to the drawings.
FIG. 25 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. The third embodiment is the same as the first embodiment except that at least a part of the capacitor contact 13c is composed of the lower electrode 14. In other words, in the third embodiment, the capacitive contact 13c is configured by a part of the capacitive element 19, and the capacitive element is connected to a contact plug (capacitor contact 13c) that connects the capacitive element 19 and the active element 3a. 19 lower electrodes 14 are used.

  In the third embodiment, as shown in FIG. 25, the hole 23 in which the capacitive element 19 is embedded penetrates the contact interlayer insulating film 5 together with the interlayer insulating films 7a and 7b, and is formed on the upper surface of the cell contact 10b. Has reached. The opening diameter of the hole 23 may gradually decrease from the upper surface to the lower surface, and as shown in FIG. 25, a corner portion is formed on the side wall, and a multistage having two or more opening diameters. You may have a structure.

  Further, in the hole 23 embedded in the contact interlayer insulating film 5, the lower electrode 14 is embedded entirely. For example, all the stacked bodies (capacitor elements 19) of the lower electrode 14, the capacitor insulating film 15, and the upper electrode 16. ) May be buried. The former capacitive contact 13c functions as a contact plug for connecting the cell contact 10b and the capacitive element 19, and the latter capacitive contact 13c exhibits the function of the capacitive element as well as the function of the contact plug.

  FIG. 26 is a process cross-sectional view illustrating the manufacturing procedure of the semiconductor device according to the third embodiment. The manufacturing method of the third embodiment is substantially the same as that of the first embodiment, but the step of forming the opening pattern of the capacitor contact 13c connecting the capacitor element 19 and the active element 3a by self-alignment. Including points are different. That is, as shown in FIG. 26, a contact pattern (hole 23) is opened in the contact interlayer insulating film 5 between the bit lines 12 by self-alignment. Thereafter, the lower electrode 14 is formed on at least the bottom surface and the side wall of the hole 23 as in FIG. Through the steps after FIG. 15, the capacitor 19 and the cell contact 10 b are electrically connected to obtain the semiconductor device of the third embodiment.

In the third embodiment, since the capacitor contact 13c is self-aligned, a series of patterning steps including lithography and processing can be eliminated once, and the manufacturing cost can be reduced.
In the third embodiment, the metal film constituting the lower electrode is used in combination with the capacitive contact 13c and the lower electrode 14 of the capacitive element 19, thereby eliminating one patterning step. In addition, the cell capacity can be increased by increasing the surface area of the capacitive element 19, and a low-cost and high-performance storage circuit can be realized. Furthermore, since the difference between the design parameters of the pure logic chip and the design parameters of the logic portion of the embedded DRAM can be reduced, the number of man-hours required for redesign when using an IP designed with a pure logic product in the embedded DRAM. Can be reduced. Further, by adopting a low dielectric constant film for the contact interlayer insulating film 5b in which the bit line 12 is embedded, the bit line parasitic capacitance is reduced, and the signal voltage margin at the time of DRAM reading is widened, thereby improving the operation reliability. Can be improved. Note that the same effects as those of the first embodiment are also obtained in the third embodiment.

(Fourth embodiment)
Next, a semiconductor device according to a fourth embodiment will be described with reference to the drawings.
FIG. 27 is a cross-sectional view showing the structure of the semiconductor device of the fourth embodiment. In the fourth embodiment, the capacitor is provided in the multilayer wiring layer and includes the lower electrode 14, the capacitor insulating film 15, and the upper electrode 16 in the recess 40 in which the capacitor element 19 is embedded. The upper surface 30 of the upper connection wiring 18 stacked on the element 19 and the wiring 8b constituting the logic circuit 100 provided in the uppermost layer (interlayer insulating film 7b) among the wiring layers in which the capacitive element 19 is embedded. The upper surface 34 of the cap layer 6c provided so as to be in contact with the upper surface is the same as that of the first embodiment except that it forms the same surface. In the fourth embodiment, the same plane is specified by the same definition as that of the first embodiment.

  The method for manufacturing a semiconductor device according to the fourth embodiment is a method for manufacturing a semiconductor device having a memory circuit 200 and a logic circuit 100 on the same substrate (semiconductor substrate 1), and an insulating layer on the semiconductor substrate 1. (Cap film 6a, interlayer insulating film 7b), forming a wiring groove (opening 37) in the insulating layer, and forming a metal film (conductive film 38) filling the wiring groove; And forming a cap film 6c on the metal film, and removing the cap film 6c and a part of the insulating layer (cap films 6a and 6b, interlayer insulating films 7a and 7b) to form a recess 40. In the recess 40, the lower electrode 14, the capacitor insulating film 15, and the upper electrode 16 are embedded, and an upper connection wiring forming metal film (conductive film 39) is formed in the recess 40 and on the cap film 6c. Process and By selectively removing the upper connection wiring forming metal film on the cap layer (conductive film 39), in which and a step of forming an upper connection wiring 18.

  In the fourth embodiment, the upper surface 30 of the capacitive element 19 constituting the memory circuit 200 and the upper surface 34 of the cap film 6c provided so as to be in contact with the upper surface of the wiring 8b constituting the logic circuit 100 are provided. It constitutes the same surface. Thus, since it is set as the same surface, compared with the prior art of patent document 1, for example, the height of the recessed part 40 can be made high by a cap film thickness. For this reason, the height of the capacitive element 19 embedded in the recess 40 can be further increased. As a result, according to the fourth embodiment, it is possible to realize an increase in the capacitance of the capacitive element 19 as compared with the prior art. Note that the fourth embodiment can provide the same effects as those of the first embodiment.

(Fifth embodiment)
Next, a semiconductor device according to a fifth embodiment will be described with reference to the drawings.
FIG. 28 is a cross-sectional view showing the structure of the semiconductor device of the fifth embodiment. In the fifth embodiment, the recess 40 includes a hole 23 in which the capacitive element 19 is embedded, and a wiring groove 28 that is provided continuously outside the hole 23 and in which the upper connection wiring 18 is embedded. The lower surface 41 of the wiring groove 28 and the lower surface 43 of the cap film 6c are the same as those in the fourth embodiment except that they form the same surface. Here, the same surface is specified by the same definition as that of the first embodiment.

  In the fifth embodiment, since the lower surface 41 of the wiring groove 28 and the lower surface 43 of the cap film 6c are the same surface, the film thickness of the upper connection wiring 18 can be reduced as compared with the fourth embodiment. Therefore, the height of the hole 23 in which the capacitive element 19 is embedded can be increased. Therefore, since the area of the capacitive element 19 provided along the inner wall of the hole 23 can be increased, the capacitance of the capacitive element 19 can be increased. With such a configuration, a short circuit failure between the metal electrode of the capacitive element 19 and the wiring 8c constituting the upper logic circuit is suppressed while securing the capacitance of the capacitive element 19 as compared with the case of the fourth embodiment. Thus, stabilization of DRAM operation can be realized. In the fifth embodiment, the same effect as in the first embodiment can be obtained.

  Further, the lower surface 41 of the wiring groove 28 is made higher than the lower surface 43 of the cap film 6c. In other words, the height of the wiring groove 28 (for example, the film thickness from the buried electrode 18c to the capacitive insulating film 15 immediately below it) is capped. It may be thinner than the film 6c.

  Note that the manufacturing method of the semiconductor device manufacturing method of the fifth embodiment is substantially the same as the manufacturing process of the fourth embodiment, but in the step of forming the wiring groove 28 of the upper connection wiring 18, wiring is performed. The difference is that the etching of the groove 28 is performed only on the cap film 6c under the condition of being selective with respect to the low dielectric constant film (interlayer insulating film 7b).

(Sixth embodiment)
Next, a semiconductor device according to a sixth embodiment will be described with reference to the drawings.
FIG. 29 is a cross-sectional view showing the structure of the semiconductor device according to the sixth embodiment. In the sixth embodiment, as shown in FIG. 29, between the capacitive element 19 (for example, the lower electrode 14 and the capacitive insulating film 15 constituting the capacitive element 19) and the interlayer insulating films 7a and 7b, A sidewall protective film 50 is formed. That is, the sidewall protective film 50 is formed so that the lower electrode 14 does not contact the interlayer insulating films 7 a and 7 b in the region between the adjacent capacitive elements 19. In other words, the side wall of the lower electrode 14 is covered with the seamless side wall protective film 50 over all the interlayer insulating films 7 a and 7 b provided with the lower electrode 14. In recent miniaturized semiconductor devices, a so-called porous film that forms fine pores in the interlayer insulating films 7a and 7b may be used in order to reduce the relative dielectric constant between wirings. However, as shown in the present embodiment, by forming the sidewall protective film 50 between the adjacent capacitive elements 19, the lower electrode 14 penetrates into the interlayer insulating films 7a and 7b in the region between them. Can be prevented. As a result, the lower electrode 14 can be stably formed, and the effects of reducing the leakage current between the lower electrode 14 and the capacitive element 19 adjacent to each other and improving the long-term insulation reliability can be obtained. As such a sidewall protective film 50, for example, a barrier insulating film containing an organic silica material such as divinylsiloxane benzocyclobutene as shown as a barrier insulating film in International Publication No. WO 2004/107434 may be used. . Alternatively, a silicon nitride film (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), or silicon oxycarbide (SiOC) may be used as the sidewall protective film 50. In the present embodiment, the sidewall protective film 50 (deposited layer) can have a higher density than the adjacent insulating layers (interlayer insulating films 7a and 7b).
FIG. 29 shows a drawing in which the present embodiment is applied to the first embodiment. Needless to say, the present embodiment is another embodiment of the present invention. It can also be applied to.

Next, a manufacturing method according to the sixth embodiment will be described.
According to the manufacturing method according to the sixth embodiment, as shown in FIG. 11 of the manufacturing process according to the first embodiment, after forming the recess 40 (hole 23 and wiring groove 28), for example, the hole 23 An insulating film to be the sidewall protective film 50 having a film density higher than that of the interlayer insulating films 7a and 7b is deposited on the sidewalls. Such a deposited layer (side wall protective film 50) is preferably an insulating film containing at least silicon atoms. For example, silicon oxide film (SiO ₂ ), silicon carbide (SiC), silicon nitride film (SiN), silicon carbonitride Insulating film by chemical vapor deposition method, such as oxide (SiCN), or insulating film containing silicon, oxygen, carbon or plasma polymerization method, generally called low dielectric constant film, or benzocyclobutene A film formed by the above may be used. That is, in order to obtain the effect of the present embodiment, an insulating film that can block the hole portion formed in the side wall of the interlayer insulating films 7a and 7b may be used.

  Next, the sidewall protective film 50 at least on the bottom surface of the opening 23 is etched back by a method such as reactive ion etching or RF sputtering. Thus, the capacitor contact 13c and the lower electrode 14 to be formed later are electrically connected. This sidewall protective film 50 is particularly effective when a porous insulating film composed of continuous pores is used as an interlayer insulating film. In general, a porous insulating film composed of continuous pores forms a void by decomposing a low-temperature pyrolyzable organic substance existing in the film by irradiating the substrate with ultraviolet rays while heating the substrate. Low temperature pyrolyzable organic substances may be mixed by using a gas mixture of low temperature pyrolyzable organic gas and interlayer insulating film source gas to grow the interlayer insulating film, or in the interlayer insulating film source molecules at low temperature. A material obtained by chemically bonding a thermally decomposable organic substance may be used. At least after the growth process of the interlayer insulating film, a porous insulating film formed by a process of decomposing the organic substance by irradiating ultraviolet rays while heating the substrate can be used.

  Next, in the same manner as in the step shown in FIG. 12, the lower electrode 14 is formed on at least the bottom surface and the side wall of the opening 23. By forming the sidewall protective film 50, for example, even when the fine holes formed in the interlayer insulating films 7 a and 7 b have a shape that penetrates from the sidewall to the inside of the insulating film, It is possible to prevent the electrode 14 from entering the interlayer insulating film 7.

  After the lower electrode 14 is formed by the above-described process, a process for forming the capacitor element 19 may be performed in the same manner as the processes after FIG.

(Seventh embodiment)
Next, a manufacturing method according to the seventh embodiment will be described.
FIG. 30 is a cross-sectional view showing the seventh embodiment. In the seventh embodiment, as shown in FIG. 30, sidewall protective films 50a and 50b are provided between the lower electrode 14 and the capacitive insulating film 15 constituting the capacitive element 19 and the wiring interlayer insulating films 7a and 7b. Is formed. Further, these side wall protective films 50a and 50b are formed only in the region of the interlayer insulating films 7a and 7b, that is, the interlayer insulating films 7a and 7b in the region between the capacitor elements 19 adjacent to the lower electrode 14 Side wall protective films 50a and 50b and cap films 6a and 6b are formed on the side walls of the lower electrode 14 so as not to contact each other. In other words, the sidewalls of the lower electrode 14 are covered with the sidewall protective films 50a and 50b and the cap films 6a and 6b over all the interlayer insulating films 7a and 7b where the lower electrode 14 is provided. These sidewall protective films 50a and 50b contain at least one of the elements contained in the interlayer insulating films 7a and 7b, and have a higher density than the interlayer insulating films 7a and 7b.

  In recent miniaturized semiconductor devices, a so-called porous film that forms fine pores in the interlayer insulating films 7a and 7b may be used in order to reduce the relative dielectric constant between wirings. However, as shown in the present embodiment, the sidewall protective films 50a and 50b are formed between the adjacent capacitive elements 19, so that the lower electrode 14 is inserted into the interlayer insulating films 7a and 7b in the region between them. Intrusion can be prevented. As a result, the lower electrode 14 can be stably formed, and the effects of reducing the leakage current between the lower electrodes 14 of the adjacent capacitive elements 19 and improving the long-term insulation reliability can be obtained.

The sidewall protective films 50a and 50b in the seventh embodiment are formed on the surface layer of the interlayer insulating films 7a and 7b at least in contact with the lower electrode 14, unlike the sixth embodiment. As such side wall protective films 50a and 50b, for example, as disclosed in the pamphlet of International Publication No. 2007/132879, the surface layer of the interlayer insulating films 7a and 7b is modified, Alternatively, a modified layer with a small amount of carbon per unit deposition and an increased number of oxygen atoms may be formed, or as disclosed in JP 2009-123886 A, a modified layer by hydrogen plasma may be formed. It may be formed. Furthermore, a modified layer containing nitrogen atoms and fluorine atoms as disclosed in WO 03/083935 may be formed. If the side wall protective films 50a and 50b contain fluorine atoms and form a compound with the lower electrode 14 to be formed later, the conductivity of the lower electrode 14 is impaired. Since the fluorine atoms included in the sidewall protective films 50a and 50b have a strong bond with the nitrogen atom, the lower electrode 14 and the sidewall protective films 50a and 50b form a compound, and the conductivity of the lower electrode 14 is reduced. The problem of being lost does not occur.
Note that FIG. 30 shows a drawing in which this embodiment is applied to the first embodiment, but it goes without saying that this embodiment is another embodiment of the present invention. It can also be applied to.

Next, a manufacturing method according to the seventh embodiment will be described.
According to the manufacturing method according to the seventh embodiment, as shown in FIG. 11 of the manufacturing process according to the first embodiment, after forming the hole 23 and the wiring groove 28, the sidewall protective films 50a and 50b are formed. A modified layer is formed. Such a modified layer is formed by modifying the surface layer of the interlayer insulating films 7a and 7b. That is, by exciting plasma in an atmosphere in which an inert gas such as helium or argon is added to hydrogen, nitrogen, carbon, fluorine, or the like, the surface layers of the interlayer insulating films 7a and 7b are modified, thereby forming the sidewall protective film 50a. , 50b. Alternatively, by performing ultraviolet irradiation treatment in an atmosphere containing at least oxygen, the surface layers of the interlayer insulating films 7a and 7b are modified to form the sidewall protective films 50a and 50b.

Next, the lower electrode 14 is formed in the same manner as the step shown in FIG. By forming the side wall protective films 50a and 50b, for example, even when the fine holes formed in the interlayer insulating films 7a and 7b have a shape that penetrates from the side walls to the inside of the insulating film. The lower electrode 14 can be prevented from entering the interlayer insulating films 7a and 7b.
After the lower electrode 14 is formed by the above-described process, a process for forming the capacitor element 19 may be performed in the same manner as the processes after FIG.

Here, terms used in the present embodiment will be described.
A semiconductor substrate is a substrate on which a semiconductor device is configured. In particular, an SOI (Silicon On Insulator) substrate, a TFT (Thin Film Transistor), a liquid crystal manufacturing substrate, and the like are not limited to those formed on a single crystal silicon substrate. The substrate is also included.

  Hard mask is a function to stack and protect on the interlayer insulation film when it is difficult to perform direct plasma etching or CMP due to mechanical strength reduction and process resistance reduction due to lower dielectric constant of the interlayer insulation film. Refers to the insulating film. The plasma CVD method is, for example, a method in which a gaseous raw material is continuously supplied to a reaction chamber under reduced pressure, a molecule is excited by plasma energy, and a continuous film is formed on a substrate by a gas phase reaction or a substrate surface reaction. It is a technique to form.

  The PVD method is, in addition to the usual sputtering method, improved embedding characteristics, improved film quality, and uniformity of film thickness within the wafer surface, such as long throw sputtering method, collimated sputtering method, ionized sputtering method, This is a technique including a sputtering method with high directivity. When sputtering an alloy, a metal film other than the main component is previously contained in the metal target at a solid solubility limit or less, so that the formed metal film can be used as an alloy film. In the present invention, it can be used mainly when forming a Cu seed layer or a barrier metal layer when forming a damascene Cu wiring.

  Needless to say, the above-described embodiment and a plurality of modifications can be combined within a range in which the contents do not conflict with each other. Further, in the above-described embodiments and modifications, the structure of each part has been specifically described, but the structure and the like can be changed in various ways within a range that satisfies the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation film 3a, 3b Active element 4 Contact interlayer insulation film 5, 5a, 5b, 5c Contact interlayer insulation film 6a, 6b, 6c, 6d Cap film 7a, 7b, 7c Interlayer insulation film 8a, 8b, 8c Wiring 9a, 9b, 9c, 9d Opening 10 Cell contact 10a, 10b Cell contact 11 Bit contact 12 Bit line 13, 13a, 13b Connection contact 13c Capacitance contact 14 Lower electrode 15 Capacitor insulating film 16 Upper electrode 18 Upper connection wiring 18a Wiring portion 18c Embedded electrode 19 Capacitance element 20 Silicide 21a, 21b, 21c Hard mask 22 Photo resist 23 Hole
24a, 24b, 24c Lower layer resist 25a, 25b, 25c Low-temperature oxide film 26a, 26b, 26c Antireflection film 27a, 27b, 27c Photoresist 28 Wiring groove 29 Photoresist 30 Upper surface 34 Upper surface 37 Opening 38 Conductive film 39 Conductive film 40 Recess 41 Lower surface 43 Lower surface 50, 50a, 50b Side wall protective film 100 Logic circuit 110 Semiconductor substrate 200 Memory circuit 201 Wire 202 having a fixed potential Signal wire 210 Capacitance element 220 Peripheral circuit

Claims (10)

A substrate,
A multilayer wiring layer provided on the substrate, in which a plurality of wiring layers composed of wiring and insulating layers are laminated;
In plan view, formed in a memory circuit region in the substrate, and a first active element, at least one capacitive element provided in the multilayer wiring layer and electrically connected to the first active element, And a memory circuit having a peripheral circuit;
In plan view, formed in a logic circuit region that is different from the memory circuit region in the substrate, and a logic circuit having a second active element;
A capacitor contact formed in the memory circuit region and electrically connecting the first active element and the capacitor;
A connection contact which is formed in the logic circuit region and electrically connects the second active element and the first wiring;
The first wiring is located in the lowermost wiring layer of the wiring layer in which the capacitive element is embedded;
The connection contact is provided in the same layer as the capacitor contact,
The semiconductor device, wherein the first wiring and the connection contact have a dual damascene structure. A substrate,
A multilayer wiring layer provided on the substrate, in which a plurality of wiring layers composed of wiring and insulating layers are laminated;
In plan view, formed in a memory circuit region in the substrate, and a first active element, at least one capacitive element provided in the multilayer wiring layer and electrically connected to the first active element, And a memory circuit having a peripheral circuit;
In plan view, formed in a logic circuit region that is different from the memory circuit region in the substrate, and a logic circuit having a second active element;
A capacitor contact formed in the memory circuit region and electrically connecting the first active element and the capacitor;
A connection contact which is formed in the logic circuit region and electrically connects the second active element and the first wiring;
The first wiring is located in the lowermost wiring layer of the wiring layer in which the capacitive element is embedded;
The connection contact is provided in the same layer as the capacitor contact,
The first wiring and the connection contact have a single machine structure, and are each made of a metal material containing copper. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the capacitive contact is formed of a part of the capacitive element. The semiconductor device according to any one of claims 1 to 3,
A contact insulating layer in which the capacitor contact and the connection contact are embedded; or
A semiconductor device, wherein the cell contact insulating layer, which is located between the contact insulating layer and the substrate and in which the first cell contact and the second cell contact are embedded, has a dielectric constant lower than that of the silicon oxide film. The semiconductor device according to claim 4,
A bit line provided in the contact insulating layer in which the capacitor contact is formed;
A semiconductor device in which the bit line is made of a material containing W. A semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the capacitive contact is made of a material containing W. The semiconductor device according to any one of claims 1 to 6,
A semiconductor device, wherein a sidewall protective film is formed between the insulating layer and the capacitive element. A semiconductor device according to any one of claims 1 to 7,
An upper connection wiring embedded in a recess provided in the multilayer wiring layer and stacked on the capacitive element composed of a lower electrode, a capacitive insulating film, and an upper electrode;
A cap layer provided so as to be in contact with the upper surface of the wiring constituting the logic circuit provided in the uppermost layer of the wiring layer in which the capacitive element is embedded;
A semiconductor device, wherein an upper surface of the upper connection wiring and an upper surface of the cap layer constitute the same surface. A method for manufacturing a semiconductor device having a memory circuit and a logic circuit on the same substrate,
Forming a contact insulating layer on the substrate;
Forming a first contact hole penetrating the contact insulating layer in the memory circuit formation region, and embedding the first contact hole with a first metal material, thereby forming a capacitor contact;
Forming an insulating layer on the contact insulating layer;
In the logic circuit formation region, by selectively removing the contact insulating layer and the insulating layer, a second through hole penetrating the contact insulating layer is formed, and the insulating layer is selectively removed. Forming a wiring groove continuous with the second through hole in the insulating layer, and forming a connection contact and a wiring by embedding the second through hole and the wiring groove with a second metal material; ,
Forming a recess reaching the capacitor contact in the insulating layer in which the wiring is formed, and embedding a capacitor element in the recess. A method for manufacturing a semiconductor device having a memory circuit and a logic circuit on the same substrate,
Forming a contact insulating layer on the substrate;
Forming a first contact hole penetrating the contact insulating layer in the memory circuit formation region, and embedding the first contact hole with a first metal material, thereby forming a capacitor contact;
Forming an insulating layer on the contact insulating layer;
In the logic circuit formation region, by selectively removing the contact insulating layer and the insulating layer, a second through hole penetrating the contact insulating layer is formed, and the second through hole includes a second copper containing copper. A connection contact is formed by embedding with a metal material, and by selectively removing the insulating layer, a wiring groove continuing to the second through hole is formed in the insulating layer, and the wiring groove is formed. Forming a wiring by embedding with the second metal material including copper;
Forming a recess reaching the capacitor contact in the insulating layer in which the wiring is formed, and embedding a capacitor element in the recess.

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