TW201442231A - An integrated structure - Google Patents

Abstract

An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate.

Description

Integrated structure

The present invention relates to an integrated structure, and more particularly to an integrated structure having through-through holes.

In order to save valuable layout space or increase the efficiency of interconnects, a plurality of integrated circuit (IC) chips can be stacked together to form an IC package structure. To achieve this, a three-dimensional (3D) stacked package technology can be used to package multiple integrated circuit chips together. Such three-dimensional (3D) stacked package technology is widely used to penetrate through vias (TSVs). A Through Through Hole (TSV) is a vertical conductive via that can extend completely through a wafer, a raft, or a substrate or wafer of any material. Today, 3D integrated circuits (3D ICs) are widely used in many fields such as memory stacking, image sensing wafers, and the like.

There are many integration problems encountered in fabricating integrated circuits with through-holes, one of which is the problem of copper protrusion. The volume through the through hole is one hundred times or more compared to a single transistor or a single interconnect. The mechanical stress, characteristic mismatch or electrical influence caused by the through-hole through-hole of this size cannot be neglected, so it is necessary to establish a better integration technique to manufacture an integrated circuit having a through-hole.

An integrated structure includes: a substrate having a first dielectric layer and a second dielectric cap layer disposed thereon; a metal gate transistor having a high dielectric constant gate dielectric disposed on the substrate a gate, a gate electrode embedded in the first dielectric layer, and a source/drain in the substrate; a first metal contact plug extending through the first dielectric layer and in direct contact with the source/drain And through the through hole, through the second dielectric cap layer, the first dielectric layer and the substrate.

100. . . Substrate

221. . . Clearance wall

222. . . Source and bungee (S/D)

231. . . The buffer layer

232. . . High dielectric constant dielectric layer

233. . . Work function metal layer

234. . . Low resistivity filler metal

250. . . Transistor

261. . . Contact hole etch stop layer

262. . . First interlayer dielectric layer

270. . . Contact plug

272. . . First cover

273. . . Contact hole

277. . . Deep ditches

278. . . Electrical insulation

279. . . Conductive through hole

280. . . Transitional through hole (TSV)

281. . . Third cover

282. . . Second cover

283, 284. . . Buffered conductive structure

283’, 284’. . . Buffered conductive structure

290_1, 290_2. . . Double damascene interconnect structure

290’_1, 290’_2, 290’_3. . . Double damascene interconnect structure

292. . . Second interlayer dielectric layer

295_1. . . Conductive through hole

295’_1. . . Conductive through hole

295’_2. . . Conductive through hole

295’_3. . . Conductive through hole

295_2. . . Conductive through hole

296_1. . . First metal (M1) layer

296’_1. . . First metal (M1) layer

296’_2. . . First metal (M1) layer

296’_3. . . First metal (M1) layer

296_2. . . First metal (M1) layer

300. . . Through the through hole

390_1, 390_2. . . Double damascene interconnect structure

390’_1, 390’_2, 390’_3. . . Double damascene interconnect structure

395_1. . . Conductive through hole

395’_1. . . Conductive through hole

395’_2. . . Conductive through hole

395’_3. . . Conductive through hole

395_2. . . Conductive through hole

396_1. . . First metal (M1) layer

396’_1. . . First metal (M1) layer

396’_2. . . First metal (M1) layer

396’_3. . . First metal (M1) layer

396_2. . . First metal (M1) layer

1000. . . Connection layer at a higher level

D1, d2, d3, d4, d4', d5, d5'. . . Height/distance

D1, D2, D1', D2', D1", D1". . . Height/distance

The above objects and advantages of the present invention will become more apparent from the written description of the appended claims.

1-4 and 5A are cross-sectional views showing a manufacturing method of an integrated structure having a TSV according to a first embodiment of the present invention;

5B is a cross-sectional view showing an integrated structure having a TSV according to a second embodiment of the present invention;

6A is a cross-sectional view showing an integrated structure having a TSV according to a third embodiment of the present invention;

6B is a cross-sectional view showing an integrated structure having a TSV according to a fourth embodiment of the present invention;

Fig. 7 is a view showing the final structure of an integrated structure having a TSV according to a first embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the preferred embodiments of the present invention will be described in detail, and the components, components, structures, materials, configurations, and the like described herein may be arbitrarily combined into new embodiments without the order of the description or the embodiments. These embodiments are within the scope of the invention. After reading the present invention, it will be apparent to those skilled in the art that the above-described elements, components, structures, materials, configurations, etc. may be modified and retouched without departing from the spirit and scope of the invention. The scope of patent protection is subject to the definition of the scope of the patent application attached to the specification, and such modifications and refinements fall within the scope of the present invention.

The embodiments of the invention and the figures are numerous, and similar elements are denoted by the same or like numerals in order to avoid obscuring. The figures illustrate the concepts and spirit of the present invention, so that the distances, sizes, ratios, shapes, connection relationships, etc. shown in the figures are all illustrative and not actual, all of which can achieve the same function or result in the same manner. Distance, size, proportion, shape, connection relationship, etc. can be regarded as equivalents.

Referring to Figures 1-4 and 5A, there are shown cross-sectional overviews of a method of fabricating an integrated structure having a TSV in accordance with a first embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a germanium substrate, a germanium-containing substrate, or an insulating layer overlying (SOI) substrate. Next, a high-k dielectric layer metal gate transistor 250 (hereinafter simply referred to as a transistor 250) embedded in the contact hole etch stop layer 261 and the first interlayer dielectric layer 262 is formed on the semiconductor substrate 100. The term "high-k dielectric layer metal gate transistor" as used herein refers to a transistor having a metal as its gate electrode and a high-k dielectric layer as its gate dielectric layer. Although transistor 250 appears to be fabricated from a high dielectric constant post and gate post process in FIG. 1, transistor 250 can represent any process such as a high dielectric constant pre- and gate pre-process, The high dielectric constant pre- and post-gate process produces a transistor, and the transistor 250 may be a P-type conductive transistor or an N-type conductive transistor.

As shown in FIG. 1, the transistor 250 includes a selective buffer layer 231, a U-shaped high-k dielectric layer 232 as a gate dielectric layer, a U-shaped work function metal layer 233 as a gate electrode, and a low The resistivity fills the metal 234, the spacers 221, and the source and drain (S/D) 222. In a preferred embodiment, the selective buffer layer 231 can be a conventional hafnium oxide layer to separate the high-k dielectric layer 232 from the substrate 100. The high-k dielectric layer 232 is selected from the group consisting of tantalum nitride (SiN), niobium oxynitride (SiON), and metal oxides. Metal oxides include: hafnium oxide (HfO ₂ ), hafnium oxide (HfSiO), hafnium oxynitride (HfSiON), alumina (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), alumina lanthanum (LaAlO) ₃ ), lanthanum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), cerium zirconium oxide (ZrSiO ₄ ), and cerium zirconium oxide. The U-shaped work function metal layer 233 may be selected from an N-type conductive work function material according to the performance considerations of the transistor 250 and the conductivity type (the work function is between about 3.9 eV and about 4.3 eV, such as TiAl, TiAlN, ZrAl, WAl, TaAl, HfAl), P-type conductive work function materials (work function between about 4.8 eV and about 5.2 eV, such as TiN, TaC) and intermediate work function materials (most commonly TiN containing impurities). The low-resistivity filler metal 234 may be a multi-layered structure, and the material thereof may be selected from the group consisting of Al, Ti, Ta, W, Nb, Mo, Cu, TiN, TiC, TaN, Ti/W, and Ti/TiN. . In a preferred embodiment, if the transistor 250 is a PMOS, the U-shaped work function metal layer 233 includes TiN, and if the transistor 250 is an NMOS, the U-shaped work function metal layer 233 includes TiAl; and the low-resistivity filler metal 234 includes aluminum. . The spacer 221 may be a multi-layered structure and may include a high temperature oxide layer (HTO), tantalum nitride, hafnium oxide, tantalum carbide, niobium oxynitride, and/or hafnium nitride (HCD-SiN) formed of hexachlorodioxane. The source/drain (S/D) 222 is formed by dopants distributed in the substrates on both sides of the gate. The conductivity type and species of the dopant depend on the conductivity type and performance considerations of the transistor 250. Additionally, a selective epitaxial growth (SEG) method can be used to form the lift source/drain (not shown in Figure 1). For example, when the transistor 250 is a PMOS, an epitaxial layer having germanium may be used to form the source/drain 222; when the transistor 250 is an NMOS, an epitaxial layer having carbon or phosphorus may be used to form the source. Pole/bungee (S/D). It should be noted that in order to remove excess material from the transistor 250 and form a globally flat surface, one or more chemical mechanical polishing processes may be performed prior to completing the transistor 250 shown in FIG.

Referring now to Figure 2, a first cap layer 272 is formed on a flat surface. Next, at least one contact hole 273 is formed in the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer 261. The first cap layer 272 comprises one or more dielectric materials selected from the group consisting of cerium oxide, cerium nitride, cerium oxide formed by using tetraethoxy decane as a precursor, cerium carbide, cerium oxynitride, carbon oxidation. Niobium, niobium oxycarbide and polymers. The process for forming the at least one contact hole 273 includes at least one lithography process and at least one etching process. If the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer 261 use different materials, more than one etching process may be required. Since the size and spacing of the contact holes (other layers are also smaller) become smaller, if necessary, a so-called 2P2E process (i.e., two lithography processes and two etching processes) can be used to form the contact holes. Although only one contact hole 273 exposing the source/drain 222 is shown in FIG. 2, the contact hole 273 represents the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer. All of the contact holes in 261 and any contact holes formed in either of the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer 261. For example, the contact hole can land on the metal electrode of the transistor 250 and be in direct contact with the low resistivity fill metal 234. For example, the contact holes can simultaneously land on both the source/drain 222 of the transistor 250 and the metal electrode and simultaneously contact the two. Not only the location of the contact hole, but also its shape is not limited. For example, the sidewall of the contact hole can be straight or slightly inclined. For example, to simultaneously contact both the source/drain 222 of the transistor 250 and the metal electrode, the contact hole may be oval. Further, after the contact hole 273 is formed, a vaporized layer directly contacting the source/drain 222 may be formed at the bottom of the contact hole 273 (not shown in FIG. 2).

Referring now to FIG. 3, a contact plug 270 is formed in the contact hole 273 and a second cover layer 282 is formed on the first cover layer 272. Next, a deep trench 277 for the through hole is formed in the second cap layer 282, the first cap layer 272, the first interlayer dielectric layer 262, the contact hole etch stop layer 261, and the substrate 100. Contact plug 270 can be formed by forming one or more conductive materials on the substrate into contact holes 273; followed by a chemical mechanical polishing process to remove excess material and form a globally flat surface. The conductive material for the contact plug 270 comprises a barrier/adhesive material and a low resistivity filler material. The barrier/adhesive material may be selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese, copper, and is preferably tantalum/niobium nitride or titanium/titanium nitride. The low resistivity fill material may be selected from the group consisting of tungsten, copper, aluminum, polycrystalline germanium, and is preferably tungsten. The second cap layer 282 comprises one or more dielectric materials, and the dielectric materials may be selected from the group consisting of cerium oxide, cerium nitride, cerium oxide formed by using tetraethoxy decane as a precursor, cerium carbide, cerium oxynitride. , cerium oxyhydroxide, cerium oxynitride and polymers. The second cap layer 282 is preferably tantalum nitride or tantalum carbide. The process used to form the deep trenches 277 includes at least one lithography process and at least one etch process. Considering the large size of the deep trench 277 compared to the ordinary contact plug (the ordinary contact plug has a diameter of several nanometers to several tens of nanometers, a depth of several tens of nanometers) (the deep trench 277 has a diameter of several μm to several tens of μm) , a few μm to a few hundred μm depth), can be used for the deep trench 277 to customize the photoresist used in the lithography process, the etching species used in the etching process and the etching recipe.

Referring now to Figure 4, an electrically insulating layer (not shown) is formed on the sidewalls and bottom surface of the deep trench 277 and a conductive material (not shown) is formed in the deep trench 277 to fill the deep trench 277. After forming the electrically insulating layer and the electrically conductive material, a chemical mechanical polishing process is performed to remove excess material to form a globally planar surface and complete a transitional through via (TSV) comprising an electrically insulating layer 278 and a conductive via 279. 280. The electrically insulating layer can be formed by a thermal oxidation process, and is not formed on the second cap layer 282, the first cap layer 272, the first interlayer dielectric layer 262, the sidewalls of the contact hole etch stop layer 261, and the second layer. On the upper surface of the cover layer 282. Alternatively, the electrically insulating layer can be formed by a deposition process such as a conventional chemical vapor deposition (CVD) process, a flowable CVD process, a plasma-enhanced CVD process, and a high density. Formed by a plasma chemical vapor deposition (HDP CVD) process. The electrically insulating layer may comprise one or more materials selected from the group consisting of cerium oxide, cerium nitride, cerium oxynitride, cerium carbide, cerium carbonitride and a polymer. The electrically insulating layer is preferably a single layer of hafnium oxide. The conductive material used for the conductive vias 279 comprises a barrier/adhesive material, a selective seed material, and a low resistivity fill material. The barrier/adhesive material may be selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese, and copper. The selective seed material is typically the same as the low resistivity fill material and is selected from the group consisting of tungsten, copper, aluminum, and polysilicon. The low resistivity fill material is preferably copper formed by an electroplating process and the selective seed material is preferably copper formed by physical sputter deposition.

In FIG. 4, it is clear that the height d1 of the transistor 250 (the distance from the upper surface of the substrate 100 to the upper surface of the low-resistivity filler metal 234) is due to the thickness of the first cap layer 272. It is smaller than the height d2 of the contact plug 270 (from the upper surface of the substrate 100 to the upper surface of the contact plug 270). It can also be clearly seen that due to the thickness of the second cap layer 282, the height d2 of the contact plug 270 is smaller than the height d3 of the transition through the via hole 280 above the substrate (from the upper surface of the substrate 100 to the transition through) The distance between the upper surfaces of the through holes 280).

Referring now to FIG. 5A, a second interlayer dielectric layer 292 is formed overlying the second cap layer 282 and the transition through vias 280, and then dual damascene interconnect structures 290_1 and 290_2 are formed in the second interlayer dielectric layer 292. The second interlayer dielectric layer 292 may be a multi-layer structure, which may include cerium oxide, tantalum carbide, tantalum nitride, hafnium oxynitride, niobium carbonitride, and/or low formed by tetraethoxy decane as a precursor. Dielectric constant dielectric material. The low-k dielectric material may be selected from fluorine-doped ceria, carbon-doped ceria, porous ceria, porous doped ceria, spin-on organic polymer, helium oxygen Resin-based organic polymer. The dual damascene interconnect structure 290_1 is composed of an integrally formed conductive via 295_1 and a first metal (M1) layer 296_1 and is in direct contact with the contact plug 270. The dual damascene interconnect structure 290_2 is formed by integrally forming a plurality of conductive vias 295_2 (four shown in FIG. 5A) and a first metal (M1) layer 296_2, and is in direct contact with the transition through vias 280. . The materials used in the dual damascene interconnect structure include barrier/adhesive materials and low resistivity fill materials. The barrier/adhesive material may be selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese and copper, and preferably niobium/tantalum nitride or titanium/titanium nitride. The low resistivity filler material may be selected from the group consisting of tungsten, copper, aluminum, and polysilicon, and copper is preferred. The dual damascene interconnect structures 290_1 and 290_2 can be formed by forming vias and trenches in the second interlayer dielectric layer 292; forming a barrier/adhesive material and a low resistivity fill material on the substrate to fill the pass Holes and trenches; and chemical mechanical polishing processes to remove excess material and form a globally flat surface.

In FIG. 5A, it can be clearly seen that since the dual damascene interconnect structure 290_1 penetrates the second cap layer 282 not only through the second interlayer dielectric layer 292, the height D1 of the dual damascene interconnect structure 290_1 (from the upper surface of the contact plug 270 to the distance between the upper surfaces of the dual damascene interconnect structure 290_1) is greater than the height D2 of the dual damascene interconnect structure 290_2 (from the transition through the upper surface of the through via 280 to the dual damascene The distance between the upper surfaces of the interconnect structure 290_1).

Referring to Figures 1-4 and 5B, such cross-sectional overviews illustrate a method of fabricating an integrated structure having a TSV in accordance with a second embodiment of the present invention. The process, materials and structure of Figures 1-4 are the same as described in the previous paragraph and will not be repeated here. In this embodiment, after forming the contact plug 270 and the second cap layer 282, the buffer conductive structures 283 and 284 are formed on the transistor 250 and the contact plug 270, respectively. The buffer conductive structures 283 and 284 may use the processes and materials used for the contact pins 270 or the dual damascene interconnects 290, so the details thereof will not be described in detail. It should be noted that the buffer conductive structures 283 and 284 may be formed after the completion of the transition through vias 280, or the buffer conductive structures 283 and 284 may be formed prior to forming the deep trenches 277. After forming the buffer conductive structures 283 and 284, following the process of FIG. 5A, a second interlayer dielectric layer 292 covering the second cap layer 282, the transition through vias 280 and the buffer conductive structures 283 and 284 is formed, and then Dual damascene interconnect structures 290'_1, 290'_2 and 290'_3 are formed in the two-layer dielectric layer 292. The dual damascene interconnect structure 290'_1 is composed of an integrally formed conductive via 295'_1 and a first metal (M1) layer 296'_1 and is in direct contact with the buffer conductive structure 284. The dual damascene interconnect structure 290'_2 is composed of a plurality of integrally formed conductive vias 295'_2 (four shown in FIG. 5B) and a first metal (M1) layer 296'_2. The through holes 280 are in direct contact. The dual damascene interconnect structure 290'_3 is formed by integrally formed conductive vias 295'_3 and first metal (M1) layers 296'_3 and in direct contact with the buffer conductive structures 283.

In FIG. 5B, it can be clearly seen that due to the thickness of the first cap layer 272, the height d4 of the buffer conductive structure 283 (the distance from the upper surface of the transistor 250 to the upper surface of the buffer conductive structure 283) is Greater than the height d5 of the buffer conductive structure 284 (the distance from the upper surface of the contact plug 270 to the upper surface of the buffer conductive structure 284). Further, not in the first embodiment shown in Fig. 5A, all of the dual damascene interconnect structures 290'_1, 290'_2 and 290'_3 in this embodiment have the same height.

Referring to Figures 1-4 and 6A, such cross-sectional overviews illustrate a method of fabricating an integrated structure having a TSV in accordance with a third embodiment of the present invention. The process, materials and structure of Figures 1-4 are the same as described in the previous paragraph and will not be repeated here. In this embodiment, the third cap layer 281 is formed after the completion of the transition through via 280 and before the formation of the second interlayer dielectric layer 292. The material used for the third cover layer 281 is similar to that used for the first and second cover layers. After the third cap layer is formed, a second interlayer dielectric layer 292 covering the third cap layer 281 is formed according to the process of FIG. 6A, and then a dual damascene is formed in the second interlayer dielectric layer 292 and the third cap layer 281. The interconnect structures 390_1 and 390_2. The dual damascene interconnect structure 390_1 is composed of an integrally formed conductive via 395_1 and a first metal (M1) layer 396_1 and is in direct contact with the contact plug 270. The dual damascene interconnect structure 390_2 is formed by integrally forming a plurality of conductive vias 395_2 (four shown in FIG. 6A) and a first metal (M1) layer 396_2 and in direct contact with the transition through vias 280.

Similar to FIG. 5A, in FIG. 6A, since the dual damascene interconnect structure 390_1 penetrates the second cap layer 282 not only through the second interlayer dielectric layer 292 and the third cap layer, the dual damascene interconnect structure The height D1' of 390_1 (from the upper surface of the contact plug 270 to the distance between the upper surfaces of the dual damascene interconnect structure 390_1) is greater than the height D2' of the dual damascene interconnect structure 390_2 (from the transition through the through hole 280) The distance from the upper surface to the surface above the dual damascene interconnect structure 390_2).

Referring to Figures 1-4, 6A and 6B, these cross-sectional overviews illustrate a method of fabricating an integrated structure having a TSV in accordance with a fourth embodiment of the present invention. The process, materials and structure of Figures 1-4 are the same as described in the previous paragraph and will not be repeated here. In this embodiment, after the third cap layer 281 is formed, buffer conductive structures 283' and 284' are formed on the transistor 250 and the contact plug 270, respectively. The buffer conductive structures 283' and 284' can use the processes and materials used for the contact pins 270 or the dual damascene interconnects 290, so the details thereof will not be described in detail. After forming the buffer conductive structures 283' and 284', the second interlayer dielectric layer 292 covering the third cap layer 281, the buffer conductive structures 283' and 284' is formed in accordance with the process of FIG. 6A, and then the second interlayer dielectric layer is formed. Dual damascene interconnect structures 390'_1, 390'_2 and 390'_3 are formed in 292. The dual damascene interconnect structure 390'_1 is composed of an integrally formed conductive via 395'_1 and a first metal (M1) layer 396'_1 and is in direct contact with the buffer conductive structure 284'. The dual damascene interconnect structure 390'_2 is composed of a plurality of integrally formed conductive vias 395'_2 (four shown in FIG. 6B) and a first metal (M1) layer 396'_2. The through holes 280 are in direct contact. The dual damascene interconnect structure 390'_3 is formed by integrally formed conductive vias 395'_3 and first metal (M1) layers 396'_3 and in direct contact with the buffer conductive structures 283'.

Much different from the previous embodiment, the height D1" of the dual damascene interconnect structure 390'_1 (from the upper surface of the contact plug 270 to the dual damascene interconnect) is due to the buffered conductive structures 283' and 284' in FIG. 6B. The distance between the top surfaces of the structures 390'_1) is less than the height D2" of the dual damascene interconnect structure 390'_2 (from the transition through the upper surface of the through via 280 to the dual damascene interconnect structure 390'_2 The distance between the surfaces). Moreover, due to the thickness of the first cap layer 272, the height d4' of the buffer conductive structure 283' (the distance from the upper surface of the transistor 250 to the upper surface of the buffer conductive structure 283') is greater than the height of the buffer conductive structure 284'. D5' (distance from the upper surface of the contact plug 270 to the upper surface of the buffer conductive structure 284').

Referring now to Figure 7, there is shown a final structural schematic of an integrated structure having through-through vias in accordance with a first embodiment of the present invention (corresponding to Figure 5A). After completing the integrated structure shown in FIG. 5A, a higher level inner interconnect layer 1000 is formed. The higher level interconnect layer 1000 can include one or more inter-metal dielectric layers, one or more dual damascene interconnect structures, one or more passive components such as metal-insulator-metal (MIM) capacitors, An inductor, a resistor, one or more test structures, and one or more pads. After completing the higher level interconnect layer 1000, the substrate 100 is flipped and the back side of the substrate 100 is ground, ground, and/or thinned to expose the conductive vias 279 and complete through the vias 300. Although FIG. 7 only shows the schematic final structure of the first embodiment shown in FIG. 5A, other embodiments (ie, FIGS. 5B, 6A, and 6B) can follow the same process to manufacture a higher level interconnect layer 1000. And the through hole 300 is completed. Manufacturing the higher level inner interconnect layer 1000 and completing such processes through the through via 300 does not alter the geometric features of the various embodiments described above.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Substrate

222. . . Source and bungee (S/D)

250. . . Transistor

261. . . Contact hole etch stop layer

262. . . First interlayer dielectric layer

270. . . Contact plug

272. . . First cover

278. . . Electrical insulation

279. . . Conductive through hole

280. . . Transitional through hole

282. . . Second cover

D1, d2, d3. . . Height/distance

Claims (10)

An integrated structure that includes:
a substrate having a first dielectric layer and a second dielectric cap layer disposed thereon in sequence;
a metal gate transistor having a high dielectric constant gate dielectric layer disposed on the substrate, a metal electrode embedded in the first dielectric layer, and a source/drain electrode located in the substrate;
a first metal contact plug penetrating the first dielectric layer and in direct contact with the source/drain; and a through-via via extending through the second dielectric cap layer, the first dielectric layer and the substrate. The integrated structure of claim 1, wherein the upper surface of the first metal contact plug is higher than the upper surface of the metal electrode. The integrated structure of claim 1, wherein the upper surface of the through hole is higher than the upper surface of the first metal contact plug. The integrated structure of claim 1, wherein the first dielectric layer comprises a first interlayer dielectric layer and a first dielectric cap layer, and an upper surface of the first metal contact plug is coupled to the first dielectric layer The cap layer is coplanar, and the metal gate is coplanar with the first interlayer dielectric layer. The integrated structure of claim 1, wherein the metal electrode comprises a U-shaped work function metal layer and a low resistivity fill layer. The integrated structure of claim 1, wherein the metal electrode comprises aluminum, the first metal contact plug comprises tungsten and the through hole comprises copper. For example, the integrated structure of the first application scope of the patent scope includes:
a second dielectric layer disposed on the second dielectric cap layer and covering the through via hole;
a first interconnect structure extending through the second dielectric cap layer and connected to the through via hole; and a second interconnect structure extending through the second dielectric layer and the second dielectric cap layer Connected to the first metal contact plug. For example, the integrated structure of the first application scope of the patent scope includes:
The first buffer conductive structure is disposed on the metal electrode; and the second buffer conductive structure is disposed on the first metal contact plug. The integrated structure of claim 8 wherein the upper surface of the first buffered conductive structure and the upper surface of the second buffered conductive structure are coplanar with the second dielectric cap layer. For example, the integrated structure of the first application scope of the patent scope includes:
a second dielectric layer disposed on the second dielectric cap layer and covering the through via via, the first buffer conductive structure and the second buffer conductive structure;
a first interconnect structure connected to the through via via through the second dielectric layer;
a second interconnect structure connected to the first buffer conductive structure through the second dielectric layer; and a third interconnect structure connected to the second buffer conductive structure through the second dielectric layer .