JP2012159960A - Semiconductor design device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor design device capable of easily designing a semiconductor device including an asynchronous data path by a simple way, and the semiconductor device including the asynchronous data path.SOLUTION: A flip-flop (FF) insertion part 9 inserts a flip-flop (FF1) into an asynchronous data path. When metastable convergence time Tr is shorter than latency Tcl of a clock tree (CT) in a flip-flop (FF2) on a receiving side of the asynchronous data path, a delay setting part 8 sets a first clock, which is output from a node having the CT, to an input clock of the FF1, and sets a second clock, which is output from another node of the CT and is delayed by Tr from the first clock, to an input clock of the FF2. When the Tr is equal to or greater than the Tcl, the delay setting part 8 sets the first clock to the input clock of the FF1, and sets the second clock after delaying the first clock by the Tr with a delay circuit to the input clock of the FF2.

Description

  The present invention relates to a semiconductor design apparatus and a semiconductor device.

  Asynchronous path design is difficult, and chip variation and the external environment of the chip are greatly affected, so that sufficient screening cannot be performed and defective products may flow out to the field.

  For example, Japanese Patent Application Laid-Open No. 2002-215568 discloses a data transfer reference signal serving as a data transfer reference and transfer data transferred in pairs with the data transfer reference signal. In the asynchronous data transfer method performed in step 1, the transmission side uses the transfer data fixed reference timing as the clock edge of the data transfer reference signal assert timing, and the reception side first detects the transfer reference signal assertion. An asynchronous data transfer method using transfer data sampled at a clock edge is disclosed.

JP 2002-215568 A

  However, the method described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2002-215568) is costly due to circuit overhead and does not ride on platform design based on synchronous design. Spills out and the design TAT (Turn Around Time) is prolonged.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor design device capable of designing a semiconductor device including an asynchronous path and a semiconductor device including an asynchronous path easily and easily.

  A semiconductor design apparatus according to an embodiment of the present invention includes a storage unit that stores design data of a semiconductor device, a detection unit that detects an asynchronous path included in the semiconductor device based on the design data, and a detected asynchronous path. When the metastable convergence time from the start of the metastable state to the end of the inserted flip-flop is shorter than the latency of the clock tree, the signal is output from a node with the clock tree. The first clock is set to the input of the clock terminal of the first flip-flop, and the second clock output from another node of the clock tree and delayed by the metastable convergence time from the first clock is detected. The delay setting to be set at the input of the clock pin of the flip-flop on the receiving side of the asynchronous path The delay setting unit sets the first clock output from a node of the clock tree as the input of the clock terminal of the first flip-flop when the metastable convergence time is equal to or higher than the latency of the clock tree. The second clock obtained by delaying the first clock by the delay circuit other than the clock tree for the metastable convergence time is set to the input of the clock terminal of the detected flip-flop on the receiving side of the asynchronous path.

  According to an embodiment of the present invention, a semiconductor device including an asynchronous path can be designed simply and easily.

It is a figure showing the structure of the semiconductor design apparatus of 1st Embodiment. It is a flowchart showing the operation | movement procedure of the semiconductor design apparatus of 1st Embodiment. 3 is a flowchart showing a specific processing procedure of synchronization circuit insertion processing of FIG. 2. It is a figure showing the circuit block of the transmission side of an asynchronous bus | bath, and the circuit block of the receiving side of an asynchronous path | pass. FIG. 5 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl ≧ Tr. FIG. 5 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl <Tr. 6 is a flowchart showing another example of a specific processing procedure of the synchronization insertion processing of FIG. 2. FIG. 5 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl ≧ Tr. FIG. 5 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl <Tr. It is a figure showing the structure of the semiconductor chip of the 2nd Embodiment of this invention. It is a figure showing the example of the 1st circuit block of the transmission side of an asynchronous bus, the 2nd circuit block of the receiving side of an asynchronous path, and the synchronization circuit inserted in the asynchronous path. It is a figure showing another example of the 1st circuit block of the transmission side of an asynchronous bus, the 2nd circuit block of the receiving side of an asynchronous path, and the synchronizing circuit inserted in the asynchronous path. It is a figure showing the further another example of the 1st circuit block of the transmission side of an asynchronous bus | bath, the 2nd circuit block of the reception side of an asynchronous path | pass, and the synchronization circuit inserted in the asynchronous path | pass. It is a figure showing the further another example of the 1st circuit block of the transmission side of an asynchronous bus | bath, the 2nd circuit block of the reception side of an asynchronous path | pass, and the synchronization circuit inserted in the asynchronous path | pass. It is a figure showing the structure of the semiconductor design apparatus of 3rd Embodiment. It is a flowchart showing the operation | movement procedure of the semiconductor design apparatus of 3rd Embodiment. It is a flowchart showing the specific process sequence of the format verification process of FIG. It is a figure showing the 1st circuit block of the transmission side of the asynchronous path before insertion of a synchronization circuit, and the 2nd circuit block of the reception side of an asynchronous path. FIG. 19 is a diagram illustrating an example in which a synchronization circuit is inserted in the asynchronous path of FIG. 18. It is a figure showing the 1st circuit block of the transmission side of the asynchronous path before insertion of a synchronization circuit, and the 2nd circuit block of the reception side of an asynchronous path. FIG. 21 is a diagram illustrating an example in which a synchronization circuit is inserted in the asynchronous path of FIG. 20. It is a figure showing the structure of the semiconductor design apparatus of 4th Embodiment. It is a flowchart showing the operation | movement procedure of the semiconductor design apparatus of 4th Embodiment. 24 is a flowchart showing a specific processing procedure of timing verification processing of FIG. It is a figure showing the circuit of timing verification object. It is a timing chart in the conventional timing verification. It is a timing chart in timing verification of a 4th embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
The first embodiment relates to insertion of a synchronization circuit into an asynchronous path.

  The first embodiment does not realize synchronization by inserting a plurality of stages of flip-flops (hereinafter referred to as FFs) into an asynchronous path and earning a time corresponding to the insertion period as in the prior art. Is achieved by delaying the clock supplied to the FF on the receiving side by the delay time.

(Configuration of semiconductor design equipment)
FIG. 1 is a diagram illustrating the configuration of the semiconductor design apparatus according to the first embodiment.

  Referring to FIG. 1, the semiconductor design apparatus includes a logic synthesis unit 2, a design data storage unit 3, a synchronization circuit insertion unit 4, a timing verification unit 5, and a format verification unit 6.

  The logic synthesis unit 2 performs logic design of the semiconductor device from the description regarding the operation of the abstract circuit, creates design data of the semiconductor device, and writes the design data in the design data storage unit 3.

The design data storage unit 3 stores design data.
The synchronization circuit insertion unit 4 includes an asynchronous path detection unit 7, a delay setting unit 8, and an FF insertion unit 9.

  The asynchronous path detection unit 7 detects an asynchronous path included in the semiconductor device based on the design data. Here, the asynchronous path refers to a transfer bus between circuits operating at different clocks having different frequencies.

The FF insertion unit 9 inserts an FF (D-type flip-flop) into the detected asynchronous path.
The delay setting unit 8 calculates a metastable convergence time Tr based on device characteristics, circuit constraints, and MTBF (Mean time between failures). The metastable state is a state in which a halfway intermediate level where the logic level is neither low level nor high level is maintained. The metastable convergence time Tr is the time from the start to the end of the metastable state in the FF on the receiving side of the asynchronous path.

  For example, the document “Measuring metastability and its effect on communication signal processing systems” (Instrumentation and Measurement, IEEE Transactions), Intel Corp. It is shown that the following relationship is established between T0, the frequency fb of the clock on the circuit block on the transmission side of the asynchronous path, and the clock frequency fa and MTBF of the circuit block on the reception side of the asynchronous path.

MTBF = exp (−Tr / τ) / (fb × fa × T0)
When the metastable convergence time Tr of the flip-flop (FF to be described later) on the receiving side of the asynchronous path is shorter than the latency (delay time) Tcl of the clock tree, the delay setting unit 8 is output from a node in the clock tree. To the input of the clock terminal of the FF into which the first clock is inserted. The delay setting unit 8 further outputs the second flip-flop on the receiving side of the asynchronous path from which the second clock output from another node of the clock tree and detected by the metastable convergence time Tr from the first clock is detected. Set to clock pin input.

  When the metastable convergence time Tr of the flip-flop (FF to be described later) on the receiving side of the asynchronous path is equal to or longer than the latency Tcl of the clock tree, the delay setting unit 8 outputs the first clock output from a node having the clock tree. Is set to the input of the clock terminal of the FF where is inserted. The delay setting unit 8 inputs the second clock obtained by delaying the first clock by the metastable convergence time Tr by a delay circuit other than the clock tree to the input of the clock terminal of the flip-flop on the receiving side of the detected asynchronous path. Set.

  Here, the latency of the clock tree represents the time that the clock output from the end (leaf) of the clock tree is delayed with respect to the clock output from the root of the clock tree.

  The timing verification unit 5 verifies whether the designed semiconductor device operates at a desired frequency and verifies whether the timing standard value is satisfied.

  The format verification unit 6 verifies whether the logic of the semiconductor device is equivalent before and after the addition of an additional circuit such as a synchronization circuit.

(Overall operation)
FIG. 2 is a flowchart showing an operation procedure of the semiconductor design apparatus according to the first embodiment.

  Referring to FIG. 2, logic synthesis unit 2 performs logic design of the semiconductor device from the description regarding the operation of the abstract circuit, creates design data of the semiconductor device, and writes the design data to design data storage unit 3 (step S101). ).

  Next, the synchronization circuit insertion unit 4 performs processing for inserting a synchronization circuit into an asynchronous bus included in the semiconductor device, which is specific to the present embodiment described later (step S102).

  Next, the timing verification unit 5 performs a timing verification process of the semiconductor device (step S103).

Next, the format verification unit 6 performs format verification of the semiconductor device (step S104).
(Synchronization circuit insertion processing)
FIG. 3 is a flowchart showing a specific processing procedure of the synchronization circuit insertion processing of FIG.

  FIG. 4 is a diagram showing a circuit block on the transmission side of the asynchronous bus (hereinafter referred to as a first circuit block) and a circuit block on the reception side of the asynchronous path (hereinafter referred to as a second circuit block). FIG. 5 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl ≧ Tr. FIG. 6 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl <Tr.

  3 to 6, the asynchronous path detection unit 7 searches for an asynchronous path included in the semiconductor device based on the design data (step S201).

  Next, the delay setting unit 8 acquires the latency Tcl of the clock tree (step S202).

  The FF insertion unit 9 inserts one FF. In the example of FIGS. 5 and 6, the FF 62 is inserted (step S203).

  Next, the delay setting unit 8 calculates the metastable convergence time Tr of the inserted FF (step S204).

  Next, when Tcl is smaller than Tr (YES in step S205), the delay setting unit 8 delays the clock to the clock terminal of the FF of the second circuit block by Tr time from the originally input clock φ2. A delay circuit for inserting the clock φ3 is inserted (step S206).

  Furthermore, the delay setting unit 8 sets the clock to the clock terminal of the FF inserted for synchronization to the clock φ2 originally input to the clock terminal of the FF of the second circuit block. In the example of FIG. 6, the clock φ2 is input to the clock terminal of the FF 62 (step S207).

  On the other hand, when Tcl is greater than or equal to Tr (NO in step S205), the delay setting unit 8 changes the clock to the clock terminal of the FF of the second circuit block from the original clock φ2, and the leaf (terminal) of the clock tree is changed. ) To be output to the clock φ3. In the example of FIG. 5, the clock φ3 is input to the clock terminal of the FF 55 (step S208).

  Next, the delay setting unit 8 extracts from the clock tree a clock φ4 (that is, a clock on the root side of the clock tree) that is earlier than the clock φ3 output from the leaf (terminal) of the clock tree by Tr time. The delay setting unit 8 sets the clock φ4 extracted from the clock to the clock terminal of the FF of the synchronization circuit. In the example of FIG. 5, the clock φ4 is input to the clock terminal of the FF 62 (step S209).

  As described above, in this embodiment, data from the circuit block on the transmission side is sampled by the FF for synchronization that operates at the frequency on the reception side, and the data is collected after the metastable convergence time elapses in the circuit block on the reception side. By sampling, the circuit block on the receiving side can capture stable data, so even a designer with poor design skills can design an asynchronous path with a short TAT without mistakes.

  In addition, since the clock tree latency is used as much as possible in order to delay the clock supplied to the circuit block on the receiving side, it can be implemented without newly generating Area / Power overhead.

[Modification 1 of the first embodiment]
In this modification, the FF insertion unit 9 inserts a first flip-flop (front FF) and a second flip-flop (back FF) that receives data from the front FF into the detected asynchronous path.

  When the metastable convergence time Tr of the flip-flop on the receiving side of the asynchronous path (the FF preceding the inserted two-stage FF) is shorter than the clock tree length TCl, the delay setting unit 8 starts from the node in the clock tree. The output first clock is set to the input of the clock terminal of the preceding FF and the input of the detected flip-flop on the receiving side of the asynchronous data bus. The delay setting unit 8 further sets the second clock output from another node of the clock tree and having the phase difference from the first clock as the metastable convergence time Tr as the input of the clock terminal of the subsequent FF. To do.

  The delay setting unit 8 is output from a node in the clock tree when the metastable convergence time Tr of the flip-flop on the receiving side of the asynchronous path (the FF preceding the two-stage FF to be inserted) is equal to or longer than the latency Tcl of the clock tree. The first clock is set to the input of the clock terminal of the preceding FF and the input of the clock terminal of the flip-flop on the receiving side of the detected asynchronous path. The delay setting unit 8 sets the second clock obtained by delaying the first clock by the metastable convergence time Tr by a delay circuit other than the clock tree to the input of the clock terminal of the subsequent FF.

  FIG. 7 is a flowchart showing another example of a specific processing procedure of the synchronization insertion process of FIG.

  FIG. 8 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl ≧ Tr. FIG. 9 is a diagram illustrating a synchronization circuit inserted in the asynchronous path of FIG. 4 when Tcl <Tr.

  Referring to FIGS. 4 and 7 to 9, the asynchronous path detection unit 7 searches for an asynchronous path included in the semiconductor device based on the design data (step S <b> 301).

  Next, the delay setting unit 8 acquires the latency Tcl of the clock tree (step S302).

  Next, the FF insertion unit 9 inserts two stages of FFs. In the example of FIGS. 8 and 9, FF64 and FF65 are inserted (step S303).

  Next, the delay setting unit 8 calculates the metastable convergence time Tr of the FF preceding the inserted two-stage FF (step S304).

  Next, when Tcl is smaller than Tr (YES in step S305), the delay setting unit 8 originally inputs the clock to the clock terminal of the FF in the subsequent stage to the clock terminal of the FF of the second circuit block. A delay circuit for delaying Tr time from the clock φ2 is inserted. In the example of FIG. 9, the delay circuit 67 is inserted (step S306).

  Furthermore, the delay setting unit 8 is a clock that was originally input to the clock terminal of the FF of the second circuit block and the clock to the clock terminal of the FF of the second circuit block. Set to φ2. In the example of FIG. 9, the clock φ2 is input to the clock terminal of the FF 64 (step S307).

  On the other hand, when Tcl is equal to or greater than Tr (NO in step S305), the delay setting unit 8 sets the clock to the clock terminal of the subsequent stage FF from the intermediate node of the clock tree to the clock φ3. In the example of FIG. 8, the clock φ3 is input to the clock terminal of the FF 65 (step S308). Here, φ3 is selected so that the phase (delay) difference between φ3 and φ4, which will be described later, is greater than or equal to Tr.

  Next, the delay setting unit 8 extracts the clock φ4 from the leaf (end) of the clock tree. The delay setting unit 8 changes the clock to the clock terminal of the FF of the second circuit block from the clock φ2 and sets it to the clock φ4. Further, the delay setting unit 8 sets the clock to the clock terminal of the FF in the previous stage to the clock φ4. In the example of FIG. 8, the clock φ4 is input to the clock terminals of FF55 and FF64 (step S309).

  In this modification, the same effect as that of the first embodiment can be obtained. Further, in the present modification, since a plurality of stages of FFs are used, data can be captured more reliably in the circuit block on the receiving side.

[Second Embodiment]
(Semiconductor chip)
FIG. 10 is a diagram showing a configuration of a semiconductor chip according to the second embodiment of the present invention.

  Referring to FIG. 10, this semiconductor chip 70 includes a CPU (Central Processing Unit) 173, an SRAM (Static Random Access Memory) 71, a flash memory 72, and a PLL 79. The CPU 173 includes a clock tree 82, an FF 83, and a Logic 87.

  The PLL 79 outputs a reference clock to the clock tree 82. The clock tree 82 includes a plurality of stages of buffers 86 (delay elements), and supplies a clock from a plurality of nodes to each element of the CPU.

  The CPU 173 is connected to the SRAM 71 and the flash memory 72 via a data bus 80.

  Further, this semiconductor chip includes an I2C bus interface 574 and a USB controller 575 as peripheral IP blocks, and further includes a PLL 76.

  The CPU 173 is connected to the I2C bus interface 574 and the USB controller 575 via the peripheral bus 81.

  The PLL 76 outputs the reference clock to a clock tree (not shown) in the I2C bus interface 574 and a clock tree (not shown) in the USB controller 575. Each of these clock trees includes a plurality of buffers (delay elements), and supplies clocks from a plurality of nodes to each element.

  Since the CPU 173 and the I2C bus interface 574 operate with clocks supplied from separate clock trees, the data path between the CPU 173 and the I2C bus interface 574 operates asynchronously.

  Similarly, since the CPU 173 and the USB controller 575 operate with clocks supplied from separate clock trees, the data path between the CPU 173 and the USB controller 575 operates asynchronously.

  A synchronization circuit 77 is inserted in an asynchronous path from the CPU 173 (transmission side circuit block) to the I2C bus interface 574 (reception side circuit block).

  A synchronization circuit 78 is inserted in an asynchronous path from the CPU 173 (transmission side circuit block) to the USB controller 575 (reception side circuit block).

Synchronization circuit 77 and synchronization circuit 78 receive test signal TEST from terminal Tm.
(Synchronization circuit)
Next, details of the synchronization circuit 77 of FIG. 10 will be described. The synchronization circuit 78 is similar to this.

  FIG. 11 is a diagram illustrating an example of the first circuit block on the transmission side of the asynchronous data bus, the second circuit block on the reception side of the asynchronous path, and the synchronization circuit inserted in the asynchronous path.

  The first circuit block 74 includes an FF 84. The clock φ1 is input to the clock terminal of the FF84.

The synchronization circuit 77 includes an FF 91 and a selector 188.
The selector 188 receives the first clock φ4 and the second clock φ3. The second clock φ3 is a signal obtained by delaying the first clock φ4 by the metastable convergence time Tr of the FF 91. The first clock φ 4 and the second clock φ 3 are supplied from separate nodes of the clock tree 82. The second clock φ3 is a clock output from the end (leaf) of the clock tree. The first clock φ4 is output from a node on the root side of the end (leaf) of the clock tree.

  The selector 188 activates the test signal TEST during the test, and outputs the second clock φ3 to the clock terminal of the FF 91. Thereby, at the time of the test, FF83 and FF91 operate with the same clock φ3. The selector 188 normally deactivates the test signal TEST and outputs the first clock φ4 to the clock terminal of the FF 91. The FF 91 receives the output of the FF 84. The output of the selector 188 is input to the clock terminal of the FF 91.

The second circuit block 73 includes a Logic 87 and an FF 83.
Logic 87 receives the output of FF 91 in synchronization circuit 77, performs logical operation processing, and outputs the result to FF 83.

  The FF 83 receives the output from the Logic 87. The second clock φ3 is input to the clock terminal of the FF83.

[Modification 1 of Second Embodiment]
FIG. 12 is a diagram illustrating another example of the first circuit block on the transmission side of the asynchronous data bus, the second circuit block on the reception side of the asynchronous path, and the synchronization circuit inserted in the asynchronous path.

  The first circuit block 74 includes an FF 84. The clock φ1 is input to the clock terminal of the FF84.

The synchronization circuit 77 includes an FF 91, a selector 188, and a delay circuit 90.
The delay circuit 90 delays the first clock φ2 by the metastable convergence time Tr of the FF 91, and outputs the second clock φ3. The first clock φ2 is supplied from the clock tree 82.

  The selector 188 receives the second clock φ3 and the first clock φ2. The selector 188 activates the test signal TEST during the test, and outputs the second clock φ3 to the clock terminal of the FF 91. Thereby, at the time of the test, FF83 and FF91 operate with the same clock φ3. The selector 188 normally deactivates the test signal TEST and outputs the first clock φ2 to the clock terminal of the FF 91. The FF 91 receives the output of the FF 84. The output of the selector 188 is input to the clock terminal of the FF 91.

The second circuit block 73 includes a Logic 87 and an FF 83.
Logic 87 receives the output of FF 91 in synchronization circuit 77, performs logical operation processing, and outputs the result to FF 83.

  The FF 83 receives the output from the Logic 87. The second clock φ3 is input to the clock terminal of the FF83.

[Modification 2 of the second embodiment]
FIG. 13 is a diagram illustrating still another example of the first circuit block on the transmission side of the asynchronous data bus, the second circuit block on the reception side of the asynchronous path, and the synchronization circuit inserted in the asynchronous path.

  The first circuit block 74 includes an FF 84. The clock φ1 is input to the clock terminal of the FF84.

The synchronization circuit 77 includes a front-stage FF 93, a rear-stage FF 92, and a selector 94.
The selector 94 receives the first clock φ4 and the second clock φ3. The second clock φ3 is a signal obtained by delaying the phase of the first clock φ4 by the metastable convergence time Tr of the FF93. The first clock φ 4 and the second clock φ 3 are supplied from separate nodes of the clock tree 82. For example, the first clock φ4 is a clock output from the end (leaf) of the clock tree. The second clock φ3 is output from a node on the root side of the end (leaf) of the clock tree. Here, a phase (delay) difference equal to or greater than Tr is secured between φ3 and φ4.

  The selector 94 activates the test signal TEST during the test, and outputs the first clock φ4 to the clock terminal of the FF 92. Thereby, at the time of a test, FF83, FF93, and FF92 operate with the same clock φ4. The selector 94 normally deactivates the test signal TEST, and outputs the second clock φ3 to the clock terminal of the FF 92.

  The FF 93 receives the output of the FF 84. The first clock φ4 is input to the clock terminal of the FF93.

  The FF 92 receives the output of the FF 93. The output of the selector 94 is input to the clock terminal of the FF 92.

The second circuit block 73 includes a Logic 87 and an FF 83.
The Logic 87 receives the output of the FF 92 in the synchronization circuit 77, performs logical operation processing, and outputs the result to the FF 83.

  The FF 83 receives the output from the Logic 87. The first clock φ4 is input to the clock terminal of the FF83.

[Modification 3 of the second embodiment]
FIG. 14 is a diagram illustrating still another example of the first circuit block on the transmission side of the asynchronous data bus, the second circuit block on the reception side of the asynchronous path, and the synchronization circuit inserted in the asynchronous path.

  The first circuit block 74 includes an FF 84. The clock φ1 is input to the clock terminal of the FF84.

  The synchronization circuit 77 includes a front-stage FF 93, a rear-stage FF 92, a selector 94, and a delay circuit 95.

  The delay circuit 95 delays the first clock φ2 by the metastable convergence time Tr of the FF 93 and outputs the second clock φ3. The first clock φ2 is supplied from a node of the clock tree 82.

  The selector 94 receives the first clock φ2 and the second clock φ3. The selector 94 activates the test signal TEST during the test, and outputs the first clock φ2 to the clock terminal of the FF 92. Thereby, at the time of a test, FF83, FF93, and FF92 operate with the same clock φ2. The selector 94 normally deactivates the test signal TEST, and outputs the second clock φ3 to the clock terminal of the FF 92.

  The FF 93 receives the output of the FF 84. The first clock φ2 is input to the clock terminal of the FF93.

  The FF 92 receives the output of the FF 93. The output of the selector 94 is input to the clock terminal of the FF 92.

The second circuit block 73 includes a Logic 87 and an FF 83.
The Logic 87 receives the output of the FF 92 in the synchronization circuit 77, performs logical operation processing, and outputs the result to the FF 83.

  The FF 83 receives the output from the Logic 87. The first clock φ2 is input to the clock terminal of the FF83.

  As described above, according to the second embodiment and the modification of the second embodiment, the data from the circuit block on the transmission side is sampled by the FF for synchronization that operates at the reception side frequency, and is received. By sampling the data after the metastable convergence time has elapsed in the circuit block on the side, the circuit block on the receiving side can capture stable data.

  Further, by providing a selector in the synchronization circuit, the synchronization circuit and the circuit block on the receiving side can be operated with the same clock during the test.

  In the second embodiment and the second modification, the second clock φ3 is a clock output from the end (leaf) of the clock tree. However, the present invention is not limited to this. Any clock may be used as long as the first clock and the second clock are output from different nodes in the clock tree by the metastable convergence time.

[Third Embodiment]
FIG. 15 is a diagram illustrating the configuration of the semiconductor design apparatus according to the third embodiment.

  The semiconductor design apparatus 11 of FIG. 15 is different from the semiconductor design apparatus 1 of FIG.

  The format verification unit 12 includes a synchronization circuit detection unit 14, a logical compression unit 15, and a match determination unit 16.

  The synchronization circuit detection unit 14 detects an asynchronous path between the first circuit block and the second circuit block that operate with different clocks. The synchronization circuit detection unit 14 detects the synchronization circuit inserted in the asynchronous path.

  The logic compression unit 15 logically compresses the input logic of the second circuit block by deleting the inserted synchronization circuit.

  The coincidence determination unit 16 determines whether or not the input logic of the second circuit block before the synchronization circuit is inserted matches the input logic of the second circuit block after the logic compression.

(Overall operation)
FIG. 16 is a flowchart showing the operation procedure of the semiconductor design apparatus according to the third embodiment.

  Referring to FIG. 16, logic synthesis unit 2 performs logic design of the semiconductor device from the description regarding the operation of the abstract circuit, creates design data of the semiconductor device, and writes the design data in design data storage unit 3 (step S401). ).

  Next, the synchronization circuit insertion unit 4 performs a process of inserting the synchronization circuit into the asynchronous data bus included in the semiconductor device (step S402).

  Next, the timing verification unit 5 performs a timing verification process of the semiconductor device (step S403).

  Next, the format verification unit 12 performs format verification of the semiconductor device unique to the embodiment of the present invention to be described later (step S404).

(Form verification process)
FIG. 17 is a flowchart showing a specific processing procedure of the format verification processing of FIG.

  Referring to FIG. 17, first, the synchronization circuit detection unit 14 detects an asynchronous path between the first circuit block and the second circuit block that operate with different clocks (step S501).

  Next, the synchronization circuit detection unit 14 detects the synchronization circuits (the front-stage FF1 and the rear-stage FF2) inserted in the asynchronous path (step S502).

  Next, the logical compression unit 15 logically compresses the input logic of the second circuit block by deleting the FF2 (step S503).

  Further, the logical compression unit 15 logically compresses the input logic of the second circuit block by deleting FF1 (step S504).

  If the logic after logic compression is equal to the logic before the synchronization circuit insertion (YES in step S505), the match determination unit 16 outputs a match as a verification result (step S506).

  On the other hand, when the logic after logic compression is not equal to the logic before the synchronization circuit insertion (NO in step S505), the match determination unit 16 outputs a mismatch as the verification result (step S507).

(Example 1)
FIG. 18 is a diagram illustrating a first circuit block on the transmission side of the asynchronous path before insertion of the synchronization circuit and a second circuit block on the reception side of the asynchronous path.

  The input logic of the FF 53 of the first circuit block 51 is FA1. The input logic of the FF 55 of the second circuit block 52 is FB1.

It is assumed that Logic 54 does not particularly perform a logical operation.
FB1 is the input logic of FF55.
FB1 = FA1 @ φ1 (2-1)
It is expressed as Here, @ and below represent clock domains.

FIG. 19 is a diagram illustrating an example in which a synchronization circuit is inserted in the asynchronous path of FIG.
The synchronizing circuit detection unit 14 generates data input to the FF 64 in synchronization with the clock φ1 in a clock domain different from the clock φ4, although data is latched in the preceding FF 64 in synchronization with the clock φ4. Therefore, it recognizes that asynchronous transfer is being performed. Further, when the FF 64 is forward-traced, the synchronization circuit detection unit recognizes that the subsequent FF 65 is found and there is no other branch. Further, the synchronization circuit detection unit 14 forward-traces the FF 65 and recognizes that the FF 55 is found via the Logic 54 and there is no other branch. Therefore, the synchronization circuit detection unit 14 determines that the FF 64 and the FF 65 are inserted as synchronization circuits.

  The logic of the input of the FF 64 of the synchronization circuit 63 is FB3, and the logic of the input of the FF 65 is FB4.

  Since this embodiment verifies the matching of functions, no delay is considered. Accordingly, the delay clock φ3 in FIG. 19 is determined to be equivalent to φ4.

FB1 is the input logic of FF55.
FB1 = FB4 @ φ4 (2-2)
It becomes. further,
FB4 = FB3 @ φ4 (2-3)
FB3 = FA1 @ φ1 (2-4)
It is expressed as

  The logical compression unit 15 logically compresses the logical FB1 input to the FF 55 as follows by deleting the FF 65 using Expression (2-3).

FB1 = FB3 @ φ4 (2-5)
Further, the logical compression unit 15 logically compresses the logical FB1 input to the FF 55 as follows by deleting the FF 64 using Expression (2-4).

FB1 = FA1 @ φ1 (2-6)
Since the logical expression (2-1) and the logical expression (2-6) match, the match determination unit 16 outputs a match as the verification result.

(Example 2)
FIG. 20 is a diagram illustrating a first circuit block on the transmission side of the asynchronous path before insertion of the synchronization circuit and a second circuit block on the reception side of the asynchronous path.

  The logic of the input of the FF 163 of the first circuit block 161 is FA1, and the logic of the input of the FF 164 is FA2.

  The input logic of the FF 167 of the second circuit block 162 is FB1, and the input logic of the FF 168 is FB2.

It is assumed that Logic 165 performs addition, and Logic 166 performs subtraction.
FB1 is the input logic of FF167.
FB1 = (FA1 + FA2) @ φ1-FB2φ2 (3-1)
It is expressed as Here, @ and below represent clock domains.

FIG. 21 is a diagram illustrating an example in which a synchronization circuit is inserted in the asynchronous path of FIG.
In the synchronization circuit detection unit 14, the data is latched in the FF 64 in synchronization with the clock φ 4, but the data input to the FF 64 is generated in synchronization with the clock φ 1 in a clock domain different from the clock φ 4. Therefore, it recognizes that asynchronous transfer is being performed. Furthermore, when the FF 64 is forward traced, the synchronization circuit detection unit 14 recognizes that the FF 65 is found and there is no other branch. Further, the synchronization circuit detection unit 14 forward-traces the FF 65 and recognizes that the FF 167 is found via the Logic 166 and there is no other branch. Therefore, the synchronization circuit detection unit 14 determines that the FF 64 and the FF 65 are inserted as synchronization circuits.

  The logic of the input of the FF 64 of the synchronization circuit 63 is FB3, and the logic of the input of the FF 65 is FB4. Note that this embodiment does not consider a delay in order to verify matching of functions. Accordingly, the delay clock φ3 in FIG. 19 is determined to be equivalent to φ2.

FB1 is the input logic of FF167.
FB1 = FB4 @ φ2-FB2φ2 (3-2)
It becomes. further,
FB4 = FB3 @ φ2 (3-3)
FB3 = (FA1 + FA2) @ φ1 (3-4)
It is expressed as

  The logical compression unit 15 logically compresses the logical FB1 input to the FF 167 as follows by deleting the FF 65 using Expression (3-3).

FB1 = FB3 @ φ2-FB2 @ φ2 (3-5)
Further, the logical compression unit 15 logically compresses the logical FB1 input to the FF 167 as follows by deleting the FF 64 using Expression (3-4).

FB1 = (FA1 + FA2) @ φ1-FB2φ2 (3-6)
Since the logical expression (3-1) matches the logical expression (3-6), the coincidence determination unit 16 outputs coincidence as a verification result.

  As described above, according to the embodiment of the present invention, it is possible to automatically verify whether or not the logic (function) of the circuit before and after the synchronization is the same. There is no need to re-run verification.

  Note that the format verification of the embodiment of the present invention is not only applied to the synchronization circuits described in the first embodiment and the second embodiment, but can also be applied to the format verification of other synchronization circuits. .

[Fourth Embodiment]
The present embodiment relates to format verification for directly verifying a malfunction caused by the influence of metastable.

  Usually, the FF has set-up and hold timing constraints because the validity of the captured data cannot be guaranteed against data changes in the vicinity of the active edge of the clock.

  Conventional logic simulators that perform timing verification have set the logic value on the FF simulation to be undefined ('X') when such a timing error occurs. However, since the set indeterminacy cannot be erased unless the definite value is taken in at the active edge of the clock after the next cycle, the indefinite propagates more than necessary. However, when a timing error occurs, the logical value of the FF of the actual machine returns to the final value after the metastable convergence time has elapsed, and the conventional logic simulator does not accurately reflect the operation of the actual machine.

In the embodiment of the present invention, timing verification closer to the operation of an actual machine will be described.
FIG. 22 is a diagram illustrating the configuration of the semiconductor design apparatus according to the fourth embodiment.

  The semiconductor design apparatus 17 in FIG. 22 is different from the semiconductor design apparatus 1 in FIG. Although not shown, the semiconductor design device 17 may further include the synchronization circuit insertion unit 4 described in the first embodiment.

  The timing verification unit 18 includes a timing violation detection unit 20 and an FF logical value setting unit 21.

  Based on the design data, the timing violation detection unit 20 detects an FF to which a timing violation signal is input at the time of logic simulation.

  The FF logic value setting unit 21 sets the output of the detected FF on the simulation to an indefinite value at the time of the timing violation during the logic simulation, and after the metastable convergence time in the detected FF has elapsed, Return the simulation output from the indefinite value to the final value.

(Overall operation)
FIG. 23 is a flowchart showing the operation procedure of the semiconductor design apparatus of the fourth embodiment.

  Referring to FIG. 23, logic synthesis unit 2 performs logic design of the semiconductor device from the description regarding the operation of the abstract circuit, creates design data of the semiconductor device, and writes the design data in design data storage unit 3 (step S601). ).

  Next, the timing verification unit 18 performs a timing verification process of the semiconductor device unique to the embodiment of the present invention described later (step S603).

Next, the format verification unit 6 performs format verification of the semiconductor device (step S604).
(Timing verification process)
FIG. 24 is a flowchart showing a specific processing procedure of the timing verification processing of FIG.

  Referring to FIG. 24, first, timing violation detection unit 20 detects an FF to which a timing violation signal is input during logic simulation based on design data (YES in step S702). The value setting unit 21 makes the logical value in the simulation of the detected FF undefined when the timing is violated (step S703).

  Furthermore, when the metastable convergence time Tr time in the detected FF has elapsed (YES in step S704), the FF logical value setting unit 21 returns the logical value in the simulation of the detected FF to the final value (step S704). S705).

  Furthermore, if all the parts have not been verified (NO in step S706), the process from step S702 is repeated for the unverified part. If all parts have been verified (YES in step S706), the process ends.

(Example)
FIG. 25 is a diagram illustrating a circuit to be verified for timing.

FIG. 26 is a timing chart in the conventional timing verification.
As shown in FIG. 26, it is assumed that the signal IntEnable output from the FF 44 synchronized with ClkA violates the timing constraint of the FF 45 synchronized with ClkB at time T1. In the conventional logic simulator, as shown in FIG. 24, the logic value in the simulation of the signal SyncEnable output from the FF 45 is set to be indefinite until the definite value is latched by the rise of ClkB after the next cycle. As a result, the logical value of the signal Enable output from the FF 46 that receives the signal SyncEnable and the signal SyncData output from the MUX 42 that receives the signal Enable become undefined in the next cycle. Further, the simulation logical value of the signal DataOut output from the FF 43 that receives the signal SyncData becomes indefinite in successive cycles.

This phenomenon occurs similarly at the time T2 and the time T3.
Therefore, in the conventional method, even if the synchronization is correctly performed in the actual machine, the indefiniteness propagates in the simulation, which hinders the analysis.

FIG. 27 is a timing chart in the timing verification of the fourth embodiment.
As in the conventional example of FIG. 26, it is assumed that the signal IntEnable output from the FF 44 synchronized with ClkA violates the timing constraint of the FF 45 synchronized with ClkB at time T1.

  In this case, as in the conventional example, the simulation logical value of the signal SyncEnable output from the FF 45 is set to be indefinite. Thereafter, the logical value in the simulation of the signal SyncEnable output from the FF 45 after the lapse of the metastable convergence time Tr of the FF 45 is returned from the indefinite value to the determined value.

  Since the metastable convergence time Tr is shorter than the cycle TPB of ClkB, the logical value in the SyncEnable simulation becomes a definite value ('1') before the setup restriction of the FF 46. As a result, the logical value in the simulation of the Enable signal of the next cycle also becomes a definite value ('1'), and SyncData and DataOut do not get indefinite. That is, unnecessary indefinite propagation to the subsequent stage does not occur.

  However, when the metastable convergence time Tr is equal to or longer than the ClkB period TPB, the FF 46 latches indefiniteness and propagates indefiniteness to the subsequent circuit as in the conventional case.

  As described above, in this embodiment, by changing the logic value on the simulation of the FF that has violated the timing after the metastable convergence time has elapsed from an indeterminate value to a deterministic value, unnecessary indefinite propagation can be prevented, and more Simulation close to is possible. In addition, although it is difficult to verify the timing of asynchronous paths comprehensively in an actual machine, this embodiment can be realized on simulation.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 11, 17 Semiconductor design apparatus, 2 logic synthesis unit, 3 design data storage unit, 4 synchronization circuit insertion unit, 5 timing verification unit, 6,12 format verification unit, 7 asynchronous path detection unit, 8 delay setting unit, 9 FF insertion unit, 14 synchronization circuit detection unit, 15 logic compression unit, 16 coincidence determination unit, 20 timing violation detection unit, 21 logical value setting unit, 51, 74, 161 first circuit block, 52, 73, 162 Second circuit block 41, 43, 44, 45, 46, 53, 55, 62, 64, 65, 83, 84, 85, 91, 92, 93, 163, 164, 167, 168 FF, 54, 87 , 165, 166 Logic, 61, 63, 77, 78 Synchronization circuit, 66, 67, 90, 95 Delay circuit, 188, 94 selector, 42 MUX, 70 Semiconductor chip, 7 1 SRAM, 72 flash memory, 173 CPU, 574 I2C bus interface, 575 USB controller, 76, 79 PLL, 82 clock tree, 86 buffer, 80 data bus, 81 peripheral path, Tm terminal.

Claims (9)

A storage unit for storing design data of the semiconductor device;
A detection unit that detects an asynchronous path included in the semiconductor device based on the design data;
An insertion unit for inserting a first flip-flop into the detected asynchronous path;
When the metastable convergence time from the start to the end of the metastable state in the inserted flip-flop is shorter than the latency of the clock tree, the first clock output from a node in the clock tree is the first clock. A second clock output from another node of the clock tree and delayed by the metastable convergence time from the first clock is set to the input of the clock terminal of the flip-flop of A delay setting unit for setting the input to the clock terminal of the receiving flip-flop,
The delay setting unit sets a first clock output from a node of the clock tree as an input of a clock terminal of the first flip-flop when the metastable convergence time is equal to or higher than a latency of a clock tree. A second clock obtained by delaying the first clock by a delay circuit other than the clock tree by the metastable convergence time is set as an input of a clock terminal of a flip-flop on the receiving side of the detected asynchronous path; Semiconductor design equipment. A storage unit for storing design data of the semiconductor device;
A detection unit that detects an asynchronous path included in the semiconductor device based on the design data;
An insertion unit for inserting a first flip-flop and a second flip-flop for receiving data from the first flip-flop into the detected asynchronous path;
When the metastable convergence time from the start to the end of the metastable state in the inserted first flip-flop is shorter than the latency of the clock tree, the first clock output from a node in the clock tree is Set to the input of the clock terminal of the first flip-flop and the input of the clock terminal of the flip-flop on the receiving side of the detected asynchronous path, output from another node of the clock tree, and the first clock A delay setting unit that sets a second clock whose phase difference is the metastable convergence time to the input of the clock terminal of the second flip-flop,
When the metastable convergence time is equal to or higher than the latency of the clock tree, the delay setting unit detects the first clock output from a node in the clock tree and the input of the clock terminal of the first flip-flop. The second clock obtained by delaying the first clock by the delay circuit other than the clock tree by the metastable convergence time is set to the input of the clock terminal of the flip-flop on the receiving side of the asynchronous path. Semiconductor design device set to the input of the clock terminal of the flip-flop. A flip-flop connected between the first circuit block and the second circuit block operating with clocks that are not synchronized with each other;
A selector that receives the first clock and the second clock and outputs one of the clocks to the clock terminal of the flip-flop;
The second clock is input to a clock terminal of a flip-flop of the second circuit block;

The semiconductor device, wherein the second clock is a signal obtained by delaying the first clock by a metastable convergence time from the start of the metastable state to the end of the flip-flop of the second circuit block. A first flip-flop in the preceding stage and a second flip-flop in the subsequent stage connected between the first circuit block and the second circuit block that operate with clocks that are not synchronized with each other;
A selector that receives the first clock and the second clock and outputs one of the clocks to the clock terminal of the second flip-flop;
The first clock is input to a clock terminal of a flip-flop of a second circuit block and a clock terminal of the first flip-flop;

The semiconductor device, wherein the second clock is a signal obtained by delaying the first clock by a metastable convergence time from the start of the metastable state to the end of the flip-flop of the second circuit block.   The semiconductor device according to claim 3, wherein the first clock and the second clock are signals output from different nodes of a clock tree.   The semiconductor device according to claim 5, wherein the second clock is a signal output from a terminal node of the clock tree.   5. The semiconductor device according to claim 3, further comprising a delay circuit that delays the first clock by the metastable convergence time and outputs the second clock. 6. A storage unit for storing design data of the semiconductor device;
Based on the design data, a detection unit that detects a synchronization circuit that is included in the semiconductor device and that is inserted in an asynchronous path between a first circuit block and a second circuit block that operate with different clocks, and
A compression unit that logically compresses the input logic of the second circuit block by deleting the inserted synchronization circuit;
A match determination unit that determines whether the input logic of the second circuit block before insertion of the synchronization circuit and the input logic of the second circuit block after compression match; Semiconductor design equipment. A storage unit for storing design data of the semiconductor device;
Based on the design data, at the time of logic simulation, a detection unit that detects a flip-flop to which a signal violating timing is input,
During logic simulation, when the timing is violated, the simulation output of the detected flip-flop is set to an indefinite value, and then the metastable convergence from the start to the end of the metastable state in the detected flip-flop A semiconductor design apparatus comprising: a setting unit that returns the simulation output of the flip-flop from an indefinite value to a definite value after a lapse of time.

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