JP2012150062A - Electrostatic capacitance detecting type fingerprint reading sensor - Google Patents

Electrostatic capacitance detecting type fingerprint reading sensor Download PDF

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JP2012150062A
JP2012150062A JP2011010315A JP2011010315A JP2012150062A JP 2012150062 A JP2012150062 A JP 2012150062A JP 2011010315 A JP2011010315 A JP 2011010315A JP 2011010315 A JP2011010315 A JP 2011010315A JP 2012150062 A JP2012150062 A JP 2012150062A
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sensor
discharge
layer
electric field
passivation film
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JP5269111B2 (en
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Shoichi Kiyomoto
尚一 清本
Jin-Shown Huang Chen-Tang Shie
チェントウンファン ジンシャウシェー、
Tetsuyuki Kume
徹之 久米
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SECURE DESIGN SOLUTIONS Inc
Oriental System Technology Inc
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Oriental System Technology Inc
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Abstract

PROBLEM TO BE SOLVED: To suppress an effect of static electricity on a capacitance detecting circuit or the like of a sensor interior, improve the reliability of the sensor, and stably detect the fingerprint coming into contact with the surface of the sensor at a high sensitivity in the electrostatic capacitance detecting type fingerprint reading sensor configured by disposing a plurality of sensor electrodes on an insulating layer, wrapping the upper face and the side faces of the plurality of sensor electrodes with a passivation film, and further surrounding the four sides of each sensor electrode with a discharge layer comprising a metal pattern.SOLUTION: In the electrostatic capacitance detecting type fingerprint reading sensor, the passivation film is formed into by accumulating silicone oxynitride a thick film by a PECVD method, a discharge layer is formed on the upper face of the passivation film, and a concentrated part of the electric field distribution is formed on one or two sets of discharge layers aligned in an opposed state out of discharge layers surrounding the four sides of the sensor electrodes.

Description

本発明は、静電気容量検知型指紋読み取りセンサに関する。   The present invention relates to a capacitance detection type fingerprint reading sensor.

近年、IC(集積回路)チップを搭載したICカードは、磁気ストライプカードと比較して、情報容量の増大、セキュリティ性の向上等の理由により急速に普及している。特に、電磁波を使ってデータを送受信するタイプの所謂非接触型ICカードは、電車等の公共交通手段に導入され、その利便性は著しく向上している。   In recent years, an IC card equipped with an IC (integrated circuit) chip has been rapidly spread for reasons such as an increase in information capacity and an improvement in security as compared with a magnetic stripe card. In particular, a so-called contactless IC card of a type that transmits and receives data using electromagnetic waves has been introduced into public transportation means such as trains, and its convenience is remarkably improved.

このようなICカードは、ISO国際規格に準じたカードサイズ(縦85.6mm,横54mm,厚さ0.76mm)に限りなく近づけることが、カードの保持や携帯の利便性から必須条件とされている。その一方で、盗難や偽造、変造といったICカードの不正使用に対する防御策として指紋認証による本人確認機能に対する関心も高い。ICカードのサイズの制限を満足することで利便性を損なわず、しかも、不正使用を防御するためには、ICカードに搭載し得る指紋読取りセンサが不可欠となる。ICカードに搭載し得る指紋読取りセンサとしては、半導体基板上にセンサ電極(金属プレート)を形成し、センサ電極上にパシベーション膜層を形成し、パシベーション膜を介して皮膚とセンサとの間の静電容量を検出し指紋の凹凸を検出する、所謂静電容量検知型の半導体指紋センサ(以下FPICという)が開発されている(特許文献1)。LSIの製造技術を用いて開発されるモノリシックなICチップを用いる各種半導体指紋センサの中で低消費電力、コンパクト性、および部品数の少なさから考えて最も安価に形成し得る点を勘案すると静電容量検知型指紋センサ(以下、FPICと記す)が、最も有効と考えられる。 Such an IC card must be as close as possible to the card size (85.6mm in length, 54mm in width, 0.76mm in thickness) conforming to the ISO international standards, from the viewpoint of card holding and convenience of carrying. . On the other hand, there is a high interest in the identity verification function based on fingerprint authentication as a defense against unauthorized use of IC cards such as theft, counterfeiting and alteration. A fingerprint reading sensor that can be mounted on an IC card is indispensable to satisfy the restrictions on the size of the IC card without impairing convenience and to prevent unauthorized use. As a fingerprint reading sensor that can be mounted on an IC card, a sensor electrode (metal plate) is formed on a semiconductor substrate, a passivation film layer is formed on the sensor electrode, and the static electricity between the skin and the sensor is interposed via the passivation film. A so-called capacitance detection type semiconductor fingerprint sensor (hereinafter referred to as FPIC) that detects the capacitance and detects the unevenness of the fingerprint has been developed (Patent Document 1). Among the various types of semiconductor fingerprint sensors using monolithic IC chips developed using LSI manufacturing technology, it is static considering the point that it can be formed at the lowest cost considering low power consumption, compactness, and small number of components. A capacitance detection type fingerprint sensor (hereinafter referred to as FPIC) is considered to be most effective.

FPICは、図1に示されるように、指紋センシング領域に一般的に金属プレートの配列アレイで構成される複数のセンサ電極1が縦横方向に配列され、個々のセンサ電極1が、採取される指紋画像の最小構成単位であるピクセルに対応する。   In the FPIC, as shown in FIG. 1, a plurality of sensor electrodes 1 generally composed of an array array of metal plates are arranged in a vertical and horizontal direction in a fingerprint sensing area, and each sensor electrode 1 is a fingerprint to be collected. Corresponds to the pixel that is the smallest unit of the image.

各センサ電極1は、各々下層の静電容量センシング回路2と接続されると同時に、指の一部がFPICに触れたときに各センサ電極1との間に指紋の凹凸に応じた静電容量を検知できるように電気的に絶縁されたパシベーション膜層4により覆われる。 Each sensor electrode 1 is connected to the capacitance sensing circuit 2 in the lower layer, and at the same time, the capacitance according to the unevenness of the fingerprint between each sensor electrode 1 when a part of the finger touches the FPIC. It is covered with a passivation film layer 4 that is electrically insulated so as to be detected.

図2(a)にFPICの指紋センシング領域に指の一部が触れた際の一部領域3の断面を図2(b)に拡大して図示した。この図2(b)で示されるとおり、パシベーション膜層4に触れた皮膚(指の隆線)が第2の電極として機能し、センサ電極1との間で距離dに応じて容量が形成される場合と、指紋の谷に当る領域のように皮膚の表面が第2のプレートとして機能し、空気からなる絶縁層で隔離され、空隙層とパシベーション膜層の両方の容量が直列に結ばれて形成される容量Cが形成される場合とでは、顕著に前者の容量値が大きくなる。 FIG. 2A is an enlarged cross-sectional view of the partial area 3 when a part of the finger touches the fingerprint sensing area of the FPIC. As shown in FIG. 2 (b), the skin (finger ridge) touching the passivation film layer 4 functions as a second electrode, and a capacitance is formed between the sensor electrode 1 and the sensor electrode 1 according to the distance d 0. The surface of the skin functions as a second plate, as in the region that hits the valley of the fingerprint, and is isolated by an insulating layer made of air, and the capacitance of both the air gap layer and the passivation film layer are connected in series. in the case where the capacitance C S which are formed Te is formed, significantly former capacitance increases.

成人の谷線の深さは約150μmとされているが、この値は指の表面に接するパシベーション膜層4(絶縁層)の厚さよりも遥かに大きいし、しかも空気の誘電率は絶縁層の誘電率より小さい。(静電容量∝金属対の面積/金属対間の距離、この比例式の比例定数が金属対間の誘電体固有の誘電率を表す) The depth of the adult valley line is about 150 μm, but this value is much larger than the thickness of the passivation film layer 4 (insulating layer) in contact with the finger surface, and the dielectric constant of air is that of the insulating layer. Less than dielectric constant. (Capacitance ∝ area of metal pair / distance between metal pairs, the proportionality constant of this proportional expression represents the dielectric constant specific to the dielectric between the metal pairs)

結果的に、谷線の位置での容量は、隆線の位置で形成される容量の数%にしかならない。更に、成人の指紋の谷線と隆線のピッチは約600μmとされているので、50μmのピッチで配置されるセンサ電極1の配列(解像度508dpi相当)により指紋の凹凸の情報は十分に読取り可能となる。 As a result, the capacity at the valley line is only a few percent of the capacity formed at the ridge line. Furthermore, since the pitch between valleys and ridges of an adult fingerprint is about 600 μm, the information on the unevenness of the fingerprint can be read sufficiently by the arrangement of sensor electrodes 1 arranged at a pitch of 50 μm (corresponding to a resolution of 508 dpi). It becomes.

特許3426565Patent 3426565 特許4198239Patent 4198239 米国特許6,900,644 B2US Patent 6,900,644 B2 特許4261127Patent 4261127

前述のようなFPICの優れた特性は、その一方で、指紋をセンシングする間、指先がFPICの表面に直接触れることにより指先の表面に蓄積された静電気がセンサ電極1を通じて放電され検出回路2へと流れ、結果的にセンサ・デバイスそのものを静電破壊(electrostatic damage以下ESDという)させる可能性が生じる。   On the other hand, the excellent characteristics of the FPIC as described above are that, while sensing the fingerprint, the static electricity accumulated on the surface of the fingertip is discharged through the sensor electrode 1 when the fingertip directly touches the surface of the FPIC to the detection circuit 2. As a result, there is a possibility that the sensor device itself may be electrostatically damaged (hereinafter referred to as ESD).

この種の静電気の放出は約20kV程度に達することが知られているが、空気中放電による電子機器のESDテスト方法も「IEC61000-4-2」に規格化されている。
静電容量を検知するFPICにとって、このESD保護対策が商品化のためには不可欠であり、多くの方法が報告されている。
Although it is known that this kind of static electricity discharge reaches about 20 kV, an ESD test method for electronic devices by air discharge is also standardized in “IEC61000-4-2”.
For FPIC that detects capacitance, this ESD protection measure is indispensable for commercialization, and many methods have been reported.

その一方で、厚い誘電体層をICの表面に積層させることは、誘電体層の残留応力によりウェハ自体が歪んでしまうため、その後の写真製版処理工程等のウェハ製造工程に進む事は不可能になる。そのため誘電体層の厚みは、最大でも3〜5μmほどとしている。 On the other hand, when a thick dielectric layer is laminated on the surface of the IC, the wafer itself is distorted by the residual stress of the dielectric layer, so that it is impossible to proceed to a wafer manufacturing process such as a subsequent photolithography process. become. Therefore, the thickness of the dielectric layer is about 3 to 5 μm at the maximum.

なお、パシベーション膜層として、良く知られたポリイミド(誘電率;約4.0)を厚み3μmに積層して用いているが、静電気の発生源が装置の表面に近付けば近付くほど、ESD保護用のアース電極11によるESD保護能力より、パシベーション膜層の絶縁耐力の特性に依存するので、前述のようなパシベーション膜層では、静電容量を検知する装置のESD保護能力としては、「IEC61000-4-2」の規格値を満たすことは困難と言わざるを得ない。 As the passivation film layer, a well-known polyimide (dielectric constant: about 4.0) is laminated to a thickness of 3 μm. However, as the static electricity generation source gets closer to the surface of the device, the earth for ESD protection becomes closer. Since the ESD protection capability of the electrode 11 depends on the dielectric strength characteristics of the passivation film layer, the ESD protection capability of the device for detecting the capacitance of the passivation film layer as described above is “IEC61000-4-2”. It must be said that it is difficult to satisfy the standard value.

一方、特許文献1には、絶縁層上に複数のセンサ電極を配列し、該複数のセンサ電極の上面及び側面をパシベーション膜で包み、更に各センサ電極の四辺を金属パターンからなる放電壁で囲むようにしたFPICが提案されている。 On the other hand, in Patent Document 1, a plurality of sensor electrodes are arranged on an insulating layer, the upper surfaces and side surfaces of the plurality of sensor electrodes are covered with a passivation film, and the four sides of each sensor electrode are surrounded by a discharge wall made of a metal pattern. Such an FPIC has been proposed.

このFPICは、図3に示されたように、装置表面にセンサ電極1を取囲むように格子状にアース電極11を設け、静電気を帯びた人間の指が装置表面に接触することにより装置表面に発生する電流は装置内部に流れずに柱状のアース電極11から配線13を介して接地側に流れるようにして、装置内部の容量検出回路2等への静電気の影響を抑制するものである。 As shown in FIG. 3, the FPIC is provided with ground electrodes 11 in a lattice shape so as to surround the sensor electrode 1 on the surface of the device, and a human finger charged with static electricity contacts the surface of the device. The current generated in the current flows from the columnar earth electrode 11 to the ground side via the wiring 13 without flowing into the device, thereby suppressing the influence of static electricity on the capacitance detection circuit 2 and the like inside the device.

反面、このFPICではセンサ電極1と柱状のアース電極11との間に生じる寄生容量CPX12が生じることとなる。この寄生容量12は、測定すべき指の表面との間に生じる容量Cを測定すべきところに並列接続された容量としてCに加算されてセンサ電極1に検知され、結果的に測定容量値のオフセットを引き上げると共に、見かけ上センサ・デバイスのダイナミック・レンジを狭める結果となり、採取されるべき指紋画像の濃淡(グレースケール)情報を損なうことになる。 On the other hand, in this FPIC, a parasitic capacitance C PX 12 generated between the sensor electrode 1 and the columnar earth electrode 11 is generated. The parasitic capacitance 12 is added to the C S is detected by the sensor electrode 1 as a parallel-connected capacitor capacitance C S is described where measurement occurs between the surface to be measured finger, resulting in measurement volume Increasing the value offset and apparently reducing the dynamic range of the sensor device results in a loss of grayscale information in the fingerprint image to be collected.

特許文献2では、特許文献1におけるアース電極11の寄生容量を軽減するために、センサ電極1の周囲をゼロ電位に設置された格子状の金属パターン(アース電極11に対応)で取り囲むようにしたFPICを提案した。すなわち、図3のアース電極11が、ESD保護のための金属パターンとしてセンサ電極1より上の層(厚さdの領域)にのみ配置される。 In Patent Document 2, in order to reduce the parasitic capacitance of the ground electrode 11 in Patent Document 1, the sensor electrode 1 is surrounded by a grid-like metal pattern (corresponding to the ground electrode 11) installed at zero potential. Proposed FPIC. That is, the ground electrode 11 in FIG. 3 is disposed only in a layer (area of thickness d 0 ) above the sensor electrode 1 as a metal pattern for ESD protection.

しかし、そのセルを覆う誘電体からなるパシベーション膜層や格子状の金属パターンの厚さと材質に関しては言及して居らず、しかも上述のように通常、厚さ(d)の薄い誘電体層からは、二つの金属レイヤ(センサ電極と金属パターン)の高さの違いによる効果は期待できない。 However, there is no mention of the passivation film layer made of a dielectric covering the cell and the thickness and material of the lattice-like metal pattern, and as described above, the dielectric layer is usually thin (d 0 ). The effect due to the difference in height between the two metal layers (sensor electrode and metal pattern) cannot be expected.

それ故に、センシング電極のESD保護の十分な効果を期待するための非常に厚い誘電体層を形成するには応力の小さい誘電体の材質を選ばなくてはならなくなる。勿論、ここで残留応力の小さい材質は、例えばICカードの上にセンサ・デバイスが剥き出しに装備されることを考慮して、引掻き、衝撃等の物理的な外力に対する強度を同時に勘案して選択されなければならない(特許文献4)。   Therefore, in order to form a very thick dielectric layer for expecting a sufficient effect of ESD protection of the sensing electrode, it is necessary to select a dielectric material having a low stress. Of course, the material having a small residual stress is selected in consideration of the strength against physical external force such as scratching and impact at the same time, considering that the sensor device is mounted on the IC card. Must be present (Patent Document 4).

特許文献3では、正常なセンシング・ピクセルの中の数%を「犠牲用のデバイス」として静電気の放電を受けやすいデバイスで置換え、センサ・プレートと同じレベルの金属メッシュがグランドへの放電パスに配置された構造を提案している。この方法では必然的に「犠牲的なESD画素」の存在により採取される指紋画像の品質を低下させる。 In Patent Document 3, several percent of normal sensing pixels are replaced with “sacrificial devices” that are susceptible to electrostatic discharge, and a metal mesh at the same level as the sensor plate is placed in the discharge path to ground. Proposed structure. This method necessarily degrades the quality of the fingerprint image collected due to the presence of “sacrificial ESD pixels”.

そこで、本願発明者らは非常に厚い誘電体層を形成し、且つアース電極とセンサ電極間の寄生容量を軽減させると共に、アース電極による静電気の放電が容易に行われるような静電容量検知型指紋読取りセンサを開発する目的で鋭意研究した結果、下記に述べるような本願発明を完成したものである。   Accordingly, the inventors of the present invention form a very thick dielectric layer, reduce the parasitic capacitance between the ground electrode and the sensor electrode, and at the same time detect the electrostatic capacitance easily by the ground electrode. As a result of earnest research for the purpose of developing a fingerprint reading sensor, the present invention as described below has been completed.

本願発明においては、絶縁層上に複数のセンサ電極を配列し、該複数のセンサ電極の上面及び側面をパシベーション膜で包み、更に各センサ電極の四辺を金属パターンからなる放電層で囲むようにした静電容量検知型指紋読取りセンサにおいて、上記パシペバージョン膜はシリコンオキシナイトライドをPECVD法により堆積させて膜厚に形成すると共に、パシベーション膜の上面に上記放電層を設け、更にセンサ電極の四辺を囲む放電層のうち対向状に並ぶ1又は2組の放電層に電界分布の集中部を形成するようにした静電気容量検知型指紋読取りセンサを提案するものである。 In the present invention, a plurality of sensor electrodes are arranged on the insulating layer, the upper and side surfaces of the plurality of sensor electrodes are covered with a passivation film, and the four sides of each sensor electrode are surrounded by a discharge layer made of a metal pattern. In the capacitance detection type fingerprint reading sensor, the pasipeversion film is formed to have a film thickness by depositing silicon oxynitride by PECVD, and the discharge layer is provided on the upper surface of the passivation film, and the four sides of the sensor electrode are further formed. An electrostatic capacitance detection type fingerprint reading sensor is proposed in which a concentrated portion of an electric field distribution is formed in one or two sets of discharge layers arranged in opposition to each other.

即ち、本願発明者らの研究によれば、このシリコンオキシナイトライドは、屈折率1.65〜1.75、誘電率6.4〜6.8、硬度はH8相当の各特性を持ち、シリコンオキシナイトライドをPECVD法により堆積させることにより膜厚のパシベーション膜層を形成でき、しかもこのパシベーション膜層のESD保護能力は、空気中放電による電子デバイスのESD規格である「IEC61000-4-2」の15KVを優に超える性能を達成した。 That is, according to the study by the present inventors, this silicon oxynitride has various characteristics corresponding to a refractive index of 1.65 to 1.75, a dielectric constant of 6.4 to 6.8, and a hardness equivalent to H8, and silicon oxynitride is deposited by PECVD. Passivation film layer can be formed by this, and the ESD protection ability of this passivation film layer exceeds the performance of 15KV of “IEC61000-4-2” which is the ESD standard of electronic devices by air discharge. Achieved.

また、膜厚のパシベーション膜の上面に放電層を設けることにより、放電層とセンサ電極の距離(d)が大きくなり、放電層とセンサ電極間の寄生容量を軽減できる。 Further, by providing a discharge layer on the upper surface of the passivation film having a thickness, the distance (d) between the discharge layer and the sensor electrode is increased, and the parasitic capacitance between the discharge layer and the sensor electrode can be reduced.

なお、上下に配置される放電層とセンサ電極は、重ならないように配置されることにより、放電層とセンサ電極間の寄生容量を軽減できる。 In addition, the parasitic capacitance between a discharge layer and a sensor electrode can be reduced by arrange | positioning the discharge layer and sensor electrode which are arrange | positioned up and down so that it may not overlap.

更に、放電層に電界分布の集中部を形成することにより、一つのセンサ電極1を囲む領域の中で最も高い電界をもたらし、放電を引き起こす可能性の最も高い場所を実現し、結果として放電層の電界分布の集中部に放電を誘導する。 Furthermore, by forming a concentrated portion of the electric field distribution in the discharge layer, the highest electric field is realized in the region surrounding one sensor electrode 1, and the place where the possibility of causing discharge is the highest is realized. As a result, the discharge layer This induces discharge in the concentrated portion of the electric field distribution.

なお、放電層における電界分布の集中部は、センサ電極の四辺を囲む放電層のうち対向状に並ぶ1又は2組の放電層に凹部を形成し、該凹部の対向面に突起を形成することにより設けることができる。 The electric field distribution concentration portion in the discharge layer is formed by forming a recess in one or two pairs of discharge layers arranged in a confronting manner among the discharge layers surrounding the four sides of the sensor electrode, and forming a protrusion on the opposing surface of the recess. Can be provided.

即ち、センサ電極を囲む放電層のうち対向状に並ぶ1又は2組の放電層に凹部を形成し、該凹部の対向面に突起を形成することにより、該凹部の突起周辺では、電場が歪み、電界分布の集中が生じ、結果として一つのセンサ電極1を囲む領域の中で最も高い電界をもたらし、放電を引き起こす可能性の最も高い場所を実現する。 That is, by forming a recess in one or two sets of discharge layers that are arranged opposite to each other in the discharge layer surrounding the sensor electrode and forming a protrusion on the opposite surface of the recess, the electric field is distorted around the protrusion in the recess. The concentration of the electric field distribution occurs, resulting in the highest electric field in the region surrounding one sensor electrode 1 and realizing the place most likely to cause discharge.

更に、放電層における電界分布の集中部は、センサ電極の四辺を囲む放電層のうち対向状に並ぶ1組の放電層に凹部を形成し、該凹部の対向面に突起を形成し、他1組の対向状に並ぶ放電層の表面に突起を形成することにより設けることができる。 Further, the concentrated portion of the electric field distribution in the discharge layer is formed by forming a recess in a pair of discharge layers arranged in a face-to-face manner among the discharge layers surrounding the four sides of the sensor electrode, and forming a protrusion on the opposing surface of the recess. It can be provided by forming protrusions on the surface of the discharge layers arranged in a pair of opposed shapes.

即ち、このような構成においても他の対向状に並ぶ放電層の表面に形成した突起の周辺にも、前記同様の電場が歪み、電界分布の集中が生じ、放電を引き起こす可能性の最も高い場所を実現する。 That is, even in such a configuration, the same electric field is also distorted in the periphery of the protrusion formed on the surface of the other discharge layer arranged in the opposite direction, the electric field distribution is concentrated, and the place most likely to cause discharge Is realized.

このESD保護用の放電層の端は、指紋読取りセンサ・デバイスの外部を含め前記センサ電極が配置された領域外で接地に接続されるように配線され、その上に静電気が放出された場合にその電流を指紋センサ・デバイスの接地線に流れ込むように接続されている。 The edge of the ESD protection discharge layer is wired so that it is connected to the ground outside the area where the sensor electrode is disposed, including the outside of the fingerprint reading sensor device, and when static electricity is discharged on it. The current is connected to flow into the ground line of the fingerprint sensor device.

以上本願発明によれば、装置内部の容量検出回路等への静電気の影響を抑制でき、したがって装置の信頼性が向上するとともに、装置表面に接触した指の指紋を、安定かつ高感度で検出できる。   As described above, according to the present invention, it is possible to suppress the influence of static electricity on the capacitance detection circuit or the like inside the device, and thus the reliability of the device is improved, and the fingerprint of the finger touching the device surface can be detected stably and with high sensitivity. .

静電容量検知型指紋読取りセンサの概略図Schematic of capacitance detection type fingerprint reading sensor (a)静電容量検知型指紋読取りセンサに指の置かれた状態図、(b)(a)の領域3の拡大断面と静電容量検知の原理を示す図。(A) State figure where a finger is placed on the capacitance detection type fingerprint reading sensor, (b) An enlarged cross section of region 3 in (a) and a diagram showing the principle of capacitance detection. センサ電極とアース電極間との間に生じる寄生容量を示す図。The figure which shows the parasitic capacitance produced between a sensor electrode and earth electrodes. (a)本発明による静電容量検知型指紋センサのA−A断面図、(b)本発明による静電容量検知型指紋センサの表面の拡大図。(A) AA sectional drawing of the electrostatic capacitance detection type fingerprint sensor by this invention, (b) The enlarged view of the surface of the electrostatic capacitance detection type fingerprint sensor by this invention. 本発明の他の実施例を示す静電容量検知型指紋センサの表面の拡大図The enlarged view of the surface of the electrostatic capacitance detection type fingerprint sensor which shows other examples of the present invention. シミュレーション実験の構成図Configuration diagram of simulation experiment シミュレーション実験での各観測層を示す図Diagram showing each observation layer in simulation experiment 単純な格子状のESD保護用金属線配列を想定して電場の強度分布を等高線で示したシミュレーションの結果を示す図The figure which shows the result of the simulation which showed the intensity distribution of the electric field with the contour line supposing a simple grid-like metal line for ESD protection 形状21、形状30を配備したESD保護用金属配列を想定して電場の強度分布を等高線で示したシミュレーションの結果を示した図The figure which showed the result of the simulation which showed the intensity distribution of an electric field with the contour line supposing the metal arrangement | sequence for ESD protection which arranged the shape 21 and the shape 30

絶縁層上に複数のセンサ電極を配列し、該複数のセンサ電極の上面及び側面をパシベーション膜で包み、更に各センサ電極の四辺を金属パターンからなる放電層で囲むようにした静電容量検知型指紋読取りセンサにおいて、上記パシベーション膜はシリコンオキシナイトライドをPECVD法により堆積させて膜厚に形成すると共に、パシベーション膜の上面に上記放電層を設け、更にセンサ電極の四辺を囲む放電層のうち対向状に並ぶ1又は2組の放電層に電界分布の集中部を形成するようにした静電気容量検知型指紋読取りセンサ。   Capacitance detection type in which a plurality of sensor electrodes are arranged on an insulating layer, the upper and side surfaces of the plurality of sensor electrodes are covered with a passivation film, and the four sides of each sensor electrode are surrounded by a discharge layer made of a metal pattern. In the fingerprint reading sensor, the passivation film is formed by depositing silicon oxynitride by PECVD to have a film thickness, the discharge layer is provided on the upper surface of the passivation film, and the discharge layers surrounding the four sides of the sensor electrode are opposed to each other. An electrostatic capacitance detection type fingerprint reading sensor in which a concentrated portion of electric field distribution is formed in one or two sets of discharge layers arranged in a line.

以下、本発明による半導体指紋センサの実施方法について図を参照して説明する。
図4(a)は、本発明による静電容量検知型指紋センサFPICの断面の一部を拡大したものである。この図に示されたように、パシベーション膜層(以下、IMD層4と記す)はシリコンオキシナイトライドをPECVD法により堆積させることにより膜厚に形成される。
Hereinafter, a method for implementing a semiconductor fingerprint sensor according to the present invention will be described with reference to the drawings.
FIG. 4A is an enlarged view of a part of the cross section of the capacitance detection type fingerprint sensor FPIC according to the present invention. As shown in this figure, the passivation film layer (hereinafter referred to as IMD layer 4) is formed to have a film thickness by depositing silicon oxynitride by PECVD.

IMD層4の表面にESD保護用の格子状に放電層を構成する金属線20を配置する。平行な金属線20のピッチは、センサ電極1と同じで、隣接する二つのセンサ電極1の間に配置される。金属線20の幅は、線とセンサ電極1との間の寄生容量を最小にするためにセンサ電極1に重ならないように設計され、容量の感度を損なうオフセットを生じないように考慮される。 On the surface of the IMD layer 4, metal wires 20 constituting a discharge layer are arranged in a grid shape for ESD protection. The pitch of the parallel metal wires 20 is the same as that of the sensor electrode 1 and is arranged between two adjacent sensor electrodes 1. The width of the metal line 20 is designed not to overlap the sensor electrode 1 in order to minimize the parasitic capacitance between the line and the sensor electrode 1, and is considered not to cause an offset that impairs the sensitivity of the capacitance.

22は指と直接触れるコーティング層、23が層間絶縁膜、24が容量検知回路を形成し、その下にシリコン基材が配置される。 22 is a coating layer that is in direct contact with the finger, 23 is an interlayer insulating film, 24 is a capacitance detection circuit, and a silicon substrate is disposed below the coating.

ESD保護用の金属線20は、図4(b)に示されるように左右に伸びた横方向の配線上に凹部を形成し、該凹部の対向面に突起を設けた形状21にする。すなわち、形状21は凹部の左右対向面から釘の先のような金属を向き合わせ、その端を更に細い金属線で結ぶ構造をなしている。   As shown in FIG. 4B, the metal wire 20 for ESD protection has a shape 21 in which a recess is formed on a lateral wiring extending in the left and right directions, and a protrusion is provided on the opposite surface of the recess. That is, the shape 21 has a structure in which a metal such as the tip of a nail is faced from the left and right facing surfaces of the recess and the ends thereof are connected by a thinner metal wire.

更に、金属線20の幅は、センサ電極1との間の寄生容量を最小にするためにセンサ電極1に重ならないように配置され、しかも金属線20同士のピッチは、センサ電極1と同じにする。 Further, the width of the metal wire 20 is arranged so as not to overlap the sensor electrode 1 in order to minimize the parasitic capacitance between the metal wire 20 and the pitch between the metal wires 20 is the same as that of the sensor electrode 1. To do.

形状21により電場は、21の隙間の領域の向かい合った突起の先端で鋭い曲率を呈するようになり、その先端に集中して終わるような分布を生じる。結果として、鋭い釘の先端は、周辺の中で最も高い電場を生じる。 The shape 21 causes the electric field to have a sharp curvature at the tip of the protrusions facing each other in the region of the gap 21, and a distribution that ends in a concentrated manner at the tip. As a result, the sharp nail tip produces the highest electric field in the periphery.

電場の最も高い箇所は、その周辺に比べて静電気の放電を最も受けやすいことを意味する。言い換えれば、センサ電極1およびその周辺で放電が起こるとすれば、この形状21が選択的に放電位置になる。 The highest part of the electric field means that it is most susceptible to electrostatic discharge compared to its surroundings. In other words, if a discharge occurs around the sensor electrode 1 and its surroundings, the shape 21 selectively becomes a discharge position.

すべてのESD保護用の金属線20の端は、指紋センシング領域の縁の共通アース電極(不図示)に接続され、放電電流を迂回させるためのFPIC装置のグランドに接続される。図4(b)で示されたAAの断面が、図4(a)に当る。 The ends of all the ESD protection metal wires 20 are connected to a common earth electrode (not shown) at the edge of the fingerprint sensing area, and are connected to the ground of the FPIC device for bypassing the discharge current. The cross section of AA shown in FIG. 4B corresponds to FIG.

図5は、金属線20に電界分布集中部を形成する他の実施例を示すものであり、横方向に配列された金属線20には前記同様に形状21を形成し、縦方向配列された金属線20についてセンサ電極1に隣接する表面の中央には突起を設けた形状30にする。形状30にすることにより、形状21で述べたのと同様な原理により、形状30の隙間の領域の向かい合った突起の先端で鋭い曲率を呈するようになり、その先端に集中して終わるような分布を生じる。結果として、その周辺の中で最も高い電場を生じる。ESD保護対策として大きく貢献する。 FIG. 5 shows another embodiment in which the electric field distribution concentrated portion is formed on the metal line 20, and the shape 21 is formed on the metal line 20 arranged in the horizontal direction in the same manner as described above, and arranged in the vertical direction. The metal wire 20 has a shape 30 provided with a protrusion at the center of the surface adjacent to the sensor electrode 1. By adopting the shape 30, the distribution is such that, by the same principle as described in the shape 21, a sharp curvature is exhibited at the tip of the protrusions facing each other in the gap area of the shape 30, and the concentration ends at the tip. Produce. The result is the highest electric field around it. Contributes greatly as an ESD protection measure.

以上の発明により静電容量を検知する方式の指紋読取りセンサFPICの上でセンサ電極1を取り囲む形で放電に対する高い密度の電界分布(保護ポイント)が実現される。 According to the above-described invention, a high-density electric field distribution (protection point) against discharge is realized by surrounding the sensor electrode 1 on the fingerprint reading sensor FPIC of the type detecting capacitance.

以上ESD保護用の金属線20に対する前述の形状21、30を設けることによる効果は、電場の分布を解折するシミュレーションを用いて解析された。   As described above, the effect of providing the above-described shapes 21 and 30 for the metal wire 20 for ESD protection has been analyzed by using a simulation for breaking the electric field distribution.

シミュレーションは、ESD保護テスト「IEC61000―4−2」に準拠した図6に示す構成で実施した。   The simulation was performed with the configuration shown in FIG. 6 compliant with the ESD protection test “IEC61000-4-2”.

即ち、半径4mm(R4)の半球形からなるプローブ40の先端をセンサ・デバイス表面から5mm離した状態でプローブ40に15KVを印加し、図7に示されたセンサ・デバイスの4つの各観測層(レイヤー)面での電場の強度(V/cm)を算出、解析した。センサ・デバイスの各構成要素に用いられたパラメータ(厚さ、誘電率、導電率等)の詳述は省略する。   That is, 15 KV is applied to the probe 40 with the tip of the hemisphere having a radius of 4 mm (R4) 5 mm away from the sensor device surface, and each of the four observation layers of the sensor device shown in FIG. The electric field strength (V / cm) on the (layer) plane was calculated and analyzed. Detailed description of parameters (thickness, dielectric constant, conductivity, etc.) used for each component of the sensor device will be omitted.

形状21、30を持たない単純な格子状のESD保護用金属線配列を想定した場合の第2観測層での電場の強度分布を等高線で表したシミュレーション結果を図8に示す。 FIG. 8 shows a simulation result in which the intensity distribution of the electric field in the second observation layer is expressed by contour lines when a simple grid-like ESD protection metal wire array having no shapes 21 and 30 is assumed.

同様に、形状21、形状30を配備したESD保護用金属線配列を想定した場合の第2観測層での電場の強度分布を等高線で表した結果を図9に示す。   Similarly, FIG. 9 shows the result of expressing the intensity distribution of the electric field in the second observation layer with contour lines when the ESD protection metal wire array having the shapes 21 and 30 is assumed.

図8と図9の中で書き込まれた数値はそれぞれ、その周辺での電場強度分布の極大値を示している。 The numerical values written in FIG. 8 and FIG. 9 indicate the local maximum values of the electric field intensity distribution in the vicinity thereof.

両者の図を比較するとセンサ電極1が配置されている格子の中心での電場の強度は殆ど変わらないのに対し、ESD保護用金属線に設けられた形状21、形状30の近傍の値は著しく高くなっていることが判る。 Comparing the two figures, the intensity of the electric field at the center of the grid on which the sensor electrode 1 is arranged hardly changes, but the values in the vicinity of the shapes 21 and 30 provided on the metal wire for ESD protection are remarkably large. It turns out that it is high.

各観測層でESD保護に深く関係する位置での電場の強度を表1にまとめた。この表からパシベーション膜層4の表面に当たる第2観測層同様、センサ表面、センサ電極1の表面においても格子の中央(センサ電極1の中央)の位置では、形状21、形状30を設けられたことによる影響は殆ど見られないのに対し、格子の金属線上では、電界強度は約150%の増加をもたらし、電場の稠密化が見られる。 Table 1 shows the electric field strengths at positions closely related to ESD protection in each observation layer. Similar to the second observation layer corresponding to the surface of the passivation film layer 4 from this table, the shape 21 and the shape 30 were provided on the sensor surface and the surface of the sensor electrode 1 at the center of the lattice (center of the sensor electrode 1). On the other hand, on the metal lines of the grid, the electric field strength increases by about 150%, and the electric field becomes denser.

言い換えれば、形状21、形状30を持つたESD保護用金属線を用いたことによりESD保護効果は1.5倍増加することが判明した。 In other words, it was found that the ESD protection effect is increased 1.5 times by using the ESD protection metal wire having the shape 21 and the shape 30.

Figure 2012150062
Figure 2012150062

本発明によれば、低消費電力で最も安価に形成し得る静電容量検知型の指紋センサを広く普及している利便性の高いICカード等装置に搭載し、信頼性の高い安定した本人確認手段を実現して提供できる。   According to the present invention, a capacitance detection type fingerprint sensor that can be formed at the lowest cost with low power consumption is mounted on a widespread and convenient device such as an IC card, so that reliable and stable identity verification is possible. Means can be realized and provided.

1はセンサ電極
2は容量検知回路
3は図2bの拡大領域
4はパシベーション膜層(IMD層)
11はアース電極
12は寄生容量
13は接地線
20はESD保護用の金属線断面
21は横方向に配列された金属線に施された形状
22はコーティング層
23は層間絶縁層
24はシリコン基板
30は縦方向に配列された金属線に施された形状
40はESDテストに用いるプローブ
41はシミュレーションによる電界分布の第1観測層
42はシミュレーションによる電界分布の第2観測層
43はシミュレーションによる電界分布の第3観測層
44はシミュレーションによる電界分布の第4観測層
1 is a sensor electrode 2 is a capacitance detection circuit 3 is an enlarged region 4 in FIG. 2b is a passivation film layer (IMD layer)
11 is a ground electrode 12, a parasitic capacitance 13, a ground wire 20 is a metal wire cross-section 21 for ESD protection, and a shape 22 is applied to a metal wire arranged in a horizontal direction 22 is a coating layer 23, an interlayer insulation layer 24 is a silicon substrate 30 The shape 40 applied to the metal wires arranged in the vertical direction is the probe 41 used for the ESD test, the first observation layer 42 of the electric field distribution by simulation is the second observation layer 43 of the electric field distribution by simulation, and the electric field distribution by the simulation The third observation layer 44 is a fourth observation layer of electric field distribution by simulation.

Claims (4)

絶縁層上に複数のセンサ電極を配列し、該複数のセンサ電極の上面及び側面をパシベーション膜で包み、更に各センサ電極の四辺を金属パターンからなる放電層で囲むようにした静電容量検知型指紋読取りセンサにおいて、上記パシベーション膜はシリコンオキシナイトライドをPECVD法により堆積させて膜厚に形成すると共に、パシベーション膜の上面に上記放電層を設け、更にセンサ電極の四辺を囲む放電層のうち対向状に並ぶ1又は2組の放電層に電界分布の集中部を形成するようにした静電気容量検知型指紋読取りセンサ。   Capacitance detection type in which a plurality of sensor electrodes are arranged on an insulating layer, the upper and side surfaces of the plurality of sensor electrodes are covered with a passivation film, and the four sides of each sensor electrode are surrounded by a discharge layer made of a metal pattern. In the fingerprint reading sensor, the passivation film is formed by depositing silicon oxynitride by PECVD to have a film thickness, the discharge layer is provided on the upper surface of the passivation film, and the discharge layers surrounding the four sides of the sensor electrode are opposed to each other. An electrostatic capacitance detection type fingerprint reading sensor in which a concentrated portion of electric field distribution is formed in one or two sets of discharge layers arranged in a line. センサ電極の四辺を囲む放電層のうち対向状に並ぶ1又は2組の放電層に凹部を形成し、該凹部の対向面に突起を形成して電界分布の集中部を形成する請求項1記載の静電気容量検知型指紋読取りセンサ。 2. A concave portion is formed in one or two sets of discharge layers arranged in a confronting manner among the discharge layers surrounding the four sides of the sensor electrode, and a projection is formed on the opposing surface of the concave portion to form a concentrated portion of electric field distribution. Electrostatic capacitance detection type fingerprint reading sensor. センサ電極の四辺を囲む放電層のうち対向状に並ぶ1組の放電層に凹部を形成し、該凹部の対向面に突起を形成し、他1組の対向状に並ぶ放電層の表面に突起を形成して電界分布の集中部を形成する請求項1記載の静電気容量検知型指紋読取りセンサ。 Concave portions are formed in a pair of discharge layers arranged oppositely in the discharge layers surrounding the four sides of the sensor electrode, protrusions are formed on the opposite surface of the recesses, and protrusions are formed on the surface of the other discharge layer arranged in the opposite direction. The electrostatic capacitance detection type fingerprint reading sensor according to claim 1, wherein a concentration portion of the electric field distribution is formed by forming a portion. 放電層が前記センサ電極の設置される領域外で接地に接続された請求項1記載の静電気容量検知型指紋読取りセンサ。 2. The electrostatic capacitance detection type fingerprint reading sensor according to claim 1, wherein the discharge layer is connected to the ground outside the region where the sensor electrode is installed.
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