JP2012147312A - Semiconductor integrated circuit, amplifier and optical module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, an amplifier and an optical module which can inhibit deterioration in receiving sensitivity due to a power supply noise and decrease in dynamic range.SOLUTION: A semiconductor integrated circuit 101 operates by a supplied first power source voltage. The semiconductor integrated circuit 101 comprises an amplifier circuit 2 for amplifying a received signal, a stabilizing power supply for generating a second power source voltage from the first power source voltage and a power source selection circuit 6 which can select between the first power source voltage and the second power source voltage as a supplying voltage to the amplifier circuit 2 responding to the first power source voltage and the second power source voltage.

Description

  The present invention relates to a semiconductor integrated circuit, an amplifier, and an optical module, and more particularly to a semiconductor integrated circuit, an amplifier, and an optical module that use a stabilized power source.

  In 10G-EPON (10 Gb / s Ethernet (registered trademark) Passive Optical Network), which realizes a communication speed of 10 gigabits / second in public line networks using optical fibers, optical signals from home-side devices are detected by light receiving elements. Then, a TIA (transimpedance amplifier), that is, a preamplifier for amplifying the detection current output from the light receiving element is provided in the station side device.

  As a conventional preamplifier, for example, Japanese Unexamined Patent Application Publication No. 2009-303159 (Patent Document 1) discloses the following configuration. That is, the amplifier includes a first transistor having a first conduction electrode to which a current is input, a control electrode coupled to the first conduction electrode, and a second conduction electrode coupled to a fixed voltage source; A second transistor having a first conduction electrode, a second conduction electrode coupled to the fixed voltage source, a control electrode coupled to the control electrode of the first transistor, and control of the second transistor A feedback resistor coupled to the electrode for feeding back the output of the second transistor to the control electrode of the second transistor; from the first conduction electrode of the first transistor to the control electrode of the second transistor; A variable resistance element for controlling a ratio between a current flowing to the feedback resistor and a current flowing from the first conduction electrode to the second conduction electrode of the first transistor;

JP 2009-303159 A

  In general, a preamplifier that inputs a single-ended signal is vulnerable to power supply noise. As an example of power supply noise countermeasures, for example, in a preamplifier realized by a semiconductor integrated circuit, an external supply voltage is not used as it is, but an LDO (Low Drop Out) regulator or the like is stably provided on the semiconductor integrated circuit. There is a method of supplying a stable voltage from which noise is removed by mounting an integrated power supply.

  As described above, by using the stabilized power supply, it is possible to improve the reception sensitivity of the preamplifier with respect to an input signal of a weak level.

  On the other hand, when the stabilized power supply is used, the supply voltage level to the preamplifier is lowered, so that the headroom of the transistor circuit, that is, the operating voltage range is reduced. For this reason, the reception of the strong level signal becomes weak and the dynamic range of the preamplifier becomes narrow.

  However, Patent Document 1 does not disclose a configuration for solving such a problem.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit, an amplifier, and an optical module that can prevent degradation of reception sensitivity due to power supply noise and prevent a decrease in dynamic range. Is to provide.

  In order to solve the above problems, a semiconductor integrated circuit according to an aspect of the present invention is a semiconductor integrated circuit that operates by a supplied first power supply voltage, and an amplifier circuit for amplifying a received signal; A stabilized power supply for generating a second power supply voltage from the first power supply voltage, and a voltage supplied to the amplifier circuit in response to the first power supply voltage and the second power supply voltage, A power supply selection circuit capable of selecting the first power supply voltage and the second power supply voltage;

  With such a configuration, for example, it is possible to switch between a weak signal receiving power source and a strong signal receiving power source as appropriate, thereby preventing deterioration of reception sensitivity due to power noise and preventing a decrease in dynamic range. be able to.

  Preferably, the semiconductor integrated circuit further detects the level of the signal or the signal amplified by the amplifier circuit, and controls the power source selection circuit to control the power source in accordance with the detected level. A control unit is provided for selecting the power supply voltage according to the magnitude of the absolute value of the power supply voltage from the power supply voltages selectable by the selection circuit.

  With such a configuration, for example, when a weak signal is received, the second power supply voltage having a small absolute value from the stabilized power supply is used, so that a clean voltage from which power supply noise has been removed is supplied to the semiconductor integrated circuit. The reception sensitivity can be prevented from deteriorating. That is, it is possible to improve the noise sensitivity and improve the reception sensitivity. In addition, by generating a stable voltage that does not depend on the fluctuation of the external power supply voltage by the stabilized power supply, a semiconductor integrated circuit that is less dependent on the fluctuation of the power supply voltage can be provided. Further, for example, when a strong signal is received, the first power supply voltage having a large absolute value is used, so that the reduction of the headroom of the transistor circuit due to the introduction of the stabilized power supply can be prevented, and the reduction of the dynamic range can be prevented.

  Preferably, the amplifier circuit receives and amplifies the burst signal, and the semiconductor integrated circuit further detects the level of the head portion of the burst signal or the burst signal amplified by the amplifier circuit, and outputs a detection result. Based on the control of the power supply selection circuit, a control unit is provided for selecting the power supply voltage supplied to the amplifier circuit for each burst signal.

  With such a configuration, it is possible to perform power supply switching at the time of receiving a preamble in the first settling period of the burst signal, that is, the burst signal. For this reason, it is not necessary to switch the power source in the data section, and no reception error occurs.

  More preferably, the control unit has the smallest absolute value at the start of receiving each burst signal in the amplifier circuit from among power supply voltages selectable by the power supply selection circuit as a supply voltage to the amplifier circuit. When the power supply voltage is selected and the detected level is equal to or higher than a predetermined threshold, the power supply voltage having a larger absolute value is selected.

  With such a configuration, it is possible to reduce power consumption during the burst signal standby period. In addition, since the switching of the power supply voltage at the time of preamble reception is performed for a burst signal having a large level, the influence of the transient response at the time of switching the power supply voltage can be reduced.

  More preferably, the semiconductor integrated circuit is provided in a station side device in a passive optical network, amplifies a burst signal received from one or a plurality of home side devices, and the control unit determines reception timing of the burst signal. The information to be shown is acquired, and based on the acquired information, the timing for detecting the level of the head portion of the burst signal is determined.

  With such a configuration, it is possible to grasp the timing at which a burst signal should be detected in a passive optical network and perform appropriate power source selection control based on the level detection result at an appropriate timing.

  Preferably, the power supply selection circuit further uses the first power supply voltage and the second power supply voltage as a voltage to be supplied to the amplifier circuit, and uses the first power supply voltage and the second power supply voltage. A third power supply voltage that is a voltage between the power supply voltages is generated, and the third power supply voltage can be selected.

  With such a configuration, more flexible power source selection control can be performed according to the input signal level. Further, since the configuration in which the power supply voltage is continuously switched can prevent the occurrence of a reception error due to the switching, it is useful for a semiconductor integrated circuit that receives a continuous signal instead of a burst signal.

  Preferably, the semiconductor integrated circuit further includes a differential conversion circuit for adjusting a direct current level of the signal amplified by the amplifier circuit.

  With such a configuration, it is possible to prevent a change in the direct current level of the output signal of the amplifier circuit due to power switching from affecting the subsequent circuit.

  Preferably, the second power supply voltage is generated so as to be supplied to each circuit in the semiconductor integrated circuit only.

  With such a configuration, it is possible to use a stable power supply voltage that is not affected by load fluctuation and noise generation due to the operation of a circuit other than the semiconductor integrated circuit.

  More preferably, the amplifying circuit receives the signal, a first conduction electrode receiving a power supply voltage supplied from the power supply selection circuit, a second conduction electrode coupled to a fixed potential node to which a fixed voltage is supplied, and the signal. A first transistor having a control electrode; and a feedback resistor coupled to the control electrode of the first transistor for returning the output of the first transistor to the control electrode of the first transistor; The control unit further suppresses an amount by which the output of the first transistor is fed back to the control electrode of the first transistor via the feedback resistor when the detected level is equal to or greater than a predetermined threshold. Take control.

  With such a configuration, when a strong signal is received, the negative feedback action by the feedback resistor is weakened, and the collector-emitter voltage of each transistor in the amplifier circuit is expanded by switching from the second power supply voltage to the first power supply voltage. Is possible. Thereby, the dynamic range of the semiconductor integrated circuit can be expanded.

  More preferably, the amplifier circuit further includes a first conduction electrode and a control electrode coupled to the control electrode of the first transistor, and a second conduction electrode coupled to a fixed potential node to which a fixed voltage is supplied. The control unit turns on the second transistor when the detected level is equal to or higher than the predetermined threshold, and the control unit turns on the second transistor when the detected level is lower than the predetermined threshold. The second transistor is turned off.

  With such a configuration, gain switching according to the input signal level becomes possible, and by using this configuration for gain switching, the function of negative feedback by a feedback resistor is weakened with a simple configuration, and a semiconductor integrated circuit Can expand the dynamic range.

  In order to solve the above-described problem, an amplifier according to an aspect of the present invention is an amplifier that operates with a supplied first power supply voltage, an amplifier circuit for amplifying a received signal, and the first circuit described above. The first power supply voltage and the second power supply are supplied to the amplifier circuit by receiving the power supply voltage and the second power supply voltage generated from the first power supply voltage by the stabilized power supply. A power supply selection circuit capable of selecting a voltage.

  With such a configuration, for example, it is possible to switch between a weak signal receiving power source and a strong signal receiving power source as appropriate, thereby preventing deterioration of reception sensitivity due to power noise and preventing a decrease in dynamic range. be able to.

  Preferably, the first power supply voltage is generated for supplying to the amplifier and a circuit other than the amplifier, and the second power supply voltage is generated for supplying to the amplifier.

  With such a configuration, it is possible to use a stable power supply voltage that is not affected by load fluctuations and noise generation due to the operation of circuits other than the amplifier.

  In order to solve the above problems, an optical module according to an aspect of the present invention is an optical module used in a passive optical network including an optical fiber, and includes a light receiving element optically coupled to the optical fiber. A semiconductor integrated circuit that operates with the supplied first power supply voltage and receives a current from the light receiving element as a signal, the semiconductor integrated circuit comprising: an amplifier circuit for amplifying the received signal; and A stabilized power supply for generating a second power supply voltage from the first power supply voltage, and a voltage supplied to the amplifier circuit upon receiving the first power supply voltage and the second power supply voltage, A power supply selection circuit capable of selecting a first power supply voltage and the second power supply voltage;

  With such a configuration, for example, it is possible to switch between a weak signal receiving power source and a strong signal receiving power source as appropriate, thereby preventing deterioration of reception sensitivity due to power noise and preventing a decrease in dynamic range. be able to.

  According to the present invention, it is possible to prevent deterioration of reception sensitivity due to power supply noise and to prevent a decrease in dynamic range.

It is a figure which shows the structure of the optical network which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the station side apparatus which concerns on the 1st Embodiment of this invention. It is a figure which shows schematic structure of the preamplifier which concerns on the 1st Embodiment of this invention, and power supply selection at the time of weak signal reception. It is a figure which shows schematic structure of the preamplifier which concerns on the 1st Embodiment of this invention, and power supply selection at the time of strong signal reception. 1 is a circuit diagram showing a configuration of a preamplifier according to a first embodiment of the present invention. It is a figure which shows the power supply selection operation | movement in the preamplifier which concerns on the 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the preamplifier which concerns on the 2nd Embodiment of this invention. It is a figure which shows the power supply selection operation | movement and gain selection operation | movement in the preamplifier which concerns on the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram showing a state where an N-channel MOS transistor M1 is turned on and an N-channel MOS transistor M11 is turned off in a preamplifier according to a second embodiment of the present invention. It is a figure which shows the DC potential of each node at the time of no signal input in the preamplifier which concerns on the 2nd Embodiment of this invention. It is a figure which shows the DC potential of each node at the time of no signal input in the preamplifier which concerns on the 2nd Embodiment of this invention. It is a figure which shows the relationship between the input electric current and the electric potential of each node in the preamplifier which concerns on the 2nd Embodiment of this invention. It is a figure which shows the relationship between the input electric current and the electric potential of each node in the preamplifier which concerns on the 2nd Embodiment of this invention. It is a figure which shows the relationship between the collector-emitter voltage of NPN transistors N2 and N5, and collector current. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 2mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 2mA. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 3mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 3mA. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 4mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 4mA. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 5mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 2.6V and the input current Iin = 5mA. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 5mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 5mA. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 6mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 6mA. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 7mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 7mA. It is a figure which shows the voltage waveform in the connection nodes ND1 and ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 8mA. It is a figure which shows the eye diagram in the connection node ND2 in the case of the power supply voltage PSV = 3.3V and the input current Iin = 8mA. It is a figure which shows in detail the structure of the power supply selection circuit in the preamplifier which concerns on the 2nd Embodiment of this invention. It is a figure which shows in detail the structure of the power supply selection circuit in the preamplifier which concerns on the 3rd Embodiment of this invention. It is a figure which shows selection of the power supply voltage in the preamplifier which concerns on the 3rd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of an optical network according to the first embodiment of the present invention.

  Referring to FIG. 1, an optical network 501 is, for example, 10G-EPON, and includes home side devices 401A, 401B, 401C, and 401D, a station side device 402, and splitters SP1 and SP2. Home-side devices 401A, 401B, 401C and station-side device 402 are connected via splitters SP1 and SP2 and optical fiber OPTF, and transmit / receive optical signals to / from each other. The home-side device 401D and the station-side device 402 are connected via the splitter SP2 and the optical fiber OPTF, and transmit / receive optical signals to / from each other.

  FIG. 2 is a diagram showing a configuration of the station side apparatus according to the first embodiment of the present invention.

  Referring to FIG. 2, the station side device 402 includes an optical module 301, a PON receiving unit 302, a PON transmitting unit 303, a communication control unit 304, an upper network receiving unit 305, and an upper network transmitting unit 306. Prepare. The optical module 301 includes an optical receiver 51, an optical transmitter 52, a multiplexing / demultiplexing unit 53, and terminals T1 to T3. The optical receiver 51 includes a lens 201, a light receiving element PD, and a preamplifier 101. The optical transmission unit 52 includes a lens 202 and a light emitting element 203. The PON receiving unit 302 includes a post-amplifier 54 and a clock / data recovery unit 55.

  A frame from the upper network 502 is received by the upper network receiving unit 305 and sent to the communication control unit 304. The communication control unit 304 outputs the frame to the terminal T3 of the optical module 301 via the PON transmission unit 303. In the optical transmission unit 52 of the optical module 301, the light emitting element 203 converts a frame that is an electrical signal received from the PON transmission unit 303 into an optical signal, and transmits the optical signal to the home device via the lens 202 and the multiplexing / demultiplexing unit 53. To do.

  On the other hand, the optical signal transmitted from the home side device to the station side device is received by the optical receiving unit 51 via the multiplexing / demultiplexing unit 53. In the optical receiver 51, the light receiving element PD is optically coupled to the optical fiber OPTF via the multiplexing / demultiplexing unit 53 and the lens 201. The light receiving element PD outputs an electrical signal corresponding to the amount of light received from the optical fiber OPTF. The preamplifier 101 amplifies the electrical signal received from the light receiving element PD and outputs the amplified signal to the PON receiving unit 302 via the terminal T1.

  In the PON receiving unit 302, the post-amplifier 54 amplifies the electrical signal received from the pre-amplifier 101 and outputs it to the clock / data recovery unit 55. Clock / data recovery unit 55 recovers the clock and data based on the electrical signal received from post-amplifier 54.

  The communication control unit 304 decodes the data received from the clock / data reproduction unit 55 and restores the data frame and the control frame. The communication control unit 304 transmits the frame to the upper network 502 via the upper network transmission unit 306 based on the restored frames. In addition, the communication control unit 304 manages the start timing and end timing of the burst signal from the home side device and transmits the burst signal so that the optical signal transmitted from each home side device does not compete in time. A window indicating a good period is notified to the home device as a control frame. Since the home side apparatus transmits the burst signal in the allocated window, the communication control unit 304 sends the reset signal RST via the terminal T2 at the start or end of the burst signal based on the managed timing. Output to the preamplifier 101.

  FIG. 3 is a diagram showing a schematic configuration of the preamplifier according to the first embodiment of the present invention and power source selection at the time of weak signal reception.

  Referring to FIG. 3, the preamplifier 101 includes an inverting amplifier circuit 2, a stabilized power supply 5, a power supply selection circuit 6, and a power supply selection control unit 7. The inverting amplifier circuit 2 includes a feedback resistor RF. For example, the preamplifier 101 is included in one semiconductor integrated circuit.

  The preamplifier 101 operates by a power supply voltage Vcc supplied from a power supply (not shown) provided in the station side device 402. The power supply voltage Vcc is generated to supply the preamplifier 101 and circuits other than the preamplifier 101.

  The inverting amplifier circuit 2 amplifies the electrical signal received from the light receiving element PD, such as a burst signal, and outputs the amplified signal to the terminal T1 as the output signal VOUT.

  Stabilized power supply 5 is, for example, an LDO regulator, which generates power supply voltage VST from which noise is removed from power supply voltage Vcc, and controls the level of power supply voltage VST to a predetermined value. Here, regardless of whether the power supply voltage Vcc is a positive voltage or a negative voltage, the absolute value of the power supply voltage VST is smaller than the power supply voltage Vcc. The power supply voltage VST is a power supply voltage dedicated to the preamplifier 101 and is generated to be supplied to each circuit in the preamplifier 101.

  The power supply selection circuit 6 receives the power supply voltage Vcc and the power supply voltage VST, and can select the power supply voltage Vcc and the power supply voltage VST as the power supply voltage PSV supplied to the inverting amplifier circuit 2. More specifically, power supply selection circuit 6 is, for example, a switch, and based on power supply selection signal SWC received from power supply selection control unit 7, power supply voltage Vcc supplied from the outside of preamplifier 101 or a stabilized power supply The power supply voltage VST supplied from 5 is output to the inverting amplifier circuit 2 as the power supply voltage PSV.

  FIG. 4 is a diagram showing a schematic configuration of the preamplifier according to the first embodiment of the present invention and power supply selection at the time of receiving a strong signal.

  Referring to FIGS. 3 and 4, power supply selection control unit 7 detects the level of the signal amplified by inverting amplifier circuit 2. Then, the power source selection control unit 7 controls the power source selection circuit 6 so that the absolute value of each power source voltage is selected from the power source voltages selectable by the power source selection circuit 6 in accordance with the detected level. The voltage supplied to the inverting amplifier circuit 2 is selected according to the magnitude. Specifically, the power supply selection control unit 7 controls the power supply selection circuit 6 to supply the power supply voltage Vcc to the inverting amplifier circuit 2 when the detected level is equal to or higher than a predetermined threshold. When the level is less than the predetermined threshold value, the power supply voltage VST is supplied to the inverting amplifier circuit 2.

  FIG. 5 is a circuit diagram showing the configuration of the preamplifier according to the first embodiment of the present invention.

  Referring to FIG. 5, the preamplifier 101 includes an inverting amplifier circuit 2, a differential conversion circuit 3, an output buffer circuit 4, and a power source selection control unit 7. The inverting amplifier circuit 2 includes NPN transistors N2 and N4, a feedback resistor RF, a resistor RL, and a current source IS1.

  Resistor RL has a first end connected to the collector of NPN transistor N2, and a second end connected to power supply node VN3 to which power supply voltage PSV is supplied.

  NPN transistor N2 has a base connected to the anode of light receiving element PD and the first end of feedback resistor RF, a collector connected to the first end of resistor RL and the base of NPN transistor N4, and a ground voltage. And an emitter connected to fixed potential node VN2.

  NPN transistor N2 receives, as a signal, detection current ipd from light receiving element PD at the base. In addition, NPN transistor N2 receives power supply voltage PSV supplied from power supply selection circuit 6 via resistor RL at the collector.

  NPN transistor N4 has a collector connected to power supply node VN3 and the second end of resistor RL, and an emitter connected to the second end of feedback resistor RF and the first end of current source IS1. NPN transistor N4 receives power supply voltage PSV supplied from power supply selection circuit 6 at the collector.

  The cathode of the light receiving element PD is connected to a fixed potential node VN1 to which a fixed voltage is supplied. A second end of the current source IS1 is connected to the fixed potential node VN2.

  The differential conversion circuit 3 adjusts the DC level of the signal amplified by the inverting amplifier circuit 2. More specifically, the differential conversion circuit 3 converts the output voltage VAMP of the inverting amplifier circuit 2, that is, the emitter voltage of the NPN transistor N4, into a differential signal, and outputs it to the terminal T1 through the output buffer circuit 4 as the output signal VOUT. To do.

  The feedback resistor RF feeds back the output voltage VAMP, that is, the output of the NPN transistor N2, to the base of the NPN transistor N2, thereby forming a negative feedback loop.

  The power source selection control unit 7 generates a power source selection signal SWC based on the output voltage VAMP and outputs it to the power source selection circuit 6.

  FIG. 6 is a diagram showing a power supply selection operation in the preamplifier according to the first embodiment of the present invention.

  Referring to FIG. 6, power supply selection control unit 7 monitors the level of output voltage VAMP to detect the head portion of the burst signal amplified by inverting amplifier circuit 2, that is, the level of preamble PR. The power supply selection control unit 7 controls the power supply selection circuit 6 based on the detection result, thereby selecting the power supply voltage Vcc and the power supply voltage VST to be supplied to the inverting amplifier circuit 2 for each burst signal.

  That is, the power supply selection control unit 7 determines the power supply voltage used by the inverting amplifier circuit 2 when amplifying the portion other than the preamble PR of the burst signal based on the level detection result of the burst signal.

  Further, the power supply selection control unit 7 sets the absolute value at the start of reception of each burst signal in the inverting amplification circuit 2 from the power supply voltages selectable by the power supply selection circuit 6 as the supply voltage PSV to the inverting amplification circuit 2. When the lowest power supply voltage is selected and the detected level is equal to or higher than a predetermined threshold, a power supply voltage having a larger absolute value is selected. Specifically, the power source selection control unit 7 sets the supply voltage PSV to the inverting amplifier circuit 2 as the power source voltage VST when the inverting amplifier circuit 2 starts receiving each burst signal. Then, when the detected level exceeds a predetermined threshold value, the power source selection control unit 7 switches the supply voltage PSV to the inverting amplifier circuit 2 from the power source voltage VST to the power source voltage Vcc.

  More specifically, the power supply selection control unit 7 waits for the input of a burst signal while supplying the power supply voltage VST to the inverting amplifier circuit 2. Then, when the level of the burst signal newly input to the preamplifier 101 is high, the power supply selection control unit 7 switches the supply voltage to the inverting amplifier circuit 2 from the power supply voltage VST to the power supply voltage Vcc.

  On the other hand, when the level of the burst signal newly input to the preamplifier 101 is small, the power supply selection control unit 7 maintains the supply voltage to the inverting amplifier circuit 2 as the power supply voltage VST.

  In addition, the power supply selection control unit 7 acquires information indicating the reception timing of the burst signal, and determines the timing at which the level of the preamble PR of the burst signal should be detected based on the acquired information. Specifically, power supply selection control unit 7 starts burst signal level detection in response to reset signal RST received from communication control unit 304.

  By the way, for example, in a preamplifier realized by a semiconductor integrated circuit, a stabilized power source such as an LDO regulator is mounted on the semiconductor integrated circuit instead of using an external supply voltage as it is, and is supplied externally by the stabilized power source. In a method using a voltage generated from the voltage, the supply voltage level to the preamplifier is lowered, thereby reducing the headroom or operating voltage range of the transistor circuit. For this reason, the reception of the strong level signal becomes weak and the dynamic range of the preamplifier becomes narrow.

  On the other hand, in the preamplifier according to the first embodiment of the present invention, the stabilized power supply 5 generates the power supply voltage VST from the power supply voltage Vcc. The power supply selection circuit 6 receives the power supply voltage Vcc and the power supply voltage VST, and can select the power supply voltage Vcc and the power supply voltage VST as the power supply voltage PSV supplied to the inverting amplifier circuit 2.

  That is, in the preamplifier according to the first embodiment of the present invention, two systems of an external power supply and a stabilized power supply such as an LDO regulator are prepared, and the power supply to be used can be selected according to the input signal strength. .

  With such a configuration, it is possible to switch between a weak signal receiving power source and a strong signal receiving power source as appropriate, thereby preventing deterioration in reception sensitivity due to power noise and preventing a decrease in dynamic range. Can do.

  In the preamplifier according to the first embodiment of the present invention, the power supply selection control unit 7 detects the level of the signal amplified by the inverting amplifier circuit 2. Then, the power source selection control unit 7 controls the power source selection circuit 6 so that the absolute value of each power source voltage is selected from the power source voltages selectable by the power source selection circuit 6 in accordance with the detected level. The voltage supplied to the inverting amplifier circuit 2 is selected according to the magnitude.

  In this way, when a weak signal is received, a power supply voltage having a small absolute value from the stabilized power supply is used, so that a clean voltage from which power supply noise has been removed is supplied to the preamplifier, thereby preventing deterioration of reception sensitivity due to power supply noise. be able to. That is, it is possible to improve the noise sensitivity and improve the reception sensitivity. Further, by generating a stable voltage that does not depend on the fluctuation of the external power supply voltage by the stabilized power supply, it is possible to provide a preamplifier that is less dependent on the fluctuation of the power supply voltage.

  Further, when a strong signal is received, a sufficient signal-to-noise ratio (SN ratio) is obtained, so that power supply noise is not a problem. Conversely, if the headroom of the transistor circuit, that is, the operating voltage range is narrow, the waveform is distorted when a strong signal is received, resulting in a reception error.

  In the preamplifier according to the first embodiment of the present invention, by using a power supply voltage having a large absolute value from an external power supply when a strong signal is received, the headroom of the transistor circuit is reduced by introducing a stabilized power supply. Can prevent the dynamic range from decreasing.

  Further, in the preamplifier according to the first embodiment of the present invention, the power supply selection control unit 7 detects the level of the head portion of the burst signal amplified by the inverting amplifier circuit 2, and based on the detection result By controlling the power supply selection circuit 6, the power supply voltage Vcc and the power supply voltage VST supplied to the inverting amplifier circuit 2 are selected for each burst signal.

  Here, if switching between the external power supply and the stabilized power supply is performed by a switch, for example, a reception error may occur at the time of switching.

  However, in the preamplifier according to the first embodiment of the present invention, by applying the power source selection configuration as described above to the preamplifier that receives the burst signal, the first settling interval of the burst signal, that is, It is possible to switch the power supply when receiving the preamble in the burst signal. For this reason, it is not necessary to switch the power source in the data section, and no reception error occurs.

  Further, in the preamplifier according to the first embodiment of the present invention, the power supply selection control unit 7 selects the supply voltage PSV to the inverting amplifier circuit 2 from the power supply voltages selectable by the power supply selection circuit 6. The power supply voltage having the smallest absolute value is selected at the start of reception of each burst signal in the inverting amplifier circuit 2, and the power supply voltage having a larger absolute value is selected when the detected level is equal to or greater than a predetermined threshold value.

  With such a configuration, it is possible to reduce power consumption during the burst signal standby period. In addition, since the switching of the power supply voltage at the time of preamble reception is performed for a burst signal having a large level, the influence of the transient response at the time of switching the power supply voltage can be reduced.

  Further, the preamplifier according to the first embodiment of the present invention is provided in a station side device in a passive optical network and amplifies a burst signal received from one or a plurality of home side devices. Then, the power supply selection control unit 7 acquires information indicating the reception timing of the burst signal, and determines the timing at which the level of the head portion of the burst signal should be detected based on the acquired information.

  With such a configuration, it is possible to grasp the timing at which a burst signal should be detected in a passive optical network and perform appropriate power source selection control based on the level detection result at an appropriate timing.

  In the preamplifier according to the first embodiment of the present invention, the differential conversion circuit 3 adjusts the DC level of the signal amplified by the inverting amplifier circuit 2.

  With such a configuration, it is possible to prevent a change in the DC level of the output signal of the inverting amplifier circuit 2 due to power supply switching from affecting the subsequent circuit.

  Further, in the preamplifier according to the first embodiment of the present invention, the power supply voltage Vcc is generated for supply to the preamplifier 101 and circuits other than the preamplifier 101. Further, the power supply voltage VST is generated to supply each circuit in the preamplifier 101.

  With such a configuration, it is possible to use a stable power supply voltage that is not affected by load fluctuation and noise generation due to the operation of circuits other than the preamplifier 101.

  In the first embodiment of the present invention, the configuration shown in FIGS. 3, 4 and 5 is applied to the preamplifier 101. However, the present invention is not limited to the preamplifier, and other amplifiers such as a postamplifier. It is also possible to apply to 54.

  Moreover, although the preamplifier according to the first embodiment of the present invention is configured to include the power supply selection control unit 7, the present invention is not limited to this. The power supply selection control unit 7 may be provided outside the preamplifier 101, for example, separately from the semiconductor integrated circuit.

  Moreover, although the preamplifier according to the first embodiment of the present invention is configured to include the stabilized power supply 5, the present invention is not limited to this. The stabilized power supply 5 may be provided outside the preamplifier 101, for example, separately from the semiconductor integrated circuit.

  In the preamplifier according to the first embodiment of the present invention, the power source selection control unit 7 is configured to detect the level of the head portion of the burst signal amplified by the preamplifier. However, the present invention is not limited to this.

  The power supply selection control unit 7 may be configured to detect the level of the leading portion of a burst signal before amplification, for example, a burst signal input to the inverting amplification circuit 2.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
The present embodiment relates to a preamplifier to which a gain selection function is added as compared with the preamplifier according to the first embodiment. The contents other than those described below are the same as those of the preamplifier according to the first embodiment.

  FIG. 7 is a circuit diagram showing a configuration of a preamplifier according to the second embodiment of the present invention.

  Referring to FIG. 7, preamplifier 102 further includes gain selection control unit 1, NPN transistor N1, N-channel MOS (Metal), as compared with the preamplifier according to the first embodiment of the present invention. Oxide Semiconductor) transistors M1 and M11, a capacitor C1, and an inverter INV.

  NPN transistor N1 has a collector and a base connected to the anode of light receiving element PD, and an emitter connected to the drain of N channel MOS transistor M1 and the first end of capacitor C1.

  N-channel MOS transistor M1 has a gate for receiving gain selection signal GSW from gain selection control unit 1, and a source connected to fixed potential node VN2 and the second end of capacitor C1.

  N-channel MOS transistor M11 has a gate connected to the output of inverter INV, a drain connected to fixed potential node VN4 to which a fixed voltage is supplied, and a source connected to the first end of capacitor C1.

  NPN transistor N2 includes a base connected to the base and collector of NPN transistor N1 and the first end of feedback resistor RF, a collector connected to the first end of resistor RL and the base of NPN transistor N4, and fixed potential node VN2 Connected to the emitter.

  N-channel MOS transistor M1 controls the ratio between the current flowing from light receiving element PD to NPN transistor N2 and feedback resistor RF and the current flowing from light receiving element PD to fixed potential node VN2 through the collector and emitter of NPN transistor N1. It is provided for.

  The N-channel MOS transistor M1 also serves to suppress the amount by which the output current of the NPN transistor N2 is fed back to the base of the NPN transistor N2 via the NPN transistor N4 and the feedback resistor RF.

  FIG. 8 is a diagram showing a power supply selection operation and a gain selection operation in the preamplifier according to the second embodiment of the present invention. Operations other than the gain selection are the same as those described in FIG.

  Referring to FIG. 8, gain selection control unit 1 waits for the input of a burst signal while the gain of inverting amplifier circuit 2 is high. Then, when the level of the preamble PR of the burst signal newly input to the preamplifier 101 is large, the gain selection control unit 1 switches the gain of the inverting amplifier circuit 2 to a low state.

  On the other hand, when the level of the preamble PR of the burst signal newly input to the preamplifier 101 is small, the gain selection control unit 1 maintains the high gain of the inverting amplifier circuit 2.

  FIG. 9 is a circuit diagram showing a state where the N-channel MOS transistor M1 is on and the N-channel MOS transistor M11 is off in the preamplifier according to the second embodiment of the present invention.

  The gain selection control unit 1 generates and outputs a gain selection signal GSW based on the output voltage VAMP. More specifically, the gain selection control unit 1 outputs a logic low level gain switching signal GSW at the head of the burst signal and starts receiving the burst signal. Thereafter, an average value of the levels of the output voltage VAMP in a period corresponding to a plurality of bits of the burst signal is calculated.

  Then, when the average value of the output voltage VAMP of the inverting amplifier circuit 2 is less than a predetermined threshold, that is, when the level of the burst signal is large, the gain selection control unit 1 outputs a logic high level gain selection signal GSW. N channel MOS transistor M1 is turned on. As a result, the emitter potential of the NPN transistor N1 decreases and the NPN transistor N1 is turned on. Thereby, bypass current ibps flows from light receiving element PD to fixed potential node VN2 through NPN transistor N1 and N channel MOS transistor M1. That is, the detection current ipd from the light receiving element PD is divided into the input current iin and the bypass current ibps to the inverting amplifier circuit 2.

  At this time, since the emitters of NPN transistors N2 and N1 are respectively coupled to fixed potential node VN2, NPN transistors N2 and N1 operate like a current mirror circuit, and a current corresponding to bypass current ibps is applied to NPN transistor. It flows from the collector of N2 to the emitter. In the present invention, “coupled” is not limited to the state in which the circuit elements are directly connected to each other, but includes cases in which other circuit elements are connected between the circuit elements.

  On the other hand, the gain selection control unit 1 outputs a logic low level gain selection signal GSW when the average value of the output voltage VAMP is equal to or higher than the predetermined threshold value, that is, the level of the burst signal is small. Turn off M1. Then, the emitter potential of NPN transistor N1 rises and NPN transistor N1 is turned off. As a result, the detection current ipd from the light receiving element PD does not flow but flows to the inverting amplifier circuit 2 as the input current iin.

  The gain selection control unit 1 detects the bottom value of the output voltage VAMP in a period corresponding to a plurality of bits of the burst signal at the head of the burst signal, instead of the average value of the level of the output voltage VAMP. Based on this, the logic level of the gain selection signal GSW may be determined.

  Inverter INV inverts the logic level of gain selection signal GSW received from gain selection control unit 1 and outputs the result to the gate of N-channel MOS transistor M11.

  The gain selection control unit 1 receives the reset signal RST from the communication control unit 304 for each burst signal, and turns on the N-channel MOS transistor M11. Thereby, charges are injected from the fixed potential node VN4 into the capacitor C1, so that the emitter potential of the NPN transistor N1 can be quickly raised. Here, the voltage supplied from fixed potential node VN4 only needs to be larger than the base-emitter voltage of NPN transistor N1. However, when the N-channel MOS transistor M1 is turned from OFF to ON, the voltage supplied from the fixed potential node VN4 is the base-emitter voltage of the NPN transistor N1 in order to shorten the time for extracting the charge from the capacitor C1. The voltage is preferably close to.

  The gain selection control unit 1 receives the reset signal RST from the communication control unit 304 for each burst signal, and clears the average value of the output voltage VAMP. The light intensity of the burst signal may vary greatly depending on the home device. By clearing the average value of the output voltage VAMP for each burst signal, the level of the output voltage VAMP is accurately detected for a newly received burst signal without being affected by the burst signal received in the past, A gain selection signal GSW can be generated.

  The gain selection control unit 1 is not limited to the configuration that receives the reset signal RST from the communication control unit 304, but is the configuration that detects the start or end of the burst signal and returns the logic level of the gain selection signal GSW to the initial value. May be. Further, when the station side device 402 receives a continuous signal instead of a burst signal, the reset signal RST may not exist.

  In addition, the power source selection control unit 7 detects the level of the burst signal, for example, in the same manner as the gain selection control unit 1 as described above. The level detection portions of the gain selection control unit 1 and the power source selection control unit 7 may be shared.

  Thus, in the preamplifier according to the second embodiment of the present invention, based on the output voltage VAMP, the shunt ratio of the detection current ipd from the light receiving element PD, that is, the ratio between the input current iin and the bypass current ibps is set. Control. With such a configuration, the bypass current ibps is determined by the ratio to the detection current ipd, and the amount of the bypass current ibps can be increased when a strong signal is input, and the amount of the bypass current ibps can be decreased when a weak signal is input. As a result, it is possible to prevent the inverting amplifier circuit 2 from being saturated and the dynamic range of the preamplifier 101 from becoming narrow, and to prevent the S / N ratio from deteriorating. Further, the shunt ratio of the detection current ipd is a stable value with respect to manufacturing variations and temperature fluctuations determined by the resistance ratio and the transconductance ratio of the transistor, and parameter adjustment is easy.

  In the preamplifier according to the second embodiment of the present invention, the output signal VOUT is monitored, and the N-channel MOS transistor M1 is turned on when the level of the burst signal is high. Accordingly, a part of the detection current ipd from the light receiving element PD is bypassed to the ground as a bypass current ibps, and the input current iin to the inverting amplifier circuit 2 is reduced, so that the gain of the preamplifier 101 is apparently reduced. . With such a configuration, there is no need to switch the resistance value of the feedback resistor, so that the characteristics of the feedback loop are not changed before and after gain switching, and phase margin control can be made unnecessary.

  Here, the inventor of the present application has found that the power supply switching by the power supply selection control unit 7 has a great effect in a configuration including a gain control (AGC) circuit such as the preamplifier 102.

  In summary, in the preamplifier 101, when the power supply voltage VST is switched to the power supply voltage Vcc, negative feedback by the feedback resistor RF works greatly, and the DC potential of each transistor in the inverting amplifier circuit 2 is difficult to change.

  On the other hand, when the AGC circuit is operated in the preamplifier 102, the negative feedback function by the feedback resistor RF is weakened, and the collector of each transistor in the inverting amplifier circuit 2 is switched from the power supply voltage VST to the power supply voltage Vcc. The emitter-to-emitter voltage can be increased. Thereby, the dynamic range of the input current Iin from the light receiving element PD can be expanded.

  Specifically, as described above, the gain selection control unit 1 detects the level of the preamble PR of the burst signal, turns on the NPN transistor N1 when the detected level is equal to or higher than a predetermined threshold, and detects the detected level. Is less than the predetermined threshold value, the NPN transistor N1 is turned off. By the operation of turning on the NPN transistor N1, the amount of the output of the NPN transistor N2 fed back to the base of the NPN transistor N2 via the feedback resistor RF can be suppressed, and the negative feedback function by the feedback resistor RF can be weakened. Can do.

Hereinafter, the verification contents of the above discovery by the inventors will be described in detail.
10 and 11 are diagrams showing DC potentials of the respective nodes when no signal is input in the preamplifier according to the second embodiment of the present invention.

  10 and 11, the preamplifier 102 used in this verification has an NPN transistor N3, an NPN transistor N5, an NPN transistor N5, and a preamplifier 102 shown in FIG. And a constant current source IS2. The NPN transistor N5 corresponds to the constant current source IS1 shown in FIG. The constant current source IS2 supplies a bias current to the NPN transistor N1. The gain selection control unit 1 outputs a control signal to the constant current source IS2, thereby switching between the OFF state and the ON state of the constant current source IS2, that is, whether to stop the current output of the constant current source IS2.

  The NPN transistor N3 is connected in series between the resistor RL and the NPN transistor N2, and the first stage circuit of the preamplifier 102 has a cascode configuration of the NPN transistors N2 and N3.

  Here, description will be made on the assumption that the power supply voltage Vcc = 3.3V and the power supply voltage VST = 2.6V.

  In the preamplifier 102, the resistance value of the resistor RL is 175Ω, the resistance value of the feedback resistor RF is 1 kΩ, and the output current of the constant current source IS2 is 1 mA. Further, the base potential of the NPN transistor N3 is set to 1.5V, and the base potential of the NPN transistor N5 is set to 0.85V.

  Further, a logic high level signal is output from the gain selection control unit 1 to the N channel MOS transistor M1, and the N channel MOS transistor M1 is in the ON state. As a result, the NPN transistor N1 is also turned on. N-channel MOS transistor M11 is in an off state.

  FIG. 10 shows a case where a power supply voltage VST of 2.6 V is supplied as the power supply voltage PSV.

When the collector current of the NPN transistor N2 is Ic2, the potential V1 at the connection node ND1 between the base of the NPN transistor N4, the first end of the resistor RL, and the collector of the NPN transistor N3 is expressed by the following equation.
V1 = Vcc−Ic2 × RL = 2.6 [V] −1.9 [mA] × 175 [Ω] = 2.27 [V]

When the base-emitter voltage of the NPN transistor N4 is Vbe4, the potential V2 at the connection node ND2 between the emitter of the NPN transistor N4, the second end of the feedback resistor RF, and the collector of the NPN transistor N5 is expressed by the following equation. Is done.
V2 = V1-Vbe4 = 2.27 [V] -0.87 [V] = 1.40 [V]

  The base-emitter voltage Vbe4 of the NPN transistor N4 is relatively stable at 0.8V to 0.9V.

  The potential of the input node NDIN, which is a connection node between the base of the NPN transistor N1, the base of the NPN transistor N2, and the first end of the feedback resistor RF is 0.82V, and the collector potential of the NPN transistor N2 is 0.66V. is there.

  FIG. 11 shows a case where a power supply voltage Vcc of 3.3 V is supplied as the power supply voltage PSV.

Referring to FIG. 11, potential V1 at connection node ND1 is represented by the following equation.
V1 = Vcc−Ic2 × RL = 3.3 [V] −2.6 [mA] × 175 [Ω] = 2.85 [V] (B1)

  It should be noted that Ic2 slightly increases as compared with the case shown in FIG. 10 as the base-emitter voltage Vbe2 of the NPN transistor N2 increases.

Further, the potential V2 at the connection node ND2 is expressed by the following equation.
V2 = V1-Vbe4 = 2.85 [V] -0.88 [V] = 1.97 [V] (B2)

  The base potential of the NPN transistor N2 is 0.83V, and the collector potential of the NPN transistor N2 is 0.65V.

  In this way, by switching the power supply voltage PSV from the power supply voltage VST to the power supply voltage and increasing it, the potential V1 at the connection node ND1 and the potential V2 at the connection node ND2 can be increased compared to the case shown in FIG. . The significance of increasing the potential V1 and the potential V2 will be described with reference to FIGS.

  Here, consider a case where N-channel MOS transistor M1 is off, N-channel MOS transistor M11 is on, NPN transistor N1 is off, and constant current source IS2 is off. In this case, the circuit configuration is equivalent to that of the preamplifier 101 having no gain selection function.

  In this case, when the power supply voltage PSV is increased from 2.6V to 3.3V, the potentials of the connection nodes ND1 and ND2 are increased.

Then, bias current Ib from connection node ND2 to input node NDIN increases. The bias current Ib is expressed by the following formula.
Ib = (V2-VIN) / RF

  When the bias current Ib increases, the base current of the NPN transistor N2 increases and the collector current Ic2 of the NPN transistor N2 increases.

  As a result, in the formula (B1), the current Ic2 becomes larger than 2.6 mA and the voltage drop in the resistor RL becomes large, so that the potentials of the connection nodes ND1 and ND2 are lowered. That is, in the inverting amplifier circuit 2, negative feedback acts greatly in the direction in which the potential increase at the connection nodes ND1 and ND2 is suppressed, and the potential at the connection nodes ND1 and ND2 does not increase so much.

  On the other hand, when the N-channel MOS transistor M1 is on, the N-channel MOS transistor M11 is on, the NPN transistor N1 is on, and the constant current source IS2 is on, the same as above Negative feedback works in the inverting amplifier circuit 2. However, the bias current Ib fed back from the connection node ND2 to the input node NDIN via the feedback resistor RF is divided into the base current of the NPN transistor N2, the base current of the NPN transistor N1, and the collector current of the NPN transistor N1. .

  Here, since the collector current of the NPN transistor generally flows more than β times the base current (β> 100), the distribution of the collector current of the NPN transistor N1 among the three divided currents becomes large. That is, the increase in the base current of the NPN transistor N2 due to the bias current Ib is small, and the increase in the collector current Ic2 of the NPN transistor N2 is also small.

  Thus, most of bias current Ib flows to fixed potential node VN2 via NPN transistor N1 and N channel MOS transistor M1. That is, the diode-connected NPN transistor N1 suppresses an increase in the base current of the NPN transistor N2 due to the bias current Ib, so that the effect of negative feedback is reduced, as shown in the equations (B1) and (B2). By switching the power supply voltage PSV to the power supply voltage Vcc, the potentials of the connection nodes ND1 and ND2 can be raised. That is, the potentials of connection nodes ND1 and ND2 that are likely to be saturated due to the change in power supply voltage PSV can be increased.

  In the preamplifier, it is conceivable to reduce the gain by reducing the value of the feedback resistor RF from, for example, 1000Ω to 200Ω at the time of strong signal reception input.

  However, if the feedback resistance RF is reduced, the change of the bias current Ib = (V2−VIN) / RF from the connection node ND2 to the input node NDIN becomes larger, so that the negative feedback function becomes stronger. For this reason, the same effect as that of the preamplifier 102 that diverts the bias current Ib to the input node NDIN using the NPN transistor N1 cannot be obtained.

  12 and 13 are diagrams showing the relationship between the input current and the potential of each node in the preamplifier according to the second embodiment of the present invention. FIG. 12 shows a case where a power supply voltage Vcc of 2.6 V is supplied as the power supply voltage PSV. FIG. 13 shows a case where a power supply voltage Vcc of 3.3 V is supplied as the power supply voltage PSV.

12 and 13, when the mutual conductance of the NPN transistor N1 is gm1 and the mutual conductance of the NPN transistor N2 is gm2, the current-voltage gain Zt is expressed by the following equation from Equation (7) in Patent Document 1. expressed.
Zt = {gm2 × RL / (gm1 × RL + gm2 × RF)} × RF

  Here, the ratio of gm1 and gm2 is determined by the device size ratio, and assuming this ratio is 4: 5, Zt≈180Ω.

  Here, the “transistor size” means a structural size that determines the mutual conductance of the transistor. For example, NPN transistor has emitter width × emitter length, and N-channel MOS transistor has gate width / gate length. When a plurality of transistors are connected in parallel, the size is the sum of the sizes of the transistors connected in parallel.

The potential decrease amount ΔV of the potential V1 and the potential V2 is expressed by the following formula.
ΔV = Iin × Zt (B3)

  From equation (B3), it can be seen that as the input current Iin increases, the potential V1 and the potential V2 decrease, and the collector-emitter voltages of the NPN transistors N2 and N5 decrease.

  FIG. 14 is a diagram showing the relationship between the collector-emitter voltage of NPN transistors N2 and N5 and the collector current. FIG. 14 shows a case where the base-emitter voltages of the NPN transistors N2 and N5 are 0.85V.

  Referring to FIG. 14, when collector-emitter voltage Vce> 1.1V of NPN transistors N2 and N5, collector current Ic shows a constant value regardless of voltage Vce. On the other hand, the collector current Ic decreases when the voltage Vce falls below 1.1V.

Therefore, in order to stably operate the NPN transistors N2 and N5, the potential V1 of the connection node ND1 and the potential V2 of the connection node ND2 are set so as to satisfy the following expression.
V1> 0.66 + 1.1 = 1.76V
V2> 0.0 + 1.1 = 1.1V

  That is, for example, the potentials of connection nodes ND1 and ND2 must be kept at V1> 1.8V and V2> 1.1V so that Vce> 1.1V in NPN transistors N2 and N5.

  Here, from FIG. 12 and FIG. 13, when the input current Iin increases, the connection node ND2 does not satisfy V2> 1.1V first.

  That is, as shown in FIG. 12, the preamplifier 102 can receive an input current of about 2 mA at the maximum when PSV = 2.6V.

  On the other hand, as shown in FIG. 13, the preamplifier 102 can receive an input current of about 5 mA at the maximum when PSV = 3.3V.

  Thus, the dynamic range can be improved by 3 mA by switching the power supply voltage PSV from 2.6 V to 3.3 V.

Here, the improvement amount ΔIin of the dynamic range is a value obtained by dividing the increase ΔV2 of the potential V2 by the slope Zt, that is, the current voltage gain Zt. Further, due to the negative feedback in the preamplifier 102, ΔV2 becomes a value about 10% smaller than ΔVcc. ΔIin is expressed by the following equation.
ΔIin = ΔV2 / Zt <ΔVcc / Zt

  Next, the improvement of the dynamic range by switching the power supply voltage PSV from 2.6V to 3.3V will be described in detail. Here, a case where the signal rate is 10.3125 Gb / s will be described.

  FIG. 15 shows voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 2.6V and input current Iin = 2mA. FIG. 16 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV is 2.6 V and the input current Iin is 2 mA. Here, the eye diagram is a waveform in which the waveform is overwritten in the time direction for each bit.

  FIG. 17 is a diagram showing voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 2.6V and input current Iin = 3 mA. FIG. 18 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV = 2.6V and the input current Iin = 3 mA.

  FIG. 19 is a diagram showing voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 2.6V and input current Iin = 4 mA. FIG. 20 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV = 2.6V and the input current Iin = 4 mA.

  FIG. 21 shows voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 2.6V and input current Iin = 5 mA. FIG. 22 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV = 2.6V and the input current Iin = 5 mA.

  As shown in FIGS. 15, 17, 19, and 21, when the amplitude of the input current Iin is increased from 2 mA toward 5 mA, the amplitude of the voltage waveform at the connection nodes ND1 and ND2 increases. As shown in FIGS. 16, 18, 20, and 22, when the input current Iin = 2mA is exceeded, the eye diagram is distorted in the region of V2 <1.1V.

  FIG. 23 shows voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 3.3V and input current Iin = 5 mA. FIG. 24 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV = 3.3V and the input current Iin = 5 mA.

  FIG. 25 shows voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 3.3V and input current Iin = 6 mA. FIG. 26 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV = 3.3V and the input current Iin = 6 mA.

  FIG. 27 shows voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 3.3V and input current Iin = 7 mA. FIG. 28 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV = 3.3V and the input current Iin = 7 mA.

  FIG. 29 shows voltage waveforms at connection nodes ND1 and ND2 when power supply voltage PSV = 3.3V and input current Iin = 8 mA. FIG. 30 is a diagram showing an eye diagram at the connection node ND2 when the power supply voltage PSV = 3.3V and the input current Iin = 8 mA.

  As shown in FIGS. 23, 25, 27, and 29, when the amplitude of the current input Iin is increased from 5 mA to 8 mA, the amplitude of the voltage waveform at the connection nodes ND1 and ND2 increases. As shown in FIGS. 24, 26, 28, and 30, when the input current Iin exceeds 5 mA, the eye diagram is distorted in the region of V2 <1.1V.

  As described above, by switching the power supply voltage PSV from 2.6 V to 3.3 V, waveform distortion can be reduced in the range of the input current Iin = 5 mA or less, and the dynamic range can be improved.

  FIG. 31 is a diagram showing in detail the configuration of the power supply selection circuit in the preamplifier according to the second embodiment of the present invention.

  Referring to FIG. 31, power supply selection circuit 6 includes P channel MOS transistors P1, P2.

  P-channel MOS transistor P1 has a source for receiving power supply voltage VST, a drain connected to power supply node VN3, and a gate for receiving power supply selection signal SWC from power supply selection control unit 7.

  P-channel MOS transistor P2 has a source for receiving power supply voltage Vcc, a drain connected to power supply node VN3, and a gate for receiving power supply selection signal SWC from power supply selection control unit 7.

  When the level of the burst signal is small, the power supply selection control unit 7 outputs a logic low level signal to the gate of the P channel MOS transistor P1 to turn on the transistor, and the logic high level signal P channel MOS transistor P2 To turn off the transistor. Thereby, the power supply voltage VST is supplied as the power supply voltage PSV. The gain selection control unit 1 outputs a logic low level signal to the gate of the N channel MOS transistor M1 to turn off the transistor, and outputs a logic high level signal to the gate of the N channel MOS transistor M11. Turn on the transistor. As a result, the gain of the preamplifier 102 is increased. At this time, the gain selection control unit 1 outputs the control signal to the constant current source IS2, thereby setting the output current of the constant current source IS2 to 0 mA.

  When the level of the burst signal is large, the power supply selection control section 7 outputs a logic high level signal to the gate of the P channel MOS transistor P1 to turn off the transistor, and the logic low level signal P channel MOS transistor P2 To turn on the transistor. Thereby, the power supply voltage Vcc is supplied as the power supply voltage PSV. The gain selection control unit 1 outputs a logic high level signal to the gate of the N channel MOS transistor M1 to turn on the transistor, and outputs a logic low level signal to the gate of the N channel MOS transistor M11. Turn off the transistor. As a result, the gain of the preamplifier 102 is reduced, and the function of negative feedback in the preamplifier 102 is suppressed. At this time, the gain selection control unit 1 outputs the control signal to the constant current source IS2, thereby setting the output current of the constant current source IS2 to 1 mA.

  As described above, in the preamplifier according to the second embodiment of the present invention, the gain selection control unit 1 detects the level of the burst signal from the light receiving element PD, and the detected level is equal to or higher than a predetermined threshold value. In this case, control is performed to suppress the amount by which the output of the NPN transistor N2 is fed back to the base of the NPN transistor N2 via the feedback resistor RF.

  With such a configuration, when a strong signal is received, the negative feedback function by the feedback resistor RF is weakened, and the collector-emitter voltage of each transistor in the inverting amplifier circuit 2 can be expanded by switching from the power supply voltage VST to the power supply voltage Vcc. It becomes possible. As a result, the dynamic range of the preamplifier can be expanded.

  The preamplifier according to the second embodiment of the present invention has a collector and a base coupled to the base of NPN transistor N2, and an emitter coupled to a fixed potential node VN2 to which a fixed voltage is supplied. An NPN transistor N1 is provided. The gain selection control unit 1 turns on the NPN transistor N1 when the detected level is equal to or higher than the predetermined threshold, and turns off the NPN transistor N1 when the detected level is lower than the predetermined threshold.

  With such a configuration, gain selection according to the input signal level is possible, and by using this configuration for gain selection, the function of negative feedback by the feedback resistor is weakened with a simple configuration, and the preamplifier Can expand the dynamic range.

Although the preamplifier according to the second embodiment of the present invention is configured to include the gain selection control unit 1 and the power supply selection control unit 7, the present invention is not limited to this. At least one of the gain selection control unit 1 and the power supply selection control unit 7 may be provided outside the preamplifier 102, for example, separately from the semiconductor integrated circuit.
The predetermined threshold used when the gain selection control unit 1 selects the gain may be the same value as the predetermined threshold used when the power supply selection control unit 7 selects the power supply voltage, or may be a different value. There may be.

  NPN transistors N1 and N2 may be transistors other than bipolar transistors, and can be replaced with N-channel MOS transistors, for example.

  Since other configurations and operations are the same as those of the preamplifier according to the first embodiment, detailed description thereof will not be repeated here.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Third Embodiment>
The present embodiment relates to a preamplifier in which the configuration of the power supply selection circuit is changed as compared with the preamplifier according to the second embodiment. The contents other than those described below are the same as those of the preamplifier according to the second embodiment.

  In the preamplifier according to the second embodiment of the present invention, the power supply selection circuit 6 is configured to selectively switch between the external power supply and the stabilized power supply, but the present invention is not limited to this. The external power supply and the stabilized power supply may be switched gradually, that is, gradually.

  FIG. 32 is a diagram showing in detail the configuration of the power supply selection circuit in the preamplifier according to the third embodiment of the present invention.

  Referring to FIG. 32, preamplifier 103 includes power supply selection circuit 16 instead of power supply selection circuit 6 as compared with preamplifier 102 according to the second embodiment of the present invention. Instead, NPN transistors N1A and N1B are provided, N channel MOS transistors M1A and M1B are provided instead of the N channel MOS transistor M1, N channel MOS transistors M11A and M11B are provided instead of the N channel MOS transistor M11, and instead of the inverter INV. Are provided with inverters INVA and INVB.

  Power supply selection circuit 16 includes P channel MOS transistors P1A, P1B, P2A, P2B.

  For example, the size of NPN transistors N1A and N1B is ½ of NPN transistor N1. The sizes of the N channel MOS transistors M1A and M1B are ½ of the N channel MOS transistor M1. The size of P channel MOS transistors P1A and P1B is ½ that of P channel MOS transistor P1. The size of P channel MOS transistors P2A and P2B is 1/2 that of P channel MOS transistor P2.

  Each of P channel MOS transistors P1A and P1B has a source for receiving power supply voltage VST, a drain connected to power supply node VN3, and a gate for receiving power supply selection signal SWC from power supply selection control unit 7.

  Each of P-channel MOS transistors P2A and P2B has a source receiving power supply voltage Vcc, a drain connected to power supply node VN3, and a gate receiving power supply selection signal SWC from power supply selection control unit 7.

  In the preamplifier 103, the power supply voltage PSV can be switched in three stages. More specifically, the power supply selection circuit 16 supplies the power supply voltage Vcc to the inverting amplifier circuit 2, supplies the power supply voltage VST, or uses the power supply voltage Vcc and the power supply voltage VST to supply the power supply voltage Vcc. It is possible to select whether to generate the power supply voltage VMID that is a voltage between the power supply voltage VST and supply the power supply voltage VMID. In this case, the power supply selection control unit 7 selects a power supply voltage using two types of threshold values. In the preamplifier 103, the gain can be switched in three stages.

  FIG. 33 is a diagram showing selection of the power supply voltage in the preamplifier according to the third embodiment of the present invention.

  Referring to FIG. 33, when the burst signal level is low, power supply selection control unit 7 outputs a logic low level signal to the gates of P channel MOS transistors P1A and P1B to turn on these transistors. Then, the logic high level signal P channel MOS transistors P2A and P2B are output to the gates to turn off these transistors. Thereby, the power supply voltage VST is supplied as the power supply voltage PSV. The gain selection control unit 1 outputs a logic low level signal to the gates of the N channel MOS transistors M1A and M1B to turn off these transistors, and outputs a logic high level signal to the gates of the N channel MOS transistors M11A and M11B. To turn on these transistors. As a result, the gain of the preamplifier 103 is increased. At this time, the gain selection control unit 1 outputs the control signal to the constant current source IS2, thereby setting the output current of the constant current source IS2 to 0 mA.

  Next, when the level of the burst signal is medium, the power supply selection control unit 7 outputs a logic low level signal to the gates of the P channel MOS transistors P1A and P2A to turn on these transistors, and the logic high level. A level signal is output to the gates of P channel MOS transistors P1B and P2B to turn off these transistors. Thus, voltage VMID having a level between power supply voltage VST and power supply voltage Vcc and having a level corresponding to the on-resistance ratio of P channel MOS transistor P1A and P channel MOS transistor P2A is set as power supply voltage PSV. Supplied. The gain selection control unit 1 outputs a logic high level signal to the gates of the N channel MOS transistors M1A and M11B to turn on these transistors, and outputs a logic low level signal to the gates of the N channel MOS transistors M1B and M11A. To turn off these transistors. As a result, the gain of the preamplifier 103 becomes medium. At this time, the gain selection control unit 1 outputs the control signal to the constant current source IS2, thereby setting the output current of the constant current source IS2 to 0.5 mA.

  Next, when the level of the burst signal is large, the power supply selection control unit 7 outputs a logic high level signal to the gates of the P channel MOS transistors P1A and P1B to turn off these transistors, and the logic low level signal is output. Signals P channel MOS transistors P2A and P2B are output to the gates to turn on these transistors. Thereby, the power supply voltage Vcc is supplied as the power supply voltage PSV. The gain selection control unit 1 outputs a logic high level signal to the gates of the N channel MOS transistors M1A and M1B to turn on these transistors, and outputs a logic low level signal to the gates of the N channel MOS transistors M11A and M11B. To turn off these transistors. As a result, the gain of the preamplifier 103 is reduced and the function of negative feedback in the preamplifier 103 is suppressed. At this time, the gain selection control unit 1 outputs the control signal to the constant current source IS2, thereby setting the output current of the constant current source IS2 to 1.0 mA.

  Thus, in the preamplifier according to the third embodiment of the present invention, the power supply selection circuit 16 further supplies the power supply voltage Vcc and the power supply voltage VST as the power supply voltage PSV supplied to the inverting amplifier circuit 2. The power supply voltage VMID, which is a voltage between the power supply voltage Vcc and the power supply voltage VST, is generated, and the power supply voltage VMID can be selected.

  With such a configuration, more flexible power source selection control can be performed according to the input signal level. Further, since the configuration in which the power supply voltage is continuously switched can prevent the occurrence of a reception error due to the switching, it is useful for an amplifier that receives a continuous signal instead of a burst signal.

  For example, when a weak signal is received, 100% current is supplied from the stabilized power supply 5 to the preamplifier 103, and the supply current from the stabilized power supply 5 is decreased and the supply current from the external power supply is increased as the signal strength increases. Eventually, an operation of supplying 100% current to the preamplifier 103 from the external power supply is also possible.

  Since other configurations and operations are the same as those of the preamplifier according to the second embodiment, detailed description thereof will not be repeated here.

  The above embodiment should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 Gain selection control part 2 Inversion amplifier circuit 3 Differential conversion circuit 4 Output buffer circuit 5 Stabilized power supply 6,16 Power supply selection circuit 7 Power supply selection control part 51 Optical receiving part 52 Optical transmission part 53 Multiplexing / demultiplexing part 54 Post-amplifier 55 Clock / data recovery unit 101, 102, 103 Preamplifier 201, 202 Lens 203 Light emitting element 301 Optical module 302 PON receiving unit 303 PON transmitting unit 304 Communication control unit 305 Upper network receiving unit 306 Upper network transmitting unit 401A, 401B, 401C, 401D Home side device 402 Station side device 501 Optical network C1 Capacitor INV Inverter IS1 Current source N1, N2, N4, N1A, N1B NPN transistors M1, M11, M1A, M1B N-channel MOS transistors P1, P2, P1A, P 1B, P2A, P2B P-channel MOS transistor OPTF Optical fiber SP1, SP2 Splitter T1-T3 terminal PD Photodetector RF feedback resistor RL Resistance

Claims (13)

A semiconductor integrated circuit that operates with a supplied first power supply voltage,
An amplifier circuit for amplifying the received signal;
A stabilized power supply for generating a second power supply voltage from the first power supply voltage;
A power supply selection circuit capable of receiving the first power supply voltage and the second power supply voltage and selecting the first power supply voltage and the second power supply voltage as a voltage to be supplied to the amplifier circuit; A semiconductor integrated circuit comprising: The semiconductor integrated circuit further includes:
By detecting the level of the signal or the signal amplified by the amplifier circuit and controlling the power supply selection circuit, the power supply voltage can be selected from the power supply voltages selectable by the power supply selection circuit according to the level of the detected level. The semiconductor integrated circuit according to claim 1, further comprising a control unit for selecting the power supply voltage according to the magnitude of the absolute value of the power supply voltage. The amplifier circuit receives and amplifies the burst signal,
The semiconductor integrated circuit further includes:
The level of the leading portion of the burst signal or the burst signal amplified by the amplifier circuit is detected, and the power supply selection circuit is controlled based on the detection result to select the power supply voltage to be supplied to the amplifier circuit. The semiconductor integrated circuit according to claim 1, further comprising a control unit for performing each burst signal.   The control unit, as a supply voltage to the amplifier circuit, out of the power supply voltage selectable by the power supply selection circuit, the power supply voltage having the smallest absolute value at the start of reception of each burst signal in the amplifier circuit 4. The semiconductor integrated circuit according to claim 3, wherein when the selected and detected level is equal to or higher than a predetermined threshold, the power supply voltage having a larger absolute value is selected. The semiconductor integrated circuit is provided in a station side device in a passive optical network, amplifies a burst signal received from one or a plurality of home side devices,
The control unit acquires information indicating reception timing of the burst signal, and determines a timing at which a level of a head portion of the burst signal should be detected based on the acquired information. A semiconductor integrated circuit according to 1.   The power supply selection circuit further uses the first power supply voltage and the second power supply voltage as voltages to be supplied to the amplifier circuit, and uses the first power supply voltage and the second power supply voltage. The semiconductor integrated circuit according to claim 1, wherein a third power supply voltage that is a voltage between them is generated, and the third power supply voltage can be selected. The semiconductor integrated circuit further includes:
The semiconductor integrated circuit according to claim 1, further comprising a differential conversion circuit for adjusting a direct current level of the signal amplified by the amplifier circuit.   The semiconductor integrated circuit according to claim 1, wherein the second power supply voltage is generated so as to be supplied only to each circuit in the semiconductor integrated circuit. The amplifier circuit is
A first transistor having a first conduction electrode for receiving a power supply voltage supplied from the power supply selection circuit, a second conduction electrode coupled to a fixed potential node to which a fixed voltage is supplied, and a control electrode for receiving the signal When,
A feedback resistor coupled to the control electrode of the first transistor and for feeding back the output of the first transistor to the control electrode of the first transistor;
The control unit further suppresses an amount by which the output of the first transistor is fed back to the control electrode of the first transistor via the feedback resistor when the detected level is equal to or greater than a predetermined threshold. The semiconductor integrated circuit according to claim 2, wherein control is performed. The amplifier circuit further includes:
A second transistor having a first conduction electrode and a control electrode coupled to the control electrode of the first transistor, and a second conduction electrode coupled to a fixed potential node to which a fixed voltage is supplied;
The control unit turns on the second transistor when the detected level is equal to or higher than the predetermined threshold, and turns off the second transistor when the detected level is lower than the predetermined threshold. Item 10. The semiconductor integrated circuit according to Item 9. An amplifier operating with a supplied first power supply voltage,
An amplifier circuit for amplifying the received signal;
The first power supply voltage and the second power supply voltage generated from the first power supply voltage by the stabilized power supply and supplied to the amplifier circuit are received as the first power supply voltage and the stabilized power supply. An amplifier comprising: a power supply selection circuit capable of selecting a second power supply voltage. The first power supply voltage is generated for supply to the amplifier and a circuit other than the amplifier;
The amplifier of claim 11, wherein the second power supply voltage is generated for supply to the amplifier. An optical module for use in a passive optical network comprising optical fibers,
A light receiving element optically coupled to the optical fiber;
A semiconductor integrated circuit that operates with the supplied first power supply voltage and receives a current from the light receiving element as a signal;
The semiconductor integrated circuit is:
An amplifier circuit for amplifying the received signal;
A stabilized power supply for generating a second power supply voltage from the first power supply voltage;
A power supply selection circuit capable of receiving the first power supply voltage and the second power supply voltage and selecting the first power supply voltage and the second power supply voltage as a voltage to be supplied to the amplifier circuit; Including optical module.

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