JP2012146784A - Semiconductor device, stacked package semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a veer without voids.SOLUTION: A semiconductor device comprises a veer hole 51 penetrating a semiconductor substrate 11, an inorganic insulation film 13 covering an internal surface of the veer hole 51, a coupling layer 15 formed from a coupling agent with one end being coupled to a surface of the inorganic insulation film 13 by dehydration condensation and having a mercapto group or a sulfur-containing aromatic heterocyclic group on another end, a catalyst metal 16 coupled to the mercapto group or the sulfur-containing aromatic heterocyclic group, a seed layer 17 made of an electroless plated metal formed on the catalyst metal 16, and a veer 18a made of an electrolytic plating metal 18 formed on the seed layer 17 to fill the veer hole 51.

Description

  The present invention relates to a semiconductor device, a stacked package semiconductor device, and a method for manufacturing a semiconductor device.

  A stacked package semiconductor device in which a plurality of semiconductor chips on which semiconductor circuits are formed is stacked on top of each other and accommodated in a single package can mount a large number of semiconductor chips, for example, memory chips, in a small mounting area. It is expected to be developed as a packaging technology and is being developed.

  In some stacked package type semiconductor devices, vias penetrating a substrate (semiconductor substrate) of a semiconductor chip are formed, and a semiconductor circuit and a mounting substrate are connected via the vias. In this stacked package type semiconductor device, semiconductor chips are stacked such that vias of semiconductor chips stacked one above the other overlap and are connected to each other. And the semiconductor circuit formed in the semiconductor chip laminated | stacked upward is connected to the wiring of a mounting board | substrate through the via | veer formed in two laminated | stacked semiconductor chips. In this semiconductor device, since it is not necessary to provide a wiring space for connection outside the semiconductor chip, it can be mounted with substantially the same mounting area as the semiconductor chip.

  The above-described via forming process through the semiconductor substrate is performed by first forming a blind hole to be a via hole on the upper surface of the semiconductor substrate, and forming an inorganic insulating film made of, for example, a metal oxide on the inner wall surface of the blind hole. Fill the hole with plated metal. Thereafter, the lower surface of the semiconductor substrate is ground until the plated metal is exposed, and a via penetrating the semiconductor substrate is formed. The filling of the plated metal into the blind hole is usually performed by electrolytic plating using the metal thin film as a seed layer after forming a metal thin film on the inorganic insulating film.

  However, it is desirable that the via be thin in order to reduce the chip area. On the other hand, it is desirable that the semiconductor substrate is thick in order to maintain the strength of the semiconductor substrate. Therefore, the via hole for forming the via is formed as a blind hole having a large aspect ratio, for example, an aspect ratio of 5 or more. Conventionally, the metal thin film used as a seed layer has been formed by vapor deposition or sputtering. However, in vapor deposition or sputtering, it is difficult to uniformly coat the inner wall surface of such a blind hole having a large aspect ratio.

  For this reason, formation of a seed layer by electroless plating has been proposed. However, the metal thin film formed on the inorganic insulating film by electroless plating is weak in adhesion to the insulating film and easily peels off, and a part thereof may be lost. Therefore, it is difficult to form a metal thin film uniformly on the inorganic insulating film. When such a metal thin film is used as a seed and the blind hole is filled with a plating metal, a nest or a void is generated and the reliability of the via is impaired.

  In order to increase the adhesion strength between the insulating film and the metal thin film, a coupling agent to which a functional group having a metal capturing ability is added is bonded to the insulating film, and then the catalytic metal is captured by the functional group. A method of forming a metal thin film made of electroplated metal as a seed layer has been developed.

JP 2009-019312 A JP 2007-0433131 A JP 2000-212754 A JP 2006-016684 A Japanese Patent No. 3670238

  As described above, when the inner wall surface of the blind hole is covered with an inorganic insulating film and a metal thin film is formed on the inorganic insulating film by electroless plating, the adhesive strength between the inorganic insulating film and the metal thin film is weak and uniform. It is difficult to form a metal thin film. When such a metal thin film is used as a seed layer and the blind hole is filled with a plating metal, a nest or a void is likely to occur and the reliability of the via is impaired.

  In order to increase the adhesion strength between the inorganic insulating film and the metal thin film, the inorganic insulating film is modified with a coupling agent to which a functional group having a metal capturing ability is added. Conventionally, various functional groups having a metal-trapping ability, such as mercapto groups, thiol groups, disulfide groups, amino groups, azole groups, or heterocyclic compounds containing sulfur-containing heterocyclic compounds have been proposed.

  However, in a semiconductor device in which a via is formed using a conventional coupling agent, there is an inferior adhesion between the inorganic insulating film and the electroless plating metal thin film, and it is difficult to form a highly reliable via.

  The present invention provides a semiconductor device and a stack having a highly reliable via by forming a seed layer having high adhesion strength with an inorganic insulating film using electroless plating when forming a via penetrating a semiconductor substrate. An object of the present invention is to provide a packaged semiconductor device and a manufacturing method thereof.

  According to one aspect of the present invention for solving the above-mentioned problems, a semiconductor substrate having a semiconductor circuit formed on an upper surface, a via hole penetrating the semiconductor substrate, and an inorganic insulating film covering an inner wall surface of the via hole A coupling layer formed from a coupling agent having one end bonded to the surface of the inorganic insulating film by dehydration condensation and the other end having a mercapto group or a sulfur-containing aromatic heterocyclic group, and the mercapto group or the From a catalyst metal bonded to a sulfur-containing aromatic heterocyclic group, a seed layer made of an electroless plating metal formed on the catalyst metal, and an electroplating metal formed on the seed layer with the via hole embedded therein And a via that is provided as a semiconductor device.

  According to the present invention, a seed layer made of an electroless plating metal having high adhesion strength is formed on an inorganic insulating film made of a metal oxide. For this reason, a highly reliable via without a nest or a void can be formed by embedding a via by electrolytic plating using the seed layer as a seed.

Process sectional drawing of the adhesion test of 1st Embodiment of this invention The figure showing the result of the adhesion test of 1st Embodiment of this invention The figure showing chemical formula of the coupling agent used in 1st Embodiment of this invention Cross-sectional view of the laminated structure of the first embodiment of the present invention Sectional drawing of the manufacturing process of the semiconductor device of 2nd Embodiment of this invention (the 1) Sectional drawing of the manufacturing process of the semiconductor device of 2nd Embodiment of this invention (the 2) Sectional view of manufacturing process of semiconductor device according to second embodiment of the present invention (No. 3) Sectional view of manufacturing process of semiconductor device according to second embodiment of the present invention (Part 4) Sectional drawing of the manufacturing process of the semiconductor device of 2nd Embodiment of this invention (the 5) Sectional view of manufacturing process of semiconductor device according to second embodiment of the present invention (No. 6) Sectional view of manufacturing process of semiconductor device according to second embodiment of the present invention (No. 7) Sectional view of the manufacturing process of the stacked package semiconductor device according to the second embodiment of the present invention (No. 1) Sectional view of manufacturing process of stacked package semiconductor device according to second embodiment of the present invention (No. 2)

  The inventor of the present invention includes, in the coupling agent, the adhesive strength of the electroless plating metal thin film formed on the inorganic insulating film made of the metal oxide through the treatment step with the coupling agent and the addition step of the catalytic metal. The relationship with the functional group having a catalytic metal trapping ability was investigated. As a result, when using a coupling agent containing a mercapto group or a sulfur-containing aromatic heterocyclic group as a functional group capable of capturing a catalytic metal, an electroless plated metal thin film with particularly high adhesion strength to an inorganic insulating film Found that formed. The present invention has been made based on such findings. Hereinafter, the present invention will be described in detail with reference to embodiments.

  1st Embodiment of this invention is for clarifying the relationship between the adhesive strength of the electroplating metal formed through the seed layer on the inorganic insulating film, and the coupling agent used at the time of seed layer formation Related to adhesion test.

  FIG. 1 is a process cross-sectional view of the adhesion test of the first embodiment of the present invention, and shows a sample cross-section of the adhesion test.

  In the adhesion test of the first embodiment, referring to FIG. 1A, first, a semiconductor substrate 11 whose upper surface is polished, for example, a silicon substrate, is prepared, and the upper surface of the semiconductor substrate 11 is anisotropically ionized. Etched. Thereby, fine irregularities are formed on the upper surface of the semiconductor substrate 11 irradiated with the ions 52. This anisotropic ion etching is performed to form unevenness on the upper surface of the semiconductor substrate 11 similar to the inner wall surface of the via hole in the second embodiment to be described later. Therefore, this anisotropic ion etching is preferably performed by the same method as the ion etching for forming the via hole in the second embodiment. Here, reactive ion etching (RIE) using a chlorine-based gas was used. In addition, this unevenness | corrugation functions as an anchor of the various thin films formed on it, and improves the adhesive strength of these thin films.

  Next, referring to FIG. 1B, an inorganic insulating film 13 made of a metal oxide film, such as a silicon oxide film, was formed on the upper surface of the semiconductor substrate 11 by a vapor deposition method (CVD method). Since this vapor deposition method enables deposition at a low temperature, the inorganic insulating film 13 can be formed on a semiconductor substrate on which a semiconductor circuit is formed without damaging the semiconductor circuit. Of course, other formation methods that do not damage the semiconductor circuit may be used.

  Next, referring to FIG. 1C, a coupling layer 15 in which a coupling agent is bonded is formed on the upper surface of the inorganic insulating film 13. The coupling layer 15 was formed by immersing the semiconductor substrate 11 in a 1% strength aqueous coupling agent solution for 1 minute, followed by heat dehydration treatment at 100 ° C. for 30 minutes. The coupling agent used will be described later. The coupling agent adsorbed on the surface (upper surface) of the inorganic insulating film 13 by this heat dehydration treatment is strongly bonded by dehydration condensation of the hydrolyzable group at one end of the coupling agent with the inorganic insulating film 13. 13 is formed as a coupling layer 15 having high adhesion on the upper surface.

  Next, referring to FIG. 1 (d), the semiconductor substrate 11 is a catalyst liquid having a liquid temperature of 55 ° C. containing a colloidal bath or complex salt of palladium chloride and first tin chloride (for example, a product name catalyst of Rohm and Haas Co., Ltd.). It was immersed in Pogitt 44) for 3 minutes. As a result, the catalytic metal 16 is captured by the functional group having a metal capturing ability added to the upper surface side of the coupling agent and bonded to the upper surface of the coupling layer 15.

  Subsequently, the activation process of the catalyst metal 16 was performed. By this treatment, for example, the catalyst adsorbed as a hydrolysis product is converted into an activated catalyst metal 16, for example, active metal palladium. The catalytic metal 16 activated in this way acts as a catalyst in the next electroless plating step, and promotes metal deposition. This activation treatment is performed, for example, by immersing in an aqueous solution of a trade name accelerator 19E manufactured by Rohm and Haas for 6 minutes at room temperature.

  Next, referring to FIG. 1 (e), the semiconductor substrate 11 is immersed in an electroless plating solution (for example, Rohm and Haas brand name Copper Mix) for 20 minutes at room temperature, and a catalyst is formed on the upper surface of the coupling layer 15. A seed layer 17 made of an electroless plated metal thin film having a thickness of 0.5 μm was formed through the metal 16.

  Next, referring to FIG. 1 (f), an electroplating metal 18 made of Cu having a thickness of 30 μm was deposited on the seed layer 17 using electroplating using the seed layer 17 as one electrode. Then, heat treatment was performed at 150 ° C. for 1 hour. Through this process, a sample for the adhesion test shown in FIG.

  Subsequently, the adhesion test of the electroplating metal 18 by the crosscut method (JIS K5600-5-6: ISO2409) was performed.

  In the adhesion test, referring to FIG. 1 (g), first, a groove 53 reaching the semiconductor substrate 11 through the electrolytic plating metal 18, the seed layer 17, the catalyst metal 16, the coupling layer 15 and the inorganic insulating film 13 is formed. Form using a cutter knife. The grooves 53 are formed in a grid pattern, whereby the electroplated metal 18 to the inorganic insulating film 13 are cut into a square pattern with a side length of 1 mm, 10 rows and 10 columns in each direction.

  Next, referring to FIG. 1 (h), an adhesive tape 54 was applied to the upper surface of the electroplated metal 18, and one end of the adhesive tape 54 was pulled off in the vertical direction of the semiconductor substrate. At that time, the number of electrolytic plating metal square patterns remaining on the semiconductor substrate 11 (hereinafter referred to as “remaining number”), in other words, the semiconductor substrate 11 is not peeled off from the semiconductor substrate 11 while being adhered to the adhesive tape 54. The number of square patterns remaining on 11 was counted.

  This adhesion degree test was performed twice for each coupling agent, with respect to the electroplated metal 18 formed using a plurality of types of coupling agents having different functional groups (functional groups having metal capturing ability). In addition, in the determination of the adhesion strength, the case where the remaining number was 100 to 95 was evaluated as ◯, the case where the remaining number was 94 to 80, Δ, and the case where the remaining number was 79 to 0 as ×. Of the two adhesion tests, the result with the smaller remaining number was used for the determination.

  FIG. 2 is a diagram showing the results of the adhesion test of the first embodiment of the present invention, and shows the relationship between the functional group of the coupling agent and the adhesion strength. FIG. 3 is a view showing the chemical formula of the coupling agent used in the first embodiment of the present invention. FIG. 3 (a) shows the coupling agent used in Example 1, and FIG. 2 represents the coupling agent used in Example 2. In addition, FIG.3 (b-1) has illustrated the functional group represented by X in FIG.3 (b). FIG. 4 is a cross-sectional view of the laminated structure according to the first embodiment of the present invention, and shows a cross section of the sample of the above-described adhesion test shown in FIG.

  With reference to FIG. 2, Example 1 of this 1st Embodiment uses the silane coupling agent which contains a mercapto group as a functional group which has metal capture ability as a coupling agent.

In general, the coupling agent has one or more hydrolyzable groups on one end side of the skeleton, and one or more functional groups having a metal capturing ability on the other end side. Referring to FIG. 3 (a), in Example 1, the chemical formula:
(CH ₃ O) ₃ Si (CH) ₂ CH _3-n (SH) _n
A coupling agent represented by (mercaptopropyltrimethoxysilane) (trade name KBM-803, manufactured by Shin-Etsu Silicone Co., Ltd.) was used. That is, the coupling agent used in Example 1 has a skeleton composed of Si (CH) ₂ CH _3-n , three methoxy groups at one end of the skeleton, and n (n = 1 to 2) at the other end. 3) A silane coupling agent having a mercapto group as a thiol group.

  As a coupling agent used in Example 1, a silane coupling agent having a functional group obtained by substituting one or more hydrogens of an alloaromatic cyclic compound or heteroaromatic cyclic compound with a thiol group or a mercapto group Can be used. The skeleton and hydrolyzing group of the coupling agent are the same as those used for ordinary silane coupling agents. Moreover, a titanium coupling agent can also be used similarly to a silane coupling agent.

  Referring to Example 1 of FIG. 2 again, when a coupling agent having a mercapto group was used, the results of the two adhesion tests showed that the remaining number was 97 and 95, respectively, out of 100 square patterns. The remaining ratio of the smaller one was 95%, and it was judged as good (◯).

  In Example 2 of the first embodiment, a silane coupling agent having a sulfur-containing aromatic heterocyclic compound as a functional group having a metal capturing ability was used as the coupling agent. Others are the same as in the first embodiment.

Referring to FIG. 3 (b), in the second embodiment, as a silane coupling agent, the chemical formula _{(CH 3 O) 3 Si (} CH) 2 CH 3 -X
The thiophene derivative represented by these was used. Here, X is a thienyl group shown in FIG. Further, it may be a functional group obtained by substituting one of carbons of the thiazolyl group shown in FIG. 3 (b-2) or the thienyl group shown in FIG. 3 (b-3) with oxygen. The adhesion test of the electroplated metal formed using the coupling agent having these functional groups had similar results.

  That is, referring to Example 2 of FIG. 2, the result of the adhesion test of the electroplated metal formed in Example 2 is that the remaining number of the 100 square patterns is 95, 100, whichever is smaller. The residual ratio of was 95% and judged as good (◯).

  As the coupling agent used in Example 2 of the first embodiment, a silane coupling agent or a titanium coupling agent having a sulfur-containing aromatic heterocyclic compound as a functional group having a metal capturing ability may be used. it can. The functional group having this sulfur-containing aromatic heterocyclic compound is required to bind to the catalytic metal via sulfur and not to inhibit the catalytic ability of the catalytic metal. As such a sulfur-containing aromatic heterocyclic compound, for example, a pentacyclic compound shown in FIGS. 3 (b-1) to (b-3), a compound having a thiazolidinyl group, thiazine and a derivative thereof, or a thiazyl compound is used. Can be used.

  Referring to Comparative Example 1 to Comparative Example 9 in FIG. 2, the results of the adhesion test on the electroplated metal formed using a conventionally used silane coupling agent are shown in Example 1 and Example of the present invention. The results are shown in comparison with the results of 2.

  Comparative Example 1 uses Shin-Etsu Silicon Co., Ltd. trade name KIBM-1003 as a silane coupling agent. This silane coupling agent has vinyl trimethoxysilane as a main component having a vinyl group as a functional group having a metal scavenging ability. It is said. In Comparative Examples 1 to 9, except that the coupling agent was different, an electrolytic plating metal was formed in the same process as Example 1, and an adhesion test under the same conditions was performed.

  As a result of the adhesion test, the number of residuals was 0 and the residual rate was 0% in both tests, and it was determined to be defective (x).

  Comparative Example 2 used Shin-Etsu Silicon Co., Ltd. trade name KBM-403 as a silane coupling agent. This silane coupling agent has an epoxy group as a functional group having a metal scavenging ability, and has a glycidoxypropyltrimethoxysilane. Is the main component.

  As a result of the adhesion test of Comparative Example 2, the number of residuals was 0 and the residual rate was 0% in both tests, and it was judged as defective (x).

  Comparative Example 3 uses Shin-Etsu Silicon Co., Ltd. trade name KBM-1403 as the silane coupling agent. This silane coupling agent has styryl trimethoxysilane as a functional group having a metal scavenging ability as a main component. It is said.

  As a result of the adhesion test of Comparative Example 3, the residual number was 0 and the residual rate was 0% in both tests, and it was determined to be defective (x).

  In Comparative Example 4, trade name KBM-503 manufactured by Shin-Etsu Silicon Co., Ltd. was used as the silane coupling agent. This silane coupling agent was obtained by using methacryloxypropyltrimethoxysilane having a methacryloxy group as a functional group having a metal capturing ability. The main component.

  As a result of the adhesion test of Comparative Example 4, the number of residuals was 0 and the residual rate was 0% in both tests, and it was determined to be defective (x).

  In Comparative Example 5, trade name KBM-5103 of Shin-Etsu Silicon Co., Ltd. was used as the silane coupling agent. This silane coupling agent was prepared by using acryloxypropyltrimethoxysilane having an acryloxy group as a functional group having a metal capturing ability. The main component.

  As a result of the adhesion test of Comparative Example 5, the number of residuals was 0 and the residual rate was 0% in both tests, and it was determined as defective (x).

  In Comparative Example 6, trade name KBM-603 manufactured by Shin-Etsu Silicon Co., Ltd. was used as the silane coupling agent. This silane coupling agent is mainly composed of aminoethylaminopropyltrimethoxysilane having an amino group as a functional group having a metal capturing ability.

  As a result of the two adhesion degree tests of Comparative Example 6, the remaining number was 22 and 30, respectively, and the smaller remaining rate was 22%, which was judged as defective (×).

  In Comparative Example 7, trade name KBM-585 of Shin-Etsu Silicon Co., Ltd. was used as the silane coupling agent. This silane coupling agent was mainly composed of ureidopropyltriethoxysilane having a ureido group as a functional group having a metal capturing ability. As an ingredient.

  As a result of the double adhesion test of Comparative Example 7, the number of remaining parts was 54, and the residual rate was 54%, which were judged as defective (x).

  In Comparative Example 8, trade name KBM-703 of Shin-Etsu Silicon Co., Ltd. was used as a silane coupling agent. This silane coupling agent was prepared by using chloropropyltrimethoxysilane having a chloropropyl group as a functional group having a metal capturing ability. The main component.

  As a result of the two adhesion degree tests in Comparative Example 8, the number of remaining pieces was 54, and the remaining rate was 54%, which was judged as defective (×).

  In Comparative Example 9, a trade name KBM-846 manufactured by Shin-Etsu Silicon Co., Ltd. was used as a silane coupling agent. This silane coupling agent is a polysulfide, and has bis (triethoxysilylpropyl) tetrasulfide as a main component.

  As a result of the adhesion test of Comparative Example 9, the number of residuals was 0 and the residual rate was 0% in both tests, and it was determined to be defective (x).

  As described above, in Examples 1 and 2 using a coupling agent containing a mercapto group or a sulfur-containing aromatic cyclic compound as a functional group having a metal scavenging ability, an electroplated metal with high adhesion strength is formed. It was done. On the other hand, in Adhesion Examples 1 to 8 using a coupling agent that does not contain a mercapto group or a sulfur-containing aromatic cyclic compound as a functional group having a metal capturing ability, sufficient adhesion strength cannot be obtained. The reason for this has not been clarified yet, but the inventors of the present invention consider it as follows.

  Referring to FIG. 4, in the first embodiment, a seed comprising an inorganic insulating film (silicon oxide film) 13, a coupling layer 15, a catalyst metal 16, and an electroless plating metal thin film on a semiconductor substrate 11 (silicon substrate). Layer 17 and electroplated metal 18 are laminated in this order. The skeleton 41 in the coupling layer 15 represents the skeleton 41 of the coupling agent.

  The semiconductor substrate 11 and the inorganic insulating film 13 made of a metal oxide film, such as a silicon oxide film, are bonded through oxygen. The inorganic insulating film 13 and the coupling layer 15 are bonded by a condensation reaction between silanol formed on the surface of the inorganic insulating film 13 and a hydrolysis group of the coupling agent. Further, the catalyst layer 16 and the electroless plating metal (shown as M1 in FIG. 4) are a seed layer 17 made of a thin film, and the seed layer 17 and the electroplating metal 18 (shown as M2 in FIG. 4) are metal bonded. Are combined. These bonds through oxygen, bonds by condensation reaction, and metal bonds are strong and give sufficient adhesion strength. These have the same bonding not only in Examples 1 and 2 but also in Comparative Examples 1 to 9, and have sufficient adhesion strength.

  On the other hand, the coupling layer 15 and the catalyst metal 16 (shown as Mc in FIG. 4) are bonded via sulfur (shown as S in FIG. 4) contained in the functional group in Examples 1 and 2. To do. On the other hand, in Cited Examples 1 to 8, since the functional group does not contain sulfur that reacts with the catalyst metal, such a sulfur-mediated bond does not occur. The metal bond through the sulfur of the mercapto group forms a mercaptide and becomes a strong bond. In addition, the sulfur-containing aromatic cyclic compound easily forms a strong bond with the metal. For this reason, in Examples 1 and 2, the catalytic metal 16 is firmly bonded to the coupling layer 15. As a result, the adhesion strength between the coupling layer and the seed layer 17 made of the electroless plating metal is increased, and the electrolytic plating metal 18 formed on the seed layer 17 also has a high adhesion strength and the present invention. The inventor of

  The second embodiment of the present invention relates to a semiconductor device having vias penetrating a semiconductor substrate and a stacked package semiconductor device formed by stacking the semiconductor devices.

  First, a semiconductor device having a via penetrating a semiconductor substrate will be described with reference to its manufacturing process.

  5 to 11 are cross-sectional views (part 1) to (part 7) of the manufacturing process of the semiconductor device according to the second embodiment of the present invention, showing the cross-section of the semiconductor device in the manufacturing process.

  Referring to FIG. 5A, first, a semiconductor substrate 11, for example, a silicon wafer, on which a plurality of semiconductor circuits 11a are arranged in a matrix on the upper surface is prepared. The upper surface of the semiconductor substrate 11 is covered with an insulating layer 12 made of an interlayer insulating film and a protective film. An electrode pad 11b for external connection is formed in the insulating layer 12 above the semiconductor circuit 11a. The insulating layer 12 has an opening 12a that exposes the upper surface of the electrode pad 11b.

  Next, a resist 61 is applied to the entire upper surface of the semiconductor substrate 11, and the resist 61 is exposed and developed to form an opening 61a that defines a via hole 51 (see FIG. 5B). The opening 61a is preferably formed near the electrode pad 11b from the viewpoint of shortening the wiring length. When the electrode pad 11b is disposed at the peripheral edge of the semiconductor circuit 11a, it is formed along the outer periphery of the semiconductor circuit. Is preferred. It is also possible to provide a region where no circuit is formed inside the semiconductor circuit 11a and to form the opening 61a in the region.

  Next, referring to FIG. 5B, the insulating film 12 and the semiconductor substrate 11 are sequentially etched using reactive ion etching using the resist 61 as a mask, penetrating the insulating layer 12, and the tip is the semiconductor substrate. A via hole 51 consisting of a blind hole reaching the middle of the thickness of 11 is formed. The diameter of the via hole 51 is desirably small in order to reduce the formation area. For example, the diameter of the via hole 51 is 20 μm to 100 μm. The depth is formed as a blind hole having a depth of 200 μm to 400 μm, for example, so as to penetrate the semiconductor substrate 11 of the completed semiconductor device. Here, a via hole 51 having a diameter of 30 μm and a depth of 300 μm was formed. Thereafter, the resist 61 was removed. The step of etching at least the semiconductor substrate 11 of this reactive ion etching was performed under the same conditions (excluding the etching time) as the reactive ion etching used in the first embodiment described above.

  Next, referring to FIG. 6C, an inorganic insulating film 13 made of, for example, a silicon oxide film having a thickness of 5 μm and covering the inner wall surface of the via hole 51 and the upper surface of the semiconductor substrate 11 is formed by using a vapor deposition method. . This inorganic insulating film 13 was formed under the same conditions as the inorganic insulating film 13 of the first embodiment. Thereafter, the inorganic insulating film 13 on the upper surface of the electrode pad 11b was removed, and the upper surface of the electrode pad 11b was exposed.

  Next, referring to FIG. 6D, a sputtered film 14 having a thickness of, for example, 1 μm made of a conductive metal such as Ti or Ni is formed on the upper surface of the semiconductor substrate 11 by sputtering. This sputtered film 14 is used to improve adhesion with a seed layer described later. If the sputtered film 14 is deposited thickly, the sputtered film 14 protrudes and accumulates in the shape of a bowl at the opening of the via hole 51 and closes the opening. Further, the sputtered film 14 is hardly formed on the inner wall surface of the via hole 51 having such a large aspect ratio. For this reason, it is difficult to form a sputtered film that covers the inner wall surface of the via hole 51 by sputtering.

  Next, referring to FIG. 7E, the semiconductor substrate 11 was immersed in a 1% aqueous solution of a coupling agent for 1 minute at room temperature, and then heat-treated at 100 ° C. for 30 minutes. Thereby, the coupling layer 15 made of a coupling agent condensed and bonded to the inorganic insulating film 13 was formed on the inner wall surface of the via hole 51 where the inorganic insulating film 13 was exposed. During the immersion, bubbling and ultrasonic waves were applied to prevent bubbles from remaining in the via hole 51. In the second embodiment, the coupling agent (silane coupling agent having a mercapto group) used in Example 1 of the first embodiment was used.

  Next, referring to FIG. 7 (f), the semiconductor substrate 11 is coated with a catalyst solution having a liquid temperature of 55 ° C. containing a colloidal bath or complex salt of palladium chloride and first tin chloride, as in Example 1 of the first embodiment. For 3 minutes. As a result, the catalytic metal 16 (palladium) is captured by a functional group (here, a mercapto group) having a metal capturing ability of the coupling agent, and is bonded onto the coupling layer 15.

  Subsequently, the activation process of the catalyst metal 16 was performed. This activation treatment was performed by immersing in an aqueous solution of a trade name accelerator 19E manufactured by Rohm and Haas for 6 minutes at room temperature, as in Example 1 of the first embodiment.

  Next, referring to FIG. 8G, the semiconductor substrate 11 was immersed in an electroless plating solution at room temperature for 20 minutes to form a seed layer 17 made of Cu having a thickness of 0.5 μm. The seed layer 17 is formed not only on the catalyst metal 16 but also on a sputtered film made of metal. As a result, the seed layer 17 is formed to extend from the inner surface of the via hole 51 onto the sputtered film 14. The electroless plating solution used was the Rohm and Haas brand name Copper Mix) as in Example 1 of the first embodiment.

  Next, referring to FIG. 8H, electrolytic plating metal 18 made of Cu was deposited on seed layer 17 by immersing semiconductor substrate 11 in an electrolytic plating solution and applying a pulse current to seed layer 17. The electrolytic plating metal 18 is formed so as to completely fill the via hole 51 and to extend flat on the upper surface of the semiconductor substrate 11 with a thickness of 30 μm. Then, heat treatment was performed at 150 ° C. for 1 hour. In this step, a layer made of the via 18a in which the via hole 51 is filled with the electrolytic plating metal 18 and the electrolytic plating metal 18 covering the upper surface of the semiconductor substrate 11 is formed.

  Next, referring to FIG. 9I, the layer made of the electrolytic plating metal 18 formed on the upper surface of the semiconductor substrate 11 is patterned using photolithography. Thereby, the layer made of the electrolytic plating metal 18 is patterned into an electrode (ring) formed on the upper surface of the via 18a in which the via hole 51 is embedded, and a wiring connecting the via 18a and the electrode pad 11b. As will be described later, these electrodes and wirings, for example, according to the difference between the semiconductor devices 10A and 10B (see FIG. 12) constituting the first layer and the second layer of the stacked package, for example. Can be changed to connect with different pads.

  Next, referring to FIG. 9J, an insulating protective film 19 that covers the upper surface of the semiconductor substrate 11, for example, a protective film 19 made of a photosensitive resin is formed. This protective film 19 is formed to protect the upper surface of the semiconductor substrate 11 in the next step. In addition, it may replace with the protective film 19 and you may affix a protective tape on this protective film 19 further.

  Next, referring to FIG. 10 (k), the back surface of the semiconductor substrate 11 was ground to reduce the thickness of the semiconductor substrate 11 to 250 μm. Thereby, the semiconductor substrate 11 is thinned until the via 18a completely penetrates the semiconductor substrate 11, and the via is exposed on the lower surface of the semiconductor substrate 11.

  Next, referring to FIG. 10 (k-2), an opening 19a for exposing the upper surface of the electrolytic plating metal 18 is formed in the protective film 19 immediately above the via 18a. As will be described later with reference to FIG. 12, the opening 19a is an opening 19a for connecting to the semiconductor device 10A stacked on the upper surface, and is selectively opened only directly above the via 18a that needs to be connected. It is preferable. Note that the uppermost semiconductor device 10A on which no other semiconductor device 10A is stacked may not be provided.

  Next, referring to FIG. 11, lands 21 connected to the vias 18 a are formed on the lower surface of the semiconductor substrate 11 immediately below the vias 18 a, and solder balls 22 connected to the lands 21 are further formed. The land 21 and the solder ball serve as a connection electrode 20 for connecting the via 18a to the outside.

  Next, the semiconductor substrate 11 made of a silicon wafer is diced for each semiconductor circuit 11a and divided into individual semiconductor devices 10A and 10B. Through this process, the semiconductor devices 10A and 10B of the second embodiment are manufactured.

  At this time, the semiconductor device 10A shown in FIG. 11 (l) in which the connection electrode 20 is formed on the semiconductor substrate 11 shown in FIG. 10 (k), and the connection electrode 20 on the semiconductor substrate 11 shown in FIG. 10 (k-1). The semiconductor device 10B shown in FIG. The semiconductor devices 10A and 10B differ from each other in the presence or absence of an opening 19a for exposing the electrolytic plating metal 18 on the upper surface, and may have different wiring patterns for connecting the via 18a and the semiconductor circuit 11a.

  Next, these semiconductor devices 10A and 10B were cut longitudinally, and the cross section of 200 vias 18a exposed on the cut surface was observed with a scanning electron microscope. At this time, in the via 18, no peeling or missing of the seed layer 11 was observed, and no nest or void was observed.

  The semiconductor devices 10A and 10B of the second embodiment use a coupling agent having a mercapto group when forming the via 18a. As described in the first embodiment, when such a coupling agent is used, the seed layer 17 having high adhesion strength can be formed. Similarly, even when a coupling agent having a sulfur-containing aromatic heterocyclic group is used, the seed layer 17 having high strength is formed. For this reason, a via hole having a large aspect ratio can be filled with the electroplated metal 18 without forming a nest or a void. Therefore, the via 18a having high reliability is formed.

  In addition, the formation of the via 18a of the second embodiment is a wet process or a process under atmospheric pressure after the formation of the via hole 51, the inorganic insulating film 13 and the sputtered film 14, and is performed in a vacuum. Is not processed. For this reason, the semiconductor devices 10A and 10B can be manufactured through a simple process with a short processing time.

  Next, the stacked package semiconductor device according to the second embodiment will be described with reference to the manufacturing process.

  12 to 13 are sectional views (No. 1) to (No. 2) of the manufacturing process of the stacked package type semiconductor device according to the second embodiment of the present invention, and show the cross section of the stacked package type semiconductor device in the manufacturing process. ing.

  In the manufacture of the stacked package type semiconductor device 10 according to the second embodiment shown in FIG. 13, first, referring to FIG. 12, the above-described semiconductor device 10B and the semiconductor device 10A are arranged in this order from the bottom on the interposer 30. Laminate.

  The interposer 30 has connection electrode pads 35 provided on the upper surface in the same plane arrangement as the vias 18a, and has connection electrodes 34 formed of lands 32 and solder balls 33 provided in a grid shape on the lower surface. . The via 18 a and the connection electrode 34 are connected via a multilayer wiring inside the interposer 30.

  On the interposer 30, the semiconductor device 10B having an opening 19a on the upper surface is placed on the electrode pad 35 of the interposer 30 with the connection electrode 20 of the semiconductor device 10B in contact therewith. Further, the semiconductor device 10A whose upper surface is covered with the protective film 19 is applied on the semiconductor device 10B, and the connection electrode 20 of the semiconductor device 10A is applied to the upper surface of the electroplated metal 18 exposed on the bottom surface of the opening 19 of the semiconductor device 10B. Place it in contact.

  Next, heating is performed to reflow the solder holes 20 of the semiconductor devices 10 </ b> A and 10 </ b> B, thereby forming the stacked assembly 55 in which the semiconductor devices 10 </ b> B and 10 </ b> A are joined via the solder poles 20 on the interposer 30. The loose pole 33 of the interposer 30 may be formed of a solder material that does not melt due to reflow of the solder holes 20 of the semiconductor devices 10A and 10B. Moreover, after forming from the same material and making it reflow simultaneously, you may solidify to a spherical form.

  Next, referring to FIG. 13, the stacked assembly 55 is sealed with the mold resin 31, and the stacked package semiconductor device 10 of the second embodiment is manufactured.

  In the stacked package semiconductor device 10 of the second embodiment, the semiconductor circuit 11a formed in the stacked semiconductor devices 10A and 10B penetrates the semiconductor substrate 11 and is connected to each other via vias 18a. 30 is electrically connected. In this connection, the power supply wiring or signal wiring common to both of the stacked semiconductor devices 10A and 10B, for example, the address signal wiring, is commonly connected to the vias connected up and down. On the other hand, the signal wiring that needs to distinguish between the upper and lower semiconductor devices 10A and 10B, for example, the chip obtaining enable signal wiring, is connected to the via 18a formed at different plane positions, and the electrode pad 11b and the via 18a. The pattern of the wiring formed from the electrolytic plating metal for connecting the electrodes is designed. Of course, if it is not necessary, all the wirings connecting the electrode pads 11b and the vias 18a may have the same pattern in the upper and lower semiconductor devices 10A and 10B. Moreover, it can also laminate | stack on three or more layers.

  By applying the present invention to a semiconductor device having a via penetrating a semiconductor substrate, the reliability of the via can be increased.

DESCRIPTION OF SYMBOLS 10 Stack package type semiconductor device 10A, 10B Semiconductor device 11 Semiconductor substrate 11a Semiconductor circuit 11b Electrode pad 12 Insulating layer 12a, 61a Opening 13 Inorganic insulating film 14 Sputtered film 15 Coupling layer 16 Catalyst metal 17 Seed layer 18 Electroplating metal 18a Via DESCRIPTION OF SYMBOLS 19 Protective film 19a Opening 20, 34 Connection electrode 21, 32 Land 22, 33 Solder ball 30 Interposer 31 Mold resin 35 Electrode pad 41 Skeleton 51 Via hole 52 Ion 53 Groove 54 Adhesive tape 55 Laminated assembly 61 Resist

Claims (8)

A semiconductor substrate having a semiconductor circuit formed on the upper surface;
A via hole penetrating the semiconductor substrate;
An inorganic insulating film covering an inner wall surface of the via hole;
A coupling layer formed from a coupling agent having one end bonded to the surface of the inorganic insulating film by dehydration condensation and the other end having a mercapto group or a sulfur-containing aromatic heterocyclic group;
A catalytic metal bonded to the mercapto group or the sulfur-containing aromatic heterocyclic group;
A seed layer made of electroless plating metal formed on the catalyst metal;
Vias made of electroplated metal filling the via holes and formed on the seed layer;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the coupling agent has a thiol group or a thienyl group at the other end.   The semiconductor device according to claim 1, wherein the coupling agent has a functional group containing a thiazyl compound at the other end.   4. The semiconductor device according to claim 1, further comprising a connection electrode connected to the via at a lower end of the semiconductor substrate.   The first semiconductor device according to claim 1, wherein the second semiconductor device according to claim 4 is characterized in that the connection electrode of the second semiconductor device is the first semiconductor device. A stacked package type semiconductor device, wherein the stacked package type semiconductor device is connected to and stacked on the upper end of the via. Forming a via hole comprising a blind hole on the upper surface of the semiconductor substrate;
Forming an inorganic insulating film covering the inner wall surface of the via hole;
Forming a coupling layer comprising a coupling agent having one end bonded to the surface of the inorganic insulating film by dehydration condensation and the other end having a mercapto group or a sulfur-containing aromatic heterocyclic group;
Next, after binding a catalytic metal to the mercapto group or the sulfur-containing aromatic heterocyclic group, the step of activating the catalytic metal;
Forming a seed layer made of a metal thin film on the activated catalytic metal using electroless plating;
Using electroplating with the seed layer as one electrode, forming a via made of an electroplated metal filling the via hole on the seed layer;
Grinding the lower surface of the semiconductor substrate until the via is exposed, and forming the via penetrating the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 6, wherein the coupling agent has a thiol group or a thienyl group at the other end.   The method for manufacturing a semiconductor device according to claim 6, wherein the coupling agent has a functional group containing a thiazyl compound at the other end.

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