JP2012146725A - Wiring layer formation method and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring layer formation method which can increase the surface flatness of a wiring layer and also eliminates a composition which changes a magnetic field in an extended wiring interval region, and a semiconductor device manufacturing method.SOLUTION: The wiring layer formation method includes a step in which wiring patterns 102 are formed beneath a lower side member; a step in which insulating material layers 103, 106 are formed on top of the wiring patterns 102; a step in which a part of the insulating material layers formed between the wiring patterns is left as an insulating film block 111 and the height of the insulating film block 111 is made higher than that of the insulating material layers except for the insulating film block by executing etching treatment on the insulating material layers; and a step in which the insulating material layers including the insulating film block are polished to form an interlayer film whose surface is flattened. A semiconductor device manufacturing method involves manufacturing at least one of wring layers on a semiconductor substrate by using the wiring layer formation method.

Description

  The present invention relates to a method for forming a wiring layer having a wiring pattern made of a conductive material and an interlayer film made of an insulating material, and a method for manufacturing a semiconductor device having a wiring layer on a semiconductor substrate.

  In recent years, semiconductor devices having a multilayer wiring structure in which a plurality of wiring layers are stacked on a semiconductor substrate provided with a semiconductor integrated circuit have been widely used. In the multilayer wiring structure, when the flatness of the upper surface of the lower wiring layer is low, an abnormality (for example, inclination of the wiring pattern) occurs in the upper wiring layer, or a via (via) of the upper wiring layer is generated. Opening defects (for example, insufficient opening or non-opening) are likely to occur.

  For example, as shown in the vertical cross-sectional view of FIG. 1A, when the wiring 602 is formed on the semiconductor substrate 601 with a narrow interval 609, the insulating material layer 603 formed so as to cover the wiring 602 is formed. The surface 604 is also substantially flat, and as a result, as shown in the longitudinal sectional view of FIG. 1B, the flatness of the surface 604a of the interlayer film 603a formed by CMP (Chemical Mechanical Polishing) of the insulating material layer 603. Is expensive. However, as shown in the vertical cross-sectional view of FIG. 2A, when the interval 709 between the wirings 702 formed on the semiconductor substrate 701 is wide, the insulating material layer 703 formed so as to cover the wirings 702 is formed. As a result, the undulation of the surface 704 becomes large, and as a result, as shown in the longitudinal sectional view of FIG. 2B, the surface 704a of the interlayer film 703a formed by CMP of the insulating material layer 703 has a recess (inclined portion) by dishing. (Or a step) 705 occurs, and the flatness of the surface 704a of the interlayer film 703a is low.

Further, as shown in the plan view of FIG. 3 and the longitudinal sectional view of FIG. 4, a semiconductor device 800 in which a multilayer wiring structure 802 is formed on a semiconductor substrate 801 and an inductor 861 made of a magnetic material is formed thereon, Widely used. The multilayer wiring structure 802 includes, for example, five wiring layers 810, 820, 830, 840, and 850, and each wiring layer includes wirings 812, 822, 832, 842, and 852 made of a conductive material and an insulating material. And interlayer films 813, 823, 833, 843, and 853. When the multilayer wiring structure 802 has an inductor formation region 809 of about 50 μm × 50 μm (= 2500 μm ² ), the recess due to dishing is deepened by 60 nm (= 600 angstroms) for each wiring layer. As a result, the depth of the recesses 815, 825, 835, 845, and 855 of each wiring layer increases by about 60 nm (= 600 angstroms) every time the wiring layers overlap, and as a result, the depth of the recess 855 of the wiring layer 850 is increased. The length is about 0.3 μm (= 300 nm), which is five times 60 nm. Therefore, when a metal pattern (for example, inductor 861) is formed on the wiring layer 850 using a photolithography technique, or when a via is formed in the wiring layer 850, the wiring is caused by defocusing in photolithography. Pattern abnormalities (for example, the inclination of the wiring pattern) and via opening defects (for example, insufficient or unopened) are likely to occur.

  As a countermeasure against this, as shown in FIG. 5A, insulation is formed so as to cover the wiring 902 and the dummy wiring 907 by forming a metal dummy wiring 907 in a wide area 909 of the wiring 902 on the substrate 901. The flatness of the surface 904 of the material layer 903 is increased. As a result, as shown in FIG. 5B, the flatness of the surface 904a of the interlayer film 903a formed by CMP of the insulating material layer 903 is increased. There are proposals (see, for example, Patent Documents 1 and 2).

JP 2002-110908 A JP 2009-94359 A

  However, as proposed in Patent Documents 1 and 2, when an inductive circuit element used for an RF (Radio Frequency) product or the like, for example, an inductor is formed on or near a wiring layer provided with a dummy wiring. Since the dummy wiring changes the magnetic field, there is a problem that the inductive circuit element cannot exhibit desired performance.

  Further, as proposed in Patent Documents 1 and 2, even if measures such as shifting the position of the dummy wiring from right under the inductor or reducing the arrangement density of the dummy wiring are taken, In some cases, the characteristic variation cannot be sufficiently reduced, and the inductive circuit element still cannot exhibit the desired performance.

  Therefore, the present invention has been made to solve the above-described problems of the prior art, and its purpose is to increase the flatness of the surface of the wiring layer even when there is a region where the wiring interval is wide. An object of the present invention is to provide a method for forming a wiring layer that does not have a configuration in which a magnetic field can be easily changed in a region where the wiring interval is wide, and a method for manufacturing a semiconductor device using the method for forming a wiring layer.

  A method for forming a wiring layer according to the present invention is a method for forming a wiring layer having a wiring pattern made of a conductive material and an interlayer film made of an insulating material, wherein the wiring pattern is formed on a surface of a lower member. A step of forming, an insulating material layer formed on the surface of the lower member and the surface of the wiring pattern, and a part of the insulating material layer formed between the wiring patterns is insulated. A step of etching the insulating material layer so as to leave as a film block and to make the height of the insulating film block higher than the height of the insulating material layer other than the insulating film block; and the insulating film block And polishing the insulating material layer to form the interlayer film having a planarized surface.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a step of forming a wiring layer on a semiconductor substrate, and the step of forming the wiring layer uses the method of forming the wiring layer. It is characterized by being executed.

  Another semiconductor device manufacturing method according to the present invention is a semiconductor device manufacturing method including a step of forming a multilayer wiring structure by sequentially stacking a plurality of wiring layers on a semiconductor substrate, wherein the plurality of wirings are formed. The step of forming at least one wiring layer among the layers is performed using the method for forming a wiring layer.

  According to the present invention, it is possible to increase the flatness of the surface of the wiring layer even when there is a region where the wiring interval is wide, and to eliminate the configuration in which the magnetic field is easily changed in the region where the wiring interval is wide. There is an effect that can be.

(A) And (b) is a longitudinal cross-sectional view which shows schematically the formation method (when wiring space | interval is narrow) of the conventional wiring layer, The figure (a) is a wiring pattern and it on a semiconductor substrate. FIG. 2B shows a flat interlayer film formed by polishing the insulating material layer. FIG. (A) And (b) is a longitudinal cross-sectional view which shows the formation method (when wiring space | interval is wide) of the conventional wiring layer roughly, The figure (a) is a wiring pattern and it on a semiconductor substrate. FIG. 2B shows an interlayer film having a dent formed by polishing the insulating material layer. FIG. It is a top view which shows roughly the conventional semiconductor device provided with the inductor on the multilayer wiring structure. It is a longitudinal cross-sectional view which shows roughly the surface which cut | disconnected FIG. 3 by the IV-IV line. (A) And (b) is a longitudinal cross-sectional view which shows schematically the formation method (when wiring space | interval is wide) of the conventional wiring layer using a dummy wiring, The figure (a) is on a semiconductor substrate. A state in which a wiring pattern, a dummy wiring, and an insulating material layer covering them are formed is shown. FIG. 5B shows an interlayer film having a flat surface formed by polishing the insulating material layer. It is a top view which shows roughly an example of the shape and arrangement | positioning of the metal wiring pattern and insulating film block which are formed in the formation method of the wiring layer which concerns on 1st Embodiment, and the manufacturing method of a semiconductor device. It is a schematic longitudinal cross-sectional view which shows the 1st process in the formation method of the wiring layer which concerns on 1st Embodiment, and the manufacturing method of a semiconductor device. It is a schematic longitudinal cross-sectional view which shows the 2nd process in the formation method of the wiring layer which concerns on 1st Embodiment, and the manufacturing method of a semiconductor device. It is a schematic longitudinal cross-sectional view which shows the 3rd process in the formation method of the wiring layer which concerns on 1st Embodiment, and the manufacturing method of a semiconductor device. It is a schematic longitudinal cross-sectional view which shows the 4th process in the formation method of the wiring layer which concerns on 1st Embodiment, and the manufacturing method of a semiconductor device, and shows the surface cut | disconnected by the XX line | wire of the structure of FIG. It is a schematic longitudinal cross-sectional view which shows the 5th process in the formation method of the wiring layer which concerns on 1st Embodiment, and the manufacturing method of a semiconductor device. FIG. 6 is a plan view schematically showing a modification of the shape and arrangement of the metal wiring pattern and insulating film block formed in the wiring layer forming method and semiconductor device manufacturing method according to the first embodiment. It is a schematic longitudinal cross-sectional view which shows the surface which cut | disconnected the structure of FIG. 12 by the XIII-XIII line. It is a schematic longitudinal cross-sectional view which shows the 3rd process in the formation method of the wiring layer which concerns on 2nd Embodiment, and the manufacturing method of a semiconductor device. It is a schematic longitudinal cross-sectional view which shows the 4th process in the formation method of the wiring layer which concerns on 2nd Embodiment, and the manufacturing method of a semiconductor device. It is a schematic longitudinal cross-sectional view of the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is a schematic longitudinal cross-sectional view of the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on 4th Embodiment. It is a schematic longitudinal cross-sectional view of the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on 5th Embodiment.

<< 1 >> First Embodiment << 1-1 >> Method of First Embodiment FIG. 6 illustrates a wiring pattern and insulation formed in a wiring layer forming method and a semiconductor device manufacturing method according to the first embodiment. It is a top view which shows roughly an example of the shape and arrangement | positioning of a membrane block. 7 to 11 are schematic longitudinal sectional views showing the first to fifth steps in the wiring layer forming method and the semiconductor device manufacturing method according to the first embodiment, respectively. FIG. 10 shows a plane obtained by cutting the configuration of FIG. 6 along the line XX.

As shown in FIGS. 6 to 11, the wiring layer forming method according to the first embodiment is based on a wiring pattern 102 made of a conductive material (for example, metal) and an insulating material (for example, SiO ₂ ). This is a method of forming the wiring layer 110 having the interlayer film 103a.

  In addition, the method for manufacturing a semiconductor device according to the first embodiment includes a step of forming a wiring layer on the semiconductor substrate 101, and the step of forming this wiring layer is shown in FIGS. This is performed using a method for forming a wiring layer. The method for manufacturing a semiconductor device according to the first embodiment may further include a step of forming an inductive circuit element, for example, an inductor (such as the inductor 861 shown in FIG. 3) on the wiring layer 110. .

  The method for manufacturing a semiconductor device according to the first embodiment may include a step of forming a multilayer wiring structure by sequentially stacking a plurality of wiring layers on the semiconductor substrate 101 (third, third 4. Also described in the fifth embodiment). In this case, the step of forming at least one wiring layer among the plurality of wiring layers is executed using the wiring layer forming method shown in FIGS. The method for manufacturing a semiconductor device according to the first embodiment includes a step of forming an inductive circuit element, for example, an inductor (such as the inductor 861 shown in FIG. 3) on the uppermost wiring layer of the multilayer wiring structure. Furthermore, you may have.

  Next, a method for forming the wiring layer 110 will be described in detail. In the method for forming a wiring layer according to the first embodiment, first, as shown in FIG. 7, a wiring pattern 102 is formed on the surface of a semiconductor substrate 101 as a lower member by using a photolithography technique or the like. Form. An example of the shape and arrangement of the wiring pattern 102 is shown in the plan view of FIG. 6 and the longitudinal sectional view of FIG. 7, but the method for forming a wiring layer according to the first embodiment can be applied to other wiring patterns. . The method for forming a wiring layer according to the first embodiment is particularly suitable for a wiring layer having a region with a wide wiring interval (for example, the region 109), for example, a vacant region (region without a wiring pattern) of about 500 μm × 500 μm. By applying, the effect of improving the flatness and reducing the influence on the magnetic field can be obtained.

Next, as shown in FIG. 8, an insulating material layer (interlayer film) such as SiO ₂ is formed on the surface of the semiconductor substrate 101 and the surface of the wiring pattern 102 by using, for example, a CVD (Chemical Vapor Deposition) method. The material layer 103 for forming 103a is formed. In the example of FIG. 8, since there is a region 109 having a wide wiring interval, a recess 105 is generated on the surface 104 of the insulating material layer 103 as shown in FIG.

Next, as shown in FIG. 9, an insulating material layer 106 made of an insulating material such as SiO ₂ is formed on the surface 104 of the insulating material layer 103 by using, for example, a CVD method. Since the recess 105 of the insulating material layer 103 exists in the region 109 where the wiring interval is wide, a deep recess 108 is generated on the surface 107 of the insulating material layer 106 as shown in FIG. The thickness of the insulating material layer 103 and the thickness of the insulating material layer 106 may be approximately the same.

  8 and 9 can be a series of steps using the same apparatus. In this case, in the planarization step shown in FIG. 11, the polishing rate and insulation of the insulating material layer 103 are insulated. The polishing rate (the degree of ease of polishing in the CMP process) of the material layer 106 is substantially equal. However, the insulating material layer 103 and the insulating material layer 106 may be formed using different apparatuses or different manufacturing conditions (for example, material components and formation speed). In this case, it is desirable that the polishing rate (degree of ease of polishing) of the insulating material layer 106 be lower (that is, difficult to polish) than the polishing rate (degree of ease of polishing) of the insulating material layer 103. . As the insulating material layer 106, for example, BPSG (Boron Phosphorus Silicon Glass) can be used.

As the insulating material layer 106 that is difficult to be polished, there is a SiO ₂ layer formed by HDP (High Density Plasma-CVD method), and as the insulating material layer 103 that is easily polished, ozone is used in TEOS (tetraethylorthosilicate) -CVD method. There are SiO ₂ layers formed by addition, however, these are merely examples, and the difference in easiness of polishing can also be obtained by differences in manufacturing conditions, materials, and the like.

  Next, a resist pattern is formed using a photolithography technique, and the insulating material layers 103 and 106 are etched. In this step, by etching the insulating material layers 106 and 103, as shown in FIG. 10, a part of the insulating material layer 106 formed between the wiring patterns 102 is changed into a thick insulating film. While remaining as the block 111, the height (top position) of the insulating film block 111 becomes higher than the height (top position) of the insulating material layer 103a or 106 other than the insulating film block 111 (only by the height difference ΔH). Like that. For example, ΔH is desirably 1000 angstroms (= 100 nm) or more. In etching, since a stopper film is not formed, the interlayer film thickness before etching is managed in a database, and etching is performed according to the etching conditions and etching time according to the finished interlayer film thickness, so that an insulation with a desired size can be obtained. A membrane block 111 can be formed.

  Next, by polishing the surface of the insulating film block 111 and the surface of the insulating material layer 103a using CMP, a wiring layer having an interlayer film 103b having a flattened surface 107 as shown in FIG. 110 is formed. Through the above steps, the wiring layer 110 having a high surface flatness is formed on the semiconductor substrate 101.

  You may further have the process of forming another wiring layer on the wiring layer 110 formed as mentioned above, or the process of forming an inductive circuit element, for example, an inductor etc., on the wiring layer 110.

<< 1-2 >> Effects of the First Embodiment As described above, according to the wiring layer forming method or the semiconductor device manufacturing method according to the first embodiment, due to the blocking effect of the insulating film block 111, Since dishing by CMP is suppressed, the flatness of the surface of the wiring layer 110 can be increased even when the region 109 having a wide wiring interval exists.

  In addition, according to the method for forming a wiring layer or the method for manufacturing a semiconductor device according to the first embodiment, since the flatness of the surface of the wiring layer 110 is increased by using the insulating film block 111, the wiring interval is reduced. It is possible to eliminate a magnetic material that easily changes the magnetic field in a wide area. For this reason, even when an inductive circuit element such as an inductor is formed on the region 109 on the wiring layer 110, the inductive circuit element can exhibit a desired performance.

<< 1-3 >> Modification of First Embodiment FIG. 12 shows the shape and arrangement of metal wiring patterns and insulating film blocks formed in the wiring layer forming method and semiconductor device manufacturing method according to the first embodiment. It is a top view which shows roughly the modification of this. FIG. 13 is a schematic longitudinal sectional view showing a surface obtained by cutting the configuration of FIG. 12 along line XIII-XIII. 6 and 10, the case where the insulating film blocks 111 are arranged in 2 columns × 3 rows, that is, 6 is described. However, in order to reduce the influence of dishing, as shown in FIG. One membrane block 112 (for example, width W = 500 μm) may be used. In addition, the number and interval of the insulating film blocks are not limited to the above example, and may be other numbers and arrangements such as 1 column × 3 rows, that is, an arrangement of 3 pieces. Furthermore, the planar shape of the insulating film block is not limited to a quadrangle, and may be other shapes such as a circle, an ellipse, or a polygon other than a rectangle.

<< 2 >> Second Embodiment FIGS. 14 and 15 are schematic longitudinal sectional views showing a third step and a fourth step in a method of forming a wiring layer and a method of manufacturing a semiconductor device according to a second embodiment. is there. The wiring layer forming method and the semiconductor device manufacturing method according to the second embodiment are different in that the two insulating material layers 103 and 106 in the first embodiment are changed to one insulating material layer 203. This is different from the wiring layer forming method and the semiconductor device manufacturing method according to the first embodiment.

The method for forming a wiring layer according to the second embodiment is a method for forming a wiring layer having a wiring pattern 202 made of a conductive material (for example, metal) and an interlayer film made of an insulating material (for example, SiO ₂ ). is there.

  The method for manufacturing a semiconductor device according to the second embodiment includes a step of forming a wiring layer on the semiconductor substrate 201, and the step of forming the wiring layer includes the step of forming the wiring layer according to the second embodiment. This is performed using the forming method. The method for manufacturing a semiconductor device according to the second embodiment may further include a step of forming an inductive circuit element, for example, an inductor (such as the inductor 861 shown in FIG. 3) on the wiring layer 110. .

  In addition, the method for manufacturing a semiconductor device according to the second embodiment may include a step of forming a multilayer wiring structure by sequentially stacking a plurality of wiring layers on the semiconductor substrate 201 (third, third 4. Also described in the fifth embodiment). In this case, the step of forming at least one wiring layer of the plurality of wiring layers is executed using the wiring layer forming method according to the second embodiment. The method for manufacturing a semiconductor device according to the first embodiment includes a step of forming an inductive circuit element, for example, an inductor (such as the inductor 861 shown in FIG. 3) on the uppermost wiring layer of the multilayer wiring structure. Furthermore, you may have.

In the method for forming a wiring layer according to the second embodiment, first, a wiring pattern 202 is formed on the surface of a semiconductor substrate 201 as a lower member, and then, as shown in FIG. An insulating material layer 203 such as SiO ₂ is formed on the surface of 201 and the surface of the wiring pattern 202. In the example of FIG. 14, since there is a region 209 with a wide wiring interval, a dent 205 is formed on the surface 204 of the insulating material layer 203 as shown in FIG.

  Next, a resist pattern is formed using a photolithography technique, and the insulating material layer 203 is etched. In this step, by etching the insulating material layer 203, as shown in FIG. 15, a part of the insulating material layer 203 formed between the wiring patterns 202 is changed into a thick insulating film block 211. In addition, the height (top position) of the insulating film block 211 is made higher than the height (top position) of the insulating material layer 203a other than the insulating film block 211. In etching, since a stopper film is not formed, the interlayer film thickness before etching is managed in a database, and etching is performed according to the etching conditions and etching time according to the finished interlayer film thickness, so that an insulation with a desired size can be obtained. A membrane block 211 can be formed.

  Next, the surface of the insulating film block 211 and the surface of the insulating material layer 203a are polished by CMP to form a wiring layer having an interlayer film whose surface is planarized. Through the above steps, a wiring layer having a high surface flatness is formed on the semiconductor substrate 201. Further, it may further include a step of forming another wiring layer on the wiring layer formed as described above, or a step of forming an inductive circuit element such as an inductor on the wiring layer 110. .

  As described above, according to the wiring layer forming method or the semiconductor device manufacturing method according to the second embodiment, dishing by CMP is suppressed by the blocking effect of the insulating film block 211. Even when the wide region 209 exists, the flatness of the surface of the wiring layer can be increased.

  In addition, according to the method for forming a wiring layer or the method for manufacturing a semiconductor device according to the second embodiment, since the flatness of the surface of the wiring layer is increased by using the insulating film block 211, the wiring interval is wide. It is possible to eliminate a magnetic body that easily changes the magnetic field in the region. For this reason, even when an inductive circuit element, for example, an inductor or the like is formed on the region 209 on the wiring layer, the inductive circuit element can exhibit a desired performance.

  Furthermore, according to the method for forming a wiring layer or the method for manufacturing a semiconductor device according to the second embodiment, the insulating material layer 203 can be formed in one process, so that the number of processing steps can be reduced. it can.

<< 3 >> Third Embodiment FIG. 16 is a schematic longitudinal sectional view of a semiconductor device 300 having a multilayer wiring structure 302 manufactured by a method for manufacturing a semiconductor device according to a third embodiment. As shown in FIG. 16, the multilayer wiring structure 302 includes, for example, five wiring layers 310, 320, 330, 340, and 350, and each wiring layer includes wirings 312, 322, and 332 made of a conductive material. , 342, 352 and interlayer films 313, 323, 333, 343, 353 made of an insulating material. Note that the number of wiring layers is not limited to five. The multilayer wiring structure 302 has an inductor formation region 309 having a size of about 500 μm × 500 μm. In the method for manufacturing a semiconductor device according to the third embodiment, each of the five wiring layers 310, 320, 330, 340, and 350 is the wiring layer described in the first embodiment or the second embodiment. The forming method is used. For this reason, each surface 314,324,334,344,354 of wiring layer 310,320,330,340,350 becomes flat.

  As described above, according to the semiconductor device manufacturing method according to the third embodiment, dishing by CMP is suppressed for all wiring layers due to the blocking effect of the insulating film block, so that the wiring interval is wide. Even when the region 309 exists, the flatness of the surface of the wiring layer 350 which is the uppermost layer can be increased.

  Further, according to the method of manufacturing a semiconductor device according to the third embodiment, since the magnetic material that easily changes the magnetic field is eliminated in the region 309 having a large wiring interval, the semiconductor device is disposed on the region 309 on the wiring layer 350. Inductive circuit elements, such as inductors, can exhibit desired performance.

<< 4 >> Fourth Embodiment FIG. 17 is a schematic vertical cross-sectional view of a semiconductor device 400 having a multilayer wiring structure 402 manufactured by a method for manufacturing a semiconductor device according to a fourth embodiment. As shown in FIG. 17, the multilayer wiring structure 402 includes, for example, five wiring layers 410, 420, 430, 440, and 450, and each wiring layer includes wirings 412, 422, and 432 made of a conductive material. , 442, 452 and interlayer films 413, 423, 433, 443, 453 made of an insulating material. Note that the number of wiring layers is not limited to five. The multilayer wiring structure 402 has an inductor formation region 409 of about 500 μm × 500 μm. In the method for manufacturing a semiconductor device according to the fourth embodiment, a predetermined number (for example, even number) of the five wiring layers 410, 420, 430, 440, and 450 is used. The wiring layer forming method described in the second embodiment is used. Therefore, the surfaces 424 and 444 of the wiring layers 420 and 440 are flat, but the surfaces 414, 434, and 454 of the wiring layers 410, 430, and 450 are recessed in the dents 415, 435, and 455 (depths) by dishing. ΔD = 600 angstroms) occurs. However, since the wiring layer forming method described in the first embodiment or the second embodiment is used for the even-numbered wiring layers, the depths of the recesses 415, 435, and 455 are shallow.

  As described above, according to the method of manufacturing a semiconductor device according to the fourth embodiment, dishing by CMP is suppressed for the predetermined wiring layer due to the blocking effect of the insulating film block. Even when the wide region 409 exists, the flatness of the surface of the wiring layer 450 which is the uppermost layer can be increased.

  Further, according to the method of manufacturing a semiconductor device according to the fourth embodiment, since the magnetic material that easily changes the magnetic field is eliminated in the region 409 with a wide wiring interval, it is disposed on the region 409 on the wiring layer 450. Inductive circuit elements, such as inductors, can exhibit desired performance.

  Furthermore, according to the method of manufacturing a semiconductor device according to the fourth embodiment, the number of wiring layers formed by using the wiring layer forming method described in the first embodiment or the second embodiment is reduced. Therefore, the manufacturing cost can be reduced.

<< 5 >> Fifth Embodiment FIG. 18 is a schematic longitudinal sectional view of a semiconductor device 500 having a multilayer wiring structure 502 manufactured by a method for manufacturing a semiconductor device according to a fifth embodiment. As shown in FIG. 18, the multilayer wiring structure 502 includes, for example, five wiring layers 510, 520, 530, 540, and 550, and each wiring layer includes wirings 512, 522, and 532 made of a conductive material. , 542, 552 and interlayer films 513, 523, 533, 543, 553 made of an insulating material. Note that the number of wiring layers is not limited to five. The multilayer wiring structure 502 has an inductor formation region 509 having a size of about 500 μm × 500 μm. In the method of manufacturing a semiconductor device according to the fifth embodiment, the predetermined layer (for example, every three layers) and the uppermost wiring layer among the five wiring layers 510, 520, 530, 540, and 550 are used. The method for forming a wiring layer described in the first embodiment or the second embodiment is used. For this reason, in the respective surfaces 514, 524, 544 of the wiring layers 510, 520, 540, recesses 515, 525, 545 (depth ΔD = 600 angstroms or depth 2 × ΔD = 1200 angstroms) due to dishing. However, the surfaces 534 and 554 of the wiring layers 530 and 550 become flat.

  As described above, according to the semiconductor device manufacturing method of the fifth embodiment, the dishing by CMP is suppressed for the predetermined wiring layer due to the blocking effect of the insulating film block. Even when the wide region 509 exists, the flatness of the surface of the wiring layer 550 which is the uppermost layer can be increased.

  Further, according to the method of manufacturing a semiconductor device according to the fifth embodiment, the magnetic material that easily varies the magnetic field is eliminated in the region 509 having a wide wiring interval, and therefore, the semiconductor device is disposed on the region 509 on the wiring layer 550. Inductive circuit elements, such as inductors, can exhibit desired performance.

  Furthermore, according to the semiconductor device manufacturing method of the fifth embodiment, the number of wiring layers formed by using the wiring layer forming method described in the first embodiment or the second embodiment is reduced. Therefore, the manufacturing cost can be reduced.

300, 400, 500 semiconductor device,
101, 201, 301, 401, 501 semiconductor substrate,
102, 202, 312, 322, 332, 342, 352, 412, 422, 432, 442, 452, 512, 522, 532, 542, 552 wiring pattern (wiring),
103, 103a, 106, 203 insulating material layer,
103b interlayer film,
313,323,333,343,353,413,423,433,443,453,513,523,533,543,553 interlayer film,
104, 107, 204, 314, 324, 334, 344, 354, 414, 424, 434, 444, 454, 514, 524, 534, 544, 554, the surface of the interlayer film or insulating material layer,
105, 108, 208 Indentation of the insulating material layer,
109, 209, 309, 409, 509 Wide area of wiring interval,
110, 310, 320, 330, 340, 350, 410, 420, 430, 440, 450, 510, 520, 530, 540, 550 wiring layer,
111, 211 Insulating film block.

Claims (14)

A method of forming a wiring layer having a wiring pattern made of a conductive material and an interlayer film made of an insulating material,
Forming the wiring pattern on the surface of the lower member;
Forming an insulating material layer on the surface of the lower member and on the surface of the wiring pattern;
A part of the insulating material layer formed between the wiring patterns is left as an insulating film block, and the height of the insulating film block is set higher than the height of the insulating material layer other than the insulating film block. And a step of etching the insulating material layer,
Polishing the insulating material layer including the insulating film block to form the interlayer film having a planarized surface. A method for forming a wiring layer, comprising: The step of forming the insulating material layer includes
Forming a first insulating material layer on the surface of the lower member and on the surface of the wiring pattern;
The method for forming a wiring layer according to claim 1, further comprising: forming a second insulating material layer on the first insulating material layer. The step of forming the first insulating material layer and the step of forming the second insulating material layer are a series of steps executed in the same processing apparatus,
In the planarization step, the first insulating material layer and the second insulating material layer are formed so that the polishing rate of the second insulating material layer is equal to the polishing rate of the first insulating material layer. The wiring layer forming method according to claim 2, wherein the wiring layer is formed. The step of forming the first insulating material layer and the step of forming the second insulating material layer are separate steps,
In the planarization step, the first insulating material layer and the second insulating material layer are formed so that the polishing rate of the second insulating material layer is lower than the polishing rate of the first insulating material layer. The wiring layer forming method according to claim 2, wherein the wiring layer is formed.   5. The method for forming a wiring layer according to claim 1, wherein the wiring pattern is a metal pattern. The interlayer film, method of forming a wiring layer according to any one of claims 1 to 5, characterized in that the SiO ₂ film.   The method for forming a wiring layer according to claim 1, wherein the lower member is a semiconductor substrate.   The method for forming a wiring layer according to claim 1, wherein the lower member is another wiring layer formed in advance. A method of manufacturing a semiconductor device including a step of forming a wiring layer on a semiconductor substrate,
The method for forming a wiring layer is performed using the method for forming a wiring layer according to any one of claims 1 to 7.   The method for manufacturing a semiconductor device according to claim 9, further comprising forming an inductive circuit element on the wiring layer. A method of manufacturing a semiconductor device comprising a step of forming a multilayer wiring structure by sequentially laminating a plurality of wiring layers on a semiconductor substrate,
The step of forming at least one wiring layer of the plurality of wiring layers is executed using the method for forming a wiring layer according to claim 1. Device manufacturing method. Each of the process of forming these wiring layers is performed using the formation method of the wiring layer of any one of Claim 1-8. The semiconductor of Claim 11 characterized by the above-mentioned. Device manufacturing method. The step of forming the uppermost wiring layer among the plurality of wiring layers is performed using the method for forming a wiring layer according to any one of claims 1 to 7. A method for manufacturing a semiconductor device according to claim 11.   14. The semiconductor device according to claim 11, further comprising a step of forming an inductive circuit element on a wiring layer positioned at an uppermost position among the plurality of wiring layers. Manufacturing method.

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