JP2012146254A - Memory backup device and programmable controller having memory backup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory backup device and a programmable controller having the memory backup device which accurately detects the voltage drop of a battery before the battery becomes completely exhausted and urges a user to replace the battery, thereby preventing the battery backup operation of a memory from being interrupted because of the exhaustion of the battery.SOLUTION: A memory backup device comprises: backup continuation means for continuing backup using a battery for a predetermined period after a main power supply is turned on; and battery voltage detection means for detecting a battery voltage during the continuation period, comparing it with a predetermined threshold value, and outputting the comparison result.

Description

  The present invention relates to a memory backup device for protecting memory data and a programmable controller having the memory backup device.

  FIG. 3 is a block diagram of a conventional memory backup circuit. In the figure, reference numeral 1 denotes a module power source that generates a module voltage S2. Reference numeral 2 denotes a volatile memory that holds data. When the module power supply 1 is in an off state, a voltage is supplied by a battery 5 described later to back up the data. Reference numeral 2 a denotes a voltage (memory power supply voltage) supplied to the memory 2.

  Reference numeral 5 denotes a battery for backing up the memory 2 and outputs 5a as its output voltage. A battery voltage detection circuit 6 monitors the output voltage (battery voltage 5a) of the battery 5. The battery voltage detection circuit 6 monitors the battery voltage 5a using the lower limit voltage necessary for backing up the memory 2 as the threshold voltage Eth. When the battery voltage 5a becomes lower than the threshold voltage Eth, the battery voltage detection circuit 6 outputs the battery voltage detection circuit output 6a and gives it to the display circuit 7. In addition, the battery voltage detection circuit 6 receives the battery voltage detection circuit output 6a and outputs the display circuit output 7a, issues a warning and prompts the user to replace the battery.

Reference numeral 8 denotes a reset cancellation circuit that monitors the voltage of the module voltage S2, and outputs a reset cancellation signal 8a when the module voltage S2 reaches a predetermined voltage.
Here, the characteristics of the battery will be described. The battery can be regarded as a series connection of an electromotive force source that outputs a substantially constant electromotive force and an internal impedance. Although this electromotive force decreases very little as the battery is consumed, it does not change so much, and reaches the end of the battery life and rapidly decreases. On the other hand, the internal impedance has a property of gradually increasing following the degree of consumption of the battery and increasing more rapidly when reaching the end of the battery life.

  FIG. 4 is a time chart for explaining the operation of the circuit of FIG. The module voltage S2, battery voltage 5a, memory power supply voltage 2a, reset release signal 8a, battery voltage detection circuit output 6a, and display circuit output are arranged in the order of array numbers 1), 2). 7a.

  The operation of the circuit of FIG. 3 will be described with reference to FIG. In FIG. 4, E0 is the output voltage (no-load voltage) of the battery 5 when the module voltage S2 is on. At this time, since the voltage to the memory 2 is supplied from the module power supply 1, the battery 5 is in an unloaded state when viewed from the battery 5, and E 0 is a voltage corresponding to the electromotive force of the battery 5 described above.

  E1 is the output voltage of the battery 5 when the battery 5 backs up the memory 2 (sections t0 to t1). That is, E1 is the output voltage (actual load voltage) of the battery 5 in a state where the module voltage S2 is off and the battery 5 is loaded.

  When the external power supply (not shown) is cut off at time t0, the module power supply 1 is turned off. For this reason, the diode 4 is forward biased (ON), the diode 3 is reverse biased (OFF), and the backup battery 5 starts energization to the memory 2, that is, memory backup. At this time, the diode 3 prevents the current of the battery 5 from flowing through the line of the module voltage S2. Thus, the battery voltage 5a shifts from the no-load voltage E0 to the actual load voltage E1 when the module voltage S2 is turned off.

  When the external power supply is turned on at time t1, the module power supply 1 is turned on. When the module power supply 1 is turned on, the output voltage S2 is set higher than the voltage 5a of the battery 5, so that the diode 3 is forward biased (on) and the diode 4 is reverse biased (off). A voltage is supplied from the module voltage S2 line. For this reason, the backup battery 5 is disconnected from the module voltage S2 line and the memory 2. Thus, when the module power supply 1 is turned on, the battery voltage 5a shifts from the actual load voltage E1 to the no-load voltage E0.

  At time t1, the reset release circuit 8 outputs a reset release signal 8a when the module voltage S2 reaches a predetermined voltage. The reset release signal 8a thus output is given to the battery voltage detection circuit 6. The battery voltage detection circuit 6 detects the battery voltage 5a after a predetermined time has elapsed from the rising timing of the reset release signal 8a. That is, the reset release signal 8a is output at the timing of t1, and the battery voltage 5a is detected at the timing of tc after a predetermined time has elapsed since then.

  The battery voltage detection circuit 6 compares the battery voltage 5a with the threshold voltage Eth at the timing tc. If the battery voltage 5a is less than the threshold voltage Eth, the battery voltage detection circuit output 6a indicated by the broken line is given to the display circuit 7 to output the display circuit output 7a (broken line) from the display circuit 7, and the battery voltage 5a is the threshold voltage. If it is equal to or higher than Eth, the battery voltage detection circuit output 6a and the display circuit output 7a are not output as indicated by the solid line. The threshold voltage Eth is defined as a value that does not fall below the lower limit voltage for backing up the memory 2. Specifically, when the lower limit voltage for backing up the memory 2 is 1V, it is desirable not to fall below the voltage obtained by adding the forward voltage of the diode 4 to 1V.

  In such a conventional example, the module power supply 1 is turned on, the supply voltage to the memory 2 is supplied from the module power supply 1 side, and the voltage of the backup battery 5 is detected thereafter. That is, in the above-described conventional example, the voltage (actual load voltage E1) when the backup battery backs up the memory 2 is not detected, and the voltage is detected at the timing when the battery 5 is in a no-load state. Therefore, the actual load voltage E1 when the memory 2 is backed up cannot be detected accurately.

  If the battery voltage is detected and the alarm is output in such a no-load state as described above, the battery is consumed significantly, and the battery voltage when the memory is loaded on this battery, that is, the actual load Naturally, the voltage E1 is lower than the threshold voltage Eth, and there is a high possibility that the battery has already been in a state where the memory cannot be backed up. Therefore, in the conventional battery voltage detection method described above, there is a high possibility that an alarm will not be output in spite of running out of the battery, or the output of the alarm will be delayed and the battery will not be replaced in time, and the battery will run out.

  In order to solve such a problem, the CPU temporarily switches the power supply line of the memory from the main power supply side to the battery side, creates an actual load state of the battery, and detects the battery voltage at that time. A battery backup circuit is disclosed (for example, Patent Document 1).

JP-A-2-12316

  However, the battery has a characteristic of outputting a voltage higher than the voltage immediately before the interruption for a while when the continuous use state is temporarily suspended and the use is started again. For this reason, when the backup battery in the memory backup state is brought into a no-load state and then loaded again in the backup state, the battery voltage 5a is slightly stable from the no-load voltage E0 to the actual load voltage E1, but is stable. There is a problem that it takes some time to reach (fall) the true actual load voltage E1.

  For this reason, in the invention described in Patent Document 1, the battery voltage slightly higher than the stable true actual load voltage E1 is measured, and the measured battery life is actually almost exhausted when there is still life expectancy. There is a possibility that the detection of battery consumption will be delayed and the battery will run out. Furthermore, in the invention described in Patent Document 1, the entire apparatus or a part of the function must be interrupted in order to temporarily switch from the normal read / write operation state when the main power is on to the battery backup state. There was also a problem.

  The present invention solves such a conventional problem, and an object of the present invention is to accurately detect a voltage drop of the battery before the battery is completely consumed and to prompt the user to replace the battery. It is an object of the present invention to provide a memory backup device and a programmable controller having the memory backup device that can prevent backup operation from being interrupted by battery consumption.

As a method for solving the above problems, the present invention is configured as follows.
The invention according to claim 1 is a memory backup device that backs up the storage means with a battery when the main power is off, and supplies the current to the storage means after a predetermined period after the main power is turned on. A backup switching means for switching from the battery to the main power supply; an access prohibiting means for prohibiting access to the storage means until the supply of current to the storage means is switched from the battery to the main power supply by the backup switching means; and during a predetermined period Battery voltage detection means for comparing the voltage value of the battery with a predetermined threshold and outputting the comparison result.

According to a second aspect of the present invention, in the memory backup device according to the first aspect, the predetermined threshold value is set to a voltage value set based on a lower limit voltage at which the storage unit holds data.
The invention according to claim 3 is a programmable controller having the memory backup device according to claim 1 or 2, wherein the storage means stores a parameter for determining an operation mode of the programmable controller. A control unit that determines an operation mode with reference to a parameter is provided, and the battery voltage detection means is configured to reset the control unit and stop the control unit when detecting that the battery voltage is equal to or lower than a predetermined threshold value. Is done.

  According to a fourth aspect of the present invention, in the programmable controller according to the third aspect, the control unit updates the preset threshold value to the new threshold value when a new threshold value is transferred by the support device detachable from the programmable controller. It is comprised so that the update means to perform may be provided.

  According to the present invention, the memory backup state by the battery is continued for a while after the power of the programmable controller is turned on, and the battery voltage in this state is detected. The voltage (actual load voltage E1) can be accurately detected, and the battery backup battery can be prevented from running out. That is, data loss in the memory can be prevented.

The block diagram which shows an example of the CPU module of the programmable controller which mounts the memory backup device of this invention, and a memory backup device Time chart for explaining the operation of FIG. Block diagram showing a configuration example of a conventional memory backup device Time chart for explaining the operation of FIG. The figure explaining the power supply method of a programmable controller

  Hereinafter, a preferred embodiment of the present invention will be described based on the drawings of FIGS. 1, 2, and 5. These drawings are for explaining one embodiment of the present invention, and the present invention is not limited by these drawings. Also, the same components as those in FIGS. 3 and 4 for explaining the prior art are denoted by the same reference numerals.

  An embodiment when the memory backup device of the present invention is applied to a programmable controller (hereinafter referred to as PLC) will be described. The PLC is a device that monitors and controls a device to be monitored and controlled connected to the PLC by calculating and executing an application program, and is widely used in factory automation (FA) and the like.

  FIG. 5 is a diagram showing an example of the configuration of various modules, which are basic functional parts of the PLC, and an example of a power feeding method for each module. A system power supply 200 supplies a predetermined voltage to various modules when commercial power is supplied from the outside.

  Reference numerals 301 and 302 denote CPU modules (common code is 300) that performs overall control of the entire PLC. 401, 402,..., 406 are input / output modules for inputting signals such as switches and sensors attached to appropriate positions of various types of monitoring control target devices and for providing control output signals to actuators of the monitoring control target devices. (Common code is 400), and 100 is a base board on which these various modules and system power supply are mounted.

  The system power supply 200 supplies a base board voltage (DC 24 V in this example) S1 to each of the CPU module 300 and the input / output module 400 via the base board 100. Each of the modules 300 and 400 that has received this voltage S1 generates a module voltage S2 for driving a circuit in the module by a module power supply 1 provided in each module.

  FIG. 1 is a block diagram of the memory backup circuit 01 of the present invention provided in the CPU module 300. 3 differs from the conventional configuration example of FIG. 3 in that a control unit 9, a delay circuit 10, and a transistor 11 are added.

  In FIG. 1, the control unit 9 is equipped with a microprocessor (CPU), a program memory, a working memory, etc., not shown, and an external device is connected via the input / output module 400 by executing the application program described above. Control.

  The transistor 11 is inserted in series in a line extending from the module power supply 1 to the anode of the diode 3, and serves as a switch for opening and closing a power supply path to the memory 2 for the module voltage S2. The memory 2 holds parameters (setting data) for determining the operation mode of the PLC. The control unit 9 determines the operation mode with reference to this parameter.

  The delay circuit 10 is connected to the output line of the module power supply 1 and has a role of keeping the transistor 11 off for a predetermined delay period δ after the module power supply 1 is turned on. Reference numeral 10a denotes a delay circuit output signal as an on / off drive signal which the delay circuit 10 gives to the base of the transistor 11. Thus, the delay circuit 10 and the transistor 11 allow the memory backup circuit 01 to continue the battery backup while the delay circuit 10 is operating after the module voltage S2 is turned on. That is, the delay circuit 10 and the transistor 11 switch the supply of current to the memory 2 from the battery 5 to the module power supply 1 after a predetermined period after the module power supply 1 is turned on (backup switching means).

  The reset release circuit 8 and the battery voltage detection circuit 6 are substantially the same as those shown in FIG. 3 except that the reset release signal 8a is supplied to the control unit 9 in addition to the battery voltage detection circuit 6. In addition, the battery voltage detection circuit output 6 a is provided to the control unit 9 in addition to the display circuit 7.

  1 is the same as the module power supply 1 shown in FIG. 3 in that the module voltage S2 is generated, and the memory 2, the battery 5, and the display circuit 7 are the same as those in FIG.

  FIG. 2 is a time chart for explaining the operation of the memory backup device shown in FIG. In FIG. 2, in addition to the various signals shown in FIG. 4, the output signal of the delay circuit 10 is added, and in order of array numbers 1), 2),. A module voltage S2, a battery voltage 5a, a memory power supply voltage 2a, a reset release signal 8a, a delay circuit output signal 10a, a battery voltage detection circuit output 6a, and a display circuit output 7a are shown. In FIG. 2, the time axis (horizontal axis) is enlarged from FIG.

Next, a specific operation of the memory backup device 01 of FIG. 1 will be described with reference to FIG.
Before time t1, the external power supply to the PLC is cut off, and the module voltage S2 is off. At this time, the memory 2 is backed up by the battery 5. For this reason, the battery voltage 5a at the time point t1 is a stable actual load voltage E1.

  When the external power supply to the PLC is turned on at time t1, the module voltage S2 rises and is turned on. At the beginning of this rise, the reset release circuit 8 is connected to the module as in the prior art described in FIGS. It is detected that the voltage S2 has reached a predetermined voltage, and the reset release signal 8a is turned on. When the reset release signal 8a is turned on, the reset of the control unit 9 is released and the operation is started. The reset release signal 8a is also supplied to the battery voltage detection circuit 6, and the battery voltage detection circuit 6 detects the battery voltage 5a after a predetermined time has elapsed from the rising timing of the reset release signal 8a.

  The delay circuit 10 prevents the transistor 11 from being turned on for a predetermined time after the module voltage S2 reaches a predetermined voltage. Therefore, even after the module voltage S2 is turned on, the delay circuit 10 maintains the delay circuit output signal 10a applied to the base of the transistor 11 at the low level from the rising start time t1 to the time t2 when the delay period δ elapses. 11 is kept off. For this reason, the battery 5 continues to back up the memory 2 as it is until time t2, and the battery voltage 5a maintains the actual load voltage E1.

  Subsequently, at time t2, the delay circuit 10 sets the delay circuit output signal 10a to the high level, and turns on the transistor 11. As a result, the memory 2 is supplied with a voltage from the module voltage S2 side instead of the battery 5, the battery 5 is disconnected from the memory 2, and the battery voltage 5a shifts from the actual load voltage E1 to the no-load voltage E0. To do.

  By the way, at the time tc (battery voltage detection point) before the delay period δ elapses from the time t1, the battery voltage detection circuit 6 detects the battery voltage 5a and compares it with the threshold voltage Eth. This is achieved by turning on the reset release signal 8a by the reset release circuit 8 when the module voltage S2 reaches the predetermined voltage, and detecting the battery voltage 5a after a predetermined time has elapsed from this rising timing. That is, the reset release signal 8a is output at the timing t1, and the battery voltage 5a is compared with the threshold voltage Eth at the timing tc after a predetermined time has elapsed therefrom.

  If the battery voltage 5a (actual load voltage E1) is less than the threshold voltage Eth at the timing tc, the battery voltage detection circuit output 6a is output, and the display circuit 7 receiving this output outputs the display circuit output 6a to give an alarm. To prompt the user to replace the battery. The threshold voltage Eth is a voltage determined from the lower limit voltage necessary for the backup of the memory 2 as described above. Specifically, when the lower limit voltage for backing up the memory 2 is 1V, it is desirable that the voltage be equal to or higher than the voltage obtained by adding the forward voltage of the diode 4 to 1V.

  The threshold voltage Eth can be updated by the control unit 9. When the control unit 9 receives a request for updating the threshold voltage Eth from a programming device (supporting device) that can be attached to and detached from the CPU module 300, the control unit 9 has a function of updating to a new threshold value received simultaneously with the request for updating. (Update means). The battery voltage detection circuit 6 is provided with a D / A conversion function for converting a digital value set by the control unit 9 into a predetermined voltage value, and this D / A converted output voltage is used as a threshold voltage Eth.

  Here, the time points t1, tc, and t2 are defined and the correlation between the respective time points is described. t1 is the time when the module power supply 1 is turned on as described above, that is, the time when the output voltage S2 of the module power supply 1 reaches a predetermined voltage (a voltage at which the control unit 9 can operate). Further, tc is a timing at which the battery voltage 5a is detected after a predetermined time has elapsed with reference to t1. T2 is a timing at which the voltage (current) supply to the memory 2 is switched from the battery 5 to the module power supply 1 after a predetermined time has elapsed with reference to t1. That is, t2 is a timing at which the voltage (current) supply of the memory in the backup state by the battery 5 is switched to the supply of the module power supply 1.

  The relationship between tc and t2 is that the reference is t1 and tc <t2. That is, the point of the present invention is to create the timing of tc within the period from t1 to t2 and detect the battery voltage 5a.

Hereinafter, the operation of the control unit 9 will be mainly described.
The control unit 9 includes a microprocessor (CPU), a program memory, a working memory, and the like that are not shown, and is configured to control external devices that are not shown via the input / output module 400 by executing a sequence program. Has been. In addition, the control unit 9 saves operating state data (such as RAS information) in the memory 2 when the module power supply 1 is turned off or when some malfunction occurs in the PLC.

  The PLC refers to the operating state data held in the memory 2 during the initial state after the power is turned on or after the reset start, and changes the way of rising. That is, the operation mode changes based on the contents saved in the memory 2. If the operating state data is normal data, the initial mode is exited and then the operation mode is entered. However, if traces that mean errors that directly affect the execution of the program, such as parity errors and watchdog timer errors, have been saved in the memory 2, an error that would hinder control again during control execution Since it is expected to occur, the diagnosis mode is set to prompt the diagnosis by the user. In this diagnosis mode, the PLC stays in the diagnosis mode until receiving an instruction for the operation mode from the user. When receiving an instruction for the operation mode from the user, the PLC shifts to the operation mode and executes control.

The movement of the control unit 9 will be described with reference to FIG.
When the reset release signal 8a is turned on (time t1), the control unit 9 executes an initial process for performing a work memory check and various operation settings prior to the execution of the control. In the period from t1 to t2, the control unit 9 operates by executing a program such as an initial process, but access to the memory 2 is prohibited (access prohibiting means). That is, after the module power supply 1 is turned on, access to the memory 2 is prohibited by the access prohibition means until the supply of current to the memory 2 is switched from the battery 5 to the module power supply 1 by the backup switching means.
The reason is as follows.

1) It is unclear whether the memory 2 was normally backed up by the battery 5 before the time point t1. 2) Since the memory 2 is in the backup state during the period from the time point t1 to the time point t2, when the memory 2 in this backup state is accessed The current consumption increases with this access, and the battery 5 is consumed wastefully. 3) When the battery 5 is about to expire, the voltage of the battery 5 suddenly increases due to the memory 2 being accessed. Therefore, the control unit 9 accesses the memory 2 after time t2 to read the operating state data and determines the mode transition.

  As a first method of access prohibiting means for preventing the controller 9 from inadvertently accessing the memory 2 during the period from the time point t1 to the time point t2 (this period is defined as a backup memory access prohibition period), a delay circuit 10 If the output signal 10a is provided to the control unit 9 and the CPU of the control unit 9 reads the output signal 10a via the I / O port, the access permission timing of the memory 2 can be obtained. That is, the program is configured so that the control unit 9 reads the state of the output signal 10a during initialization and does not access the memory 2 until the signal becomes 'H'.

  As a second method, the output signal 10a may be handled as an interrupt signal for the control unit 9. In this case, when the output signal 10a becomes “H” at time t2, the control unit 9 starts an interrupt program for the output signal 10a. The activated interrupt program sets flag information permitting access to the memory 2 in the working memory. The initial process refers to the flag set by the interrupt program, and the program is configured so that the memory 2 is not accessed until this flag is set.

  As a third method, it is possible to prohibit access by hardware in a logic circuit. In this method, the delay circuit output signal 10a and the access request signal to the memory 2 output from the control unit 9 are set so that the chip select signal is not output to the memory 2 unless the delay circuit output signal 10a becomes valid (H). This is achieved by taking a logical product and using the output of this logical product as the chip select of the memory 2. That is, the third method masks the chip select signal to the memory 2 unless the delay circuit output signal 10a becomes valid (H).

  Further, when the control unit 9 tries to access the memory 2 during the backup memory access prohibition section, a memory access abnormality interrupt for executing an abnormality process as an unauthorized access to the memory 2 may be activated. This can be achieved by taking a logical product of the 'L' signal of the delay circuit output signal 10a and the access request signal to the memory 2 to give a memory access abnormal interrupt to the CPU of the control unit 9. That is, if the access request signal becomes active when the delay circuit output signal 10a is 'L', the control unit 9 may activate a memory access abnormality interrupt. The activated memory access abnormality interrupt executes abnormality processing such as outputting an alarm via the display circuit 7 and stays in that state.

  Further, when the battery voltage 5 a is equal to or lower than the reference voltage Eth at the time point tc, the battery voltage detection circuit 6 outputs an alarm via the display circuit 7. At this time, the validity of the data held in the memory 2 is not guaranteed. Therefore, in order to avoid a malfunction of the control unit 9 based on erroneous data held in the memory 2, the battery voltage output circuit 6 continues to reset the CPU of the control unit 9 and stops the execution of the program. .

  Further, the function of the battery voltage detection circuit 6 and the display circuit 7, that is, while the backup of the memory 2 by the battery is continued after the main power is turned on, the voltage of the battery 5 is compared with the threshold value Eth, The function of outputting the comparison result corresponds to the battery voltage detection means.

  As described above, the present invention maintains the backup state of the memory 2 by extending the time after the main power supply is turned on until the voltage supply from the battery to the memory is switched to the voltage supply by the main power supply. The battery voltage (actual load voltage) was detected. In this way, since the actual load voltage of the battery is accurately detected, a backup device that can surely prompt the user to replace the battery before the memory backup capability of the battery 5 is exhausted, and a high-performance device equipped with this backup device. A reliable programmable controller can be provided.

  In the above description, the example in which the memory backup device of the present invention is applied to the PLC has been shown. However, the present invention can be widely applied to devices having a memory backup function, and in particular, control for executing a program. It is possible to provide a memory backup device that is extremely useful for a device including a unit.

01 Memory backup circuit 1 Module power supply 2 Memory 2a Memory power supply voltage 3, 4 Diode 5 Battery 5a Battery voltage 6 Battery voltage detection circuit 6a Battery voltage detection circuit output 7 Display circuit 7a Display circuit output 8 Reset release circuit 8a Reset release signal 9 Control Part 10 Delay circuit 10a Delay circuit output signal 11 Transistor S1 Base board voltage S2 Module voltage Eth Threshold voltage

Claims (4)

A memory backup device for backing up storage means with a battery when the main power is off,
Backup switching means for switching the supply of current to the storage means from the battery to the main power supply after a predetermined period after the main power supply is turned on;
Access prohibiting means for prohibiting access to the storage means until the supply of current to the storage means is switched from the battery to the main power supply by the backup switching means;
Battery voltage detection means for comparing the voltage value of the battery with a predetermined threshold value during the predetermined period and outputting the comparison result;
A memory backup device comprising: The memory backup device according to claim 1,
The memory backup device, wherein the predetermined threshold value is a voltage value set based on a lower limit voltage at which the storage means holds data. A programmable controller comprising the memory backup device according to claim 1 or 2,
The storage means holds a parameter for determining an operation mode of the programmable controller,
The programmable controller includes a control unit that determines the operation mode with reference to the parameter,
When the battery voltage detection unit detects that the voltage of the battery is equal to or less than the predetermined threshold, the programmable controller is configured to reset the control unit and stop the control unit. The programmable controller according to claim 3,
The said control part is equipped with the update means which updates the said preset threshold value to the said new threshold value, when the said new threshold value is transferred by the assistance apparatus which can be attached or detached to the said programmable controller, The programmable controller characterized by the above-mentioned.